From 3e0a0fbbac48e47d45e234691fddb55194052bed Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 29 Jan 2016 16:56:01 +0800 Subject: armv8/ls1043a: enable workaround for errarum A009942 DDR erratum A-009942 applies to LS1043A. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index ff3b1be..a4eb096 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -177,6 +177,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009929 +#define CONFIG_SYS_FSL_ERRATUM_A009942 #else #error SoC not defined #endif -- cgit v1.1 From bbc8e053bad16366fc74943ce4c69a910c31b8b8 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 2 Feb 2016 11:28:03 +0800 Subject: armv8/ls1043a: Implement workaround for erratum A009660 Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance. Signed-off-by: Mingkai Hu Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index a4eb096..0ef7c9d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -178,6 +178,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009929 #define CONFIG_SYS_FSL_ERRATUM_A009942 +#define CONFIG_SYS_FSL_ERRATUM_A009660 #else #error SoC not defined #endif -- cgit v1.1