From 0d6faf2bd0d12642e8b2c428d62c285f4ee28b9d Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Mon, 7 Dec 2015 16:58:54 +0800 Subject: armv8/ls1043a: Implement workaround for PEX erratum A009929 Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape/config.h') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 6e5224e..49b113d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -166,6 +166,7 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A009929 #else #error SoC not defined #endif -- cgit v1.1