From f3d7c2fe9da9b03230cecd634ddbbb2654f3d13d Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:22 +0530 Subject: Exynos5420: Add DDR3 initialization for 5420 This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/include/asm/arch-exynos/dmc.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/include/asm/arch-exynos/dmc.h') diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index 32ad3ae..d78536d 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -419,6 +419,15 @@ struct exynos5420_phy_control { unsigned int phy_con42; }; +struct exynos5420_tzasc { + unsigned char res1[0xf00]; + unsigned int membaseconfig0; + unsigned int membaseconfig1; + unsigned char res2[0x8]; + unsigned int memconfig0; + unsigned int memconfig1; +}; + enum ddr_mode { DDR_MODE_DDR2, DDR_MODE_DDR3, @@ -453,6 +462,7 @@ enum mem_manuf { #define PHY_CON0_T_WRRDCMD_SHIFT 17 #define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT) #define PHY_CON0_CTRL_DDR_MODE_SHIFT 11 +#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3 /* PHY_CON1 register fields */ #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 -- cgit v1.1