From d4898ea89684aa285cfb34fbab6831c28dc0ed33 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 30 Jul 2012 14:49:50 -0700 Subject: am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and support Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm/include/asm/arch-am33xx/ddr_defs.h') diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 0526863..6b22c45 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -47,6 +47,23 @@ #define DDR2_PHY_RANK0_DELAY 0x1 #define DDR2_IOCTRL_VALUE 0x18B +/* Micron MT41J128M16JT-125 */ +#define DDR3_EMIF_READ_LATENCY 0x06 +#define DDR3_EMIF_TIM1 0x0888A39B +#define DDR3_EMIF_TIM2 0x26337FDA +#define DDR3_EMIF_TIM3 0x501F830F +#define DDR3_EMIF_SDCFG 0x61C04AB2 +#define DDR3_EMIF_SDREF 0x0000093B +#define DDR3_ZQ_CFG 0x50074BE4 +#define DDR3_DLL_LOCK_DIFF 0x1 +#define DDR3_RATIO 0x40 +#define DDR3_INVERT_CLKOUT 0x1 +#define DDR3_RD_DQS 0x3B +#define DDR3_WR_DQS 0x85 +#define DDR3_PHY_WR_DATA 0xC1 +#define DDR3_PHY_FIFO_WE 0x100 +#define DDR3_IOCTRL_VALUE 0x18B + /** * Configure SDRAM */ -- cgit v1.1