From d3daba10f159cca7e9d24c6f154926a9b92c75e3 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:22 +0530 Subject: ARM: AM43xx: EPOS_EVM: Add support for LPDDR2 AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/include/asm/arch-am33xx/clocks_am33xx.h') diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 02ed595..4c9352a 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -28,6 +28,9 @@ #define UART_CLK_RUNNING_MASK 0x1 #define UART_SMART_IDLE_EN (0x1 << 0x3) +#define CM_DLL_CTRL_NO_OVERRIDE 0x0 +#define CM_DLL_READYST 0x4 + extern void enable_dmm_clocks(void); extern const struct dpll_params dpll_core_opp100; extern struct dpll_params dpll_mpu_opp100; -- cgit v1.1