From cd8341b7eb7bcf630a49538684778d87daef3e61 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Mon, 10 Feb 2014 11:41:49 -0500 Subject: ARM: AM43xx: GP-EVM: Correct GPIO used for VTT regulator control Schematic indicates GPIO5_7 is to be used for VTT regulator control rather than GPIO0_21 so modify enable_vtt_regulator to reflect this. Without this some boards will experience DDR3 corruption and fail to boot. Signed-off-by: Dave Gerlach [trini: Rework patch against mainline] Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/board.c | 6 +++++- arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 2 ++ 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index c7dad66..2b15a64 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -36,11 +36,15 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct gpio_bank gpio_bank_am33xx[4] = { +static const struct gpio_bank gpio_bank_am33xx[] = { { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, +#ifdef CONFIG_AM43XX + { (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX }, +#endif }; const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index 97c00b4..440cf8b 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -94,6 +94,8 @@ void enable_basic_clocks(void) &cmper->gpio1clkctrl, &cmper->gpio2clkctrl, &cmper->gpio3clkctrl, + &cmper->gpio4clkctrl, + &cmper->gpio5clkctrl, &cmper->i2c1clkctrl, &cmper->emiffwclkctrl, &cmper->emifclkctrl, -- cgit v1.1 From 6e2192a3d80b315d071dfe0cbb70a35fe0a262e9 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Sun, 16 Feb 2014 21:57:18 +0100 Subject: ARM: OMAP4: fix DDR timings for OMAP4430 ES2.0 DDR timings were broken since 47abc3df701d8bc26f311350aa523fc1d0f8ad4e for PandaBoard EA1. Signed-off-by: Janne Grunau --- arch/arm/cpu/armv7/omap4/hw_data.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 4dec73e..029533c 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -172,6 +172,20 @@ struct dplls omap4430_dplls_es1 = { .ddr = NULL }; +struct dplls omap4430_dplls_es20 = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_es2_1600mhz_ddr200mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + struct dplls omap4430_dplls = { .mpu = mpu_dpll_params_1200mhz, .core = core_dpll_params_1600mhz, @@ -413,6 +427,10 @@ void hw_data_init(void) break; case OMAP4430_ES2_0: + *dplls_data = &omap4430_dplls_es20; + *omap_vcores = &omap4430_volts; + break; + case OMAP4430_ES2_1: case OMAP4430_ES2_2: case OMAP4430_ES2_3: -- cgit v1.1 From 82da4410f8fb68d2f1f8e1692baa1779cd03909e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 18 Feb 2014 12:00:01 -0600 Subject: DRA7: fix ABB efuse offset for OPP_NOM commit 194dd74ad919e57026f385aaab7f89acf7ea79ef (DRA7: add ABB setup for MPU voltage domain) Made an offset typo error by using 0x4A003B24 as the efuse offset for OPP_NOM. As per TI documentation, 0x4A003B24 is for OPP_OD, and 0x4A003B20 is for OPP_NOM. Fix the same. Reported-by: Praveen Rao Signed-off-by: Nishanth Menon --- arch/arm/cpu/armv7/omap5/prcm-regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index ff32807..7292161 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -432,7 +432,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_srcomp_code_latch = 0x4A002E84, .control_ddr_control_ext_0 = 0x4A002E88, .control_padconf_core_base = 0x4A003400, - .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B24, + .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B20, .control_port_emif1_sdram_config = 0x4AE0C110, .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, .control_port_emif2_sdram_config = 0x4AE0C118, -- cgit v1.1 From 11f296870659e1375e7116a859458b254cc3156f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=C3=A5ns=20Rullg=C3=A5rd?= Date: Mon, 28 Oct 2013 23:19:53 +0000 Subject: ti814x: Fix illegal use of FP ops in clock_ti814x.c The function pll_sigma_delta_val uses "float" data which is not correct. The exact "why" of this mangling is lost to history, but this changes us to equivalent non-FP math to get the same results. Reported-by: Wolfgang Denk Acked-by: Matt Porter --- arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index ef14f47..9b5a47b 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -211,11 +211,8 @@ static u32 pll_dco_freq_sel(u32 clkout_dco) static u32 pll_sigma_delta_val(u32 clkout_dco) { u32 sig_val = 0; - float frac_div; - frac_div = (float) clkout_dco / 250; - frac_div = frac_div + 0.90; - sig_val = (int)frac_div; + sig_val = (clkout_dco + 225) / 250; sig_val = sig_val << 24; return sig_val; -- cgit v1.1