From 6e3dc127545247f123de063a6a101960e3eb2ccd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Thu, 27 Sep 2012 10:26:02 +0000 Subject: mx35: Fix eSDHC clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Each eSDHC instance has a dedicated clock. gd->sdhc_clk must also be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Cc: Eric Bénard Cc: Otavio Salvador --- arch/arm/cpu/arm1136/mx35/generic.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index 7dc1a8e..41e9639 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -361,8 +361,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_ipg_per_clk(); case MXC_UART_CLK: return imx_get_uartclk(); - case MXC_ESDHC_CLK: + case MXC_ESDHC1_CLK: return mxc_get_peri_clock(ESDHC1_CLK); + case MXC_ESDHC2_CLK: + return mxc_get_peri_clock(ESDHC2_CLK); + case MXC_ESDHC3_CLK: + return mxc_get_peri_clock(ESDHC3_CLK); case MXC_USB_CLK: return mxc_get_main_clock(USB_CLK); case MXC_FEC_CLK: @@ -472,7 +476,13 @@ int cpu_mmc_init(bd_t *bis) int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC - gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); +#else + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); +#endif #endif return 0; } -- cgit v1.1 From 758c3449451f20402af72fa0754a1ce32ba9af48 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 15 Oct 2012 05:37:15 +0000 Subject: mx5: lowlevel_init.S: Split init_clock macro init_clock is currently shared between mx51 and mx53 and it contains lots of ifdef's which makes it really hard to follow the code. Split the init_clock between mx51 and mx53 to allow easier readability. No functional changes are made. Signed-off-by: Fabio Estevam --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 95 +++++++++++++++++++++++----------- 1 file changed, 65 insertions(+), 30 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 529e35b..d0bab45 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -162,9 +162,9 @@ setup_pll_func: .endm .macro init_clock +#if defined (CONFIG_MX51) ldr r0, =CCM_BASE_ADDR -#if defined(CONFIG_MX51) /* Gate of clocks to the peripherals first */ ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0] @@ -190,21 +190,6 @@ setup_pll_func: 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 bne 1b -#else - ldr r1, =0x3FFFFFFF - str r1, [r0, #CLKCTL_CCGR0] - str r4, [r0, #CLKCTL_CCGR1] - str r4, [r0, #CLKCTL_CCGR2] - str r4, [r0, #CLKCTL_CCGR3] - str r4, [r0, #CLKCTL_CCGR7] - - ldr r1, =0x00030000 - str r1, [r0, #CLKCTL_CCGR4] - ldr r1, =0x00FFF030 - str r1, [r0, #CLKCTL_CCGR5] - ldr r1, =0x0F00030F - str r1, [r0, #CLKCTL_CCGR6] -#endif /* Switch ARM to step clock */ mov r1, #0x4 @@ -217,7 +202,6 @@ setup_pll_func: setup_pll PLL1_BASE_ADDR, 800 #endif -#if defined(CONFIG_MX51) setup_pll PLL3_BASE_ADDR, 665 /* Switch peripheral to PLL 3 */ @@ -234,7 +218,7 @@ setup_pll_func: str r1, [r0, #CLKCTL_CBCDR] ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] -#endif + setup_pll PLL3_BASE_ADDR, 216 /* Set the platform clock dividers */ @@ -244,21 +228,17 @@ setup_pll_func: ldr r0, =CCM_BASE_ADDR -#if defined(CONFIG_MX51) /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 movls r1, #0x1 movhi r1, #0 -#else - mov r1, #0 -#endif + str r1, [r0, #CLKCTL_CACRR] /* Switch ARM back to PLL 1 */ str r4, [r0, #CLKCTL_CCSR] -#if defined(CONFIG_MX51) /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL @@ -266,7 +246,6 @@ setup_pll_func: /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ ldr r1, =CONFIG_SYS_CLKTL_CBCDR str r1, [r0, #CLKCTL_CBCDR] -#endif /* Restore the default values in the Gate registers */ ldr r1, =0xFFFFFFFF @@ -277,17 +256,72 @@ setup_pll_func: str r1, [r0, #CLKCTL_CCGR4] str r1, [r0, #CLKCTL_CCGR5] str r1, [r0, #CLKCTL_CCGR6] -#if defined(CONFIG_MX53) - str r1, [r0, #CLKCTL_CCGR7] -#endif -#if defined(CONFIG_MX51) /* Use PLL 2 for UART's, get 66.5MHz from it */ ldr r1, =0xA5A2A020 str r1, [r0, #CLKCTL_CSCMR1] ldr r1, =0x00C30321 str r1, [r0, #CLKCTL_CSCDR1] -#elif defined(CONFIG_MX53) + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + str r4, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +#else /* CONFIG_MX53 */ + ldr r0, =CCM_BASE_ADDR + + /* Gate of clocks to the peripherals first */ + ldr r1, =0x3FFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r4, [r0, #CLKCTL_CCGR1] + str r4, [r0, #CLKCTL_CCGR2] + str r4, [r0, #CLKCTL_CCGR3] + str r4, [r0, #CLKCTL_CCGR7] + ldr r1, =0x00030000 + str r1, [r0, #CLKCTL_CCGR4] + ldr r1, =0x00FFF030 + str r1, [r0, #CLKCTL_CCGR5] + ldr r1, =0x0F00030F + str r1, [r0, #CLKCTL_CCGR6] + + /* Switch ARM to step clock */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + + setup_pll PLL1_BASE_ADDR, 800 + + setup_pll PLL3_BASE_ADDR, 216 + + /* Set the platform clock dividers */ + ldr r0, =ARM_BASE_ADDR + ldr r1, =0x00000725 + str r1, [r0, #0x14] + + ldr r0, =CCM_BASE_ADDR + + mov r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* Switch ARM back to PLL 1 */ + str r4, [r0, #CLKCTL_CCSR] + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + str r1, [r0, #CLKCTL_CCGR7] + /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00808145 @@ -306,7 +340,7 @@ setup_pll_func: and r1, r1, #0xffffffc0 orr r1, r1, #0x0a str r1, [r0, #CLKCTL_CSCDR1] -#endif + /* make sure divider effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 @@ -318,6 +352,7 @@ setup_pll_func: mov r1, #0x000A0000 add r1, r1, #0x00000F0 str r1, [r0, #CLKCTL_CCOSR] +#endif /* CONFIG_MX53 */ .endm .macro setup_wdog -- cgit v1.1 From 782b02884126cc258056e8bf581a410a934f7372 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 15 Oct 2012 05:37:16 +0000 Subject: mx5: lowlevel_init.S: Fix PLL settings for mx53 Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 96 ++++++++++++++++++++++------------ 1 file changed, 63 insertions(+), 33 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index d0bab45..d62093b 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -296,20 +296,66 @@ setup_pll_func: setup_pll PLL1_BASE_ADDR, 800 - setup_pll PLL3_BASE_ADDR, 216 + setup_pll PLL3_BASE_ADDR, 400 + + /* Switch peripheral to PLL3 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00015154 + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, =0x02888945 + orr r1, r1, #(1 << 16) + str r1, [r0, #CLKCTL_CBCDR] + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL2_BASE_ADDR, 400 + + /* Switch peripheral to PLL2 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00808145 + orr r1, r1, #(2 << 10) + orr r1, r1, #(0 << 16) + orr r1, r1, #(1 << 19) + str r1, [r0, #CLKCTL_CBCDR] + + ldr r1, =0x00016154 + str r1, [r0, #CLKCTL_CBCMR] + + /*change uart clk parent to pll2*/ + ldr r1, [r0, #CLKCTL_CSCMR1] + and r1, r1, #0xfcffffff + orr r1, r1, #0x01000000 + str r1, [r0, #CLKCTL_CSCMR1] + + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL3_BASE_ADDR, 216 + + setup_pll PLL4_BASE_ADDR, 455 /* Set the platform clock dividers */ ldr r0, =ARM_BASE_ADDR - ldr r1, =0x00000725 + ldr r1, =0x00000124 str r1, [r0, #0x14] ldr r0, =CCM_BASE_ADDR - mov r1, #0 str r1, [r0, #CLKCTL_CACRR] - /* Switch ARM back to PLL 1 */ - str r4, [r0, #CLKCTL_CCSR] + /* Switch ARM back to PLL 1. */ + mov r1, #0x0 + str r1, [r0, #CLKCTL_CCSR] + + /* make uart div=6 */ + ldr r1, [r0, #CLKCTL_CSCDR1] + and r1, r1, #0xffffffc0 + orr r1, r1, #0x0a + str r1, [r0, #CLKCTL_CSCDR1] /* Restore the default values in the Gate registers */ ldr r1, =0xFFFFFFFF @@ -322,36 +368,14 @@ setup_pll_func: str r1, [r0, #CLKCTL_CCGR6] str r1, [r0, #CLKCTL_CCGR7] - /* Switch peripheral to PLL2 */ - ldr r0, =CCM_BASE_ADDR - ldr r1, =0x00808145 - orr r1, r1, #2 << 10 - orr r1, r1, #1 << 19 - str r1, [r0, #CLKCTL_CBCDR] + mov r1, #0x00000 + str r1, [r0, #CLKCTL_CCDR] - ldr r1, =0x00016154 - str r1, [r0, #CLKCTL_CBCMR] - /* Change uart clk parent to pll2*/ - ldr r1, [r0, #CLKCTL_CSCMR1] - and r1, r1, #0xfcffffff - orr r1, r1, #0x01000000 - str r1, [r0, #CLKCTL_CSCMR1] - ldr r1, [r0, #CLKCTL_CSCDR1] - and r1, r1, #0xffffffc0 - orr r1, r1, #0x0a - str r1, [r0, #CLKCTL_CSCDR1] - - /* make sure divider effective */ -1: ldr r1, [r0, #CLKCTL_CDHIPR] - cmp r1, #0x0 - bne 1b + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] - str r4, [r0, #CLKCTL_CCDR] - - /* for cko - for ARM div by 8 */ - mov r1, #0x000A0000 - add r1, r1, #0x00000F0 - str r1, [r0, #CLKCTL_CCOSR] #endif /* CONFIG_MX53 */ .endm @@ -405,3 +429,9 @@ W_DP_665: .word DP_OP_665 W_DP_216: .word DP_OP_216 .word DP_MFD_216 .word DP_MFN_216 +W_DP_400: .word DP_OP_400 + .word DP_MFD_400 + .word DP_MFN_400 +W_DP_455: .word DP_OP_455 + .word DP_MFD_455 + .word DP_MFN_455 -- cgit v1.1 From c4fe17f6d83fa369af90be0764e82150c5879bd0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 7 May 2012 10:56:00 +0000 Subject: mx5: Add workaround for ARM erratum ID 468414 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the software workaround for ARM erratum ID 468414. According to mx53/mx51 errata document: "ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a subsequent request Description: Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded to a subsequent, unrelated memory request. The conditions are as follows: • Neon loads and stores must be in use • Neon L1 caching must be disabled • Trustzone must be configured and in use • The secure memory address space and the non-secure memory address space both use the same physical addresses, either as an alias or the same memory location or for separate memory locations The issue is reported by ARM, erratum ID 468414, Category 2" Signed-off-by: Fabio Estevam --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index d62093b..29ec957 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -26,6 +26,13 @@ .section ".text.init", "x" +.macro init_arm_erratum + /* ARM erratum ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1 +.endm + /* * L2CC Cache setup/invalidation/disable */ @@ -399,6 +406,8 @@ ENTRY(lowlevel_init) str r1, [r0, #0x4] #endif + init_arm_erratum + init_l2cc init_aips -- cgit v1.1 From 01968b96a24414ff8f0735111907cbb750c7af43 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 24 Oct 2012 10:06:28 +0200 Subject: MX5: fix warning in clock.c Patch fix warnings compiling with ELDK-4.2: clock.c: In function 'get_standard_pll_sel_clk': clock.c:341: warning: 'freq' may be used uninitialized in this function Reported-by : Marek Vasut Signed-off-by: Stefano Babic --- arch/arm/cpu/armv7/mx5/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 2709860..1c9223f 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -338,7 +338,7 @@ static u32 get_ipg_per_clk(void) /* Get the output clock rate of a standard PLL MUX for peripherals. */ static u32 get_standard_pll_sel_clk(u32 clk_sel) { - u32 freq; + u32 freq = 0; switch (clk_sel & 0x3) { case 0: -- cgit v1.1