From a78cd8613204188991c192b8dae2de0aae3b1722 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 1 Aug 2016 18:54:53 -0400 Subject: ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren Tested-by: Stephen Warren Acked-by: Ziyuan Xu Acked-by: Sandy Patterson Reported-by: Ziyuan Xu Reported-by: Sandy Patterson Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/cache_v7.c | 10 +++++----- arch/arm/cpu/armv7/psci-common.c | 2 +- arch/arm/cpu/armv7/sunxi/psci.c | 12 ++++++------ 3 files changed, 12 insertions(+), 12 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 52f1856..c4bbcc3 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -75,7 +75,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* DSB to make sure the operation is complete */ - DSB; + dsb(); } /* Invalidate TLB */ @@ -88,9 +88,9 @@ static void v7_inval_tlb(void) /* Invalidate entire instruction TLB */ asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - DSB; + dsb(); /* Full system ISB - make sure the instruction stream sees it */ - ISB; + isb(); } void invalidate_dcache_all(void) @@ -194,10 +194,10 @@ void invalidate_icache_all(void) asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - DSB; + dsb(); /* ISB - make sure the instruction stream sees it */ - ISB; + isb(); } #else void invalidate_icache_all(void) diff --git a/arch/arm/cpu/armv7/psci-common.c b/arch/arm/cpu/armv7/psci-common.c index d14b693..8cb4107 100644 --- a/arch/arm/cpu/armv7/psci-common.c +++ b/arch/arm/cpu/armv7/psci-common.c @@ -29,7 +29,7 @@ static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 }; void __secure psci_save_target_pc(int cpu, u32 pc) { psci_target_pc[cpu] = pc; - DSB; + dsb(); } u32 __secure psci_get_target_pc(int cpu) diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 7ac8406..766b8c7 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -53,16 +53,16 @@ static void __secure __mdelay(u32 ms) u32 reg = ONE_MS * ms; cp15_write_cntp_tval(reg); - ISB; + isb(); cp15_write_cntp_ctl(3); do { - ISB; + isb(); reg = cp15_read_cntp_ctl(); } while (!(reg & BIT(2))); cp15_write_cntp_ctl(0); - ISB; + isb(); } static void __secure clamp_release(u32 __maybe_unused *clamp) @@ -164,7 +164,7 @@ static u32 __secure cp15_read_scr(void) static void __secure cp15_write_scr(u32 scr) { asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr)); - ISB; + isb(); } /* @@ -190,7 +190,7 @@ void __secure __irq psci_fiq_enter(void) /* End of interrupt */ writel(reg, GICC_BASE + GICC_EOIR); - DSB; + dsb(); /* Get CPU number */ cpu = (reg >> 10) & 0x7; @@ -242,7 +242,7 @@ void __secure psci_cpu_off(void) /* Ask CPU0 via SGI15 to pull the rug... */ writel(BIT(16) | 15, GICD_BASE + GICD_SGIR); - DSB; + dsb(); /* Wait to be turned off */ while (1) -- cgit v1.1