From 104d6fb6cd064c4c9278e5b6fdf99ac025597753 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 21 Apr 2015 07:18:24 +0200 Subject: ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those. CC: Tang Yuantian CC: York Sun CC: Steve Rae CC: Andre Przywara Signed-off-by: Jan Kiszka Tested-by: Alison Wang Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 2 +- arch/arm/cpu/armv7/virt-dt.c | 2 +- arch/arm/cpu/u-boot.lds | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index e66c61e..5a76100 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -18,7 +18,7 @@ obj-y += lowlevel_init.o endif endif -ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),) +ifneq ($(CONFIG_ARMV7_NONSEC),) obj-y += nonsec_virt.o obj-y += virt-v7.o obj-y += virt-dt.o diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 1a640bb..75f0d8c 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -329,7 +329,7 @@ int arch_cpu_init(void) return 0; } -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +#ifdef CONFIG_ARMV7_NONSEC /* Set the address at which the secondary core starts from.*/ void smp_set_core_boot_addr(unsigned long addr, int corenr) { diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c index 9408e33..caaaaab 100644 --- a/arch/arm/cpu/armv7/virt-dt.c +++ b/arch/arm/cpu/armv7/virt-dt.c @@ -90,7 +90,7 @@ static int fdt_psci(void *fdt) int psci_update_dt(void *fdt) { -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +#ifdef CONFIG_ARMV7_NONSEC if (!armv7_boot_nonsec()) return 0; #endif diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 7336162..03cd9f6 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -25,7 +25,7 @@ SECTIONS *(.text*) } -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI) +#ifdef CONFIG_ARMV7_NONSEC #ifndef CONFIG_ARMV7_SECURE_BASE #define CONFIG_ARMV7_SECURE_BASE -- cgit v1.1 From 680f396851b7153f7f4243e1cc8875558b678add Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 21 Apr 2015 07:18:26 +0200 Subject: ARM: Factor out common psci_get_cpu_id Will be required for obtaining the ID of the current CPU in shared PSCI functions. The default implementation requires a dense ID space and only supports a single cluster. Therefore, the functions can be overloaded in cases where these assumptions do not hold. CC: Marc Zyngier Signed-off-by: Jan Kiszka Reviewed-by: Tom Rini Reviewed-by: Thierry Reding Tested-by: Thierry Reding Tested-by: Ian Campbell Acked-by: Ian Campbell Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/psci.S | 8 ++++++++ arch/arm/cpu/armv7/sunxi/psci.S | 12 +++++++----- 2 files changed, 15 insertions(+), 5 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index bf11a34..12ad09b 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -99,4 +99,12 @@ _smc_psci: pop {r4-r7, lr} movs pc, lr @ Return to the kernel +@ Requires dense and single-cluster CPU ID space +ENTRY(psci_get_cpu_id) + mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */ + and r0, r0, #0xff /* return CPU ID in cluster */ + bx lr +ENDPROC(psci_get_cpu_id) +.weak psci_get_cpu_id + .popsection diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index 07b2d76..bcc419d 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -19,6 +19,7 @@ #include #include +#include #include #include @@ -290,6 +291,8 @@ psci_cpu_off: .globl psci_arch_init psci_arch_init: + mov r6, lr + movw r4, #(GICD_BASE & 0xffff) movt r4, #(GICD_BASE >> 16) @@ -315,18 +318,17 @@ psci_arch_init: mcr p15, 0, r5, c1, c1, 0 @ Write SCR isb - mrc p15, 0, r4, c0, c0, 5 @ MPIDR - and r4, r4, #3 @ cpu number in cluster + bl psci_get_cpu_id mov r5, #0x400 @ 1kB of stack per CPU - mul r4, r4, r5 + mul r0, r0, r5 adr r5, text_end @ end of text add r5, r5, #0x2000 @ Skip two pages lsr r5, r5, #12 @ Align to start of page lsl r5, r5, #12 - sub sp, r5, r4 @ here's our stack! + sub sp, r5, r0 @ here's our stack! - bx lr + bx r6 text_end: .popsection -- cgit v1.1 From b0206e7d26ebb695421c7c093b13475bed92c54d Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 21 Apr 2015 07:18:27 +0200 Subject: ARM: Factor out reusable psci_cpu_off_common Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier Signed-off-by: Jan Kiszka Reviewed-by: Tom Rini Reviewed-by: Thierry Reding Tested-by: Thierry Reding Tested-by: Ian Campbell Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/psci.S | 77 +++++++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/psci.S | 63 +-------------------------------- 2 files changed, 78 insertions(+), 62 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 12ad09b..cdcdccd 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -107,4 +107,81 @@ ENTRY(psci_get_cpu_id) ENDPROC(psci_get_cpu_id) .weak psci_get_cpu_id +/* Imported from Linux kernel */ +LENTRY(v7_flush_dcache_all) + dmb @ ensure ordering with previous memory accesses + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +flush_levels: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt skip @ skip if no cache, or just i-cache + mrs r9, cpsr @ make cssr&csidr read atomic + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb @ isb to sych the new cssr&csidr + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + msr cpsr_c, r9 + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +loop1: + mov r9, r7 @ create working copy of max index +loop2: + orr r11, r10, r4, lsl r5 @ factor way and cache number into r11 + orr r11, r11, r9, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the index + bge loop2 + subs r4, r4, #1 @ decrement the way + bge loop1 +skip: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt flush_levels +finished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + dsb st + isb + bx lr +ENDPROC(v7_flush_dcache_all) + +ENTRY(psci_disable_smp) + mrc p15, 0, r0, c1, c0, 1 @ ACTLR + bic r0, r0, #(1 << 6) @ Clear SMP bit + mcr p15, 0, r0, c1, c0, 1 @ ACTLR + isb + dsb + bx lr +ENDPROC(psci_disable_smp) +.weak psci_disable_smp + +ENTRY(psci_cpu_off_common) + push {lr} + + mrc p15, 0, r0, c1, c0, 0 @ SCTLR + bic r0, r0, #(1 << 2) @ Clear C bit + mcr p15, 0, r0, c1, c0, 0 @ SCTLR + isb + dsb + + bl v7_flush_dcache_all + + clrex @ Why??? + + bl psci_disable_smp + + pop {lr} + bx lr +ENDPROC(psci_cpu_off_common) + .popsection diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index bcc419d..05d047b 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -200,53 +200,6 @@ psci_cpu_on: _target_pc: .word 0 -/* Imported from Linux kernel */ -v7_flush_dcache_all: - dmb @ ensure ordering with previous memory accesses - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field - beq finished @ if loc is 0, then no need to clean - mov r10, #0 @ start clean at cache level 0 -flush_levels: - add r2, r10, r10, lsr #1 @ work out 3x current cache level - mov r1, r0, lsr r2 @ extract cache type bits from clidr - and r1, r1, #7 @ mask of the bits for current cache only - cmp r1, #2 @ see what cache we have at this level - blt skip @ skip if no cache, or just i-cache - mrs r9, cpsr @ make cssr&csidr read atomic - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - isb @ isb to sych the new cssr&csidr - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - msr cpsr_c, r9 - and r2, r1, #7 @ extract the length of the cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the way size - clz r5, r4 @ find bit position of way size increment - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the index size -loop1: - mov r9, r7 @ create working copy of max index -loop2: - orr r11, r10, r4, lsl r5 @ factor way and cache number into r11 - orr r11, r11, r9, lsl r2 @ factor index number into r11 - mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way - subs r9, r9, #1 @ decrement the index - bge loop2 - subs r4, r4, #1 @ decrement the way - bge loop1 -skip: - add r10, r10, #2 @ increment cache number - cmp r3, r10 - bgt flush_levels -finished: - mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - dsb st - isb - bx lr - _sunxi_cpu_entry: @ Set SMP bit mrc p15, 0, r0, c1, c0, 1 @@ -262,21 +215,7 @@ _sunxi_cpu_entry: .globl psci_cpu_off psci_cpu_off: - mrc p15, 0, r0, c1, c0, 0 @ SCTLR - bic r0, r0, #(1 << 2) @ Clear C bit - mcr p15, 0, r0, c1, c0, 0 @ SCTLR - isb - dsb - - bl v7_flush_dcache_all - - clrex @ Why??? - - mrc p15, 0, r0, c1, c0, 1 @ ACTLR - bic r0, r0, #(1 << 6) @ Clear SMP bit - mcr p15, 0, r0, c1, c0, 1 @ ACTLR - isb - dsb + bl psci_cpu_off_common @ Ask CPU0 to pull the rug... movw r0, #(GICD_BASE & 0xffff) -- cgit v1.1 From 4ce4de1e6618340177eeb0914fc86054c6cc6dca Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 21 Apr 2015 07:18:28 +0200 Subject: ARM: Factor out reusable psci_cpu_entry _sunxi_cpu_entry can be converted completely into a reusable psci_cpu_entry. Tegra124 will use it as well. As with psci_disable_smp, also the enabling is designed to be overloaded in cased SMP is not controlled via ACTLR. CC: Marc Zyngier Signed-off-by: Jan Kiszka Reviewed-by: Tom Rini Reviewed-by: Thierry Reding Tested-by: Thierry Reding Tested-by: Ian Campbell Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/psci.S | 23 +++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/psci.S | 20 ++------------------ 2 files changed, 25 insertions(+), 18 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index cdcdccd..7d89b43 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -165,6 +165,15 @@ ENTRY(psci_disable_smp) ENDPROC(psci_disable_smp) .weak psci_disable_smp +ENTRY(psci_enable_smp) + mrc p15, 0, r0, c1, c0, 1 @ ACTLR + orr r0, r0, #(1 << 6) @ Set SMP bit + mcr p15, 0, r0, c1, c0, 1 @ ACTLR + isb + bx lr +ENDPROC(psci_enable_smp) +.weak psci_enable_smp + ENTRY(psci_cpu_off_common) push {lr} @@ -184,4 +193,18 @@ ENTRY(psci_cpu_off_common) bx lr ENDPROC(psci_cpu_off_common) +ENTRY(psci_cpu_entry) + bl psci_enable_smp + + bl _nonsec_init + + adr r0, _psci_target_pc + ldr r0, [r0] + b _do_nonsec_entry +ENDPROC(psci_cpu_entry) + +.globl _psci_target_pc +_psci_target_pc: + .word 0 + .popsection diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index 05d047b..90dcff1 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -139,7 +139,7 @@ out: mcr p15, 0, r7, c1, c1, 0 @ r2 = target PC .globl psci_cpu_on psci_cpu_on: - adr r0, _target_pc + ldr r0, =_psci_target_pc str r2, [r0] dsb @@ -151,7 +151,7 @@ psci_cpu_on: mov r4, #1 lsl r4, r4, r1 - adr r6, _sunxi_cpu_entry + ldr r6, =psci_cpu_entry str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector) @ Assert reset on target CPU @@ -197,22 +197,6 @@ psci_cpu_on: mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS mov pc, lr -_target_pc: - .word 0 - -_sunxi_cpu_entry: - @ Set SMP bit - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #0x40 - mcr p15, 0, r0, c1, c0, 1 - isb - - bl _nonsec_init - - adr r0, _target_pc - ldr r0, [r0] - b _do_nonsec_entry - .globl psci_cpu_off psci_cpu_off: bl psci_cpu_off_common -- cgit v1.1 From 4c681a3d22f0018186d83d753be566965c0cf7a5 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 21 Apr 2015 07:18:29 +0200 Subject: ARM: Factor out reusable psci_get_cpu_stack_top This algorithm will be useful on Tegra as well, plus we will need it for making _psci_target_pc per-CPU. CC: Marc Zyngier Signed-off-by: Jan Kiszka Reviewed-by: Tom Rini Reviewed-by: Thierry Reding Tested-by: Thierry Reding Tested-by: Ian Campbell Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/psci.S | 14 ++++++++++++++ arch/arm/cpu/armv7/sunxi/psci.S | 15 +++++---------- 2 files changed, 19 insertions(+), 10 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 7d89b43..18d85c4 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -193,6 +193,20 @@ ENTRY(psci_cpu_off_common) bx lr ENDPROC(psci_cpu_off_common) +@ expects CPU ID in r0 and returns stack top in r0 +ENTRY(psci_get_cpu_stack_top) + mov r5, #0x400 @ 1kB of stack per CPU + mul r0, r0, r5 + + ldr r5, =psci_text_end @ end of monitor text + add r5, r5, #0x2000 @ Skip two pages + lsr r5, r5, #12 @ Align to start of page + lsl r5, r5, #12 + sub r0, r5, r0 @ here's our stack! + + bx lr +ENDPROC(psci_get_cpu_stack_top) + ENTRY(psci_cpu_entry) bl psci_enable_smp diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index 90dcff1..dd583b2 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -241,17 +241,12 @@ psci_arch_init: mcr p15, 0, r5, c1, c1, 0 @ Write SCR isb - bl psci_get_cpu_id - mov r5, #0x400 @ 1kB of stack per CPU - mul r0, r0, r5 - - adr r5, text_end @ end of text - add r5, r5, #0x2000 @ Skip two pages - lsr r5, r5, #12 @ Align to start of page - lsl r5, r5, #12 - sub sp, r5, r0 @ here's our stack! + bl psci_get_cpu_id @ CPU ID => r0 + bl psci_get_cpu_stack_top @ stack top => r0 + mov sp, r0 bx r6 -text_end: + .globl psci_text_end +psci_text_end: .popsection -- cgit v1.1 From 3317b988b16b7499d2c28175d4bb77f6e04cf447 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 21 Apr 2015 07:18:30 +0200 Subject: ARM: Put target PC for PSCI CPU_ON on per-CPU stack Use a per-CPU variable for saving the target PC during CPU_ON operations. This allows us to run this service independently on targets that have more than 2 cores and also core-local power control. CC: Marc Zyngier Signed-off-by: Jan Kiszka Reviewed-by: Tom Rini Reviewed-by: Thierry Reding Tested-by: Thierry Reding Tested-by: Ian Campbell Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/psci.S | 11 +++++------ arch/arm/cpu/armv7/sunxi/psci.S | 9 ++++++--- 2 files changed, 11 insertions(+), 9 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 18d85c4..87c0c0b 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -17,6 +17,7 @@ #include #include +#include #include .pushsection ._secure.text, "ax" @@ -202,6 +203,7 @@ ENTRY(psci_get_cpu_stack_top) add r5, r5, #0x2000 @ Skip two pages lsr r5, r5, #12 @ Align to start of page lsl r5, r5, #12 + sub r5, r5, #4 @ reserve 1 word for target PC sub r0, r5, r0 @ here's our stack! bx lr @@ -212,13 +214,10 @@ ENTRY(psci_cpu_entry) bl _nonsec_init - adr r0, _psci_target_pc - ldr r0, [r0] + bl psci_get_cpu_id @ CPU ID => r0 + bl psci_get_cpu_stack_top @ stack top => r0 + ldr r0, [r0] @ target PC at stack top b _do_nonsec_entry ENDPROC(psci_cpu_entry) -.globl _psci_target_pc -_psci_target_pc: - .word 0 - .popsection diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index dd583b2..7ec0500 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -139,8 +139,11 @@ out: mcr p15, 0, r7, c1, c1, 0 @ r2 = target PC .globl psci_cpu_on psci_cpu_on: - ldr r0, =_psci_target_pc - str r2, [r0] + push {lr} + + mov r0, r1 + bl psci_get_cpu_stack_top @ get stack top of target CPU + str r2, [r0] @ store target PC at stack top dsb movw r0, #(SUN7I_CPUCFG_BASE & 0xffff) @@ -195,7 +198,7 @@ psci_cpu_on: str r6, [r0, #0x1e4] mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS - mov pc, lr + pop {pc} .globl psci_cpu_off psci_cpu_off: -- cgit v1.1 From d6b72da029ab85b344b98b28b12d7cbe800b6cc4 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 21 Apr 2015 07:18:32 +0200 Subject: virt-dt: Allow reservation of secure region when in a RAM carveout In this case the secure code lives in RAM, and hence the memory node in the device tree needs to be adjusted. This avoids that the OS will map and possibly access the reservation. Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out such a region. We only support cutting off memory from the beginning or the end of a RAM bank as we do not want to increase their number (which would happen if punching a hole) for simplicity reasons This will be used in a subsequent patch for Jetson-TK1. Signed-off-by: Jan Kiszka Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/virt-dt.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c index caaaaab..32c368f 100644 --- a/arch/arm/cpu/armv7/virt-dt.c +++ b/arch/arm/cpu/armv7/virt-dt.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -88,6 +89,34 @@ static int fdt_psci(void *fdt) return 0; } +int armv7_apply_memory_carveout(u64 *start, u64 *size) +{ +#ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE + if (*start + *size < CONFIG_ARMV7_SECURE_BASE || + *start >= (u64)CONFIG_ARMV7_SECURE_BASE + + CONFIG_ARMV7_SECURE_RESERVE_SIZE) + return 0; + + /* carveout must be at the beginning or the end of the bank */ + if (*start == CONFIG_ARMV7_SECURE_BASE || + *start + *size == (u64)CONFIG_ARMV7_SECURE_BASE + + CONFIG_ARMV7_SECURE_RESERVE_SIZE) { + if (*size < CONFIG_ARMV7_SECURE_RESERVE_SIZE) { + debug("Secure monitor larger than RAM bank!?\n"); + return -EINVAL; + } + *size -= CONFIG_ARMV7_SECURE_RESERVE_SIZE; + if (*start == CONFIG_ARMV7_SECURE_BASE) + *start += CONFIG_ARMV7_SECURE_RESERVE_SIZE; + return 0; + } + debug("Secure monitor not located at beginning or end of RAM bank\n"); + return -EINVAL; +#else /* !CONFIG_ARMV7_SECURE_RESERVE_SIZE */ + return 0; +#endif +} + int psci_update_dt(void *fdt) { #ifdef CONFIG_ARMV7_NONSEC -- cgit v1.1 From ce416fac3802528702e46663882d67cb8561b4c8 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 21 Apr 2015 07:18:34 +0200 Subject: ARM: Add board-specific initialization hook for PSCI Tegra boards will have to initialize power management for the PSCI support this way. Signed-off-by: Jan Kiszka Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/virt-v7.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 4cb8806..db4f6ad 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -75,6 +75,10 @@ void __weak smp_kick_all_cpus(void) kick_secondary_cpus_gic(gic_dist_addr); } +__weak void psci_board_init(void) +{ +} + int armv7_init_nonsec(void) { unsigned int reg; @@ -112,6 +116,8 @@ int armv7_init_nonsec(void) for (i = 1; i <= itlinesnr; i++) writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); + psci_board_init(); + /* * Relocate secure section before any cpu runs in secure ram. * smp_kick_all_cpus may enable other cores and runs into secure -- cgit v1.1 From 73169874a2867cb8ee5ec79eb9f2b176d3af34b2 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Tue, 21 Apr 2015 07:18:36 +0200 Subject: tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka Reviewed-by: Tom Rini Reviewed-by: Thierry Reding Tested-by: Thierry Reding Tested-by: Ian Campbell Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/virt-v7.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index db4f6ad..9c53306 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -46,6 +46,10 @@ static unsigned long get_gicd_base_address(void) #endif } +/* Define a specific version of this function to enable any available + * hardware protections for the reserved region */ +void __weak protect_secure_section(void) {} + static void relocate_secure_section(void) { #ifdef CONFIG_ARMV7_SECURE_BASE @@ -54,6 +58,7 @@ static void relocate_secure_section(void) memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz); flush_dcache_range(CONFIG_ARMV7_SECURE_BASE, CONFIG_ARMV7_SECURE_BASE + sz + 1); + protect_secure_section(); invalidate_icache_all(); #endif } -- cgit v1.1 From a8f2d01967d1e5304435024927a147abb7ad0f1e Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 21 Apr 2015 07:18:39 +0200 Subject: tegra: Boot in non-secure mode by default Upstream Linux is broken with default configs when PSCI, thus non-secure mode is enabled. So the user should explicitly enable this mode, e.g. when she disabled CONFIG_CPU_IDLE in Linux (in which case it's safe to use). We can revert this workaround once Linux got fixed. Signed-off-by: Jan Kiszka Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index 61e7c82..6c5d5dd 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -16,7 +16,7 @@ config ARMV7_NONSEC config ARMV7_BOOT_SEC_DEFAULT boolean "Boot in secure mode by default" if EXPERT depends on ARMV7_NONSEC - default n + default y if TEGRA ---help--- Say Y here to boot in secure mode by default even if non-secure mode is supported. This option is useful to boot kernels which do not -- cgit v1.1