From 6995a2893718a54cbd255ea3dd9b6d7306e30cf2 Mon Sep 17 00:00:00 2001 From: "Satyanarayana, Sandhya" Date: Thu, 9 Aug 2012 18:29:57 +0000 Subject: am33xx evm: Update secure_emif_sdram_config during ddr init This patch updates secure_emif_sdram_config with the same value written to sdram_config during ddr3 initialization. During suspend/resume, this value is copied into sdram_config. With this, a write to sdram_config at the end of resume sequence which triggers an init sequence can be avoided. Without this register write in place, the DDR_RESET line goes low for a few cycles during resume which is a violation of the JEDEC spec. Signed-off-by: Satyanarayana, Sandhya --- arch/arm/cpu/armv7/am33xx/ddr.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index cffd4ab..fd9fc4a 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -17,6 +17,7 @@ http://www.ti.com/ #include #include +#include #include #include @@ -46,8 +47,10 @@ void config_sdram(const struct emif_regs *regs) { writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); - if (regs->zq_config) + if (regs->zq_config){ writel(regs->zq_config, &emif_reg->emif_zq_config); + writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + } writel(regs->sdram_config, &emif_reg->emif_sdram_config); } -- cgit v1.1