From 3f0eb9faac520e2f3e50214df34ef9d6c25e011a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 6 May 2015 16:44:04 +0800 Subject: MLK-10829-1 imx:mx6sx correct i2c and video clock settings Change MXC_CCM_CCGR6_I2C4_xx to MXC_CCM_CCGR6_I2C4_SERIAL_xx Remove duplicated mxs_set_vadcclk Correct enable_pll_video usage Signed-off-by: Peng Fan --- arch/arm/cpu/armv7/mx6/clock.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index bac45e0..1ef307a 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -598,16 +598,6 @@ void enable_lcdif_clock(uint32_t base_addr) reg |= (MXC_CCM_CCGR2_LCD_MASK); writel(reg, &imx_ccm->CCGR2); } - -void mxs_set_vadcclk(void) -{ - u32 reg = 0; - - reg = readl(&imx_ccm->cscmr2); - reg &= ~MXC_CCM_CSCMR2_VID_CLK_SEL_MASK; - reg |= 0x19 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET; - writel(reg, &imx_ccm->cscmr2); -} #endif #ifdef CONFIG_MX6UL @@ -776,7 +766,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) } #ifdef CONFIG_MX6SX else { - if (enable_pll_video(pll_div, pll_num, pll_denom)) + if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) return; /* Select pre-lcd clock to PLL5 */ -- cgit v1.1