From 20187fd11c37226fac8661bbac96ddd4fdf507b1 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 16 Jul 2014 00:59:24 +0300 Subject: ARM: keystone2: add MSMC cache coherency support for K2E SOC This patch adds Keystone2 K2E SOC specific code to support MSMC cache coherency. Also create header file for msmc to hold its API. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/init.c | 12 +++++++----- arch/arm/cpu/armv7/keystone/msmc.c | 4 ++-- 2 files changed, 9 insertions(+), 7 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index f4c293a..a8f8aee 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -24,11 +25,12 @@ int arch_cpu_init(void) chip_configuration_unlock(); icache_enable(); -#ifdef CONFIG_SOC_K2HK - share_all_segments(8); - share_all_segments(9); - share_all_segments(10); /* QM PDSP */ - share_all_segments(11); /* PCIE */ + msmc_share_all_segments(8); /* TETRIS */ + msmc_share_all_segments(9); /* NETCP */ + msmc_share_all_segments(10); /* QM PDSP */ + msmc_share_all_segments(11); /* PCIE 0 */ +#ifdef CONFIG_SOC_K2E + msmc_share_all_segments(13); /* PCIE 1 */ #endif /* diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c index af858fa..7d8e597 100644 --- a/arch/arm/cpu/armv7/keystone/msmc.c +++ b/arch/arm/cpu/armv7/keystone/msmc.c @@ -8,7 +8,7 @@ */ #include -#include +#include struct mpax { u32 mpaxl; @@ -56,7 +56,7 @@ struct msms_regs { }; -void share_all_segments(int priv_id) +void msmc_share_all_segments(int priv_id) { struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE; int j; -- cgit v1.1