From e23bb6a438074e002801b43f43e9e22904530c53 Mon Sep 17 00:00:00 2001
From: Tom Warren <twarren.nvidia@gmail.com>
Date: Mon, 28 Jan 2013 13:32:10 +0000
Subject: Tegra114: Add common CPU (shared) files

These files are used by both SPL and main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/cpu/tegra-common/ap.c    |  9 ++++++++-
 arch/arm/cpu/tegra-common/board.c | 21 ++++++++++++++++++---
 2 files changed, 26 insertions(+), 4 deletions(-)

(limited to 'arch/arm/cpu/tegra-common')

diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index aebe29e..236cda8 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -31,6 +31,7 @@
 #include <asm/arch-tegra/fuse.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/scu.h>
+#include <asm/arch-tegra/tegra.h>
 #include <asm/arch-tegra/warmboot.h>
 
 int tegra_get_chip_type(void)
@@ -42,7 +43,7 @@ int tegra_get_chip_type(void)
 	/*
 	 * This is undocumented, Chip ID is bits 15:8 of the register
 	 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
-	 * Tegra30
+	 * Tegra30, and 0x35 for T114.
 	 */
 	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
@@ -68,6 +69,12 @@ int tegra_get_chip_type(void)
 			return TEGRA_SOC_T30;
 		}
 		break;
+	case CHIPID_TEGRA114:
+		switch (tegra_sku_id) {
+		case SKU_ID_T114_ENG:
+			return TEGRA_SOC_T114;
+		}
+		break;
 	}
 	/* unknown sku id */
 	return TEGRA_SOC_UNKNOWN;
diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c
index 15ac0c5..58ea628 100644
--- a/arch/arm/cpu/tegra-common/board.c
+++ b/arch/arm/cpu/tegra-common/board.c
@@ -37,8 +37,10 @@ enum {
 	/* UARTs which we can enable */
 	UARTA	= 1 << 0,
 	UARTB	= 1 << 1,
+	UARTC	= 1 << 2,
 	UARTD	= 1 << 3,
-	UART_COUNT = 4,
+	UARTE	= 1 << 4,
+	UART_COUNT = 5,
 };
 
 /*
@@ -68,7 +70,7 @@ unsigned int query_sdram_size(void)
 	case 3:
 		return 0x40000000;	/* 1GB */
 	}
-#else	/* Tegra30 */
+#else	/* Tegra30/Tegra114 */
 	/* bits 31:28 in OdmData are used for RAM size on T30  */
 	switch ((reg) >> 28) {
 	case 0:
@@ -117,12 +119,18 @@ static int uart_configs[] = {
 	-1,
 	FUNCMUX_UART4_GMC,
 	-1,
-#else	/* Tegra30 */
+#elif defined(CONFIG_TEGRA30)
 	FUNCMUX_UART1_ULPI,	/* UARTA */
 	-1,
 	-1,
 	-1,
 	-1,
+#else	/* Tegra114 */
+	-1,
+	-1,
+	-1,
+	FUNCMUX_UART4_GMI,	/* UARTD */
+	-1,
 #endif
 };
 
@@ -138,6 +146,7 @@ static void setup_uarts(int uart_ids)
 		PERIPH_ID_UART2,
 		PERIPH_ID_UART3,
 		PERIPH_ID_UART4,
+		PERIPH_ID_UART5,
 	};
 	size_t i;
 
@@ -161,9 +170,15 @@ void board_init_uart_f(void)
 #ifdef CONFIG_TEGRA_ENABLE_UARTB
 	uart_ids |= UARTB;
 #endif
+#ifdef CONFIG_TEGRA_ENABLE_UARTC
+	uart_ids |= UARTC;
+#endif
 #ifdef CONFIG_TEGRA_ENABLE_UARTD
 	uart_ids |= UARTD;
 #endif
+#ifdef CONFIG_TEGRA_ENABLE_UARTE
+	uart_ids |= UARTE;
+#endif
 	setup_uarts(uart_ids);
 }
 
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