From 9d4b7d0bc83992277d4baad16bdc19624f28c51c Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 9 Nov 2014 12:24:55 +0100 Subject: sun4i: Rename dram_clk_cfg to dram_clk_gate The data sheet just calls it DRAM_CLK_REG, and on sun6i we've both a dram_clk_cfg and dram_clk_gate, and the sun4i reg matches dram_clk_gate on sun6i, so name it the same on sun4i. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/cpu/armv7/sunxi/dram_sun4i.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c index dc9fdb9..ec8aaa7 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c @@ -428,9 +428,9 @@ static void dramc_clock_output_en(u32 on) #ifdef CONFIG_MACH_SUN4I struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; if (on) - setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); + setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); else - clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); + clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); #endif } -- cgit v1.1 From 0bd51251331a341dae8c19ae2e36a3262ae2ef72 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 8 Nov 2014 14:07:27 +0100 Subject: sunxi: Add video pll clock functions This is a preparation patch for adding support for HDMI out. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 27 +++++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index a0e49d1..49f4032 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -180,6 +180,21 @@ void clock_set_pll1(unsigned int hz) } #endif +void clock_set_pll3(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (clk == 0) { + clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); + return; + } + + /* PLL3 rate = 3000000 * m */ + writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | + CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg); +} + unsigned int clock_get_pll5p(void) { struct sunxi_ccm_reg *const ccm = @@ -200,3 +215,15 @@ unsigned int clock_get_pll6(void) int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; return 24000000 * n * k / 2; } + +void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) +{ + int pll = clock_get_pll5p(); + int div = 1; + + while ((pll / div) > hz) + div++; + + writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P | + CCM_DE_CTRL_M(div), clk_cfg); +} diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 16ab6f3..8e949c6 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -127,6 +127,23 @@ void clock_set_pll1(unsigned int clk) } #endif +void clock_set_pll3(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ + + if (clk == 0) { + clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); + return; + } + + /* PLL3 rate = 24000000 * n / m */ + writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | + CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m), + &ccm->pll3_cfg); +} + void clock_set_pll5(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -151,3 +168,15 @@ unsigned int clock_get_pll6(void) int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; return 24000000 * n * k / 2; } + +void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) +{ + int pll = clock_get_pll6() * 2; + int div = 1; + + while ((pll / div) > hz) + div++; + + writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div), + clk_cfg); +} -- cgit v1.1 From 7b02d9c943b9a8d1a61a330b76e205fc468ac1ac Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 15 Nov 2014 23:19:42 +0100 Subject: sun6i: Drop some "unknown magic" from dram init Allwinner tells us that this bit of code is the rtc ram being used to detect coming out of "super-standby" mode, and if that is the case, going out of self-refresh mode. Since we do not support "super-standby" mode, this can be dropped. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/cpu/armv7/sunxi/dram_sun6i.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c index 10a6241..699173c 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c @@ -142,9 +142,6 @@ static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para) writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST, &mctl_phy->ptr0); - /* Unknown magic performed by boot0 */ - if ((readl(SUNXI_RTC_BASE + 0x20c) & 3) == 2) - setbits_le32(&mctl_phy->ptr0, 1 << 18); writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1); writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2); -- cgit v1.1