From ab09e728667563fda9c8a8569331618fcfa0cb16 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Wed, 2 Sep 2015 13:54:14 -0500 Subject: arm: imx: common rework cache settings for imx6 Rework cache settings for imx6, move cache configuration to imx-common/cache.c so it can be reused for newer SoC Signed-off-by: Adrian Alonso --- arch/arm/cpu/armv7/mx6/soc.c | 95 -------------------------------------------- 1 file changed, 95 deletions(-) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 5110112..2f7d5c8 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -8,9 +8,6 @@ */ #include -#include -#include -#include #include #include #include @@ -440,31 +437,6 @@ int board_postclk_init(void) return 0; } -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - enum dcache_option option = DCACHE_WRITETHROUGH; -#else - enum dcache_option option = DCACHE_WRITEBACK; -#endif - - /* Avoid random hang when download by usb */ - invalidate_dcache_all(); - - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); - - /* Enable caching on OCRAM and ROM */ - mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR, - ROMCP_ARB_END_ADDR, - option); - mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, - IRAM_SIZE, - option); -} -#endif - #if defined(CONFIG_FEC_MXC) void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { @@ -605,70 +577,3 @@ void imx_setup_hdmi(void) writel(reg, &mxc_ccm->chsccdr); } #endif - -#ifndef CONFIG_SYS_L2CACHE_OFF -#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 -void v7_outer_cache_enable(void) -{ - struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; - unsigned int val; - - - /* - * Set bit 22 in the auxiliary control register. If this bit - * is cleared, PL310 treats Normal Shared Non-cacheable - * accesses as Cacheable no-allocate. - */ - setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); - -#if defined CONFIG_MX6SL - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - val = readl(&iomux->gpr[11]); - if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { - /* L2 cache configured as OCRAM, reset it */ - val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; - writel(val, &iomux->gpr[11]); - } -#endif - - /* Must disable the L2 before changing the latency parameters */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - - writel(0x132, &pl310->pl310_tag_latency_ctrl); - writel(0x132, &pl310->pl310_data_latency_ctrl); - - val = readl(&pl310->pl310_prefetch_ctrl); - - /* Turn on the L2 I/D prefetch */ - val |= 0x30000000; - - /* - * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 - * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 - * But according to ARM PL310 errata: 752271 - * ID: 752271: Double linefill feature can cause data corruption - * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 - * Workaround: The only workaround to this erratum is to disable the - * double linefill feature. This is the default behavior. - */ - -#ifndef CONFIG_MX6Q - val |= 0x40800000; -#endif - writel(val, &pl310->pl310_prefetch_ctrl); - - val = readl(&pl310->pl310_power_ctrl); - val |= L2X0_DYNAMIC_CLK_GATING_EN; - val |= L2X0_STNDBY_MODE_EN; - writel(val, &pl310->pl310_power_ctrl); - - setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); -} - -void v7_outer_cache_disable(void) -{ - struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; - - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); -} -#endif /* !CONFIG_SYS_L2CACHE_OFF */ -- cgit v1.1