From 1a43dc11a33de29712e5c5a0877d21bd6f6550c1 Mon Sep 17 00:00:00 2001 From: Soeren Moch Date: Thu, 4 Feb 2016 14:41:15 +0100 Subject: imx: mx6: Implement mmc_get_env_part commit 216d286c7e3d3d83d4d8ccaf0415192e1b1040c0 [imx: mx6: implement mmc_get_env_dev] introduced selection of the environment device according to the boot device when booting from SD/MMC. Extend this functionality for also selecting the device partition. Signed-off-by: Soeren Moch --- arch/arm/cpu/armv7/mx6/soc.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 8aeeaec..db6eabf 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -21,6 +21,7 @@ #include #include #include +#include enum ldo_reg { LDO_ARM, @@ -355,7 +356,7 @@ __weak int board_mmc_get_env_dev(int devno) return CONFIG_SYS_MMC_ENV_DEV; } -int mmc_get_env_dev(void) +static int mmc_get_boot_dev(void) { struct src *src_regs = (struct src *)SRC_BASE_ADDR; u32 soc_sbmr = readl(&src_regs->sbmr1); @@ -370,15 +371,44 @@ int mmc_get_env_dev(void) */ bootsel = (soc_sbmr & 0x000000FF) >> 6; - /* If not boot from sd/mmc, use default value */ + /* No boot from sd/mmc */ if (bootsel != 1) - return CONFIG_SYS_MMC_ENV_DEV; + return -1; /* BOOT_CFG2[3] and BOOT_CFG2[4] */ devno = (soc_sbmr & 0x00001800) >> 11; + return devno; +} + +int mmc_get_env_dev(void) +{ + int devno = mmc_get_boot_dev(); + + /* If not boot from sd/mmc, use default value */ + if (devno < 0) + return CONFIG_SYS_MMC_ENV_DEV; + return board_mmc_get_env_dev(devno); } + +#ifdef CONFIG_SYS_MMC_ENV_PART +__weak int board_mmc_get_env_part(int devno) +{ + return CONFIG_SYS_MMC_ENV_PART; +} + +uint mmc_get_env_part(struct mmc *mmc) +{ + int devno = mmc_get_boot_dev(); + + /* If not boot from sd/mmc, use default value */ + if (devno < 0) + return CONFIG_SYS_MMC_ENV_PART; + + return board_mmc_get_env_part(devno); +} +#endif #endif int board_postclk_init(void) -- cgit v1.1 From 677656bdb51afcde5c1293d28a794d189c914bd7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 Jan 2016 16:55:03 +0800 Subject: imx: mx7d: clock support for RDC If CONFIG_IMX_RDC is enabled, enable clock for RDC and SEMAPHORE. Signed-off-by: Peng Fan --- arch/arm/cpu/armv7/mx7/clock.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/mx7/clock.c b/arch/arm/cpu/armv7/mx7/clock.c index 77db6e8..4d68ad2 100644 --- a/arch/arm/cpu/armv7/mx7/clock.c +++ b/arch/arm/cpu/armv7/mx7/clock.c @@ -1067,6 +1067,12 @@ void clock_init(void) #ifdef CONFIG_NAND_MXS clock_enable(CCGR_RAWNAND, 1); #endif + + if (IS_ENABLED(CONFIG_IMX_RDC)) { + clock_enable(CCGR_RDC, 1); + clock_enable(CCGR_SEMA1, 1); + clock_enable(CCGR_SEMA2, 1); + } } #ifdef CONFIG_SECURE_BOOT -- cgit v1.1 From 0623d375cfa9593260c0e6bfe404b38d3d5c7c7c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 Jan 2016 16:55:05 +0800 Subject: imx: mx6: implement functions to boot auxiliary core Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li Signed-off-by: Peng Fan --- arch/arm/cpu/armv7/mx6/soc.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index db6eabf..a34675c 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -567,3 +567,41 @@ void imx_setup_hdmi(void) writel(reg, &mxc_ccm->chsccdr); } #endif + +#ifdef CONFIG_IMX_BOOTAUX +int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) +{ + struct src *src_reg; + u32 stack, pc; + + if (!boot_private_data) + return -EINVAL; + + stack = *(u32 *)boot_private_data; + pc = *(u32 *)(boot_private_data + 4); + + /* Set the stack and pc to M4 bootROM */ + writel(stack, M4_BOOTROM_BASE_ADDR); + writel(pc, M4_BOOTROM_BASE_ADDR + 4); + + /* Enable M4 */ + src_reg = (struct src *)SRC_BASE_ADDR; + clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK, + SRC_SCR_M4_ENABLE_MASK); + + return 0; +} + +int arch_auxiliary_core_check_up(u32 core_id) +{ + struct src *src_reg = (struct src *)SRC_BASE_ADDR; + unsigned val; + + val = readl(&src_reg->scr); + + if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK) + return 0; /* assert in reset */ + + return 1; +} +#endif -- cgit v1.1 From 83703a1ccf2fda45503e161aad7231c82e411034 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 Jan 2016 16:55:07 +0800 Subject: imx: mx7: implement functions to boot auxiliary core Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li Signed-off-by: Peng Fan --- arch/arm/cpu/armv7/mx7/soc.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index a6ab551..d934b8b 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -211,6 +211,42 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif +#ifdef CONFIG_IMX_BOOTAUX +int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) +{ + u32 stack, pc; + struct src *src_reg = (struct src *)SRC_BASE_ADDR; + + if (!boot_private_data) + return 1; + + stack = *(u32 *)boot_private_data; + pc = *(u32 *)(boot_private_data + 4); + + /* Set the stack and pc to M4 bootROM */ + writel(stack, M4_BOOTROM_BASE_ADDR); + writel(pc, M4_BOOTROM_BASE_ADDR + 4); + + /* Enable M4 */ + clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK, + SRC_M4RCR_ENABLE_M4_MASK); + + return 0; +} + +int arch_auxiliary_core_check_up(u32 core_id) +{ + uint32_t val; + struct src *src_reg = (struct src *)SRC_BASE_ADDR; + + val = readl(&src_reg->m4rcr); + if (val & 0x00000001) + return 0; /* assert in reset */ + + return 1; +} +#endif + void set_wdog_reset(struct wdog_regs *wdog) { u32 reg = readw(&wdog->wcr); -- cgit v1.1 From 35c4ce5e20d3d10d1089ba336a248896faed284c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 Jan 2016 16:55:09 +0800 Subject: imx: mx7d: isolate resources to domain 0 for A7 core In current design, if any peripheral was assigned to both A7 and M4, it will receive ipg_stop or ipg_wait when any of the 2 platforms enter low power mode. We will have a risk that, if A7 enter wait, M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait asserted same time. Also if M4 enters stop mode, A7 will have no chance to access the peripheral. There are 26 peripherals affected by this IC issue: SIM2(sim2/emvsim2) SIM1(sim1/emvsim1) UART1/UART2/UART3/UART4/UART5/UART6/UART7 SAI1/SAI2/SAI3 WDOG1/WDOG2/WDOG3/WDOG4 GPT1/GPT2/GPT3/GPT4 PWM1/PWM2/PWM3/PWM4 ENET1/ENET2 Software Workaround: The solution is to set the peripherals to Domain0 by A core, since A core in Domain0. The peripherals which will be used by M4, will be set to Domain1 by M4. For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will set WDOG4 to domain1, because M4 will use WDOG4. So the peripherals are not shared by them. This way requires the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only. M4 image will set the M4 to domain 1 and set peripheral which it will use to domain 1. This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for i.MX7D SABRESD board, and setup the 26 IP resources to domain 0. Signed-off-by: Ye.Li Signed-off-by: Peng Fan --- arch/arm/cpu/armv7/mx7/soc.c | 64 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index d934b8b..ba6cfb9 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include #include @@ -29,6 +31,65 @@ U_BOOT_DEVICE(imx7_thermal) = { }; #endif +#ifdef CONFIG_IMX_RDC +/* + * In current design, if any peripheral was assigned to both A7 and M4, + * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter + * low power mode. So M4 sleep will cause some peripherals fail to work + * at A7 core side. At default, all resources are in domain 0 - 3. + * + * There are 26 peripherals impacted by this IC issue: + * SIM2(sim2/emvsim2) + * SIM1(sim1/emvsim1) + * UART1/UART2/UART3/UART4/UART5/UART6/UART7 + * SAI1/SAI2/SAI3 + * WDOG1/WDOG2/WDOG3/WDOG4 + * GPT1/GPT2/GPT3/GPT4 + * PWM1/PWM2/PWM3/PWM4 + * ENET1/ENET2 + * Software Workaround: + * Here we setup some resources to domain 0 where M4 codes will move + * the M4 out of this domain. Then M4 is not able to access them any longer. + * This is a workaround for ic issue. So the peripherals are not shared + * by them. This way requires the uboot implemented the RDC driver and + * set the 26 IPs above to domain 0 only. M4 code will assign resource + * to its own domain, if it want to use the resource. + */ +static rdc_peri_cfg_t const resources[] = { + (RDC_PER_SIM1 | RDC_DOMAIN(0)), + (RDC_PER_SIM2 | RDC_DOMAIN(0)), + (RDC_PER_UART1 | RDC_DOMAIN(0)), + (RDC_PER_UART2 | RDC_DOMAIN(0)), + (RDC_PER_UART3 | RDC_DOMAIN(0)), + (RDC_PER_UART4 | RDC_DOMAIN(0)), + (RDC_PER_UART5 | RDC_DOMAIN(0)), + (RDC_PER_UART6 | RDC_DOMAIN(0)), + (RDC_PER_UART7 | RDC_DOMAIN(0)), + (RDC_PER_SAI1 | RDC_DOMAIN(0)), + (RDC_PER_SAI2 | RDC_DOMAIN(0)), + (RDC_PER_SAI3 | RDC_DOMAIN(0)), + (RDC_PER_WDOG1 | RDC_DOMAIN(0)), + (RDC_PER_WDOG2 | RDC_DOMAIN(0)), + (RDC_PER_WDOG3 | RDC_DOMAIN(0)), + (RDC_PER_WDOG4 | RDC_DOMAIN(0)), + (RDC_PER_GPT1 | RDC_DOMAIN(0)), + (RDC_PER_GPT2 | RDC_DOMAIN(0)), + (RDC_PER_GPT3 | RDC_DOMAIN(0)), + (RDC_PER_GPT4 | RDC_DOMAIN(0)), + (RDC_PER_PWM1 | RDC_DOMAIN(0)), + (RDC_PER_PWM2 | RDC_DOMAIN(0)), + (RDC_PER_PWM3 | RDC_DOMAIN(0)), + (RDC_PER_PWM4 | RDC_DOMAIN(0)), + (RDC_PER_ENET1 | RDC_DOMAIN(0)), + (RDC_PER_ENET2 | RDC_DOMAIN(0)), +}; + +static void isolate_resource(void) +{ + imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources)); +} +#endif + #if defined(CONFIG_SECURE_BOOT) struct imx_sec_config_fuse_t const imx_sec_config_fuse = { .bank = 1, @@ -163,6 +224,9 @@ int arch_cpu_init(void) mxs_dma_init(); #endif + if (IS_ENABLED(CONFIG_IMX_RDC)) + isolate_resource(); + return 0; } -- cgit v1.1