From 4425e6285679a22522638bd4bb5281611635a30e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: clock: Drop nonsense inlining from clock manager code The inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Scrub this hint. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Dinh Nguyen Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/clock_manager.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index 158501a..d032bbd 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -30,7 +30,7 @@ static const struct socfpga_clock_manager *clock_manager_base = CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) -static inline void cm_wait_for_lock(uint32_t mask) +static void cm_wait_for_lock(uint32_t mask) { register uint32_t inter_val; do { @@ -39,7 +39,7 @@ static inline void cm_wait_for_lock(uint32_t mask) } /* function to poll in the fsm busy bit */ -static inline void cm_wait_for_fsm(void) +static void cm_wait_for_fsm(void) { while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY) ; @@ -49,22 +49,22 @@ static inline void cm_wait_for_fsm(void) * function to write the bypass register which requires a poll of the * busy bit */ -static inline void cm_write_bypass(uint32_t val) +static void cm_write_bypass(uint32_t val) { writel(val, &clock_manager_base->bypass); cm_wait_for_fsm(); } /* function to write the ctrl register which requires a poll of the busy bit */ -static inline void cm_write_ctrl(uint32_t val) +static void cm_write_ctrl(uint32_t val) { writel(val, &clock_manager_base->ctrl); cm_wait_for_fsm(); } /* function to write a clock register that has phase information */ -static inline void cm_write_with_phase(uint32_t value, - uint32_t reg_address, uint32_t mask) +static void cm_write_with_phase(uint32_t value, + uint32_t reg_address, uint32_t mask) { /* poll until phase is zero */ while (readl(reg_address) & mask) -- cgit v1.1