From 89a7c773eabf4a3f2c23c2df95501723fef5e5a7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 13 Jan 2015 18:54:34 +0900 Subject: ARM: UniPhier: fix comments in SoC Glue init function Signed-off-by: Masahiro Yamada --- arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c') diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c index b4dd799..2cc5df6 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c @@ -21,7 +21,7 @@ void sg_init(void) #endif writel(tmp, SG_MEMCONF); - /* Input ports must be enabled deasserting reset of cores */ + /* Input ports must be enabled before deasserting reset of cores */ tmp = readl(SG_IECTRL); tmp |= 0x1; writel(tmp, SG_IECTRL); -- cgit v1.1 From 448437496b7cb2b7a80d4b3ada9f225506379c5c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 19 Jan 2015 22:31:10 +0900 Subject: ARM: UniPhier: fix IECTRL set code for PH1-Pro4 For PH1-Pro4, the bit 6 of the IECTRL must be set. It is the only available bit in this register. There is no effect of the write access to the other bits. Signed-off-by: Masahiro Yamada --- arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c') diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c index 2cc5df6..b7c4b10 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c @@ -23,6 +23,6 @@ void sg_init(void) /* Input ports must be enabled before deasserting reset of cores */ tmp = readl(SG_IECTRL); - tmp |= 0x1; + tmp |= 1 << 6; writel(tmp, SG_IECTRL); } -- cgit v1.1