From 0812a1d3e5d056b012d6a9b4b2e83469440f7018 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:05 -0500 Subject: arm: socfpga: spl: enable sdram, timer and uart Add the calls in the spl_board_init to enable SDRAM, timer, and UART. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- arch/arm/cpu/armv7/socfpga/spl.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/cpu/armv7/socfpga/spl.c') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 6a8c15d..a4dbe4f 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -144,6 +144,10 @@ void spl_board_init(void) /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); + socfpga_sdram_enable(); + socfpga_uart0_enable(); + socfpga_osc1timer_enable(); + debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ cm_basic_init(&cm_default_cfg); -- cgit v1.1 From 9fd565dbe7eadc9736c496bc67f2a0414b50069f Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:06 -0500 Subject: arm: socfpga: spl: Add call to timer_init Signed-off-by: Dinh Nguyen --- arch/arm/cpu/armv7/socfpga/spl.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/cpu/armv7/socfpga/spl.c') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index a4dbe4f..95992f0 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -148,6 +148,8 @@ void spl_board_init(void) socfpga_uart0_enable(); socfpga_osc1timer_enable(); + timer_init(); + debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ cm_basic_init(&cm_default_cfg); -- cgit v1.1 From 08e463ee8a7a5641e191be2a8e934d8284d1ca55 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:07 -0500 Subject: arm: socfpga: spl: allow bootrom to enable IOs after warm reset Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- arch/arm/cpu/armv7/socfpga/spl.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/cpu/armv7/socfpga/spl.c') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 95992f0..787ad7f 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -154,6 +154,9 @@ void spl_board_init(void) /* reconfigure the PLLs */ cm_basic_init(&cm_default_cfg); + /* Enable bootrom to configure IOs. */ + sysmgr_enable_warmrstcfgio(); + /* configure the IOCSR / IO buffer settings */ if (scan_mgr_configure_iocsr()) hang(); -- cgit v1.1 From 37ef0c70d32c8115bbbb508680fcb65004849126 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:08 -0500 Subject: arm: socfpga: spl: add sdram init and calibration Add a call to checkboard along with sdram intilialization and calibration. Signed-off-by: Dinh Nguyen --- arch/arm/cpu/armv7/socfpga/spl.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/cpu/armv7/socfpga/spl.c') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 787ad7f..756c55a 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -15,6 +15,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -174,4 +175,16 @@ void spl_board_init(void) /* enable console uart printing */ preloader_console_init(); + + if (sdram_mmr_init_full(0xffffffff) != 0) { + puts("SDRAM init failed.\n"); + hang(); + } + + debug("SDRAM: Calibrating PHY\n"); + /* SDRAM calibration */ + if (sdram_calibration_full() == 0) { + puts("SDRAM calibration failed.\n"); + hang(); + } } -- cgit v1.1 From 89ba82479e7854c5cf42d01cccd1afa81332b717 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:09 -0500 Subject: arm: socfpga: spl: printout sdram size Signed-off-by: Dinh Nguyen Reviewed-by: Marek Vasut --- arch/arm/cpu/armv7/socfpga/spl.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/cpu/armv7/socfpga/spl.c') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 756c55a..e7b4d29 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -54,6 +54,7 @@ u32 spl_boot_device(void) */ void spl_board_init(void) { + unsigned long sdram_size; #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET cm_config_t cm_default_cfg = { /* main group */ @@ -187,4 +188,7 @@ void spl_board_init(void) puts("SDRAM calibration failed.\n"); hang(); } + + sdram_size = sdram_calculate_size(); + debug("SDRAM: %ld MiB\n", sdram_size >> 20); } -- cgit v1.1 From 9ad3a4ace27fc4bd345214e4cb3788710b428db0 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:15 -0500 Subject: arm: socfpga: spl: Add SDRAM check Signed-off-by: Dinh Nguyen --- arch/arm/cpu/armv7/socfpga/spl.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/cpu/armv7/socfpga/spl.c') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index e7b4d29..d7cedad 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -191,4 +191,10 @@ void spl_board_init(void) sdram_size = sdram_calculate_size(); debug("SDRAM: %ld MiB\n", sdram_size >> 20); + + /* Sanity check ensure correct SDRAM size specified */ + if (get_ram_size(0, sdram_size) != sdram_size) { + puts("SDRAM size check failed!\n"); + hang(); + } } -- cgit v1.1 From 0ef44d1150cfae5eb5eaea27db129547ac9f1ff7 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 15 Apr 2015 16:44:32 -0500 Subject: arm: socfpga: spl: add board_init_f to SPL Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f(). Signed-off-by: Dinh Nguyen Reviewed-by: Marek Vasut --- arch/arm/cpu/armv7/socfpga/spl.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm/cpu/armv7/socfpga/spl.c') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index d7cedad..f994658 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -19,6 +20,9 @@ DECLARE_GLOBAL_DATA_PTR; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + #define MAIN_VCO_BASE ( \ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \ @@ -44,6 +48,31 @@ DECLARE_GLOBAL_DATA_PTR; CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ ) +void board_init_f(ulong dummy) +{ + struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + unsigned long reg; + /* + * First C code to run. Clear fake OCRAM ECC first as SBE + * and DBE might triggered during power on + */ + reg = readl(&sysmgr_regs->eccgrp_ocram); + if (reg & SYSMGR_ECC_OCRAM_SERR) + writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, + &sysmgr_regs->eccgrp_ocram); + if (reg & SYSMGR_ECC_OCRAM_DERR) + writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, + &sysmgr_regs->eccgrp_ocram); + + memset(__bss_start, 0, __bss_end - __bss_start); + + /* Remap SDRAM to 0x0 */ + writel(0x1, &pl310->pl310_addr_filter_start); + + board_init_r(NULL, 0); +} + u32 spl_boot_device(void) { return BOOT_DEVICE_RAM; -- cgit v1.1