From 6213db78f4820816fc52c807dfab47bb3266c809 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 3 Jun 2015 14:43:21 +0530 Subject: ARM: DRA7: DDR3: Add support for HW leveling DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence. Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/omap5/sdram.c | 76 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 73 insertions(+), 3 deletions(-) (limited to 'arch/arm/cpu/armv7/omap5/sdram.c') diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 5f8daa1..2e23852 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -421,8 +421,14 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = { 0x0 }; +/* Ext phy ctrl 1-35 regs */ const u32 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { + 0x10040100, + 0x00910091, + 0x00950095, + 0x009B009B, + 0x009E009E, 0x00980098, 0x00340034, 0x00350035, @@ -441,7 +447,7 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { 0x00500050, 0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040, 0x0, 0x0, @@ -450,8 +456,14 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { 0x0 }; +/* Ext phy ctrl 1-35 regs */ const u32 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { + 0x10040100, + 0x00910091, + 0x00950095, + 0x009B009B, + 0x009E009E, 0x00980098, 0x00330033, 0x00330033, @@ -470,7 +482,7 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { 0x00500050, 0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040, 0x0, 0x0, @@ -479,8 +491,14 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { 0x0 }; +/* Ext phy ctrl 1-35 regs */ const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = { + 0x10040100, + 0x00A400A4, + 0x00A900A9, + 0x00B000B0, + 0x00B000B0, 0x00A400A4, 0x00390039, 0x00320032, @@ -562,7 +580,7 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) *regs = &mr_regs; } -void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs) { u32 *ext_phy_ctrl_base = 0; u32 *emif_ext_phy_ctrl_base = 0; @@ -601,6 +619,58 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) } } +static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 *emif_ext_phy_ctrl_base = 0; + u32 emif_nr; + const u32 *ext_phy_ctrl_const_regs; + u32 i, hw_leveling, size; + + emif_nr = (base == EMIF1_BASE) ? 1 : 2; + + hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT; + + emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1); + + emif_get_ext_phy_ctrl_const_regs(emif_nr, + &ext_phy_ctrl_const_regs, &size); + + writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]); + writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]); + + if (!hw_leveling) { + /* + * Copy the predefined PHY register values + * in case of sw leveling + */ + for (i = 1; i < 25; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + } else { + /* + * Write the init value for HW levling to occur + */ + for (i = 21; i < 35; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + } +} + +void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +{ + if (is_omap54xx()) + do_ext_phy_settings_omap5(base, regs); + else + do_ext_phy_settings_dra7(base, regs); +} + #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS static const struct lpddr2_ac_timings timings_jedec_532_mhz = { .max_freq = 532000000, -- cgit v1.1 From 920638fa5e781de91bb70fb516219c8cd4136407 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 3 Jun 2015 14:43:23 +0530 Subject: ARM: DRA7-evm: Enable HW leveling Updating EMIF registers to enable HW leveling on DRA7-evm. Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/omap5/sdram.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) (limited to 'arch/arm/cpu/armv7/omap5/sdram.c') diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 2e23852..942a80a 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -149,15 +149,15 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E24400A, - .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00910091, .emif_ddr_ext_phy_ctrl_3 = 0x00950095, .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -174,15 +174,15 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E24400A, - .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00910091, .emif_ddr_ext_phy_ctrl_3 = 0x00950095, .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -453,6 +453,11 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { 0x0, 0x0, 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0 }; @@ -488,6 +493,11 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { 0x0, 0x0, 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0 }; -- cgit v1.1 From f308b4fce5d0c8a9ebae1e369d4b188f9432f79c Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 3 Jun 2015 14:43:24 +0530 Subject: ARM: DRA72-evm: Enable HW leveling Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers. Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/omap5/sdram.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'arch/arm/cpu/armv7/omap5/sdram.c') diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 942a80a..3022b9e 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -191,15 +191,15 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { .sdram_config_init = 0x61862B32, .sdram_config = 0x61862B32, .sdram_config2 = 0x08000000, - .ref_ctrl = 0x0000493E, + .ref_ctrl = 0x0000514C, .ref_ctrl_final = 0x0000144A, .sdram_tim1 = 0xD113781C, - .sdram_tim2 = 0x308F7FE3, - .sdram_tim3 = 0x009F86A8, + .sdram_tim2 = 0x305A7FDA, + .sdram_tim3 = 0x409F86A8, .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190B, + .zq_config = 0x5007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E24400D, + .emif_ddr_phy_ctlr_1_init = 0x0024400D, .emif_ddr_phy_ctlr_1 = 0x0E24400D, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, @@ -207,7 +207,7 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -533,6 +533,11 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = { 0x0, 0x0, 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0 }; -- cgit v1.1 From ee4dc2590f00d0109bcdb282ad86fd3dce567e50 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 3 Jun 2015 16:57:47 +0530 Subject: ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register When DLL_CALIB_INTERVAL is set, an extra delay is added which is not required and it consumes EMIF bandwidth. So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0. Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap5/sdram.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/cpu/armv7/omap5/sdram.c') diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 3022b9e..cf4452d 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -146,7 +146,7 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400B, @@ -171,7 +171,7 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400B, -- cgit v1.1