From f75fba3a63f23ef980a98c4072f38d71fbd6fdba Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 25 Jun 2015 17:06:17 -0300 Subject: MLK-11201 mx7: clock: Fix PLL divider for the 100MHz case We should divide the 1000MHz ENET PLL clock by 10 in order to achieve 100MHz, so fix the divider accordingly. Signed-off-by: Fabio Estevam --- arch/arm/cpu/armv7/mx7/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv7/mx7/clock.c') diff --git a/arch/arm/cpu/armv7/mx7/clock.c b/arch/arm/cpu/armv7/mx7/clock.c index 39fdd75..0bfa2e3 100644 --- a/arch/arm/cpu/armv7/mx7/clock.c +++ b/arch/arm/cpu/armv7/mx7/clock.c @@ -315,7 +315,7 @@ static u32 mxc_get_pll_enet_derive(int derive) break; case PLL_ENET_MAIN_100M_CLK: if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK) - return freq / 16; + return freq / 10; break; case PLL_ENET_MAIN_50M_CLK: if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK) -- cgit v1.1