From 4632ad773ed31f4dd6aeb859de148402f8932111 Mon Sep 17 00:00:00 2001 From: tang yuantian Date: Fri, 16 Oct 2015 16:06:05 +0800 Subject: arm: ls1021a: Add sata support on qds and twr board Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 42 +++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c (limited to 'arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c') diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c new file mode 100644 index 0000000..deeb674 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c @@ -0,0 +1,42 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +/* port register default value */ +#define AHCI_PORT_PHY_1_CFG 0xa003fffe +#define AHCI_PORT_PHY_2_CFG 0x28183411 +#define AHCI_PORT_PHY_3_CFG 0x0e081004 +#define AHCI_PORT_PHY_4_CFG 0x00480811 +#define AHCI_PORT_PHY_5_CFG 0x192c96a4 +#define AHCI_PORT_TRANS_CFG 0x08000025 + +#define SATA_ECC_REG_ADDR 0x20220520 +#define SATA_ECC_DISABLE 0x00020000 + +int ls1021a_sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 + out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE); +#endif + + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); + out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG); + out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)AHCI_BASE_ADDR); + scsi_scan(0); + + return 0; +} -- cgit v1.1