From 7ea7f689cab5bf715255e22c31aeefb23259afe5 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 4 Jun 2013 11:00:57 +0200 Subject: arm, am33xx: move uart soft reset code to common place move uart soft reset code to common place and call this function from board code, instead of copy and paste this code for every board. Signed-off-by: Heiko Schocher Cc: Matt Porter Cc: Lars Poeschel Cc: Tom Rini Cc: Enric Balletbo i Serra Acked-by: Tom Rini [trini: Fix igep0033 build, remove 'regval' on pcm051] Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/board.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm/cpu/armv7/am33xx') diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index d3b3612..b935a29 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -166,4 +166,26 @@ void rtc32k_enable(void) /* Enable the RTC 32K OSC by setting bits 3 and 6. */ writel((1 << 3) | (1 << 6), &rtc->osc); } + +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +void uart_soft_reset(void) +{ + struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; + u32 regval; + + regval = readl(&uart_base->uartsyscfg); + regval |= UART_RESET; + writel(regval, &uart_base->uartsyscfg); + while ((readl(&uart_base->uartsyssts) & + UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) + ; + + /* Disable smart idle */ + regval = readl(&uart_base->uartsyscfg); + regval |= UART_SMART_IDLE_EN; + writel(regval, &uart_base->uartsyscfg); +} #endif -- cgit v1.1