From be0ecdbed5efc7833275701ebdb1ff8ef7ffd4c0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 Apr 2014 03:38:40 +0200 Subject: arm: mxs: Wait when disabling VDDMEM current limiter According to i.MX23 datasheet Table 32-17, we must wait for the supply to settle before disabling the current limiter. Indeed, not waiting a little here causes the system to crash at times. Signed-off-by: Marek Vasut Cc: Stefano Babic --- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/cpu/arm926ejs') diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 3baf4dd..de8841a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -240,9 +240,14 @@ static void mx23_mem_setup_vddmem(void) struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; + /* We must wait before and after disabling the current limiter! */ + early_delay(10000); + clrbits_le32(&power_regs->hw_power_vddmemctrl, POWER_VDDMEMCTRL_ENABLE_ILIMIT); + early_delay(10000); + } static void mx23_mem_init(void) -- cgit v1.1 From 7c604e98c2213619af6a8c3064418af9b689cf56 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 Apr 2014 03:38:41 +0200 Subject: arm: mxs: Wait for DRAM to start Instead of waiting for a fixed period of time and hoping for the best that the DRAM will start, read back an EMI status register which tells us exactly when the DRAM started. Signed-off-by: Marek Vasut Cc: Stefano Babic --- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu/arm926ejs') diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index de8841a..97ef67d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -274,7 +274,13 @@ static void mx23_mem_init(void) setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); - early_delay(20000); + + /* Wait for EMI_STAT bit DRAM_HALTED */ + for (;;) { + if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1))) + break; + early_delay(1000); + } /* Adjust EMI port priority. */ clrsetbits_le32(0x80020000, 0x1f << 16, 0x2); -- cgit v1.1