From 56df16f25ab81196669538c648ff466c24a43788 Mon Sep 17 00:00:00 2001 From: Robert Delien Date: Sun, 26 Feb 2012 12:15:07 +0000 Subject: Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registers This patch fixes erroneous 32-bit access to registers hw_clkctrl_frac0 and hw_clkctrl_frac1. Signed-off-by: Robert Delien Acked-by: Marek Vasut Tested-by: Marek Vasut --- arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) (limited to 'arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c') diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index 4af9eb7..0b1c109 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -96,22 +96,20 @@ void mx28_mem_init_clock(void) (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; /* Gate EMI clock */ - writel(CLKCTRL_FRAC0_CLKGATEEMI, - &clkctrl_regs->hw_clkctrl_frac0_set); + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); - /* EMI = 205MHz */ - writel(CLKCTRL_FRAC0_EMIFRAC_MASK, - &clkctrl_regs->hw_clkctrl_frac0_set); - writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) & - CLKCTRL_FRAC0_EMIFRAC_MASK, - &clkctrl_regs->hw_clkctrl_frac0_clr); + /* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */ + writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK), + &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); /* Ungate EMI clock */ - writel(CLKCTRL_FRAC0_CLKGATEEMI, - &clkctrl_regs->hw_clkctrl_frac0_clr); + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); early_delay(11000); + /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), &clkctrl_regs->hw_clkctrl_emi); @@ -128,10 +126,10 @@ void mx28_mem_setup_cpu_and_hbus(void) struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - /* CPU = 454MHz and ungate CPU clock */ - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0, - CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU, - 19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET); + /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz + * and ungate CPU clock */ + writeb(19 & CLKCTRL_FRAC_FRAC_MASK, + (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); /* Set CPU bypass */ writel(CLKCTRL_CLKSEQ_BYPASS_CPU, -- cgit v1.1