From 6eb15e50f48927c65a67371555b5afc24b3c7d21 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Mon, 30 Mar 2015 13:36:04 +0300 Subject: arc: add support for SLC (System Level Cache, AKA L2-cache) ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). This change adds functions required for controlling SLC: * slc_enable/disable * slc_flush/invalidate For now we just disable SLC to escape DMA coherency issues until either: * SLC flush/invalidate is supported in DMA APIin U-Boot * hardware DMA coherency is implemented (that might be board specific so probably we'll need to have a separate Kconfig option for controlling SLC explicitly) Signed-off-by: Alexey Brodkin --- arch/arc/include/asm/arcregs.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arc/include/asm/arcregs.h') diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 6a36a81..0e11dcc 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -46,6 +46,10 @@ #define ARC_AUX_DC_PTAG 0x5C #endif #define ARC_BCR_DC_BUILD 0x72 +#define ARC_BCR_SLC 0xce +#define ARC_AUX_SLC_CONTROL 0x903 +#define ARC_AUX_SLC_FLUSH 0x904 +#define ARC_AUX_SLC_INVALIDATE 0x905 #ifndef __ASSEMBLY__ /* Accessors for auxiliary registers */ -- cgit v1.1