From f94e50c82f14136d95afa54c5539bf00c764594d Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Thu, 27 Feb 2014 16:42:02 +0800 Subject: ENGR00301441 ENET:FEC Update fec_mxc driver for iMX6SX 1. iMX6SX enet rx have 64 bytes alignment limitation for DMA transfer. For i.MX6SX platform, need to add below define in config file: #define CONFIG_FEC_DMA_MINALIGN 64 2. FEC mdio clock source is ipg_clock_s, correct the clock source. Signed-off-by: Fugang Duan Signed-off-by: Ye.Li --- drivers/net/fec_mxc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 2f46482..5b0172b 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -141,7 +141,7 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. */ - writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, + writel((((mxc_get_clock(MXC_IPG_CLK) / 1000000) + 2) / 5) << 1, ð->mii_speed); debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); } @@ -296,12 +296,20 @@ static int fec_rbd_init(struct fec_priv *fec, int count, int dsize) * Allocate memory for the buffers. This allocation respects the * alignment */ +#if defined(CONFIG_FEC_DMA_MINALIGN) + size = roundup(dsize, CONFIG_FEC_DMA_MINALIGN); +#else size = roundup(dsize, ARCH_DMA_MINALIGN); +#endif for (i = 0; i < count; i++) { uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); if (data_ptr == 0) { +#if defined(CONFIG_FEC_DMA_MINALIGN) + uint8_t *data = memalign(CONFIG_FEC_DMA_MINALIGN, size); +#else uint8_t *data = memalign(ARCH_DMA_MINALIGN, size); +#endif if (!data) { printf("%s: error allocating rxbuf %d\n", __func__, i); -- cgit v1.1