From b8e5b072255c32b74118339c19f3ffba6a940a48 Mon Sep 17 00:00:00 2001 From: "Haijun.Zhang" Date: Mon, 1 Jul 2013 14:26:01 +0800 Subject: Powerpc: eSDHC: Fix mmc read write err in uboot of T4240QDS board Fill the right command type when using CMD12 to stop data transfer. Signed-off-by: Haijun Zhang CC: Fleming Andrew-AFLEMING CC: Scott Wood Signed-off-by: Andy Fleming --- drivers/mmc/fsl_esdhc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 973b19f..4e43e3e 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -100,7 +100,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) else if (cmd->resp_type & MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; -#ifdef CONFIG_MX53 +#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; #endif -- cgit v1.1 From ca6d4d0f8f0fb8ae09a7ba271177367bdfdf3136 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Mon, 15 Jul 2013 15:30:30 +0400 Subject: drivers/mmc/dw_mmc - remove extra arch specific "asm/arch/clk.h" inclusion 1. No contents of "asm/arch/clk.h" is used within "dw_mmc.c". 2. If arch doesn't have "asm/arch/clk.h" driver won't build. Without mentioned inclusion dw_mmc driver could be built for arches other than ARM. For ARM driver still builds without it. Signed-off-by: Alexey Brodkin Cc: Mischa Jonker Cc: Andy Fleming Cc: Rajeshwari Shinde Cc: Amar Cc: Minkyu Kang Cc: Jaehoon Chung Signed-off-by: Andy Fleming --- drivers/mmc/dw_mmc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 5da20ed..684a2a8 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #define PAGE_SIZE 4096 -- cgit v1.1 From a61da72bda80e09f36afbc9037a8c8b63b482de4 Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Mon, 15 Jul 2013 15:44:29 +0200 Subject: fsl_esdhc: Touch only relevant sys ctrl bits Dealing with the sys ctrl register should touch only the relevant bits and not accidently the whole register. On i.MX6, the sys control register contains bits which shouldn't be reset to 0, e.g. SYS_CTRL[3-0] and IPP_RST_N (SYS_CTRL[23]). Do this by read/modify/write instead of just a 32bit write. Signed-off-by: Dirk Behme Acked-by: Stefano Babic Signed-off-by: Andy Fleming --- drivers/mmc/fsl_esdhc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4e43e3e..eba1de3 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -470,7 +470,7 @@ static int esdhc_init(struct mmc *mmc) int timeout = 1000; /* Reset the entire host controller */ - esdhc_write32(®s->sysctl, SYSCTL_RSTA); + esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); /* Wait until the controller is available */ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) @@ -481,7 +481,7 @@ static int esdhc_init(struct mmc *mmc) esdhc_write32(®s->scr, 0x00000040); #endif - esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); + esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */ mmc_set_clock(mmc, 400000); @@ -515,7 +515,7 @@ static void esdhc_reset(struct fsl_esdhc *regs) unsigned long timeout = 100; /* wait max 100 ms */ /* reset the controller */ - esdhc_write32(®s->sysctl, SYSCTL_RSTA); + esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); /* hardware clears the bit when it is done */ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) -- cgit v1.1