From cd040a4953e55efe89dc3af4acf0302d5923026f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 18 Jun 2010 15:55:15 +0200 Subject: arch/arm/cpu/arm_cortexa8/omap3/cache.S: make build with older tools The push / pop instructions used in this file are available only with more recent tool chains: cache.S: Assembler messages: cache.S:133: Error: bad instruction `push {r0,r1,r2,lr}' cache.S:160: Error: bad instruction `pop {r1,r2,r3,pc}' cache.S:164: Error: bad instruction `push {r0,r1,r2,lr}' cache.S:191: Error: bad instruction `pop {r1,r2,r3,pc}' Change push/pop into stmfd/ldmfd instructions to support older versions of binutils as well. I verified that the modified source code generates exactly the same binary code. Signed-off-by: Wolfgang Denk Cc: Sandeep Paulraj Cc: Tom Rix --- arch/arm/cpu/arm_cortexa8/omap3/cache.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/arm_cortexa8/omap3/cache.S b/arch/arm/cpu/arm_cortexa8/omap3/cache.S index 0f63815..4b65ac5 100644 --- a/arch/arm/cpu/arm_cortexa8/omap3/cache.S +++ b/arch/arm/cpu/arm_cortexa8/omap3/cache.S @@ -130,7 +130,7 @@ finished_inval: l2_cache_enable: - push {r0, r1, r2, lr} + stmfd r13!, {r0, r1, r2, lr} @ ES2 onwards we can disable/enable L2 ourselves bl get_cpu_rev cmp r0, #CPU_3XX_ES20 @@ -157,11 +157,11 @@ l2_cache_enable_EARLIER_THAN_ES2: mov ip, r3 str r3, [sp, #4] l2_cache_enable_END: - pop {r1, r2, r3, pc} + ldmfd r13!, {r1, r2, r3, pc} l2_cache_disable: - push {r0, r1, r2, lr} + stmfd r13!, {r0, r1, r2, lr} @ ES2 onwards we can disable/enable L2 ourselves bl get_cpu_rev cmp r0, #CPU_3XX_ES20 @@ -188,4 +188,4 @@ l2_cache_disable_EARLIER_THAN_ES2: mov ip, r3 str r3, [sp, #4] l2_cache_disable_END: - pop {r1, r2, r3, pc} + ldmfd r13!, {r1, r2, r3, pc} -- cgit v1.1 From 9312bba01a41191f20821b66b84b3ff1d2902e8a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 20 Jun 2010 02:16:44 +0200 Subject: include/compiler.h: remove redundant declaration of errno Commit 37566090 "compiler.h: unify system ifdef cruft here" added both a "#include " and a "extern int errno;" to include/compiler.h which is causing build warnings for some systems, for example for the "netstar" board: In file included from /home/wd/git/u-boot/work/lib/crc32.c:15: include/compiler.h:28: warning: function declaration isn't a prototype The declaration of "errno" should be redundant, as is supposed to provide a correct declaration, so drop it. Signed-off-by: Wolfgang Denk Cc: Mike Frysinger --- include/compiler.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/compiler.h b/include/compiler.h index 8030bf6..23f4b83 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -25,8 +25,6 @@ #include #include -extern int errno; - #if !defined(__WIN32__) && !defined(__MINGW32__) # include #endif -- cgit v1.1 From 9c00b2f0a3fe0f779761607024f99b7690c9776c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 20 Jun 2010 12:30:22 +0200 Subject: net/eth.c: eth_mac_skip() is only needed when CONFIG_NET_MULTI is set Move it inside the #ifdef CONFIG_NET_MULTI to avoid eth.c:64: warning: 'eth_mac_skip' defined but not used messages from anumber of old, non-CONFIG_NET_MULTI boards. Signed-off-by: Wolfgang Denk Cc: Ben Warren --- net/eth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/eth.c b/net/eth.c index 45e4a26..83d559c 100644 --- a/net/eth.c +++ b/net/eth.c @@ -60,6 +60,8 @@ int eth_getenv_enetaddr_by_index(int index, uchar *enetaddr) return eth_getenv_enetaddr(enetvar, enetaddr); } +#ifdef CONFIG_NET_MULTI + static int eth_mac_skip(int index) { char enetvar[15]; @@ -68,8 +70,6 @@ static int eth_mac_skip(int index) return ((skip_state = getenv(enetvar)) != NULL); } -#ifdef CONFIG_NET_MULTI - /* * CPU and board-specific Ethernet initializations. Aliased function * signals caller to move on -- cgit v1.1 From e397e59e861aa818cda12a23206dde06f7e9f660 Mon Sep 17 00:00:00 2001 From: Fillod Stephane Date: Fri, 11 Jun 2010 19:26:43 +0200 Subject: ip/defrag: fix processing of last short fragment TFTP'ing a file of size 1747851 bytes with CONFIG_IP_DEFRAG and CONFIG_TFTP_BLOCKSIZE set to 4096 fails with a timeout, because the last fragment is not taken into account. This patch fixes IP fragments having less than 8 bytes of payload. Signed-off-by: Stephane Fillod Acked-by: Alessandro Rubini Signed-off-by: Ben Warren --- net/net.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/net.c b/net/net.c index cda7319..33fcd90 100644 --- a/net/net.c +++ b/net/net.c @@ -1201,7 +1201,8 @@ static IP_t *__NetDefragment(IP_t *ip, int *lenp) h = payload + h->next_hole; } - if (offset8 + (len / 8) <= h - payload) { + /* last fragment may be 1..7 bytes, the "+7" forces acceptance */ + if (offset8 + ((len + 7) / 8) <= h - payload) { /* no overlap with holes (dup fragment?) */ return NULL; } -- cgit v1.1 From 6de27bdc788e7c4532ee0721ae291aeb5df475dc Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 20 Jun 2010 12:32:37 +0200 Subject: net/eth.c: eth_mac_skip() is only needed when CONFIG_NET_MULTI is set Move it inside the #ifdef CONFIG_NET_MULTI to avoid eth.c:64: warning: 'eth_mac_skip' defined but not used messages from a number of old, non-CONFIG_NET_MULTI boards. Signed-off-by: Wolfgang Denk Signed-off-by: Ben Warren --- net/eth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/eth.c b/net/eth.c index 45e4a26..83d559c 100644 --- a/net/eth.c +++ b/net/eth.c @@ -60,6 +60,8 @@ int eth_getenv_enetaddr_by_index(int index, uchar *enetaddr) return eth_getenv_enetaddr(enetvar, enetaddr); } +#ifdef CONFIG_NET_MULTI + static int eth_mac_skip(int index) { char enetvar[15]; @@ -68,8 +70,6 @@ static int eth_mac_skip(int index) return ((skip_state = getenv(enetvar)) != NULL); } -#ifdef CONFIG_NET_MULTI - /* * CPU and board-specific Ethernet initializations. Aliased function * signals caller to move on -- cgit v1.1 From a71da1b6c96205549ca2e7cf991e2340181bbfcf Mon Sep 17 00:00:00 2001 From: Vitaly Kuzmichev Date: Tue, 15 Jun 2010 22:18:11 +0400 Subject: ARM: Align stack to 8 bytes The ARM ABI requires that the stack be aligned to 8 bytes as it is noted in Procedure Call Standard for the ARM Architecture: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/index.html Unaligned SP also causes the problem with variable-length arrays allocation when VLA address becomes less than stack pointer during aligning of this address, so the next 'push' in the stack overwrites first 4 bytes of VLA. Signed-off-by: Vitaly Kuzmichev Tested on tx25(mx25), imx27lite(mx27), qong(mx31) and trab(s3c2400) Tested-by: Wolfgang Denk --- arch/arm/cpu/arm1136/start.S | 1 + arch/arm/cpu/arm1176/start.S | 1 + arch/arm/cpu/arm720t/start.S | 1 + arch/arm/cpu/arm920t/start.S | 1 + arch/arm/cpu/arm925t/start.S | 1 + arch/arm/cpu/arm926ejs/start.S | 2 +- arch/arm/cpu/arm946es/start.S | 1 + arch/arm/cpu/arm_cortexa8/start.S | 2 +- arch/arm/cpu/arm_intcm/start.S | 1 + arch/arm/cpu/ixp/start.S | 1 + arch/arm/cpu/lh7a40x/start.S | 1 + arch/arm/cpu/pxa/start.S | 6 ++---- arch/arm/cpu/s3c44b0/start.S | 1 + arch/arm/cpu/sa1100/start.S | 1 + 14 files changed, 15 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 922d01c..41eb82d 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -185,6 +185,7 @@ stack_setup: #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ #endif /* CONFIG_PRELOADER */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index a540edb..f98a7aa 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -276,6 +276,7 @@ stack_setup: sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 022b873..d6f2c16 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -172,6 +172,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 779f192..e532f55 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -204,6 +204,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 567e804..346615e 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -196,6 +196,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 3b81151..cf40ce1 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -196,7 +196,7 @@ stack_setup: #endif #endif /* CONFIG_PRELOADER */ sub sp, r0, #12 /* leave 3 words for abort-stack */ - bic sp, r0, #7 /* 8-byte align stack for ABI compliance */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 627e3cb..8844d44 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -163,6 +163,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm_cortexa8/start.S b/arch/arm/cpu/arm_cortexa8/start.S index 29dae2f..1e0a150 100644 --- a/arch/arm/cpu/arm_cortexa8/start.S +++ b/arch/arm/cpu/arm_cortexa8/start.S @@ -164,7 +164,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 @ leave 3 words for abort-stack - and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d + bic sp, sp, #7 @ 8-byte alignment for ABI compliance /* Clear BSS (if any). Is below tx (watch load addr - need space) */ clear_bss: diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index bb1f003..328bae0 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -161,6 +161,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index 5ebce53..6efe333 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -289,6 +289,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S index a1321b1..14a1fbe 100644 --- a/arch/arm/cpu/lh7a40x/start.S +++ b/arch/arm/cpu/lh7a40x/start.S @@ -178,6 +178,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 3989fa6..e07c8c2 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -140,10 +140,8 @@ stack_setup: #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif /* CONFIG_USE_IRQ */ - sub r0, r0, #12 /* leave 3 words for abort-stack */ - bic sp, r0, #7 /* NOTE: stack MUST be aligned to */ - /* 8 bytes in case we want to use */ - /* 64bit datatypes (eg. VSPRINTF64) */ + sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index f5a3d3a..0063063 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -163,6 +163,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ ldr pc, _start_armboot diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 278c500..deb4745 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -153,6 +153,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ -- cgit v1.1 From 95bc39e848dd3f741a064c826d1c282c48125d41 Mon Sep 17 00:00:00 2001 From: Terry Lv Date: Thu, 6 May 2010 18:30:55 +0800 Subject: ARM: fix bug in macro __arch_ioremap. Signed-off-by: Terry Lv Fix commit message and code formatting. Signed-off-by: Wolfgang Denk --- arch/arm/include/asm/io.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 0a4b5be..e8f3eb1 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -248,13 +248,13 @@ extern void __iounmap(void *addr); * iomem_to_phys(off) */ #ifdef iomem_valid_addr -#define __arch_ioremap(off,sz,nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,0); \ - _ret; \ +#define __arch_ioremap(off,sz,nocache) \ + ({ \ + unsigned long _off = (off), _size = (sz); \ + void *_ret = (void *)0; \ + if (iomem_valid_addr(_off, _size)) \ + _ret = __ioremap(iomem_to_phys(_off),_size,nocache); \ + _ret; \ }) #define __arch_iounmap __iounmap -- cgit v1.1 From 23fdf0580660edf38cb7118f05b8865f2f73c674 Mon Sep 17 00:00:00 2001 From: Albert Aribaud <[albert.aribaud@free.fr]> Date: Tue, 22 Jun 2010 15:50:28 +0530 Subject: Fix wrong orion5x MPP and GIPO writel arguments Orion5x MPP and GPIO setting code had writel arguments the wrong way around. Fixed and tested. Signed-off-by: Albert Aribaud --- arch/arm/cpu/arm926ejs/orion5x/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index c2f5253..03c6d06 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -260,10 +260,10 @@ int arch_misc_init(void) /* Set CPIOs and MPPs - values provided by board include file */ - writel(ORION5X_MPP_BASE+0x00, ORION5X_MPP0_7); - writel(ORION5X_MPP_BASE+0x04, ORION5X_MPP8_15); - writel(ORION5X_MPP_BASE+0x50, ORION5X_MPP16_23); - writel(ORION5X_GPIO_BASE+0x04, ORION5X_GPIO_OUT_ENABLE); + writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00); + writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04); + writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50); + writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04); return 0; } -- cgit v1.1 From d6b937142008463d628ef26a753f9c20c57f3617 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 21 Jun 2010 18:13:21 +0400 Subject: Makefile: always call date with LC_ALL=C set Ensure that date is called only with LC_ALL=C locale set to make dates locale neutral thus preventing lurking of non-ASCII characters into U-Boot binary. Signed-off-by: Ilya Yanok Changed LANG= into LC_ALL= as suggested by Mike Frysinger Signed-off-by: Wolfgang Denk --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 55bb964..9a436fe 100644 --- a/Makefile +++ b/Makefile @@ -385,8 +385,8 @@ $(VERSION_FILE): @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ $(TIMESTAMP_FILE): - @date +'#define U_BOOT_DATE "%b %d %C%y"' > $@ - @date +'#define U_BOOT_TIME "%T"' >> $@ + @LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@ + @LC_ALL=C date +'#define U_BOOT_TIME "%T"' >> $@ gdbtools: $(MAKE) -C tools/gdb all || exit 1 @@ -3751,6 +3751,6 @@ endif backup: F=`basename $(TOPDIR)` ; cd .. ; \ - gtar --force-local -zcvf `date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F + gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F ######################################################################### -- cgit v1.1 From b8c4eea56b5f41f9bdbb89d3d5c79b7d282d513c Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 14 Apr 2010 15:32:06 +0200 Subject: remove myself as a maintainer of several ARM boards Since I haven't been actively maintaining these boards for a long while, keeping myself as their maintainer makes no sense. Signed-off-by: Guennadi Liakhovetski --- MAINTAINERS | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index f10e924..d7aec98 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -677,12 +677,6 @@ Sergey Lapin afeb9260 ARM926EJS (AT91SAM9260 SoC) -Guennadi Liakhovetski - - imx31_phycore_eet i.MX31 - mx31ads i.MX31 - SMDK6400 S3C6400 - Nishanth Menon omap3_sdp3430 ARM CORTEX-A8 (OMAP3xx SoC) @@ -825,6 +819,10 @@ Unknown / orphaned boards: ixdp425 xscale Kyle Harris / dead address lubbock xscale Kyle Harris / dead address + imx31_phycore_eet i.MX31 Guennadi Liakhovetski / resigned + mx31ads i.MX31 Guennadi Liakhovetski / resigned + SMDK6400 S3C6400 Guennadi Liakhovetski / resigned + ######################################################################### # x86 Systems: # # # -- cgit v1.1 From ceeba0030844b2e84ce4e47f4be7ad347cd1e827 Mon Sep 17 00:00:00 2001 From: Peter Horton Date: Sat, 12 Jun 2010 10:11:56 +0900 Subject: UBI: initialise update marker UBI: initialise update marker The in kernel copy of a volume's update marker is not initialised from the volume table. This means that volumes where an update was unfinnished will not be treated as "forbidden to use". This is basically that the update functionality was broken. Signed-off-by: Peter Horton Signed-off-by: Artem Bityutskiy Signed-off-by: Kyungmin Park Acked-by: Stefan Roese --- drivers/mtd/ubi/vtbl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c index 9264ac6..f679f06 100644 --- a/drivers/mtd/ubi/vtbl.c +++ b/drivers/mtd/ubi/vtbl.c @@ -520,6 +520,7 @@ static int init_volumes(struct ubi_device *ubi, const struct ubi_scan_info *si, vol->reserved_pebs = be32_to_cpu(vtbl[i].reserved_pebs); vol->alignment = be32_to_cpu(vtbl[i].alignment); vol->data_pad = be32_to_cpu(vtbl[i].data_pad); + vol->upd_marker = vtbl[i].upd_marker; vol->vol_type = vtbl[i].vol_type == UBI_VID_DYNAMIC ? UBI_DYNAMIC_VOLUME : UBI_STATIC_VOLUME; vol->name_len = be16_to_cpu(vtbl[i].name_len); -- cgit v1.1 From 47ea6edfb3004fb2d2a979e19c3f6e4e32f45e51 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Fri, 18 Jun 2010 19:31:10 +0900 Subject: ARM: remove unused VIDEOLFB ATAG ATAG_VIDEOLFB is not used anywhere. The belowing warning is occurred due to this ATAG. [ 0.000000] Ignoring unrecognised tag 0x54410008 This patch fixed it. Signed-off-by: Minkyu Kang Signed-off-by: Kyungmin Park Acked-by: Martin Krause --- arch/arm/lib/bootm.c | 43 +++---------------------------------------- 1 file changed, 3 insertions(+), 40 deletions(-) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 128b7e3..5ac1302 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -33,9 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; defined (CONFIG_CMDLINE_TAG) || \ defined (CONFIG_INITRD_TAG) || \ defined (CONFIG_SERIAL_TAG) || \ - defined (CONFIG_REVISION_TAG) || \ - defined (CONFIG_VFD) || \ - defined (CONFIG_LCD) + defined (CONFIG_REVISION_TAG) static void setup_start_tag (bd_t *bd); # ifdef CONFIG_SETUP_MEMORY_TAGS @@ -49,10 +47,6 @@ static void setup_initrd_tag (bd_t *bd, ulong initrd_start, # endif static void setup_end_tag (bd_t *bd); -# if defined (CONFIG_VFD) || defined (CONFIG_LCD) -static void setup_videolfb_tag (gd_t *gd); -# endif - static struct tag *params; #endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ @@ -87,9 +81,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) defined (CONFIG_CMDLINE_TAG) || \ defined (CONFIG_INITRD_TAG) || \ defined (CONFIG_SERIAL_TAG) || \ - defined (CONFIG_REVISION_TAG) || \ - defined (CONFIG_LCD) || \ - defined (CONFIG_VFD) + defined (CONFIG_REVISION_TAG) setup_start_tag (bd); #ifdef CONFIG_SERIAL_TAG setup_serial_tag (¶ms); @@ -107,9 +99,6 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) if (images->rd_start && images->rd_end) setup_initrd_tag (bd, images->rd_start, images->rd_end); #endif -#if defined (CONFIG_VFD) || defined (CONFIG_LCD) - setup_videolfb_tag ((gd_t *) gd); -#endif setup_end_tag (bd); #endif @@ -136,9 +125,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) defined (CONFIG_CMDLINE_TAG) || \ defined (CONFIG_INITRD_TAG) || \ defined (CONFIG_SERIAL_TAG) || \ - defined (CONFIG_REVISION_TAG) || \ - defined (CONFIG_LCD) || \ - defined (CONFIG_VFD) + defined (CONFIG_REVISION_TAG) static void setup_start_tag (bd_t *bd) { params = (struct tag *) bd->bi_boot_params; @@ -214,30 +201,6 @@ static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end) } #endif /* CONFIG_INITRD_TAG */ - -#if defined (CONFIG_VFD) || defined (CONFIG_LCD) -extern ulong calc_fbsize (void); -static void setup_videolfb_tag (gd_t *gd) -{ - /* An ATAG_VIDEOLFB node tells the kernel where and how large - * the framebuffer for video was allocated (among other things). - * Note that a _physical_ address is passed ! - * - * We only use it to pass the address and size, the other entries - * in the tag_videolfb are not of interest. - */ - params->hdr.tag = ATAG_VIDEOLFB; - params->hdr.size = tag_size (tag_videolfb); - - params->u.videolfb.lfb_base = (u32) gd->fb_base; - /* Fb size is calculated according to parameters for our panel - */ - params->u.videolfb.lfb_size = calc_fbsize(); - - params = tag_next (params); -} -#endif /* CONFIG_VFD || CONFIG_LCD */ - #ifdef CONFIG_SERIAL_TAG void setup_serial_tag (struct tag **tmp) { -- cgit v1.1 From 460c2ce362e56890c2a029e2c3b1ff2796c7fc54 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 21 Jun 2010 22:29:59 +0200 Subject: MPC5200: workaround data corruption for unaligned local bus accesses The MPC5200 has a nasty problem that will cause silent data corruption when performing unaligned 16 or 32 byte accesses when reading from the local bus - typically this affects reading from flash. The problem can be easily shown: => md fc0c0000 10 fc0c0000: 323e4337 01626f6f 74636d64 3d72756e 2>C7.bootcmd=run fc0c0010: 206e6574 5f6e6673 00626f6f 7464656c net_nfs.bootdel fc0c0020: 61793d35 00626175 64726174 653d3131 ay=5.baudrate=11 fc0c0030: 35323030 00707265 626f6f74 3d656368 5200.preboot=ech => md fc0c0001 10 fc0c0001: 65636801 00000074 0000003d 00000020 ech....t...=... fc0c0011: 0000005f 00000000 00000074 00000061 ..._.......t...a fc0c0021: 00000000 00000064 00000065 00000035 .......d...e...5 fc0c0031: 00000000 00000062 0000003d 0000006f .......b...=...o => md.w fc0c0001 10 fc0c0001: 0000 3701 0000 6f74 0000 643d 0000 6e20 ..7...ot..d=..n fc0c0011: 0000 745f 0000 7300 0000 6f74 0000 6c61 ..t_..s...ot..la This commit implements a workaround at least for the most blatant problem: using memcpy() from NOR flash. We rename the assembler routine into __memcpy() and provide a wrapper, which will use a byte-wise copy loop for unaligned source or target addresses when reading from NOR flash, and branch to the optimized __memcpy() in all other cases, thus minimizing the performance impact. Tested on lite5200b and TQM5200S. Signed-off-by: Wolfgang Denk Cc: Detlev Zundel --- arch/powerpc/cpu/mpc5xxx/Makefile | 5 +++ arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c | 71 +++++++++++++++++++++++++++++++ arch/powerpc/lib/Makefile | 5 +++ 3 files changed, 81 insertions(+) create mode 100644 arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile index 0ee0611..4ab2b7b 100644 --- a/arch/powerpc/cpu/mpc5xxx/Makefile +++ b/arch/powerpc/cpu/mpc5xxx/Makefile @@ -30,6 +30,11 @@ SOBJS = io.o firmware_sc_task_bestcomm.impl.o COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \ loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o +# Workaround for local bus unaligned access problem on MPC5200 +#ifdef CONFIG_MPC5200 +COBJS += memcpy_mpc5200.o +#endif + SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) START := $(addprefix $(obj),$(START)) diff --git a/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c b/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c new file mode 100644 index 0000000..0950354 --- /dev/null +++ b/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This is a workaround for issues on the MPC5200, where unaligned + * 32-bit-accesses to the local bus will deliver corrupted data. This + * happens for example when trying to use memcpy() from an odd NOR + * flash address; the behaviour can be also seen when using "md" on an + * odd NOR flash address (but there it is not a bug in U-Boot, which + * only shows the behaviour of this processor). + * + * For memcpy(), we test if either the source or the target address + * are not 32 bit aligned, and - if so - if the source address is in + * NOR flash: in this case we perform a byte-wise (slow) then; for + * aligned operations of non-flash areas we use the optimized (fast) + * real __memcpy(). This way we minimize the performance impact of + * this workaround. + * + */ + +#include +#include +#include + +void *memcpy(void *trg, const void *src, size_t len) +{ + extern void* __memcpy(void *, const void *, size_t); + char *s = (char *)src; + char *t = (char *)trg; + void *dest = (void *)src; + + /* + * Check is source address is in flash: + * If not, we use the fast assembler code + */ + if (((((unsigned long)s & 3) == 0) /* source aligned */ + && /* AND */ + (((unsigned long)t & 3) == 0)) /* target aligned, */ + || /* or */ + (addr2info((ulong)s) == NULL)) { /* source not in flash */ + return __memcpy(trg, src, len); + } + + /* + * Copying from flash, perform byte by byte copy. + */ + while (len-- > 0) + *t++ = *s++; + + return dest; +} diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 5f85502..bf23790 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -43,6 +43,11 @@ COBJS-y += time.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +# Workaround for local bus unaligned access problem on MPC5200 +ifdef CONFIG_MPC5200 +$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy +endif + $(LIB): $(obj).depend $(OBJS) @if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\ then \ -- cgit v1.1 From 482126e27b3dbf0e69a6445da8b94b3551adf05d Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 23 Jun 2010 20:50:54 +0200 Subject: Prepare v2010.06-rc3 Signed-off-by: Wolfgang Denk --- CHANGELOG | 752 +++++++++++++++++++++++++ Makefile | 2 +- arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S | 140 ++--- common/cmd_setexpr.c | 2 +- 4 files changed, 824 insertions(+), 72 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 91664a0..5399007 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,736 @@ +commit 460c2ce362e56890c2a029e2c3b1ff2796c7fc54 +Author: Wolfgang Denk +Date: Mon Jun 21 22:29:59 2010 +0200 + + MPC5200: workaround data corruption for unaligned local bus accesses + + The MPC5200 has a nasty problem that will cause silent data corruption + when performing unaligned 16 or 32 byte accesses when reading from the + local bus - typically this affects reading from flash. The problem can + be easily shown: + + => md fc0c0000 10 + fc0c0000: 323e4337 01626f6f 74636d64 3d72756e 2>C7.bootcmd=run + fc0c0010: 206e6574 5f6e6673 00626f6f 7464656c net_nfs.bootdel + fc0c0020: 61793d35 00626175 64726174 653d3131 ay=5.baudrate=11 + fc0c0030: 35323030 00707265 626f6f74 3d656368 5200.preboot=ech + => md fc0c0001 10 + fc0c0001: 65636801 00000074 0000003d 00000020 ech....t...=... + fc0c0011: 0000005f 00000000 00000074 00000061 ..._.......t...a + fc0c0021: 00000000 00000064 00000065 00000035 .......d...e...5 + fc0c0031: 00000000 00000062 0000003d 0000006f .......b...=...o + => md.w fc0c0001 10 + fc0c0001: 0000 3701 0000 6f74 0000 643d 0000 6e20 ..7...ot..d=..n + fc0c0011: 0000 745f 0000 7300 0000 6f74 0000 6c61 ..t_..s...ot..la + + This commit implements a workaround at least for the most blatant + problem: using memcpy() from NOR flash. We rename the assembler + routine into __memcpy() and provide a wrapper, which will use a + byte-wise copy loop for unaligned source or target addresses when + reading from NOR flash, and branch to the optimized __memcpy() + in all other cases, thus minimizing the performance impact. + + Tested on lite5200b and TQM5200S. + + Signed-off-by: Wolfgang Denk + Cc: Detlev Zundel + +commit 47ea6edfb3004fb2d2a979e19c3f6e4e32f45e51 +Author: Minkyu Kang +Date: Fri Jun 18 19:31:10 2010 +0900 + + ARM: remove unused VIDEOLFB ATAG + + ATAG_VIDEOLFB is not used anywhere. + The belowing warning is occurred due to this ATAG. + + [ 0.000000] Ignoring unrecognised tag 0x54410008 + + This patch fixed it. + + Signed-off-by: Minkyu Kang + Signed-off-by: Kyungmin Park + Acked-by: Martin Krause + +commit ceeba0030844b2e84ce4e47f4be7ad347cd1e827 +Author: Peter Horton +Date: Sat Jun 12 10:11:56 2010 +0900 + + UBI: initialise update marker + + UBI: initialise update marker + + The in kernel copy of a volume's update marker is not initialised from the + volume table. This means that volumes where an update was unfinnished will + not be treated as "forbidden to use". This is basically that the update + functionality was broken. + + Signed-off-by: Peter Horton + Signed-off-by: Artem Bityutskiy + Signed-off-by: Kyungmin Park + Acked-by: Stefan Roese + +commit b8c4eea56b5f41f9bdbb89d3d5c79b7d282d513c +Author: Guennadi Liakhovetski +Date: Wed Apr 14 15:32:06 2010 +0200 + + remove myself as a maintainer of several ARM boards + + Since I haven't been actively maintaining these boards for a long while, + keeping myself as their maintainer makes no sense. + + Signed-off-by: Guennadi Liakhovetski + +commit d6b937142008463d628ef26a753f9c20c57f3617 +Author: Ilya Yanok +Date: Mon Jun 21 18:13:21 2010 +0400 + + Makefile: always call date with LC_ALL=C set + + Ensure that date is called only with LC_ALL=C locale set to make dates + locale neutral thus preventing lurking of non-ASCII characters into + U-Boot binary. + + Signed-off-by: Ilya Yanok + + Changed LANG= into LC_ALL= as suggested by Mike Frysinger + Signed-off-by: Wolfgang Denk + +commit 23fdf0580660edf38cb7118f05b8865f2f73c674 +Author: Albert Aribaud <[albert.aribaud@free.fr]> +Date: Tue Jun 22 15:50:28 2010 +0530 + + Fix wrong orion5x MPP and GIPO writel arguments + + Orion5x MPP and GPIO setting code had writel arguments + the wrong way around. Fixed and tested. + + Signed-off-by: Albert Aribaud + +commit 95bc39e848dd3f741a064c826d1c282c48125d41 +Author: Terry Lv +Date: Thu May 6 18:30:55 2010 +0800 + + ARM: fix bug in macro __arch_ioremap. + + Signed-off-by: Terry Lv + + Fix commit message and code formatting. + + Signed-off-by: Wolfgang Denk + +commit a71da1b6c96205549ca2e7cf991e2340181bbfcf +Author: Vitaly Kuzmichev +Date: Tue Jun 15 22:18:11 2010 +0400 + + ARM: Align stack to 8 bytes + + The ARM ABI requires that the stack be aligned to 8 bytes as it is noted + in Procedure Call Standard for the ARM Architecture: + http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/index.html + + Unaligned SP also causes the problem with variable-length arrays + allocation when VLA address becomes less than stack pointer during + aligning of this address, so the next 'push' in the stack overwrites + first 4 bytes of VLA. + + Signed-off-by: Vitaly Kuzmichev + + Tested on tx25(mx25), imx27lite(mx27), qong(mx31) and trab(s3c2400) + Tested-by: Wolfgang Denk + +commit 6de27bdc788e7c4532ee0721ae291aeb5df475dc +Author: Wolfgang Denk +Date: Sun Jun 20 12:32:37 2010 +0200 + + net/eth.c: eth_mac_skip() is only needed when CONFIG_NET_MULTI is set + + Move it inside the #ifdef CONFIG_NET_MULTI to avoid + + eth.c:64: warning: 'eth_mac_skip' defined but not used + + messages from a number of old, non-CONFIG_NET_MULTI boards. + + Signed-off-by: Wolfgang Denk + Signed-off-by: Ben Warren + +commit e397e59e861aa818cda12a23206dde06f7e9f660 +Author: Fillod Stephane +Date: Fri Jun 11 19:26:43 2010 +0200 + + ip/defrag: fix processing of last short fragment + + TFTP'ing a file of size 1747851 bytes with CONFIG_IP_DEFRAG and + CONFIG_TFTP_BLOCKSIZE set to 4096 fails with a timeout, because + the last fragment is not taken into account. This patch fixes + IP fragments having less than 8 bytes of payload. + + Signed-off-by: Stephane Fillod + Acked-by: Alessandro Rubini + Signed-off-by: Ben Warren + +commit 9c00b2f0a3fe0f779761607024f99b7690c9776c +Author: Wolfgang Denk +Date: Sun Jun 20 12:30:22 2010 +0200 + + net/eth.c: eth_mac_skip() is only needed when CONFIG_NET_MULTI is set + + Move it inside the #ifdef CONFIG_NET_MULTI to avoid + + eth.c:64: warning: 'eth_mac_skip' defined but not used + + messages from anumber of old, non-CONFIG_NET_MULTI boards. + + Signed-off-by: Wolfgang Denk + Cc: Ben Warren + +commit 9312bba01a41191f20821b66b84b3ff1d2902e8a +Author: Wolfgang Denk +Date: Sun Jun 20 02:16:44 2010 +0200 + + include/compiler.h: remove redundant declaration of errno + + Commit 37566090 "compiler.h: unify system ifdef cruft here" added both + a "#include " and a "extern int errno;" to include/compiler.h + which is causing build warnings for some systems, for example for the + "netstar" board: + + In file included from /home/wd/git/u-boot/work/lib/crc32.c:15: + include/compiler.h:28: warning: function declaration isn't a prototype + + The declaration of "errno" should be redundant, as is + supposed to provide a correct declaration, so drop it. + + Signed-off-by: Wolfgang Denk + Cc: Mike Frysinger + +commit cd040a4953e55efe89dc3af4acf0302d5923026f +Author: Wolfgang Denk +Date: Fri Jun 18 15:55:15 2010 +0200 + + arch/arm/cpu/arm_cortexa8/omap3/cache.S: make build with older tools + + The push / pop instructions used in this file are available only with + more recent tool chains: + + cache.S: Assembler messages: + cache.S:133: Error: bad instruction `push {r0,r1,r2,lr}' + cache.S:160: Error: bad instruction `pop {r1,r2,r3,pc}' + cache.S:164: Error: bad instruction `push {r0,r1,r2,lr}' + cache.S:191: Error: bad instruction `pop {r1,r2,r3,pc}' + + Change push/pop into stmfd/ldmfd instructions to support older + versions of binutils as well. + + I verified that the modified source code generates exactly the same + binary code. + + Signed-off-by: Wolfgang Denk + Cc: Sandeep Paulraj + Cc: Tom Rix + +commit ce9c227cc71afc3b4c78dcc0a565c40d4ad943e4 +Author: Albert Aribaud <[albert.aribaud@free.fr]> +Date: Thu Jun 17 19:38:21 2010 +0530 + + Add support for the LaCie ED Mini V2 board + + This patch adds support for the LaCie ED Mini V2 product + which is based on the Marvell Orion5x SoC. + + Signed-off-by: Albert Aribaud + +commit 83142c112d30ee3da23b62387909d33db064bdc4 +Author: Albert Aribaud <[albert.aribaud@free.fr]> +Date: Thu Jun 17 19:37:01 2010 +0530 + + Add Orion5x support to 16550 device driver + + This patch provides access to the 16550-compatible + serial device of the Orion5x SoC. + + Signed-off-by: Albert Aribaud + +commit 0c61e6f9257ef416959b740ee3cf191bf682007d +Author: Albert Aribaud <[albert.aribaud@free.fr]> +Date: Thu Jun 17 19:36:07 2010 +0530 + + Initial support for Marvell Orion5x SoC + + This patch adds support for the Marvell Orion5x SoC. + It has no use alone, and must be followed by a patch + to add Orion5x support for serial, then support for + the ED Mini V2, an Orion5x-based product from LaCie. + + Signed-off-by: Albert Aribaud + +commit 376e7fadbad3285231e390c6534feb5af86d594b +Author: Minkyu Kang +Date: Tue Jun 8 14:40:47 2010 +0900 + + SAMSUNG: goni: add the GPL licence + + Signed-off-by: Minkyu Kang + Signed-off-by: Kyungmin Park + Acked-by: Tom + +commit c474a8ebb880e564df0c701c6a8cf73b7779b1d2 +Author: Minkyu Kang +Date: Mon May 31 22:02:42 2010 +0900 + + s5pc1xx: Add support for Samsung Goni board + + This patch adds support for the Samsung Goni board (S5PC110 SoC) + + Signed-off-by: Minkyu Kang + Signed-off-by: Kyungmin Park + +commit ffb4b02554d9972d66502efbe97b3933620c8a31 +Author: Minkyu Kang +Date: Fri May 28 12:34:29 2010 +0900 + + s5pc1xx: gpio: bug fix at gpio_set_pull function + + When set to PULL_NONE, gpio_set_pull function is returned without write the register. + This patch fixed it. + + Signed-off-by: Minkyu Kang + +commit a9046b9e1aeeedc66ddf1d00474ad0ce8c6aa6e4 +Author: Wolfgang Denk +Date: Sun Jun 13 17:48:15 2010 +0200 + + Prepare v2010-rc2 + + Signed-off-by: Wolfgang Denk + +commit 3a96ad851f4f9267e1199b700cb838a77334e4b2 +Author: Marek Vasut +Date: Sun Apr 11 08:53:55 2010 +0200 + + PXA: Align stack to 8 bytes + + Part of this patch is by: Mikhail Kshevetskiy. + + Stack must be aligned to 8 bytes on PXA (possibly all armv5te) for LDRD/STRD + instructions. In case LDRD/STRD is issued on an unaligned address, the behaviour + is undefined. + + The issue was observed when working with the NAND code, which was rendered + disfunctional. Also, the vsprintf() function had serious problems with printing + 64bit wide long longs. After aligning the stack, this wrong behaviour is no + longer present. + + Tested on: + Marvell Littleton PXA310 board + Toradex Colibri PXA320 board + Aeronix Zipit Z2 PXA270 handheld + Voipac PXA270 board + + Signed-off-by: Marek Vasut + +commit 89b765c7f6ddfde07ba673dd4adbeb5da391a81b +Author: Sudhakar Rajashekhara +Date: Thu Jun 10 15:18:15 2010 +0530 + + TI: DaVinci: Add board specific code for da850 EVM + + Provides initial support for TI OMAP-L138/DA850 SoC devices on + a Logic PD EVM board. + + Provides: + Initial boot and configuration. + Support for i2c. + UART support (console). + + Signed-off-by: Sudhakar Rajashekhara + Acked-by: Ben Gardiner + Reviewed-by: Wolfgang Denk + Signed-off-by: Sandeep Paulraj + +commit 158557001afe167dcb848bb14ba0f2f20aeb25a1 +Author: Sudhakar Rajashekhara +Date: Tue Jun 8 11:01:58 2010 +0530 + + TI: DaVinci: Prepare for da850 support + + DA850/OMAP-L138 is a new SoC from Texas Instruments + (http://focus.ti.com/docs/prod/folders/print/omap-l138.html). + This SoC is similar to DA830/OMAP-L137 in many aspects. Hence + rename the da830 specific files and folders to da8xx to + accommodate DA850/OMAP-L138. + + Signed-off-by: Sudhakar Rajashekhara + Acked-by: Ben Gardiner + Reviewed-by: Wolfgang Denk + Signed-off-by: Sandeep Paulraj + +commit 9d79956029ec379e7137948ba3a7debbea61325f +Author: Sudhakar Rajashekhara +Date: Mon Jun 7 12:39:59 2010 +0530 + + da830: Move common code out of da830evm.c file + + TI's DA850/OMAP-L138 platform is similar to DA830/OMAP-L137 + in many aspects. So instead of repeating the same code in + multiple files, move the common code to a different file + and call those functions from the respective da830/da850 + files. + + Signed-off-by: Sudhakar Rajashekhara + Acked-by: Nick Thompson + Acked-by: Ben Gardiner + Signed-off-by: Sandeep Paulraj + +commit 5246d01edd8935e04cdf79a5b9a03874509a31b1 +Author: Grazvydas Ignotas +Date: Tue Jun 8 17:19:22 2010 -0400 + + OMAP3: pandora: enable battery backup capacitor + + Pandora has a capacitor connected as backup battery, which allows + retaining RTC for some time while main battery is removed. Enable backup + battery charge function to charge that capacitor. + + Signed-off-by: Grazvydas Ignotas + Signed-off-by: Sandeep Paulraj + +commit 9268236529161312c877e638a14c011fd3c883e1 +Author: Delio Brignoli +Date: Mon Jun 7 17:16:13 2010 -0400 + + DaVinci: Improve DaVinci SPI speed. + + I have updated this patch based on the comments [1] by Wolfgang Denk and + removed unused variables. + [1][http://lists.denx.de/pipermail/u-boot/2010-May/071728.html] + + Reduce the number of reads per byte transferred on the BUF register from 2 to 1 and + take advantage of the TX buffer in the SPI module. On LogicPD OMAP-L138 EVM, + SPI read throughput goes up from ~0.8Mbyte/s to ~1.3Mbyte/s. Tested with a 2Mbyte image file. + Remove unused variables in the spi_xfer() function. + + Signed-off-by: Delio Brignoli + Tested-by: Ben Gardiner + Signed-off-by: Sandeep Paulraj + +commit 1a5038ca6831e31875cf67c46226f04743574032 +Author: Vaibhav Hiremath +Date: Mon Jun 7 15:20:53 2010 -0400 + + AM35x: Add support for EMIF4 + + This patch adds support for the EMIF4 interface + available in the AM35x processors. + + Signed-off-by: Vaibhav Hiremath + Signed-off-by: Sanjeev Premi + Signed-off-by: Sandeep Paulraj + +commit ed01e45cfa20d60ee83a4ee0128d843730055294 +Author: Vaibhav Hiremath +Date: Mon Jun 7 15:20:43 2010 -0400 + + AM35x: Add support for AM3517EVM + + This patch adds basic support for the AM3517EVM. + It includes: + - Board files (.c and .h) + - Default configuration file + - Updates for Makefile + + Signed-off-by: Vaibhav Hiremath + Signed-off-by: Sanjeev Premi + Signed-off-by: Sandeep Paulraj + +commit cae377b59a179e34d27cd6b79dee24d967de839c +Author: Vaibhav Hiremath +Date: Mon Jun 7 15:20:34 2010 -0400 + + omap3: Consolidate SDRC related operations + + Consolidated SDRC related functions into one file - sdrc.c + + And also replaced sdrc_init with generic memory init + function (mem_init), this generalization of omap memory setup + is necessary to support the new emif4 interface introduced in AM3517. + + Signed-off-by: Vaibhav Hiremath + Signed-off-by: Sandeep Paulraj + +commit d11212e3772c8fe43a1f487bbf58f3341118a241 +Author: Vaibhav Hiremath +Date: Mon Jun 7 15:20:29 2010 -0400 + + omap3: Calculate CS1 size only when SDRC is + + initialized for CS1 + + From: Vaibhav Hiremath + + The patch makes sure that size for SDRC CS1 gets calculated + only when the CS1 SDRC is initialized. + + Signed-off-by: Vaibhav Hiremath + Signed-off-by: Sandeep Paulraj + +commit 675e0eaf0f0429aac3c6fb41634fbcea2350fe49 +Author: Vaibhav Hiremath +Date: Mon Jun 7 15:20:19 2010 -0400 + + OMAP3EVM: Added NAND support + + The EVMS have been shipping with NAND (instead of OneNAND) as default. + So, this patch sets NAND as default. + + To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the + config file omap3_evm.h. + + Signed-off-by: Vaibhav Hiremath + Signed-off-by: Sandeep Paulraj + +commit 5cc48f7e55df0d74a12d338de2117f05951fc536 +Author: Cyril Chemparathy +Date: Mon Jun 7 14:13:36 2010 -0400 + + TI: TNETV107X EVM initial support + + TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a + bunch on on-chip integrated peripherals. This patch adds support for the + TNETV107X EVM board. + + Signed-off-by: Cyril Chemparathy + Signed-off-by: Sandeep Paulraj + +commit 3712367c4830e87b4e7af5b480e82d316bab1251 +Author: Cyril Chemparathy +Date: Mon Jun 7 14:13:32 2010 -0400 + + ARM1176: TI: TNETV107X soc initial support + + TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a + bunch on on-chip integrated peripherals. This is an initial commit with + basic functionality, more commits with drivers, etc. to follow. + + Signed-off-by: Cyril Chemparathy + Signed-off-by: Sandeep Paulraj + +commit 678e008c3a3a27fe2d30cf423679d2d11d0fa5c2 +Author: Cyril Chemparathy +Date: Mon Jun 7 14:13:27 2010 -0400 + + ARM1176: Coexist with other ARM1176 platforms + + The current ARM1176 CPU specific code is too specific to the SMDK6400 + architecture. The following changes were necessary prerequisites for the + addition of other SoCs based on ARM1176. + + Existing board's (SMDK6400) configuration has been modified to keep behavior + unchanged despite these changes. + + 1. Peripheral port remap configurability + The earlier code had hardcoded remap values specific to s3c64xx in start.S. + This change makes the peripheral port remap addresses and sizes configurable. + + 2. U-Boot code relocation support + Most architectures allow u-boot code to run initially at a different + address (possibly in NOR) and then get relocated to its final resting place + in RAM. Added support for this capability in ARM1176 architecture. + + 3. Disable TCM if necessary + If a ROM based bootloader happened to have initialized TCM, we disable it here + to keep things sane. + + 4. Remove unnecessary SoC specific includes + ARM1176 code does not really need this SoC specific include. The presence + of this include prevents builds on other ARM1176 archs. + + 5. Modified virt-to-phys conversion during MMU disable + The original MMU disable code masks out too many bits from the load address + when it tries to figure out the physical address of the jump target label. + Consequently, it ends up branching to the wrong address after disabling the + MMU. + + Signed-off-by: Cyril Chemparathy + Signed-off-by: Sandeep Paulraj + +commit 23911740486c59851df57521c49bfd81ce1865ec +Author: Delio Brignoli +Date: Mon Jun 7 17:16:13 2010 -0400 + + DaVinci: Improve DaVinci SPI speed. + + I have updated this patch based on the comments [1] by Wolfgang Denk and + removed unused variables. + [1][http://lists.denx.de/pipermail/u-boot/2010-May/071728.html] + + Reduce the number of reads per byte transferred on the BUF register from 2 to 1 and + take advantage of the TX buffer in the SPI module. On LogicPD OMAP-L138 EVM, + SPI read throughput goes up from ~0.8Mbyte/s to ~1.3Mbyte/s. Tested with a 2Mbyte image file. + Remove unused variables in the spi_xfer() function. + + Signed-off-by: Delio Brignoli + Tested-by: Ben Gardiner + Signed-off-by: Sandeep Paulraj + +commit 05ee415e316e3b1617aba06a747649f4d4053d41 +Author: Vaibhav Hiremath +Date: Mon Jun 7 15:20:53 2010 -0400 + + AM35x: Add support for EMIF4 + + This patch adds support for the EMIF4 interface + available in the AM35x processors. + + Signed-off-by: Vaibhav Hiremath + Signed-off-by: Sanjeev Premi + Signed-off-by: Sandeep Paulraj + +commit 3d9f0ffddaf1ece95a826785b971860ebdadf424 +Author: Vaibhav Hiremath +Date: Mon Jun 7 15:20:43 2010 -0400 + + AM35x: Add support for AM3517EVM + + This patch adds basic support for the AM3517EVM. + It includes: + - Board files (.c and .h) + - Default configuration file + - Updates for Makefile + + Signed-off-by: Vaibhav Hiremath + Signed-off-by: Sanjeev Premi + Signed-off-by: Sandeep Paulraj + +commit 8aa5c7cdc4e534df9129485ba317a2871c4f9880 +Author: Vaibhav Hiremath +Date: Mon Jun 7 15:20:34 2010 -0400 + + omap3: Consolidate SDRC related operations + + Consolidated SDRC related functions into one file - sdrc.c + + And also replaced sdrc_init with generic memory init + function (mem_init), this generalization of omap memory setup + is necessary to support the new emif4 interface introduced in AM3517. + + Signed-off-by: Vaibhav Hiremath + Signed-off-by: Sandeep Paulraj + +commit 16807ee411d83762804d075a3fe11f0a2b5eaf39 +Author: Vaibhav Hiremath +Date: Mon Jun 7 15:20:29 2010 -0400 + + omap3: Calculate CS1 size only when SDRC is + + initialized for CS1 + + From: Vaibhav Hiremath + + The patch makes sure that size for SDRC CS1 gets calculated + only when the CS1 SDRC is initialized. + + Signed-off-by: Vaibhav Hiremath + Signed-off-by: Sandeep Paulraj + +commit 7ca4766bd7f74e5f7371fb331b573ec384230c1d +Author: Vaibhav Hiremath +Date: Mon Jun 7 15:20:19 2010 -0400 + + OMAP3EVM: Added NAND support + + The EVMS have been shipping with NAND (instead of OneNAND) as default. + So, this patch sets NAND as default. + + To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the + config file omap3_evm.h. + + Signed-off-by: Vaibhav Hiremath + Signed-off-by: Sandeep Paulraj + +commit 04cbc19fedb55265d08cddea294c3b6d9f8b2d18 +Author: Cyril Chemparathy +Date: Mon Jun 7 14:13:36 2010 -0400 + + TI: TNETV107X EVM initial support + + TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a + bunch on on-chip integrated peripherals. This patch adds support for the + TNETV107X EVM board. + + Signed-off-by: Cyril Chemparathy + Signed-off-by: Sandeep Paulraj + +commit da1ec42aafcc821ce6b5d316a2d4105292960d6b +Author: Cyril Chemparathy +Date: Mon Jun 7 14:13:32 2010 -0400 + + ARM1176: TI: TNETV107X soc initial support + + TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a + bunch on on-chip integrated peripherals. This is an initial commit with + basic functionality, more commits with drivers, etc. to follow. + + Signed-off-by: Cyril Chemparathy + Signed-off-by: Sandeep Paulraj + +commit b87996d24a41cfc15fea125e5c805163af4acba1 +Author: Cyril Chemparathy +Date: Mon Jun 7 14:13:27 2010 -0400 + + ARM1176: Coexist with other ARM1176 platforms + + The current ARM1176 CPU specific code is too specific to the SMDK6400 + architecture. The following changes were necessary prerequisites for the + addition of other SoCs based on ARM1176. + + Existing board's (SMDK6400) configuration has been modified to keep behavior + unchanged despite these changes. + + 1. Peripheral port remap configurability + The earlier code had hardcoded remap values specific to s3c64xx in start.S. + This change makes the peripheral port remap addresses and sizes configurable. + + 2. U-Boot code relocation support + Most architectures allow u-boot code to run initially at a different + address (possibly in NOR) and then get relocated to its final resting place + in RAM. Added support for this capability in ARM1176 architecture. + + 3. Disable TCM if necessary + If a ROM based bootloader happened to have initialized TCM, we disable it here + to keep things sane. + + 4. Remove unnecessary SoC specific includes + ARM1176 code does not really need this SoC specific include. The presence + of this include prevents builds on other ARM1176 archs. + + 5. Modified virt-to-phys conversion during MMU disable + The original MMU disable code masks out too many bits from the load address + when it tries to figure out the physical address of the jump target label. + Consequently, it ends up branching to the wrong address after disabling the + MMU. + + Signed-off-by: Cyril Chemparathy + Signed-off-by: Sandeep Paulraj + +commit b5d289fc29842095d5cd0f82cceab1b0b2e824ba +Author: Asen Dimov +Date: Tue Apr 20 22:49:04 2010 +0300 + + add new board pm9g45 + + Add the new board PM9G45 from Ronetix GmbH. + * AT91SAM9G45 MCU at 400Mhz. + * 128MB DDR2 SDRAM + * 256MB NAND + * 10/100 MBits Ethernet DP83848 + * Serial number chip DS2401 + + The board is made as SODIMM200 module. + For more info www.ronatix.at or info@ronetix.at. + + Signed-off-by: Asen Dimov + commit f986325dd569faeaec4186f678d113505c5c4828 Author: Ron Madrid Date: Tue Jun 1 17:00:49 2010 -0700 @@ -13,6 +746,25 @@ Date: Tue Jun 1 17:00:49 2010 -0700 Signed-off-by: Ron Madrid Signed-off-by: Kim Phillips +commit 409a07c9d72b0d833c1cce264bdb4bb2628fe28e +Author: George G. Davis +Date: Tue May 11 10:15:36 2010 -0400 + + ARM1136: Fix cache_flush() error and correct cpu_init_crit() comments + + The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" + instruction which means "Invalidate Both Caches" when in fact the intent + is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, + c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate + Both Caches" instruction to insure that memory is consistent with any + dirty cache lines. + + Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so + that they correctly describe the actual ARM1136 CP15 C7 Cache Operations + used. + + Signed-off-by: George G. Davis + commit 3057c6be5efda781a72ca04432e0a4ed6e670030 Author: Kim Phillips Date: Fri Apr 23 12:20:11 2010 -0500 diff --git a/Makefile b/Makefile index 9a436fe..87d5214 100644 --- a/Makefile +++ b/Makefile @@ -24,7 +24,7 @@ VERSION = 2010 PATCHLEVEL = 06 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else diff --git a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S index b0e15f6..0523bd4 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S @@ -87,30 +87,30 @@ lowlevel_init: /* Use 'r4 as the base for internal register accesses */ - ldr r4, =ORION5X_REGS_PHY_BASE + ldr r4, =ORION5X_REGS_PHY_BASE /* move internal registers from the default 0xD0000000 * to their intended location, defined by SoC */ ldr r3, =0xD0000000 add r3, r3, #0x20000 - str r4, [r3, #0x80] + str r4, [r3, #0x80] /* Use R3 as the base for DRAM registers */ - add r3, r4, #0x01000 + add r3, r4, #0x01000 /*DDR SDRAM Initialization Control */ ldr r6, =0x00000001 str r6, [r3, #0x480] /* Use R3 as the base for PCI registers */ - add r3, r4, #0x31000 + add r3, r4, #0x31000 /* Disable arbiter */ ldr r6, =0x00000030 str r6, [r3, #0xd00] /* Use R3 as the base for DRAM registers */ - add r3, r4, #0x01000 + add r3, r4, #0x01000 /* set all dram windows to 0 */ mov r6, #0 @@ -127,63 +127,63 @@ lowlevel_init: ldr r6, =SDRAM_CONTROL str r6, [r3, #0x404] - /* 3) Write SDRAM address control register */ + /* 3) Write SDRAM address control register */ ldr r6, =SDRAM_ADDR_CTRL str r6, [r3, #0x410] - /* 4) Write SDRAM bank 0 size register */ + /* 4) Write SDRAM bank 0 size register */ ldr r6, =SDRAM_BANK0_SIZE str r6, [r3, #0x504] /* keep other banks disabled */ - /* 5) Write SDRAM open pages control register */ + /* 5) Write SDRAM open pages control register */ ldr r6, =SDRAM_OPEN_PAGE_EN str r6, [r3, #0x414] - /* 6) Write SDRAM timing Low register */ + /* 6) Write SDRAM timing Low register */ ldr r6, =SDRAM_TIME_CTRL_LOW str r6, [r3, #0x408] - /* 7) Write SDRAM timing High register */ + /* 7) Write SDRAM timing High register */ ldr r6, =SDRAM_TIME_CTRL_HI str r6, [r3, #0x40C] - /* 8) Write SDRAM mode register */ - /* The CPU must not attempt to change the SDRAM Mode register setting */ - /* prior to DRAM controller completion of the DRAM initialization */ - /* sequence. To guarantee this restriction, it is recommended that */ - /* the CPU sets the SDRAM Operation register to NOP command, performs */ - /* read polling until the register is back in Normal operation value, */ - /* and then sets SDRAM Mode register to its new value. */ + /* 8) Write SDRAM mode register */ + /* The CPU must not attempt to change the SDRAM Mode register setting */ + /* prior to DRAM controller completion of the DRAM initialization */ + /* sequence. To guarantee this restriction, it is recommended that */ + /* the CPU sets the SDRAM Operation register to NOP command, performs */ + /* read polling until the register is back in Normal operation value, */ + /* and then sets SDRAM Mode register to its new value. */ /* 8.1 write 'nop' to SDRAM operation */ - ldr r6, =SDRAM_OP_NOP + ldr r6, =SDRAM_OP_NOP str r6, [r3, #0x418] - /* 8.2 poll SDRAM operation until back in 'normal' mode. */ + /* 8.2 poll SDRAM operation until back in 'normal' mode. */ 1: ldr r6, [r3, #0x418] cmp r6, #0 bne 1b - /* 8.3 Now its safe to write new value to SDRAM Mode register */ + /* 8.3 Now its safe to write new value to SDRAM Mode register */ ldr r6, =SDRAM_MODE str r6, [r3, #0x41C] - /* 8.4 Set new mode */ - ldr r6, =SDRAM_OP_SETMODE + /* 8.4 Set new mode */ + ldr r6, =SDRAM_OP_SETMODE str r6, [r3, #0x418] - /* 8.5 poll SDRAM operation until back in 'normal' mode. */ + /* 8.5 poll SDRAM operation until back in 'normal' mode. */ 2: ldr r6, [r3, #0x418] cmp r6, #0 bne 2b - /* DDR SDRAM Address/Control Pads Calibration */ + /* DDR SDRAM Address/Control Pads Calibration */ ldr r6, [r3, #0x4C0] - /* Set Bit [31] to make the register writable */ + /* Set Bit [31] to make the register writable */ orr r6, r6, #SDRAM_PAD_CTRL_WR_EN str r6, [r3, #0x4C0] @@ -192,20 +192,20 @@ lowlevel_init: bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK - /* Get the final N locked value of driving strength [22:17] */ - mov r1, r6 - mov r1, r1, LSL #9 - mov r1, r1, LSR #26 /* r1[5:0] = r3[22:17] */ - orr r1, r1, r1, LSL #6 /* r1[11:6] = r1[5:0] */ + /* Get the final N locked value of driving strength [22:17] */ + mov r1, r6 + mov r1, r1, LSL #9 + mov r1, r1, LSR #26 /* r1[5:0] = r3[22:17] */ + orr r1, r1, r1, LSL #6 /* r1[11:6] = r1[5:0] */ - /* Write to both bits [5:0] and bits [11:6] */ + /* Write to both bits [5:0] and bits [11:6] */ orr r6, r6, r1 str r6, [r3, #0x4C0] - /* DDR SDRAM Data Pads Calibration */ + /* DDR SDRAM Data Pads Calibration */ ldr r6, [r3, #0x4C4] - /* Set Bit [31] to make the register writable */ + /* Set Bit [31] to make the register writable */ orr r6, r6, #SDRAM_PAD_CTRL_WR_EN str r6, [r3, #0x4C4] @@ -214,21 +214,21 @@ lowlevel_init: bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK - /* Get the final N locked value of driving strength [22:17] */ - mov r1, r6 - mov r1, r1, LSL #9 - mov r1, r1, LSR #26 - orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17] */ + /* Get the final N locked value of driving strength [22:17] */ + mov r1, r6 + mov r1, r1, LSL #9 + mov r1, r1, LSR #26 + orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17] */ - /* Write to both bits [5:0] and bits [11:6] */ + /* Write to both bits [5:0] and bits [11:6] */ orr r6, r6, r1 str r6, [r3, #0x4C4] - /* Implement Guideline (GL# MEM-3) Drive Strength Value */ - /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + /* Implement Guideline (GL# MEM-3) Drive Strength Value */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ - ldr r1, =DDR1_PAD_STRENGTH_DEFAULT + ldr r1, =DDR1_PAD_STRENGTH_DEFAULT /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */ ldr r6, [r3, #0x4C0] @@ -252,42 +252,42 @@ lowlevel_init: orr r6, r6, r1 str r6, [r3, #0x4C4] - /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ - /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ - /* Get the "sample on reset" register for the DDR frequancy */ + /* Get the "sample on reset" register for the DDR frequancy */ ldr r3, =0x10000 - ldr r6, [r3, #0x010] - ldr r1, =MSAR_ARMDDRCLCK_MASK - and r1, r6, r1 - - ldr r6, =FTDLL_DDR1_166MHZ - cmp r1, #MSAR_ARMDDRCLCK_333_167 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_500_167 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_667_167 - beq 3f - - ldr r6, =FTDLL_DDR1_200MHZ - cmp r1, #MSAR_ARMDDRCLCK_400_200_1 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_400_200 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_600_200 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_800_200 - beq 3f - - ldr r6, =0 + ldr r6, [r3, #0x010] + ldr r1, =MSAR_ARMDDRCLCK_MASK + and r1, r6, r1 + + ldr r6, =FTDLL_DDR1_166MHZ + cmp r1, #MSAR_ARMDDRCLCK_333_167 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_500_167 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_667_167 + beq 3f + + ldr r6, =FTDLL_DDR1_200MHZ + cmp r1, #MSAR_ARMDDRCLCK_400_200_1 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_400_200 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_600_200 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_800_200 + beq 3f + + ldr r6, =0 3: /* Use R3 as the base for DRAM registers */ - add r3, r4, #0x01000 + add r3, r4, #0x01000 ldr r2, [r3, #0x484] orr r2, r2, r6 str r2, [r3, #0x484] /* Return to U-boot via saved link register */ - mov pc, lr + mov pc, lr diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c index 2d37197..da9e844 100644 --- a/common/cmd_setexpr.c +++ b/common/cmd_setexpr.c @@ -32,7 +32,7 @@ static ulong get_arg(char *s, int w) { ulong *p; - /* + /* * if the parameter starts with a '*' then assume * it is a pointer to the value we want */ -- cgit v1.1