From f1b985f2d724ccaa4d3def07917f0caaf18fa77d Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 30 Mar 2008 16:39:53 +0200 Subject: use correct at91rm9200 register name in m501sk board This fixes a naming bug for at91rm9200 lowlevel init code: NOR boot flash is on chipselect 0, not chipselect 2. This makes code use the register name from chip datasheets. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/m501sk/memsetup.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S index 9e174b5..6aea723 100644 --- a/board/m501sk/memsetup.S +++ b/board/m501sk/memsetup.S @@ -52,8 +52,8 @@ #define MC_AASR_VAL 0x00000000 #define EBI_CFGR 0xFFFFFF64 #define EBI_CFGR_VAL 0x00000000 -#define SMC2_CSR 0xFFFFFF70 -#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define SMC_CSR0 0xFFFFFF70 +#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ /* clocks */ #define PLLAR 0xFFFFFC28 @@ -141,8 +141,8 @@ SMRDATA: .word MC_AASR_VAL .word EBI_CFGR .word EBI_CFGR_VAL - .word SMC2_CSR - .word SMC2_CSR_VAL + .word SMC_CSR0 + .word SMC_CSR0_VAL .word PLLAR .word PLLAR_VAL .word PLLBR -- cgit v1.1