From d3da7225526d996493fd45ec3d259c467db9a9d0 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Wed, 12 Jan 2011 10:14:42 +0100 Subject: xilinx_ppc_boards: Change address of RESET_VECTOR Old address of RESET_VECTOR were overwritten by the bss sector, making impossible its run from xmd. Signed-off-by: Ricardo Ribalda Delgado Signed-off-by: Stefan Roese --- boards.cfg | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/boards.cfg b/boards.cfg index 554e06c..d4cbb06 100644 --- a/boards.cfg +++ b/boards.cfg @@ -718,9 +718,9 @@ yellowstone powerpc ppc4xx yosemite amcc yosemite powerpc ppc4xx yosemite amcc - yosemite:YOSEMITE yucca powerpc ppc4xx - amcc AP1000 powerpc ppc4xx ap1000 amirix -fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o +fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o fx12mm_flash powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o -v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o +v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o v5fx30teval_flash powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o CRAYL1 powerpc ppc4xx L1 cray CATcenter powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1 @@ -780,11 +780,11 @@ p3p440 powerpc ppc4xx - prodriv KAREF powerpc ppc4xx karef sandburst METROBOX powerpc ppc4xx metrobox sandburst xpedite1000 powerpc ppc4xx - xes -ml507 powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o +ml507 powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o ml507_flash powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o -xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC +xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000 xilinx-ppc405-generic_flash powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC -xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1 +xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC rsk7203 sh sh2 rsk7203 renesas - mpr2 sh sh3 mpr2 - - -- cgit v1.1 From 6853cc4b9452f6a03df95cdb5846655a498bd08b Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 6 Apr 2011 13:53:43 +0200 Subject: ppc4xx: Improve DLVision-10G PLL setup Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- board/gdsys/common/osd.c | 55 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 52 insertions(+), 3 deletions(-) diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 4d8c046..6e4edae 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -30,7 +30,12 @@ #define CH7301_I2C_ADDR 0x75 #define ICS8N3QV01_I2C_ADDR 0x6E -#define ICS8N3QV01_FREF 114285 +#define ICS8N3QV01_FREF 114285000 +#define ICS8N3QV01_FREF_LL 114285000LL +#define ICS8N3QV01_F_DEFAULT_0 156250000LL +#define ICS8N3QV01_F_DEFAULT_1 125000000LL +#define ICS8N3QV01_F_DEFAULT_2 100000000LL +#define ICS8N3QV01_F_DEFAULT_3 25175000LL #define SIL1178_MASTER_I2C_ADDRESS 0x38 #define SIL1178_SLAVE_I2C_ADDRESS 0x39 @@ -150,6 +155,41 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout) #endif #ifdef CONFIG_SYS_ICS8N3QV01 + +static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index) +{ + unsigned long long n; + unsigned long long mint; + unsigned long long mfrac; + u8 reg_a, reg_b, reg_c, reg_d, reg_f; + unsigned long long fout_calc; + + if (index > 3) + return 0; + + reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index); + reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index); + reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index); + reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index); + reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index); + + mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20); + mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1) + | (reg_d >> 7); + n = reg_d & 0x7f; + + fout_calc = (mint * ICS8N3QV01_FREF_LL + + mfrac * ICS8N3QV01_FREF_LL / 262144LL + + ICS8N3QV01_FREF_LL / 524288LL + + n / 2) + / n + * 1000000 + / (1000000 - 100); + + return fout_calc; +} + + static void ics8n3qv01_calc_parameters(unsigned int fout, unsigned int *_mint, unsigned int *_mfrac, unsigned int *_n) @@ -160,7 +200,7 @@ static void ics8n3qv01_calc_parameters(unsigned int fout, unsigned int mint; unsigned long long mfrac; - n = 2550000000U / fout; + n = (2215000000U + fout / 2) / fout; if ((n & 1) && (n > 5)) n -= 1; @@ -184,9 +224,18 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout) unsigned int n; unsigned int mint; unsigned int mfrac; + unsigned int fout_calc; + unsigned long long fout_prog; + long long off_ppm; u8 reg0, reg4, reg8, reg12, reg18, reg20; - ics8n3qv01_calc_parameters(fout, &mint, &mfrac, &n); + fout_calc = ics8n3qv01_get_fout_calc(screen, 1); + off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000 + / ICS8N3QV01_F_DEFAULT_1; + printf(" PLL is off by %lld ppm\n", off_ppm); + fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc + / ICS8N3QV01_F_DEFAULT_1; + ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n); reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0; reg0 |= (mint & 0x1f) << 1; -- cgit v1.1 From b9ab8a994d9f83adc8439b758b2a1984def6288c Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 6 Apr 2011 13:53:44 +0200 Subject: ppc4xx: Improve video board detection Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- board/gdsys/405ep/dlvision-10g.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index df7fb14..d7b4fb2 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -31,6 +31,9 @@ #include "../common/osd.h" +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) +#define LATCH2_MC2_PRESENT_N 0x0080 + enum { UNITTYPE_VIDEO_USER = 0, UNITTYPE_MAIN_USER = 1, @@ -206,8 +209,8 @@ static void print_fpga_info(unsigned dev) */ int checkboard(void) { - unsigned k; char *s = getenv("serial#"); + u16 latch2 = in_le16((void *)LATCH2_BASE); printf("Board: "); @@ -220,20 +223,27 @@ int checkboard(void) puts("\n"); - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) - print_fpga_info(k); + print_fpga_info(0); + if (!(latch2 & LATCH2_MC2_PRESENT_N)) + print_fpga_info(1); return 0; } int last_stage_init(void) { - unsigned k; + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); + u16 versions = in_le16(&fpga->versions); + u16 latch2 = in_le16((void *)LATCH2_BASE); + + if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER) + return 0; + + if (!get_fpga_state(0)) + osd_probe(0); - for (k = 0; k < CONFIG_SYS_OSD_SCREENS; ++k) - if (!get_fpga_state(k) - || (get_fpga_state(k) == FPGA_STATE_DONE_FAILED)) - osd_probe(k); + if (!(latch2 & LATCH2_MC2_PRESENT_N) && !get_fpga_state(1)) + osd_probe(1); return 0; } -- cgit v1.1 From 8aa50540e4e8fe599857db522d58a55469bbb254 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Mon, 18 Apr 2011 10:42:19 +0200 Subject: ppc4xx: Enable LM64 on DLVision 10G Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- include/configs/dlvision-10g.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index f7609d7..ae209fa 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -111,7 +111,7 @@ /* Temp sensor/hwmon/dtt */ #define CONFIG_DTT_LM63 1 /* National LM63 */ -#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ +#define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */ #define CONFIG_DTT_PWM_LOOKUPTABLE \ { { 40, 10 }, { 50, 20 }, { 60, 40 } } #define CONFIG_DTT_TACH_LIMIT 0xa10 -- cgit v1.1 From 5cb4100f5825de5181be1edce8a020bf646a9475 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 6 Apr 2011 13:53:46 +0200 Subject: ppc4xx: Adapt DLVision 10G to new FPGA firmware Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- board/gdsys/405ep/405ep.c | 9 ++++++++- board/gdsys/405ep/dlvision-10g.c | 25 ++++++++++++++++++++----- include/configs/dlvision-10g.h | 2 ++ include/gdsys_fpga.h | 8 +++----- 4 files changed, 33 insertions(+), 11 deletions(-) diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c index 86a3ec8..8b80533 100644 --- a/board/gdsys/405ep/405ep.c +++ b/board/gdsys/405ep/405ep.c @@ -110,6 +110,11 @@ int board_early_init_f(void) for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k); +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI + u16 *reflection_target = &fpga->reflection_low; +#else + u16 *reflection_target = &fpga->reflection_high; +#endif /* * wait for fpga out of reset */ @@ -117,9 +122,11 @@ int board_early_init_f(void) while (1) { out_le16(&fpga->reflection_low, REFLECTION_TESTPATTERN); - if (in_le16(&fpga->reflection_high) == + + if (in_le16(reflection_target) == REFLECTION_TESTPATTERN_INV) break; + udelay(100000); if (ctr++ > 5) { gd->fpga_state[k] |= diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index d7b4fb2..0388541 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -34,6 +34,8 @@ #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) #define LATCH2_MC2_PRESENT_N 0x0080 +#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) + enum { UNITTYPE_VIDEO_USER = 0, UNITTYPE_MAIN_USER = 1, @@ -63,6 +65,20 @@ enum { RAM_DDR2_64 = 2, }; +static unsigned int get_hwver(void) +{ + u16 latch3 = in_le16((void *)LATCH3_BASE); + + return latch3 & 0x0003; +} + +static unsigned int get_mc2_present(void) +{ + u16 latch2 = in_le16((void *)LATCH2_BASE); + + return !(latch2 & LATCH2_MC2_PRESENT_N); +} + static void print_fpga_info(unsigned dev) { ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev); @@ -210,7 +226,6 @@ static void print_fpga_info(unsigned dev) int checkboard(void) { char *s = getenv("serial#"); - u16 latch2 = in_le16((void *)LATCH2_BASE); printf("Board: "); @@ -224,7 +239,7 @@ int checkboard(void) puts("\n"); print_fpga_info(0); - if (!(latch2 & LATCH2_MC2_PRESENT_N)) + if (get_mc2_present()) print_fpga_info(1); return 0; @@ -234,15 +249,15 @@ int last_stage_init(void) { ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); u16 versions = in_le16(&fpga->versions); - u16 latch2 = in_le16((void *)LATCH2_BASE); if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER) return 0; - if (!get_fpga_state(0)) + if (!get_fpga_state(0) || (get_hwver() == HWVER_101)) osd_probe(0); - if (!(latch2 & LATCH2_MC2_PRESENT_N) && !get_fpga_state(1)) + if (get_mc2_present() && + (!get_fpga_state(1) || (get_hwver() == HWVER_101))) osd_probe(1); return 0; diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index ae209fa..548b7eb 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -136,6 +136,8 @@ #define CONFIG_SYS_LATCH1_RESET 0xffcf #define CONFIG_SYS_LATCH1_BOOT 0xffff +#define CONFIG_SYS_FPGA_NO_RFL_HI + /* * FLASH organization */ diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 1fccd27..eaf6daa 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -94,13 +94,11 @@ typedef struct ihs_fpga { u16 extended_interrupt; /* 0x001c */ u16 reserved_1[9]; /* 0x001e */ ihs_i2c_t i2c; /* 0x0030 */ - u16 reserved_2[35]; /* 0x0038 */ - u16 reflection_high; /* 0x007e */ - u16 reserved_3[15]; /* 0x0080 */ + u16 reserved_2[51]; /* 0x0038 */ u16 videocontrol; /* 0x009e */ - u16 reserved_4[176]; /* 0x00a0 */ + u16 reserved_3[176]; /* 0x00a0 */ ihs_osd_t osd; /* 0x0200 */ - u16 reserved_5[764]; /* 0x0208 */ + u16 reserved_4[764]; /* 0x0208 */ u16 videomem; /* 0x0800 */ } ihs_fpga_t; #endif -- cgit v1.1 From 52158e361606fffca89136481db720fdaab608d0 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 6 Apr 2011 13:53:47 +0200 Subject: ppc4xx: Set DLVision 10G osd position to linux defaults Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- board/gdsys/common/osd.c | 2 ++ include/gdsys_fpga.h | 7 +++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 6e4edae..5065f9d 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -376,6 +376,8 @@ int osd_probe(unsigned screen) out_le16(&osd->control, 0x0049); out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1)); + out_le16(&osd->x_pos, 0x007f); + out_le16(&osd->y_pos, 0x005f); return 0; } diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index eaf6daa..b02e28c 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -50,6 +50,9 @@ typedef struct ihs_osd { u16 features; u16 control; u16 xy_size; + u16 xy_scale; + u16 x_pos; + u16 y_pos; } ihs_osd_t; #ifdef CONFIG_IO @@ -79,7 +82,7 @@ typedef struct ihs_fpga { u16 reserved_2[93]; /* 0x0044 */ u16 reflection_high; /* 0x00fe */ ihs_osd_t osd; /* 0x0100 */ - u16 reserved_3[892]; /* 0x0108 */ + u16 reserved_3[88]; /* 0x010e */ u16 videomem; /* 0x0800 */ } ihs_fpga_t; #endif @@ -98,7 +101,7 @@ typedef struct ihs_fpga { u16 videocontrol; /* 0x009e */ u16 reserved_3[176]; /* 0x00a0 */ ihs_osd_t osd; /* 0x0200 */ - u16 reserved_4[764]; /* 0x0208 */ + u16 reserved_4[761]; /* 0x020e */ u16 videomem; /* 0x0800 */ } ihs_fpga_t; #endif -- cgit v1.1 From 7749c84e9d3a00b16b764368e727a5c12e0c4493 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 6 Apr 2011 13:53:48 +0200 Subject: ppc4xx: Enable MPC92469AC on DLVision 10G Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- include/configs/dlvision-10g.h | 1 + include/gdsys_fpga.h | 8 +++++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index 548b7eb..368aceb 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -312,6 +312,7 @@ * OSD Setup */ #define CONFIG_SYS_ICS8N3QV01 +#define CONFIG_SYS_MPC92469AC #define CONFIG_SYS_SIL1178 #define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index b02e28c..c0b1b5c 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -97,11 +97,13 @@ typedef struct ihs_fpga { u16 extended_interrupt; /* 0x001c */ u16 reserved_1[9]; /* 0x001e */ ihs_i2c_t i2c; /* 0x0030 */ - u16 reserved_2[51]; /* 0x0038 */ + u16 reserved_2[16]; /* 0x0038 */ + u16 mpc3w_control; /* 0x0058 */ + u16 reserved_3[34]; /* 0x005a */ u16 videocontrol; /* 0x009e */ - u16 reserved_3[176]; /* 0x00a0 */ + u16 reserved_4[176]; /* 0x00a0 */ ihs_osd_t osd; /* 0x0200 */ - u16 reserved_4[761]; /* 0x020e */ + u16 reserved_5[761]; /* 0x020e */ u16 videomem; /* 0x0800 */ } ihs_fpga_t; #endif -- cgit v1.1 From 6c57c88dd27152770b1e913a3db1a8afe9247a8d Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 6 Apr 2011 13:53:49 +0200 Subject: ppc4xx: Improve fan PWM curve on DLVision 10G Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- include/configs/dlvision-10g.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index 368aceb..c3f7438 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -113,7 +113,8 @@ #define CONFIG_DTT_LM63 1 /* National LM63 */ #define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */ #define CONFIG_DTT_PWM_LOOKUPTABLE \ - { { 40, 10 }, { 50, 20 }, { 60, 40 } } + { { 40, 10 }, { 43, 13 }, { 46, 16 }, \ + { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } } #define CONFIG_DTT_TACH_LIMIT 0xa10 /* EBC peripherals */ -- cgit v1.1 From 6cfa9eecb4409b1b4e8b4753b2ddfbe33e28bd93 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 6 Apr 2011 13:53:50 +0200 Subject: ppc4xx: Do not stop booting on any keypress on dlvision-10g Use CONFIG_AUTOBOOT_KEYED on dlvision-10g so that booting can only be stopped with well defined keypresses. Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- include/configs/dlvision-10g.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index c3f7438..4fc5262 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -42,6 +42,10 @@ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ +#define CONFIG_AUTOBOOT_STOP_STR " " + /* * Configure PLL */ -- cgit v1.1