From 70bfb032ec592c99f78791305641b22f85fb52db Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 21 Jul 2011 16:50:22 -0500 Subject: powerpc/85xx: Fix setting of EPAPR_MAGIC value Had a typo in the ifdef for 85xx, should be CONFIG_MPC85xx for it to get triggered. Was pull in the non-BookE magic number. Reported-by: John Cortell Signed-off-by: Kumar Gala --- arch/powerpc/lib/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 4e0cb8f..05adada 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -87,7 +87,7 @@ static void boot_jump_linux(bootm_headers_t *images) * r8: 0 * r9: 0 */ -#if defined(CONFIG_85xx) || defined(CONFIG_440) +#if defined(CONFIG_MPC85xx) || defined(CONFIG_440) #define EPAPR_MAGIC (0x45504150) #else #define EPAPR_MAGIC (0x65504150) -- cgit v1.1 From f110fe940c7bca04cf0104952555fd931b075fac Mon Sep 17 00:00:00 2001 From: Stephen George Date: Wed, 20 Jul 2011 09:47:26 -0500 Subject: powerpc/85xx: Adding configuration for DCSRCR to enable 32M access Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 11 +++++++++++ arch/powerpc/include/asm/immap_85xx.h | 7 ++++++- board/freescale/corenet_ds/law.c | 3 ++- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b3da970..f1f80f7 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -222,6 +222,10 @@ static void corenet_tb_init(void) void cpu_init_f (void) { extern void m8560_cpm_reset (void); +#ifdef CONFIG_SYS_DCSRBAR_PHYS + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + #ifdef CONFIG_MPC8548 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); uint svr = get_svr(); @@ -262,6 +266,13 @@ void cpu_init_f (void) /* Invalidate the CPC before DDR gets enabled */ invalidate_cpc(); + + #ifdef CONFIG_SYS_DCSRBAR_PHYS + /* set DCSRCR so that DCSR space is 1G */ + setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); + in_be32(&gur->dcsrcr); +#endif + } /* Implement a dummy function for those platforms w/o SERDES */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 267a940..6aaade0 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,7 +1759,8 @@ typedef struct ccsr_gur { u32 cgencrl; /* Core general control */ u8 res31[184]; u32 sriopstecr; /* SRIO prescaler timer enable control */ - u8 res32[1788]; + u32 dcsrcr; /* DCSR Control register */ + u8 res32[1784]; u32 pmuxcr; /* Pin multiplexing control */ u8 res33[60]; u32 iovselsr; /* I/O voltage selection status */ @@ -1772,6 +1773,10 @@ typedef struct ccsr_gur { u8 res37[380]; } ccsr_gur_t; +#define FSL_CORENET_DCSR_SZ_MASK 0x00000003 +#define FSL_CORENET_DCSR_SZ_4M 0x0 +#define FSL_CORENET_DCSR_SZ_1G 0x3 + /* * On p4080 we have an LIODN for msg unit (rmu) but not maintenance * everything after has RMan thus msg unit LIODN is used for maintenance diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/corenet_ds/law.c index dd6f6f7..58f23c5 100644 --- a/board/freescale/corenet_ds/law.c +++ b/board/freescale/corenet_ds/law.c @@ -37,7 +37,8 @@ struct law_entry law_table[] = { #endif SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), #ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -- cgit v1.1 From 88b91f2d3b71101830e58f48cf31e6cefa25b1c8 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 21 Jul 2011 00:20:19 -0500 Subject: powerpc/85xx: Rename P2040 id & SERDES to P2041 P2041 is the superset part that covers both P2040 & P2041. The only difference between the two devices is that P2041 supports 10g/XAUI and has an L2 cache. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 6 +- arch/powerpc/cpu/mpc85xx/p2040_ids.c | 109 -------------------------------- arch/powerpc/cpu/mpc85xx/p2040_serdes.c | 90 -------------------------- arch/powerpc/cpu/mpc85xx/p2041_ids.c | 109 ++++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/p2041_serdes.c | 90 ++++++++++++++++++++++++++ 5 files changed, 202 insertions(+), 202 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc85xx/p2040_ids.c delete mode 100644 arch/powerpc/cpu/mpc85xx/p2040_serdes.c create mode 100644 arch/powerpc/cpu/mpc85xx/p2041_ids.c create mode 100644 arch/powerpc/cpu/mpc85xx/p2041_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 8a0a8e9..7026bca 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -78,8 +78,8 @@ COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments -COBJS-$(CONFIG_PPC_P2040) += p2040_ids.o -COBJS-$(CONFIG_PPC_P2041) += p2040_ids.o +COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o +COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o @@ -111,7 +111,7 @@ COBJS-$(CONFIG_P1024) += p1021_serdes.o COBJS-$(CONFIG_P1025) += p1021_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o -COBJS-$(CONFIG_PPC_P2040) += p2040_serdes.o +COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/p2040_ids.c b/arch/powerpc/cpu/mpc85xx/p2040_ids.c deleted file mode 100644 index 112ea56..0000000 --- a/arch/powerpc/cpu/mpc85xx/p2040_ids.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { - /* dqrr liodn, frame data liodn, liodn off, sdest */ - SET_QP_INFO( 1, 2, 1, 0), - SET_QP_INFO( 3, 4, 2, 1), - SET_QP_INFO( 5, 6, 3, 2), - SET_QP_INFO( 7, 8, 4, 3), - SET_QP_INFO( 9, 10, 5, 4), - SET_QP_INFO( 0, 0, 0, 5), - SET_QP_INFO( 0, 0, 0, 6), - SET_QP_INFO( 0, 0, 0, 7), - SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ - SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ -}; -#endif - -struct liodn_id_table liodn_tbl[] = { -#ifdef CONFIG_SYS_DPAA_QBMAN - SET_QMAN_LIODN(31), - SET_BMAN_LIODN(32), -#endif - - SET_SDHC_LIODN(1, 64), - - SET_PME_LIODN(117), - - SET_USB_LIODN(1, "fsl-usb2-mph", 125), - SET_USB_LIODN(2, "fsl-usb2-dr", 126), - - SET_SATA_LIODN(1, 127), - SET_SATA_LIODN(2, 128), - - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), - - SET_DMA_LIODN(1, 197), - SET_DMA_LIODN(2, 198), - - SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), - SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), - SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), - SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), -}; -int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); - -#ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { - SET_FMAN_RX_1G_LIODN(1, 0, 10), - SET_FMAN_RX_1G_LIODN(1, 1, 11), - SET_FMAN_RX_1G_LIODN(1, 2, 12), - SET_FMAN_RX_1G_LIODN(1, 3, 13), - SET_FMAN_RX_1G_LIODN(1, 4, 14), -#if (CONFIG_SYS_NUM_FM1_10GEC == 1) - SET_FMAN_RX_10G_LIODN(1, 0, 15), -#endif -}; -int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#endif - -struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JR_LIODN_ENTRY(0, 129, 130), - SET_SEC_JR_LIODN_ENTRY(1, 131, 132), - SET_SEC_JR_LIODN_ENTRY(2, 133, 134), - SET_SEC_JR_LIODN_ENTRY(3, 135, 136), - SET_SEC_RTIC_LIODN_ENTRY(a, 154), - SET_SEC_RTIC_LIODN_ENTRY(b, 155), - SET_SEC_RTIC_LIODN_ENTRY(c, 156), - SET_SEC_RTIC_LIODN_ENTRY(d, 157), - SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), - SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), -}; -int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); - -struct liodn_id_table liodn_bases[] = { - [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), -#ifdef CONFIG_SYS_DPAA_FMAN - [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), -#endif -#ifdef CONFIG_SYS_DPAA_PME - [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), -#endif -}; diff --git a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c deleted file mode 100644 index 83bc82f..0000000 --- a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include "fsl_corenet_serdes.h" - -static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { - [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, - NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, - [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, - NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, - [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, - PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1, - SATA2, NONE, NONE, NONE, NONE, }, - [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, - PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, - NONE, NONE, NONE, NONE, NONE, NONE, }, - [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, - PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3, - PCIE3, NONE, NONE, NONE, NONE, }, - [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, - SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, - [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, - PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA, - SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, - NONE, NONE, NONE, }, - [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, - NONE, NONE, NONE, }, - [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE, - NONE, NONE, NONE, NONE, NONE, }, - [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, - PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, - NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, - [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, - SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, - NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, - [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA, - SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, }, -}; - -enum srds_prtcl serdes_get_prtcl(int cfg, int lane) -{ - if (!serdes_lane_enabled(lane)) - return NONE; - - return serdes_cfg_tbl[cfg][lane]; -} - -int is_serdes_prtcl_valid(u32 prtcl) -{ - int i; - - if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) - return 0; - - for (i = 0; i < SRDS_MAX_LANES; i++) { - if (serdes_cfg_tbl[prtcl][i] != NONE) - return 1; - } - - return 0; -} diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c new file mode 100644 index 0000000..112ea56 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -0,0 +1,109 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO( 1, 2, 1, 0), + SET_QP_INFO( 3, 4, 2, 1), + SET_QP_INFO( 5, 6, 3, 2), + SET_QP_INFO( 7, 8, 4, 3), + SET_QP_INFO( 9, 10, 5, 4), + SET_QP_INFO( 0, 0, 0, 5), + SET_QP_INFO( 0, 0, 0, 6), + SET_QP_INFO( 0, 0, 0, 7), + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ +}; +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), +#endif + + SET_SDHC_LIODN(1, 64), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 125), + SET_USB_LIODN(2, "fsl-usb2-dr", 126), + + SET_SATA_LIODN(1, 127), + SET_SATA_LIODN(2, 128), + + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + + SET_DMA_LIODN(1, 197), + SET_DMA_LIODN(2, 198), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 10), + SET_FMAN_RX_1G_LIODN(1, 1, 11), + SET_FMAN_RX_1G_LIODN(1, 2, 12), + SET_FMAN_RX_1G_LIODN(1, 3, 13), + SET_FMAN_RX_1G_LIODN(1, 4, 14), +#if (CONFIG_SYS_NUM_FM1_10GEC == 1) + SET_FMAN_RX_10G_LIODN(1, 0, 15), +#endif +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 129, 130), + SET_SEC_JR_LIODN_ENTRY(1, 131, 132), + SET_SEC_JR_LIODN_ENTRY(2, 133, 134), + SET_SEC_JR_LIODN_ENTRY(3, 135, 136), + SET_SEC_RTIC_LIODN_ENTRY(a, 154), + SET_SEC_RTIC_LIODN_ENTRY(b, 155), + SET_SEC_RTIC_LIODN_ENTRY(c, 156), + SET_SEC_RTIC_LIODN_ENTRY(d, 157), + SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), + SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c new file mode 100644 index 0000000..83bc82f --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c @@ -0,0 +1,90 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, + [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, + [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1, + SATA2, NONE, NONE, NONE, NONE, }, + [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, NONE, }, + [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3, + PCIE3, NONE, NONE, NONE, NONE, }, + [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, + SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, + [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, + NONE, NONE, NONE, }, + [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, + NONE, NONE, NONE, }, + [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, }, + [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, + NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, + [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, + SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, + NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, + [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA, + SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, }, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(u32 prtcl) +{ + int i; + + if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} -- cgit v1.1 From db564bccefaa537b4a2bd46778b00536bab17258 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 21 Jul 2011 00:20:20 -0500 Subject: powerpc/85xx: Add support for P2041[e] XAUI in SERDES We add XAUI_FM1 into the SERDES tables for P2041[e] devices. However for the P2040[e] devices that dont support XAUI we handle this at runtime via SVR checks. If we are on a P2040[e] device the SERDES functions will behave as follows: is_serdes_prtcl_valid() will always report invalid if prtcl passed in is XAUI_FM1. serdes_get_prtcl() will report NONE if the prtcl in the table is set to XAUI_FM1. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/p2041_serdes.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c index 83bc82f..f68f281 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c @@ -37,8 +37,8 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, - PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, - NONE, NONE, NONE, NONE, NONE, NONE, }, + PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, }, [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, NONE, NONE, }, @@ -53,8 +53,8 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE, - NONE, NONE, NONE, NONE, NONE, }, + SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1, + XAUI_FM1, NONE, NONE, NONE, NONE, }, [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, @@ -68,19 +68,35 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { enum srds_prtcl serdes_get_prtcl(int cfg, int lane) { + enum srds_prtcl prtcl; + u32 svr = get_svr(); + u32 ver = SVR_SOC_VER(svr); + if (!serdes_lane_enabled(lane)) return NONE; - return serdes_cfg_tbl[cfg][lane]; + prtcl = serdes_cfg_tbl[cfg][lane]; + + /* P2040[e] does not support XAUI */ + if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + prtcl = NONE; + + return prtcl; } int is_serdes_prtcl_valid(u32 prtcl) { int i; + u32 svr = get_svr(); + u32 ver = SVR_SOC_VER(svr); if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) return 0; + /* P2040[e] does not support XAUI */ + if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + return 0; + for (i = 0; i < SRDS_MAX_LANES; i++) { if (serdes_cfg_tbl[prtcl][i] != NONE) return 1; -- cgit v1.1 From acf3f8da98fdd432a7b0bbcc8c94d706f1bb5c72 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 21 Jul 2011 00:20:21 -0500 Subject: powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E The P2040/P2040E have no L2 cache. So we utilize the SVR to determine if we are one of these devices and skip the L2 init code in cpu_init.c and release. For the device tree we skip the updating of the L2 cache properties but we still update the chain of caches so the CPC/L3 node can be properly updated. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 ++++++++ arch/powerpc/cpu/mpc85xx/fdt.c | 23 +++++++++++++++-------- arch/powerpc/cpu/mpc85xx/release.S | 15 ++++++++++++++- 3 files changed, 37 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index f1f80f7..6aca166 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -392,6 +392,12 @@ int cpu_init_r(void) puts("enabled\n"); } #elif defined(CONFIG_BACKSIDE_L2_CACHE) + if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || + (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) { + puts("N/A\n"); + goto skip_l2; + } + u32 l2cfg0 = mfspr(SPRN_L2CFG0); /* invalidate the L2 cache */ @@ -412,6 +418,8 @@ int cpu_init_r(void) ; printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); } + +skip_l2: #else puts("disabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 812bb3f..c49f59b 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -228,6 +228,12 @@ static inline void ft_fixup_l2cache(void *blob) u32 *ph; u32 l2cfg0 = mfspr(SPRN_L2CFG0); u32 size, line_size, num_ways, num_sets; + int has_l2 = 1; + + /* P2040/P2040E has no L2, so dont set any L2 props */ + if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || + (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) + has_l2 = 0; size = (l2cfg0 & 0x3fff) * 64 * 1024; num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; @@ -250,21 +256,22 @@ static inline void ft_fixup_l2cache(void *blob) goto next; } + if (has_l2) { #ifdef CONFIG_SYS_CACHE_STASHING - { u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); if (reg) fdt_setprop_cell(blob, l2_off, "cache-stash-id", (*reg * 2) + 32 + 1); - } #endif - fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); - fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); - fdt_setprop_cell(blob, l2_off, "cache-size", size); - fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); - fdt_setprop_cell(blob, l2_off, "cache-level", 2); - fdt_setprop(blob, l2_off, "compatible", "cache", 6); + fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, l2_off, "cache-block-size", + line_size); + fdt_setprop_cell(blob, l2_off, "cache-size", size); + fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); + fdt_setprop_cell(blob, l2_off, "cache-level", 2); + fdt_setprop(blob, l2_off, "compatible", "cache", 6); + } if (l3_off < 0) { ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 56a853e..6678ed4 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * Kumar Gala * * See file CREDITS for list of people who contributed to this @@ -144,6 +144,18 @@ __secondary_start_page: #endif #ifdef CONFIG_BACKSIDE_L2_CACHE + /* skip L2 setup on P2040/P2040E as they have no L2 */ + mfspr r2,SPRN_SVR + lis r3,SVR_P2040@h + ori r3,r3,SVR_P2040@l + cmpw r2,r3 + beq 3f + + lis r3,SVR_P2040_E@h + ori r3,r3,SVR_P2040_E@l + cmpw r2,r3 + beq 3f + /* Enable/invalidate the L2 cache */ msync lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h @@ -169,6 +181,7 @@ __secondary_start_page: andis. r1,r3,L2CSR0_L2E@h beq 2b #endif +3: #define EPAPR_MAGIC (0x45504150) #define ENTRY_ADDR_UPPER 0 -- cgit v1.1 From cd420e0b2a8966300b108c7fdab2608e12179404 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Thu, 21 Jul 2011 17:03:54 -0500 Subject: powerpc/p2041rdb: Enable backside L2 cache support Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- include/configs/P2041RDB.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 2beb357..c35d763 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -108,6 +108,8 @@ * These can be toggled for performance analysis, otherwise use default. */ #define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ENABLE_36BIT_PHYS -- cgit v1.1 From 0a9fe8ee7e5c4d1d677fab71514d4f4a9be2f6be Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Mon, 23 May 2011 08:38:53 +0000 Subject: powerpc/85xx: provide 85xx flush_icache for cmd_cache This provides a function that will override the weak function flush_icache to let 85xx boards to flush the icache cc: Kumar Gala Signed-off-by: Matthew McClintock --- arch/powerpc/cpu/mpc85xx/start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 626ccce..878a3d6 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -676,6 +676,8 @@ mck_return: /* Cache functions. */ +.globl flush_icache +flush_icache: .globl invalidate_icache invalidate_icache: mfspr r0,L1CSR1 -- cgit v1.1 From 28415b62d1fe0b12e5a48743285ed52502d75004 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 25 Jul 2011 15:15:44 +0200 Subject: 85xx: enable FDT support for STX SSA board We also have to shift TEXT_BASE to accomodate for the additional code size. Signed-off-by: Wolfgang Denk Signed-off-by: Kumar Gala --- board/stx/stxssa/stxssa.c | 8 ++++++++ include/configs/stxssa.h | 7 ++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index 83ffcd2..3077eb3 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -247,6 +248,13 @@ reset_phy(void) #endif } +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup (blob, bd); +} +#endif /* CONFIG_OF_BOARD_SETUP */ + int board_early_init_f(void) { diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index d5dd94f..141da26 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -43,7 +43,7 @@ #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ #define CONFIG_MPC8560 1 -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 +#define CONFIG_SYS_TEXT_BASE 0xFFF80000 #define CONFIG_PCI /* PCI ethernet support */ #define CONFIG_TSEC_ENET /* tsec ethernet support*/ @@ -194,6 +194,11 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + /* * I2C */ -- cgit v1.1 From 65bb8b060a873fa4f5188f2951081f6011259614 Mon Sep 17 00:00:00 2001 From: Bhaskar Upadhaya Date: Fri, 4 Mar 2011 20:27:58 +0530 Subject: powerpc/85xx: Fix up clock_freq property in CAN node of dts Fix up the device tree property associated with the Flexcan clock frequency. This property is used to calculate the bit timing parameters for Flexcan. Signed-off-by: Bhaskar Upadhaya Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/fdt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index c49f59b..c62b12f 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -635,4 +635,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) */ do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", "timer-frequency", gd->bus_clk/2, 1); + + do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", + "clock_freq", gd->bus_clk, 1); } -- cgit v1.1 From 8992738db72f817e99f25ec4c675e67d0e702a3d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 25 Jul 2011 09:28:39 -0500 Subject: powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500 At some point we broke the detection of e500v1 class cores. Fix that and simply the code to just utilize PVR_VER() to have a single case statement. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu.c | 32 +++++++++++++------------------- arch/powerpc/include/asm/processor.h | 4 ++++ 2 files changed, 17 insertions(+), 19 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index ce59c25..976e86e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -46,7 +46,6 @@ int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; - uint fam; uint ver; uint major, minor; struct cpu_type *cpu; @@ -94,30 +93,25 @@ int checkcpu (void) printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); - fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); - if (PVR_FAM(PVR_85xx)) { - switch(PVR_MEM(pvr)) { - case 0x1: - case 0x2: - puts("E500"); - break; - case 0x3: - puts("E500MC"); - break; - case 0x4: - puts("E5500"); - break; - default: - puts("Unknown"); - break; - } - } else { + switch(ver) { + case PVR_VER_E500_V1: + case PVR_VER_E500_V2: + puts("E500"); + break; + case PVR_VER_E500MC: + puts("E500MC"); + break; + case PVR_VER_E5500: + puts("E5500"); + break; + default: puts("Unknown"); + break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 9c4651a..0c4cc25 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -938,6 +938,10 @@ #define PVR_85xx 0x80200000 #define PVR_85xx_REV1 (PVR_85xx | 0x0010) #define PVR_85xx_REV2 (PVR_85xx | 0x0020) +#define PVR_VER_E500_V1 0x8020 +#define PVR_VER_E500_V2 0x8021 +#define PVR_VER_E500MC 0x8023 +#define PVR_VER_E5500 0x8024 #define PVR_86xx 0x80040000 -- cgit v1.1 From aa7f281ce4af14a95f1df88bf32d828562fb4604 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Wed, 27 Jul 2011 09:55:51 +0800 Subject: powerpc/p2041rdb: Enable SATA support Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- include/configs/P2041RDB.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index c35d763..638dbe7 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -454,6 +454,26 @@ #define CONFIG_DOS_PARTITION #endif /* CONFIG_PCI */ +/* SATA */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 -- cgit v1.1 From 74d9d5239f5eb5ae6b6ed92d13db304d4bd2f699 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 28 Jul 2011 14:34:30 -0500 Subject: powerpc/85xx: Fix build failure for P1023RDS When we added the fman fdt fixup we forgot to fixup the P1023RDS platform. So we would get: fdt.c: In function 'fdt_fixup_fman_firmware': fdt.c:465:15: error: 'CONFIG_SYS_FMAN_FW_LENGTH' undeclared (first use in this function) fdt.c:465:15: note: each undeclared identifier is reported only once for each function it appears in Add the needed #defines in P1023RDS.h to fix this. Signed-off-by: Kumar Gala --- include/configs/P1023RDS.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index 4f14a02..95f3a2c 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -536,16 +536,16 @@ extern unsigned long get_clock_freq(void); #define CONFIG_FMAN_ENET #endif +#define CONFIG_SYS_FMAN_FW #ifndef CONFIG_NAND /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 -#define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR #else #define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000 -#define CONFIG_SYS_FMAN_FW_ADDR 0x10000000 -#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 #endif +#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 -- cgit v1.1 From 21cd5815a7e956e689ac78be2ade05e61fd5dce7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 25 Jul 2011 10:13:53 +0200 Subject: MPC8xxx: drop redundant boot messages Current code would print RAM size information like this: DRAM: DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Turn a number of printf()s into debug() to get rid of the redundant "DDR: " string like this: DRAM: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Signed-off-by: Wolfgang Denk Acked-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- board/freescale/corenet_ds/ddr.c | 2 +- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 2 +- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 2 +- board/freescale/p2041rdb/ddr.c | 2 +- board/sbc8641d/sbc8641d.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 976e86e..22fa461 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -352,7 +352,7 @@ phys_size_t initdram(int board_type) lbc_sdram_init(); #endif - puts("DDR: "); + debug("DDR: "); return dram_size; } #endif /* CONFIG_SYS_RAMBOOT */ diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index a184592..b937015 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -256,6 +256,6 @@ phys_size_t initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); + debug(" DDR: "); return dram_size; } diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 4e4b7c0..8aceddb 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -145,7 +145,7 @@ initdram(int board_type) setup_ddr_bat(dram_size); - puts(" DDR: "); + debug(" DDR: "); return dram_size; } diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index e3916fc..455569e 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -69,7 +69,7 @@ initdram(int board_type) setup_ddr_bat(dram_size); - puts(" DDR: "); + debug(" DDR: "); return dram_size; } diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c index 46de910..e9c699c 100644 --- a/board/freescale/p2041rdb/ddr.c +++ b/board/freescale/p2041rdb/ddr.c @@ -110,6 +110,6 @@ phys_size_t initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); + debug(" DDR: "); return dram_size; } diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index dd58541..bed8f53 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -63,7 +63,7 @@ phys_size_t initdram (int board_type) dram_size = fixed_sdram (); #endif - puts (" DDR: "); + debug (" DDR: "); return dram_size; } -- cgit v1.1 From 90f89f099d0741ed5557adbce4a2dde96887a824 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 3 May 2011 13:24:08 -0500 Subject: powerpc/85xx: verify the device tree before booting Linux Introduce ft_verify_fdt(), a function that is called after the device tree has been fixed up, that displays warning messages if there is a mismatch between the physical addresses of some devices that U-Boot has configured with what the device tree says the addresses are. This is a particular problem when booting a 36-bit device tree from a 32-bit U-Boot (or vice versa), because the physical address of CCSR is wrong in the device tree. When the operating system boots, no messages are displayed, so the user generally has no idea what's wrong. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/fdt.c | 72 ++++++++++++++++++++++++++++++++++++++++++ arch/powerpc/lib/bootm.c | 21 ++++++++++++ 2 files changed, 93 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index c62b12f..8f13cd8 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -639,3 +639,75 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", "clock_freq", gd->bus_clk, 1); } + +/* + * For some CCSR devices, we only have the virtual address, not the physical + * address. This is because we map CCSR as a whole, so we typically don't need + * a macro for the physical address of any device within CCSR. In this case, + * we calculate the physical address of that device using it's the difference + * between the virtual address of the device and the virtual address of the + * beginning of CCSR. + */ +#define CCSR_VIRT_TO_PHYS(x) \ + (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) + +/* + * Verify the device tree + * + * This function compares several CONFIG_xxx macros that contain physical + * addresses with the corresponding nodes in the device tree, to see if + * the physical addresses are all correct. For example, if + * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address + * of the first UART. We convert this to a physical address and compare + * that with the physical address of the first ns16550-compatible node + * in the device tree. If they don't match, then we display a warning. + * + * Returns 1 on success, 0 on failure + */ +int ft_verify_fdt(void *fdt) +{ + uint64_t ccsr = 0; + int aliases; + int off; + + /* First check the CCSR base address */ + off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); + if (off > 0) + ccsr = fdt_get_base_address(fdt, off); + + if (!ccsr) { + printf("Warning: could not determine base CCSR address in " + "device tree\n"); + /* No point in checking anything else */ + return 0; + } + + if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) { + printf("Warning: U-Boot configured CCSR at address %llx,\n" + "but the device tree has it at %llx\n", + (uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr); + /* No point in checking anything else */ + return 0; + } + + /* + * Get the 'aliases' node. If there isn't one, then there's nothing + * left to do. + */ + aliases = fdt_path_offset(fdt, "/aliases"); + if (aliases > 0) { +#ifdef CONFIG_SYS_NS16550_COM1 + if (!fdt_verify_alias_address(fdt, aliases, "serial0", + CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) + return 0; +#endif + +#ifdef CONFIG_SYS_NS16550_COM2 + if (!fdt_verify_alias_address(fdt, aliases, "serial1", + CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) + return 0; +#endif + } + + return 1; +} diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 05adada..1375474 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -226,6 +226,24 @@ static int boot_bd_t_linux(bootm_headers_t *images) return ret; } +/* + * Verify the device tree. + * + * This function is called after all device tree fix-ups have been enacted, + * so that the final device tree can be verified. The definition of "verified" + * is up to the specific implementation. However, it generally means that the + * addresses of some of the devices in the device tree are compared with the + * actual addresses at which U-Boot has placed them. + * + * Returns 1 on success, 0 on failure. If 0 is returned, U-boot will halt the + * boot process. + */ +static int __ft_verify_fdt(void *fdt) +{ + return 1; +} +__attribute__((weak, alias("__ft_verify_fdt"))) int ft_verify_fdt(void *fdt); + static int boot_body_linux(bootm_headers_t *images) { ulong rd_len; @@ -298,6 +316,9 @@ static int boot_body_linux(bootm_headers_t *images) /* fixup the initrd now that we know where it should be */ if (*initrd_start && *initrd_end) fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); + + if (!ft_verify_fdt(*of_flat_tree)) + return -1; } #endif /* CONFIG_OF_LIBFDT */ return 0; -- cgit v1.1 From a3a3e7b2c35d8bb3c3b6944cb9381d7f66f7875d Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Thu, 28 Jul 2011 16:17:32 +0800 Subject: powerpc/85xx: enable USB2 gadget mode for corenet ds board to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to 'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break out if it cannot find 'usb1', so drop the 'else' clause to make driver scan all the 'usbx'. Signed-off-by: Shaohui Xie Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/fdt.c | 2 -- board/freescale/corenet_ds/corenet_ds.c | 1 + include/configs/corenet_ds.h | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index d9e3e7e..6c757f8 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -163,8 +163,6 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) usb1_defined = 1; if (mode_idx < 0 && phy_idx < 0) printf("WARNING: invalid phy or mode\n"); - } else { - break; } } if (!usb1_defined) { diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index cf9b7b8..b1e7823 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -236,6 +236,7 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); } int board_eth_init(bd_t *bis) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 0b7becb..adf9906 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -595,6 +595,7 @@ #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB #define CONFIG_MMC -- cgit v1.1 From 57567361769bfa02d0622c06e5e9f66392e2593a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 29 Jul 2011 08:51:26 -0500 Subject: powerpc/8xxx: Remove dependency on We used for USB_MAX_DEVICE. However this requires we actual build in support for USB into u-boot (which should not be required for device tree fixup). At this time no FSL SoC that utilizies this code (83xx/85xx) has more than 2 USB controllers. So we replace USB_MAX_DEVICE with a local define FSL_MAX_NUM_USB_CTRLS. If/when a device shows up with more than 2 controllers we can easily bump this value or refactor into a proper define per SoC. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/fdt.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 6c757f8..285051d 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -30,9 +30,8 @@ #include #include #include -#ifdef CONFIG_HAS_FSL_DR_USB -#include -#endif + +#define FSL_MAX_NUM_USB_CTRLS 2 #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -135,7 +134,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) char str[5]; int i, j; - for (i = 1; i <= USB_MAX_DEVICE; i++) { + for (i = 1; i <= FSL_MAX_NUM_USB_CTRLS; i++) { int mode_idx = -1, phy_idx = -1; sprintf(str, "%s%d", "usb", i); if (hwconfig(str)) { -- cgit v1.1