From 193b4a3bb3acaddf798da8de0da05d94ba8774ee Mon Sep 17 00:00:00 2001
From: Jeffrey Mann <mannj@embeddedplanet.com>
Date: Mon, 7 May 2007 19:42:49 +0200
Subject: [PATCH] ppc4xx: Fix CONFIG_SYS_CLK_FREQ definition in Sequoia config
 file

A '3' got cut off in the formatting of the last patch to automatically
change the clock speed of the system clock on sequoia board.

Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/sequoia.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index b7f79c2..e1572ba 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -40,7 +40,7 @@
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 /* Detect Sequoia PLL input clock automatically via CPLD bit		*/
 #define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
-				3333333 : 33000000)
+				33333333 : 33000000)
 
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
-- 
cgit v1.1


From 343c48bd84606c4025c8a7c7263fda465d6e284c Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Fri, 11 May 2007 12:01:06 +0200
Subject: ppc4xx: Set bd->bi_pci_busfreq on 440EPx/GRx too

Signed-off-by: Stefan Roese <sr@denx.de>
---
 lib_ppc/board.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 24e8e97..f37a86a 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -568,7 +568,9 @@ void board_init_f (ulong bootflag)
 
 	bd->bi_procfreq = gd->cpu_clk;	/* Processor Speed, In Hz */
 	bd->bi_plb_busfreq = gd->bus_clk;
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	bd->bi_pci_busfreq = get_PCI_freq ();
 	bd->bi_opbfreq = get_OPB_freq ();
 #elif defined(CONFIG_XILINX_ML300)
-- 
cgit v1.1


From 61936667e86a250ae12fd2dc189d3588f0a59e0b Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Fri, 11 May 2007 12:01:49 +0200
Subject: ppc4xx: Add mtcpr/mfcpr access macros

Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/ppc440.h | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/include/ppc440.h b/include/ppc440.h
index bc1d7aa..07f75de 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1425,9 +1425,6 @@
 /*----------------------------------------------------------------------------+
 | Clock / Power-on-reset DCR's.
 +----------------------------------------------------------------------------*/
-#define CPR0_CFGADDR			0x00C
-#define CPR0_CFGDATA			0x00D
-
 #define CPR0_CLKUPD			0x20
 #define CPR0_CLKUPD_BSY_MASK		0x80000000
 #define CPR0_CLKUPD_BSY_COMPLETED	0x00000000
@@ -3314,6 +3311,23 @@
 #define mtsdr(reg, data)	do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
 #define mfsdr(reg, data)	do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
 
+/*
+ * All 44x except 440GP have CPR registers (indirect DCR)
+ */
+#if !defined(CONFIG_440GP)
+#define CPR0_CFGADDR		0x00C
+#define CPR0_CFGDATA		0x00D
+
+#define mtcpr(reg, data)	do { \
+		mtdcr(CPR0_CFGADDR, reg); \
+		mtdcr(CPR0_CFGDATA, data); \
+	} while (0)
+
+#define mfcpr(reg, data)	do { \
+		mtdcr(CPR0_CFGADDR, reg); \
+		data = mfdcr(CPR0_CFGDATA); \
+	} while (0)
+#endif
 
 #ifndef __ASSEMBLY__
 
-- 
cgit v1.1


From ada4697d0230d6da552867777f98a67ec3ba2579 Mon Sep 17 00:00:00 2001
From: Jeffrey Mann <mannj@embeddedplanet.com>
Date: Wed, 16 May 2007 13:23:10 +0200
Subject: [PATCH] Run new sequoia boards with an EBC speed of 83MHz

Because the Sequoia board does not boot with an EBC faster than 66MHz,
the clock divider are changed after the initial boot process.

This allows for maximum clocking speeds  to be achieved on newer boards.
Sequoia boards with 666.66 MHz processors require that the EBC divider
be set to 3 in order to start the initial boot process at a slower EBC
speed. After the initial boot process, the divider can be set back to 2,
which will cause the boards to run at 83.333MHz. This is backward
compatible with boards with 533.33 MHz processors, as these boards will
already be set with an EBC divider of 2.

Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
---
 board/amcc/sequoia/sequoia.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 930fa71..8704014 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -132,6 +132,12 @@ int board_early_init_f(void)
 		(0x80000000 >> (28 + CFG_NAND_CS));
 	mtsdr(SDR0_CUST0, sdr0_cust0);
 
+	/* Update EBC speed after booting from i2c bootstrap settings
+	 * on newer boards with 33.333 MHZ Clocks
+	 */
+	if (in8(CFG_BCSR_BASE + 3) & 0x80)
+		mtcpr(0xe0, 0x02000000);
+
 	return 0;
 }
 
@@ -363,8 +369,8 @@ int checkboard(void)
 	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 #endif
 
-	rev = *(u8 *)(CFG_BCSR_BASE + 0);
-	val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01;
+	rev = in8(CFG_BCSR_BASE + 0);
+	val = in8(CFG_BCSR_BASE + 5) & 0x01;
 	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
 	if (s != NULL) {
-- 
cgit v1.1


From 10603d76767426be803dadd4fb688b97eb69481c Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 21 May 2007 07:41:22 +0200
Subject: ppc4xx: Fix problem in 405EZ OCM initialization

As spotted by Bruce Adler this patch fixes an initialization problem
for the 405EZ OCM.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 cpu/ppc4xx/start.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index a96083c..85660b4 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -783,7 +783,7 @@ _start:
 	mtdcr	ocmdscr2, r3            /* Set Data Side */
 	mtdcr	ocmiscr2, r3            /* Set Instruction Side */
 	addis	r3,0,0x0800             /* OCM Data Parity Disable - 1 Wait State */
-	mtdcr	ocmdsisdpc,r4
+	mtdcr	ocmdsisdpc,r3
 
 	isync
 #else /* CONFIG_405EZ */
-- 
cgit v1.1


From 6f3dfc139a838b0841c151efe00ad47db2366e79 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Tue, 22 May 2007 12:46:10 +0200
Subject: ppc4xx: Add 405 support to 4xx NAND driver ndfc.c

This patch adds support for 405 PPC's to the 4xx NAND driver
ndfc.c. This is in preparation for the new AMCC 405EZ.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 cpu/ppc4xx/ndfc.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index b198ff4..08dfc32 100644
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -33,12 +33,13 @@
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
 	(defined(CONFIG_440EP) || defined(CONFIG_440GR) ||	     \
-	 defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
+	 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||	     \
+	 defined(CONFIG_405EZ))
 
 #include <nand.h>
 #include <linux/mtd/ndfc.h>
 #include <asm/processor.h>
-#include <ppc440.h>
+#include <ppc4xx.h>
 
 static u8 hwctl = 0;
 
@@ -176,8 +177,7 @@ int board_nand_init(struct nand_chip *nand)
 	/*
 	 * Setup EBC (CS0 only right now)
 	 */
-	mtdcr(ebccfga, xbcfg);
-	mtdcr(ebccfgd, 0xb8400000);
+	mtebc(EBC0_CFG, 0xb8400000);
 
 	mtebc(pb0cr, CFG_EBC_PB0CR);
 	mtebc(pb0ap, CFG_EBC_PB0AP);
-- 
cgit v1.1


From 9f0077abd69f7a7c756a915b961037302be3e6f2 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Tue, 22 May 2007 12:48:09 +0200
Subject: ppc4xx: Use do { ... } while (0) for CPR & SDR access macros

Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/ppc405.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/ppc405.h b/include/ppc405.h
index a2503a9..fffae4d 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -547,8 +547,8 @@
 #define sdrcfga (SDR_DCR_BASE+0x0)	/* ADDR */
 #define sdrcfgd (SDR_DCR_BASE+0x1)	/* Data */
 
-#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
-#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
+#define mtsdr(reg, data)	do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
+#define mfsdr(reg, data)	do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
 
 #define sdrnand0	0x4000
 #define sdrultra0	0x4040
@@ -593,8 +593,8 @@
 /*
  * Macro for accessing the indirect CPR register
  */
-#define mtcpr(reg, data)  mtdcr(cprcfga,reg);mtdcr(cprcfgd,data)
-#define mfcpr(reg, data)  mtdcr(cprcfga,reg);data = mfdcr(cprcfgd)
+#define mtcpr(reg, data)	do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0)
+#define mfcpr(reg, data)	do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0)
 
 #define CPR_CLKUPD_ENPLLCH_EN  0x40000000     /* Enable CPR PLL Changes */
 #define CPR_CLKUPD_ENDVCH_EN   0x20000000     /* Enable CPR Sys. Div. Changes */
-- 
cgit v1.1


From 5d4a179013d59a76446462e1eb0a969fba63eb81 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 24 May 2007 08:22:09 +0200
Subject: ppc4xx: Update AMCC Acadia support for board revision 1.1

This patch updates the Acadia (405EZ) support for the new 1.1 board
revision. It also adds support for NAND FLASH via the 4xx NDFC.

Please note that the jumper J7 must be in position 2-3 for this
NAND support. Position 1-2 is for NAND booting only. NAND booting
support will follow later.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/amcc/acadia/acadia.c |  9 ++++++++-
 include/configs/acadia.h   | 27 +++++++++------------------
 2 files changed, 17 insertions(+), 19 deletions(-)

diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
index baf598c..3b63c8a 100644
--- a/board/amcc/acadia/acadia.c
+++ b/board/amcc/acadia/acadia.c
@@ -62,6 +62,10 @@ int board_early_init_f(void)
 
 	acadia_gpio_init();
 
+	/* Configure 405EZ for NAND usage */
+	mtsdr(sdrnand0, 0x80c00000);
+	mtsdr(sdrultra0, 0x8d110000);
+
 	/* USB Host core needs this bit set */
 	mfsdr(sdrultra1, reg);
 	mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
@@ -91,8 +95,11 @@ int misc_init_f(void)
 int checkboard(void)
 {
 	char *s = getenv("serial#");
+	u8 rev;
+
+	rev = in8(CFG_CPLD_BASE + 0);
+	printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
 
-	printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");
 	if (s != NULL) {
 		puts(", serial# ");
 		puts(s);
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 35b6a51..c72d933 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -34,7 +34,9 @@
 #define CONFIG_ACADIA		1		/* Board is Acadia	*/
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_405EZ		1		/* Specifc 405EZ support*/
-#define CONFIG_SYS_CLK_FREQ	66666666	/* external freq to pll	*/
+/* Detect Acadia PLL input clock automatically via CPLD bit		*/
+#define CONFIG_SYS_CLK_FREQ    ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \
+				66666666 : 33333000)
 
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_F	1		/* Call misc_init_f	*/
@@ -224,16 +226,6 @@
 #define CONFIG_USB_OHCI
 #define CONFIG_USB_STORAGE
 
-#if 0 /* test-only */
-#define TEST_ONLY_NAND
-#endif
-
-#ifdef TEST_ONLY_NAND
-#define CMD_NAND		CFG_CMD_NAND
-#else
-#define CMD_NAND		0
-#endif
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -252,7 +244,7 @@
 			       CFG_CMD_I2C	|	\
 			       CFG_CMD_IRQ	|	\
 			       CFG_CMD_MII	|	\
-			       CMD_NAND		|	\
+			       CFG_CMD_NAND	|	\
 			       CFG_CMD_NET	|	\
 			       CFG_CMD_NFS	|	\
 			       CFG_CMD_PCI	|	\
@@ -300,7 +292,6 @@
  */
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#ifdef TEST_ONLY_NAND
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
@@ -308,7 +299,6 @@
 #define NAND_MAX_CHIPS		1
 #define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
 #define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
-#endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -322,7 +312,7 @@
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
+#define CFG_NAND_CS		3		/* NAND chip connected to CSx	*/
 
 /* Memory Bank 0 (Flash) initialization						*/
 #define CFG_EBC_PB0AP		0x03337200
@@ -358,7 +348,8 @@
 /*-----------------------------------------------------------------------
  * Definitions for GPIO_0 setup (PPC405EZ specific)
  *
- * GPIO0[0-3]	- External Bus Controller CS_4 - CS_7 Outputs
+ * GPIO0[0-2]	- External Bus Controller CS_4 - CS_6 Outputs
+ * GPIO0[3]	- NAND FLASH Controller CE3 (NFCE3) Output
  * GPIO0[4]	- External Bus Controller Hold Input
  * GPIO0[5]	- External Bus Controller Priority Input
  * GPIO0[6]	- External Bus Controller HLDA Output
@@ -376,10 +367,10 @@
  */
 #define CFG_GPIO0_TCR		0xC0000000
 #define CFG_GPIO0_OSRL		0x50000000
-#define CFG_GPIO0_OSRH		0x00000055
+#define CFG_GPIO0_OSRH		0x02000055
 #define CFG_GPIO0_ISR1L		0x00000000
 #define CFG_GPIO0_ISR1H		0x00000055
-#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TSRL		0x02000000
 #define CFG_GPIO0_TSRH		0x00000055
 
 /*-----------------------------------------------------------------------
-- 
cgit v1.1


From d756894722c888d09a9fa1df8323753772d3dcce Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 24 May 2007 09:49:00 +0200
Subject: ppc4xx: Fix small 405EZ OCM initilization bug in start.S

As pointed out by Bruce Adler <bruce.adler@acm.org> this patch
fixes a small bug in the 405EZ OCM initialization. Thanks for
spotting.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 cpu/ppc4xx/start.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index a96083c..85660b4 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -783,7 +783,7 @@ _start:
 	mtdcr	ocmdscr2, r3            /* Set Data Side */
 	mtdcr	ocmiscr2, r3            /* Set Instruction Side */
 	addis	r3,0,0x0800             /* OCM Data Parity Disable - 1 Wait State */
-	mtdcr	ocmdsisdpc,r4
+	mtdcr	ocmdsisdpc,r3
 
 	isync
 #else /* CONFIG_405EZ */
-- 
cgit v1.1


From a11c0b85dc3664bb3c1e781137118730c8f619ab Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 16:51:48 +0200
Subject: Motion-PRO: Add LED support.

Signed-off-by: Jan Wrobel <wrr@semihalf.com>
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 board/motionpro/motionpro.c | 30 ++++++++++++++++++++++++++++++
 include/configs/motionpro.h | 22 ++++++++++++++++++++++
 include/status_led.h        | 12 ++++++++++++
 3 files changed, 64 insertions(+)

diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index 887aade..98357c7 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -33,6 +33,10 @@
 #include <ft_build.h>
 #endif
 
+#if defined(CONFIG_STATUS_LED)
+#include <status_led.h>
+#endif /* CONFIG_STATUS_LED */
+
 /* Kollmorgen DPR initialization data */
 struct init_elem {
 	unsigned long addr;
@@ -180,3 +184,29 @@ void ft_board_setup(void *blob, bd_t *bd)
 	ft_cpu_setup(blob, bd);
 }
 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+
+
+#if defined(CONFIG_STATUS_LED)
+void __led_init (led_id_t regaddr, int state)
+{
+	*((vu_long *) regaddr) |= ENABLE_GPIO_OUT;
+
+	if (state == STATUS_LED_ON)
+		*((vu_long *) regaddr) |= LED_ON;
+	else
+		*((vu_long *) regaddr) &= ~LED_ON;
+}
+
+void __led_set (led_id_t regaddr, int state)
+{
+	if (state == STATUS_LED_ON)
+		*((vu_long *) regaddr) |= LED_ON;
+	else
+		*((vu_long *) regaddr) &= ~LED_ON;
+}
+
+void __led_toggle (led_id_t regaddr)
+{
+	*((vu_long *) regaddr) ^= LED_ON;
+}
+#endif /* CONFIG_STATUS_LED */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index e6e0eb1..5c2b1cd 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -310,6 +310,28 @@
 
 
 /*
+ * Status LED configuration
+ */
+#define CONFIG_STATUS_LED		/* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED
+
+#define ENABLE_GPIO_OUT		0x00000024
+#define LED_ON			0x00000010
+
+#ifndef __ASSEMBLY__
+/*
+ * In case of Motion-PRO, a LED is identified by its corresponding
+ * GPT Enable and Mode Select Register.
+ */
+typedef volatile unsigned long * led_id_t;
+
+extern void __led_init(led_id_t id, int state);
+extern void __led_toggle(led_id_t id);
+extern void __led_set(led_id_t id, int state);
+#endif /* __ASSEMBLY__ */
+
+
+/*
  * Environment settings
  */
 #define CFG_ENV_IS_IN_FLASH	1
diff --git a/include/status_led.h b/include/status_led.h
index db4c60f..71a202f 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -355,6 +355,18 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_ACTIVE	0		/* LED on for bit == 0 */
 # define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
 
+#elif defined(CONFIG_MOTIONPRO)
+
+#define STATUS_LED_BIT		((vu_long *) MPC5XXX_GPT6_ENABLE)
+#define STATUS_LED_PERIOD	(CFG_HZ / 10)
+#define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+#define STATUS_LED_BIT1		((vu_long *) MPC5XXX_GPT7_ENABLE)
+#define STATUS_LED_PERIOD1	(CFG_HZ / 10)
+#define STATUS_LED_STATE1	STATUS_LED_OFF
+
+#define STATUS_LED_BOOT		0	/* LED 0 used for boot status */
+
 #else
 # error Status LED configuration missing
 #endif
-- 
cgit v1.1


From c99512d6bd3973f01ca2fc4896d829b46e68f150 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 16:53:43 +0200
Subject: MPC5xxx: Change names of defines related to IPB and PCI clocks.

Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining
them does not cause PCI or IPB clocks to run at the specified speed.
Instead, they configure divisors used to calculate said clocks. This
patch renames the defines according to their real function.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 cpu/mpc5xxx/cpu_init.c      |  8 ++++----
 include/configs/BC3450.h    | 12 ++++++------
 include/configs/IceCube.h   |  4 ++--
 include/configs/PM520.h     |  2 +-
 include/configs/TB5200.h    | 12 ++++++------
 include/configs/TOP5200.h   |  2 +-
 include/configs/TQM5200.h   | 12 ++++++------
 include/configs/Total5200.h |  2 +-
 include/configs/aev.h       | 12 ++++++------
 include/configs/canmb.h     |  2 +-
 include/configs/cpci5200.h  |  2 +-
 include/configs/hmi1001.h   |  2 +-
 include/configs/inka4x0.h   |  2 +-
 include/configs/mcc200.h    |  2 +-
 include/configs/motionpro.h |  4 ++--
 include/configs/o2dnt.h     | 12 ++++++------
 include/configs/pf5200.h    |  2 +-
 include/configs/smmaco4.h   | 12 ++++++------
 include/configs/spieval.h   | 12 ++++++------
 include/configs/uc101.h     |  2 +-
 include/configs/v38b.h      |  2 +-
 21 files changed, 61 insertions(+), 61 deletions(-)

diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index 7e65821..d744030 100644
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -156,21 +156,21 @@ void cpu_init_f (void)
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
 	*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
 
-# if defined(CFG_IPBSPEED_133)
+# if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 	/* Motorola reports IPB should better run at 133 MHz. */
 	*(vu_long *)MPC5XXX_ADDECR |= 1;
 	/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
 	addecr = *(vu_long *)MPC5XXX_CDM_CFG;
 	addecr &= ~0x103;
-#  if defined(CFG_PCISPEED_66)
+#  if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2)
 	/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
 	addecr |= 0x01;
 #  else
 	/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
 	addecr |= 0x02;
-#  endif /* CFG_PCISPEED_66 */
+#  endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */
 	*(vu_long *)MPC5XXX_CDM_CFG = addecr;
-# endif	/* CFG_IPBSPEED_133 */
+# endif	/* CFG_IPBCLK_EQUALS_XLBCLK */
 	/* Configure the XLB Arbiter */
 	*(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
 	*(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index 5b54f30..bc30977 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -282,17 +282,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet
- * hasn't been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#if defined(CFG_IPBSPEED_133)
-# define CFG_PCISPEED_66			/* define for 66MHz speed */
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
+# define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -488,7 +488,7 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 # define CFG_BOOTCS_CFG		0x0008DF30	/* for pci_clk	= 66 MHz */
 #else
 # define CFG_BOOTCS_CFG		0x0004DF30	/* for pci_clk = 33 MHz	 */
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 0d38254..09f8d20 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -167,9 +167,9 @@
  * IPB Bus clocking configuration.
  */
 #if defined(CONFIG_LITE5200B)
-#define CFG_IPBSPEED_133 	/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK 	/* define for 133MHz speed */
 #else
-#undef CFG_IPBSPEED_133   	/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK   	/* define for 133MHz speed */
 #endif
 #endif /* CONFIG_MPC5200 */
 
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index 9c241e6..7d91a01 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -160,7 +160,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK   		/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index 8a6e5a6..b42cfb6 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -200,17 +200,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2		/* define for 66MHz speed */
 #endif
 
 /*
@@ -432,7 +432,7 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 #define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
 #define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index f41dbd0..1cc9ce9 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -186,7 +186,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK   		/* define for 133MHz speed */
 
 /*
  * I2C configuration
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 7069b35..7935593 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -269,17 +269,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
+ * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -594,7 +594,7 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 #define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
 #define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index 8175703..d8686dd 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -183,7 +183,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK   		/* define for 133MHz speed */
 #endif
 
 /*
diff --git a/include/configs/aev.h b/include/configs/aev.h
index 8d9f0a1..6c2a360 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -166,17 +166,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -362,7 +362,7 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 #define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
 #define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 2c160a4..ec6d57e 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -111,7 +111,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK   		/* define for 133MHz speed */
 
 /*
  * Flash configuration, expect one 16 Megabyte Bank at most
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
index f9586fb..f5efcd9 100644
--- a/include/configs/cpci5200.h
+++ b/include/configs/cpci5200.h
@@ -179,7 +179,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index cfaf153..45a28c7 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -110,7 +110,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 773d5d2..ad3cf06 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -147,7 +147,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * Flash configuration
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index f60973b..00d2e07 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -169,7 +169,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 5c2b1cd..358c380 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -160,9 +160,9 @@
 
 
 /*
- * Set IPB speed to 100MHz (yes, the #define is misnamed)
+ * Set IPB speed to 100MHz
  */
-#define CFG_IPBSPEED_133
+#define CFG_IPBCLK_EQUALS_XLBCLK
 
 
 /*
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 5c05a74..63d0da7 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -137,17 +137,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 #endif
 
@@ -276,7 +276,7 @@
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
 
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 /*
  * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
  */
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
index fefdb3c..7151a9e 100644
--- a/include/configs/pf5200.h
+++ b/include/configs/pf5200.h
@@ -171,7 +171,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
index e106b3b..185c2d4 100644
--- a/include/configs/smmaco4.h
+++ b/include/configs/smmaco4.h
@@ -138,17 +138,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -357,7 +357,7 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 #define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
 #define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index f40dde2..fd138a5 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -219,17 +219,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -444,7 +444,7 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 #define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
 #define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/uc101.h b/include/configs/uc101.h
index 8cd8e9b..ff061ee 100644
--- a/include/configs/uc101.h
+++ b/include/configs/uc101.h
@@ -114,7 +114,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index e19591d..0b7b19e 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -167,7 +167,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133			/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK			/* define for 133MHz speed */
 #endif
 
 /*
-- 
cgit v1.1


From c75e639630cc132dc19cd1ecda5922c0db0bfbba Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 16:55:23 +0200
Subject: Motion-PRO: Add displaying of CPLD revision information during boot.

Signed-off-by: Jan Wrobel <wrr@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 board/motionpro/motionpro.c | 3 ++-
 include/configs/motionpro.h | 6 ++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index 98357c7..1729ae7 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -173,7 +173,8 @@ long int initdram (int board_type)
 
 int checkboard (void)
 {
-	puts("Board: Promess Motion-PRO board\n");
+	uchar rev = *(vu_char *)CPLD_REV_REGISTER;
+	printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
 	return 0;
 }
 
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 358c380..8ffcc4c 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -357,6 +357,12 @@ extern void __led_set(led_id_t id, int state);
 
 
 /*
+ * Motion-PRO's CPLD revision control register
+ */
+#define CPLD_REV_REGISTER	(CFG_CS2_START + 0x06)
+
+
+/*
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory    */
-- 
cgit v1.1


From 93b78f534a6e708b4cf1a4ffb4d8438c67a007db Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 16:57:15 +0200
Subject: Motion-PRO: Add support for the temperature sensor.

Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/motionpro.h | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 8ffcc4c..a4df64a 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -54,7 +54,8 @@
 				CFG_CMD_JFFS2	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_DATE	| \
-				CFG_CMD_EEPROM)
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_DTT)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -297,6 +298,7 @@
  * EEPROM configuration
  */
 #define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE	1	/* DTT driver needs this */
 #define CFG_EEPROM_PAGE_WRITE_BITS	3
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
 #define CFG_I2C_MULTI_EEPROMS		1	/* 2 EEPROMs (addr:50,52) */
@@ -332,6 +334,13 @@ extern void __led_set(led_id_t id, int state);
 
 
 /*
+ * Temperature sensor
+ */
+#define CONFIG_DTT_LM75		1
+#define CONFIG_DTT_SENSORS	{ 0x49 }
+
+
+/*
  * Environment settings
  */
 #define CFG_ENV_IS_IN_FLASH	1
-- 
cgit v1.1


From c00125e07c1ebc125bab40e1e18bceed8be0c162 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 16:58:45 +0200
Subject: MPC5XXX, Motion-PRO: Fix PHY initialization problem.

After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which
networking does not function. This commit switches PHY to TX mode by clearing
the FX_SEL bit of Mode Control Register. It also reverses commit
008861a2f3ef2c062744d733787c7e530a1b8761, i.e., a temporary workaround.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 board/motionpro/motionpro.c | 18 +++++++++++++++++-
 cpu/mpc5xxx/fec.c           |  4 ----
 include/configs/motionpro.h |  2 +-
 3 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index 1729ae7..b05e2ab 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -28,7 +28,7 @@
 
 #include <common.h>
 #include <mpc5xxx.h>
-
+#include <miiphy.h>
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
 #endif
@@ -82,6 +82,22 @@ int board_early_init_r(void)
 }
 
 
+/*
+ * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
+ * PHY goes into FX mode.  To take it out of the FX mode and switch into
+ * desired TX operation, one needs to clear the FX_SEL bit of Mode Control
+ * Register.
+ */
+void reset_phy(void)
+{
+	unsigned short mode_control;
+
+	miiphy_read("FEC ETHERNET", CONFIG_PHY_ADDR, 0x15, &mode_control);
+	miiphy_write("FEC ETHERNET", CONFIG_PHY_ADDR, 0x15,
+			mode_control & 0xfffe);
+	return;
+}
+
 #ifndef CFG_RAMBOOT
 /*
  * Helper function to initialize SDRAM controller.
diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index 0b8f24d..62b5f4e 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -395,9 +395,7 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
 {
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
-#ifndef CONFIG_MOTIONPRO
 	const uint8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
-#endif /* !CONFIG_MOTIONPRO */
 
 #if (DEBUG & 0x1)
 	printf ("mpc5xxx_fec_init_phy... Begin\n");
@@ -437,7 +435,6 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
  * PHY initialization for the Motion-PRO board, until a proper fix is found.
  */
 
-#ifndef CONFIG_MOTIONPRO
 	if (fec->xcv_type != SEVENWIRE) {
 		/*
 		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
@@ -560,7 +557,6 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
 		}
 
 	}
-#endif /* !CONFIG_MOTIONPRO */
 
 #if (DEBUG & 0x2)
 	if (fec->xcv_type != SEVENWIRE)
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index a4df64a..a7021b0 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -76,7 +76,7 @@
 #define CONFIG_MPC5xxx_FEC	1
 #define CONFIG_PHY_ADDR		0x2
 #define CONFIG_PHY_TYPE		0x79c874
-
+#define CONFIG_RESET_PHY_R	1
 
 /*
  * Autobooting
-- 
cgit v1.1


From 630ec84aef7228fc1dbfb38dec78541403a786cd Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 17:03:37 +0200
Subject: Motion-PRO: Update EEPROM's page write bits and write delay.

Change EEPROM configuration according to the datasheet: "The 24C01A and 24C02A
have a page write capability of two bytes", and "This device offers fast (1ms)
byte write". Add 3ms of extra delay.

Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/motionpro.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index a7021b0..2c405b5 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -299,8 +299,8 @@
  */
 #define CFG_I2C_EEPROM_ADDR_LEN		1
 #define CFG_EEPROM_PAGE_WRITE_ENABLE	1	/* DTT driver needs this */
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CFG_EEPROM_PAGE_WRITE_BITS	1	/* 2 bytes per write cycle */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	5	/* 2ms/cycle + 3ms extra */
 #define CFG_I2C_MULTI_EEPROMS		1	/* 2 EEPROMs (addr:50,52) */
 
 
-- 
cgit v1.1


From 9160b96f71483a116de81c68985e8ee306d36764 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 17:04:18 +0200
Subject: Fix: Add missing NULL termination in strings expanded by macros
 parser.

Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 common/main.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/common/main.c b/common/main.c
index cc4b50f..8f196a4 100644
--- a/common/main.c
+++ b/common/main.c
@@ -1219,6 +1219,8 @@ static void process_macros (const char *input, char *output)
 
 	if (outputcnt)
 		*output = 0;
+	else
+		*(output - 1) = 0;
 
 #ifdef DEBUG_PARSER
 	printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n",
-- 
cgit v1.1


From a26eabeec31746f06d309103690892805696e344 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 17:05:11 +0200
Subject: Motion-PRO: Change maximum console buffer size from 256 to 1024
 bytes.

Allow passing longer command line to the kernel - useful especially
for passing MTD partition layout.

Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/motionpro.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 2c405b5..bbd823a 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -376,7 +376,7 @@ extern void __led_set(led_id_t id, int state);
  */
 #define CFG_LONGHELP			/* undef to save memory    */
 #define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
 #define CFG_MAXARGS		16		/* max number of command args */
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-- 
cgit v1.1


From 4520fd4d2c450da49637216aa0e53739b61c60ac Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 17:06:36 +0200
Subject: Motion-PRO: Add support for redundant environment.

Enable redundant environment, add a MTD partition for it; also add env.
variable command for passing MTD partitions to the kernel command line.

Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/motionpro.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index bbd823a..8170ccb 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -125,6 +125,7 @@
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=$(serverip):$(rootpath)\0"			\
 	"fat_args=setenv bootargs rw\0"					\
+	"addmtd=setenv bootargs $(bootargs) $(mtdparts)\0"		\
 	"addip=setenv bootargs $(bootargs) "				\
 		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
 		"$(netmask):$(hostname):$(netdev):off panic=1 "		\
@@ -269,7 +270,8 @@
 #define MTDIDS_DEFAULT		"nor0=motionpro-0"
 #define MTDPARTS_DEFAULT	"mtdparts=motionpro-0:"			  \
 					"13m(fs),2m(kernel),256k(uboot)," \
-					"64k(env),64k(dtb),-(user_data)"
+					"64k(env),64k(redund_env),64k(dtb)," \
+					"-(user_data)"
 
 /*
  * IDE/ATA configuration
@@ -349,6 +351,9 @@ extern void __led_set(led_id_t id, int state);
 #define CFG_ENV_SIZE		0x1000
 #define CFG_ENV_SECT_SIZE	0x10000
 
+/* Configuration of redundant environment */
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 
 /*
  * Pin multiplexing configuration
-- 
cgit v1.1


From 7049288fb1f16f1b317140226cdebd07bd416395 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 17:26:46 +0200
Subject: Motion-PRO: Code cleanup, fix of a typo in OF_STDOUT_PATH.

Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
---
 board/motionpro/motionpro.c | 12 ++++++------
 include/configs/motionpro.h | 32 ++++++++++++++++----------------
 2 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index b05e2ab..40d304b 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -102,7 +102,7 @@ void reset_phy(void)
 /*
  * Helper function to initialize SDRAM controller.
  */
-static void sdram_start (int hi_addr)
+static void sdram_start(int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
 
@@ -134,7 +134,7 @@ static void sdram_start (int hi_addr)
 /*
  * Initalize SDRAM - configure SDRAM controller, detect memory size.
  */
-long int initdram (int board_type)
+long int initdram(int board_type)
 {
 	ulong dramsize = 0;
 #ifndef CFG_RAMBOOT
@@ -187,7 +187,7 @@ long int initdram (int board_type)
 }
 
 
-int checkboard (void)
+int checkboard(void)
 {
 	uchar rev = *(vu_char *)CPLD_REV_REGISTER;
 	printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
@@ -204,7 +204,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 
 #if defined(CONFIG_STATUS_LED)
-void __led_init (led_id_t regaddr, int state)
+void __led_init(led_id_t regaddr, int state)
 {
 	*((vu_long *) regaddr) |= ENABLE_GPIO_OUT;
 
@@ -214,7 +214,7 @@ void __led_init (led_id_t regaddr, int state)
 		*((vu_long *) regaddr) &= ~LED_ON;
 }
 
-void __led_set (led_id_t regaddr, int state)
+void __led_set(led_id_t regaddr, int state)
 {
 	if (state == STATUS_LED_ON)
 		*((vu_long *) regaddr) |= LED_ON;
@@ -222,7 +222,7 @@ void __led_set (led_id_t regaddr, int state)
 		*((vu_long *) regaddr) &= ~LED_ON;
 }
 
-void __led_toggle (led_id_t regaddr)
+void __led_toggle(led_id_t regaddr)
 {
 	*((vu_long *) regaddr) ^= LED_ON;
 }
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 8170ccb..e3899a5 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -117,27 +117,27 @@
 	"fdt_file=/tftpboot/motionpro/motionpro.dtb\0"			\
 	"ramdisk_file=/tftpboot/motionpro/uRamdisk\0"			\
 	"multi_image_file=kernel+initrd+dtb.img\0"			\
-	"load=tftp $(u-boot_addr) $(u-boot)\0"				\
+	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
 	"update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; "	\
-		"cp.b $(u-boot_addr) fff00000 $(filesize);"		\
+		"cp.b ${u-boot_addr} fff00000 ${filesize};"		\
 		"prot on fff00000 fff3ffff\0"				\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
 	"fat_args=setenv bootargs rw\0"					\
-	"addmtd=setenv bootargs $(bootargs) $(mtdparts)\0"		\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
-		"$(netmask):$(hostname):$(netdev):off panic=1 "		\
-		"console=$(console)\0"					\
-	"net_nfs=tftp $(kernel_addr) $(bootfile); "			\
-		"tftp $(fdt_addr) $(fdt_file); run nfsargs addip; "	\
-		"bootm $(kernel_addr) - $(fdt_addr)\0"			\
-	"net_self=tftp $(kernel_addr) $(bootfile); "			\
-		"tftp $(fdt_addr) $(fdt_file); "			\
-		"tftp $(ramdisk_addr) $(ramdisk_file); "		\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+		"${netmask}:${hostname}:${netdev}:off panic=1 "		\
+		"console=${console}\0"					\
+	"net_nfs=tftp ${kernel_addr} ${bootfile}; "			\
+		"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip; "	\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_self=tftp ${kernel_addr} ${bootfile}; "			\
+		"tftp ${fdt_addr} ${fdt_file}; "			\
+		"tftp ${ramdisk_addr} ${ramdisk_file}; "		\
 		"run ramargs addip; "					\
-		"bootm $(kernel_addr) $(ramdisk_addr) $(fdt_addr)\0"	\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
 	"fat_multi=run fat_args addip; fatload ide 0:1 "		\
 		"${multi_image_addr} ${multi_image_file}; "		\
 		"bootm ${multi_image_addr}\0"				\
@@ -418,6 +418,6 @@ extern void __led_set(led_id_t id, int state);
 #define OF_CPU			"PowerPC,5200@0"
 #define OF_SOC			"soc5200@f0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PAT		"/soc5200@f0000000/serial@2000"
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
 
 #endif /* __CONFIG_H */
-- 
cgit v1.1