From 4f434e3d6dd33162f44a19da64d0853b8147539d Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 27 Aug 2012 23:56:40 +0000 Subject: MX28: mx28evk: Align SSP clock speed Align the SSP clock speed with oscilator to achieve higher transfer stability. Signed-off-by: Otavio Salvador Acked-by: Marek Vasut --- board/freescale/mx28evk/mx28evk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index 867d3c8..d782aea 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -49,8 +49,8 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); - /* SSP2 clock at 96MHz */ - mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); + /* SSP2 clock at 160MHz */ + mx28_set_sspclk(MXC_SSPCLK2, 160000, 0); #ifdef CONFIG_CMD_USB mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); -- cgit v1.1 From de6dc4ea3973b1308cf013a60d6a594232c10e88 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 27 Aug 2012 23:56:41 +0000 Subject: MX28: mx28evk: Enable SPI DMA Signed-off-by: Otavio Salvador --- include/configs/mx28evk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 4e1e6bc..e34fd96 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -199,6 +199,7 @@ #ifdef CONFIG_CMD_SPI #define CONFIG_HARD_SPI #define CONFIG_MXS_SPI +#define CONFIG_MXS_SPI_DMA_ENABLE #define CONFIG_SPI_HALF_DUPLEX #define CONFIG_DEFAULT_SPI_BUS 2 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 -- cgit v1.1 From ddfcc810d3947a085fb85cefcb6cb04c723eadf9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 28 Aug 2012 09:29:06 +0000 Subject: mx28evk: Convert to mxs_adjust_memory_params() Recent conversion from mx28_adjust_memory_params to mxs_adjust_memory_params missed to update mx28evk, which caused the board not to boot. Apply the conversion so that the board can boot again. Signed-off-by: Fabio Estevam Acked-by: Marek Vasut --- board/freescale/mx28evk/iomux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index 16a6d8a..ae6eda3 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -173,7 +173,7 @@ const iomux_cfg_t iomux_setup[] = { #define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ ADDR_PINS << 8 | APREBIT) -void mx28_adjust_memory_params(uint32_t *dram_vals) +void mxs_adjust_memory_params(uint32_t *dram_vals) { dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; } -- cgit v1.1 From c16ecb09088f303cb36fd3c55108857cdf934b98 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Aug 2012 15:12:48 +0000 Subject: M28: Fix the use of gpmi-nand in mtdparts The mtd name of the NAND in Linux is "gpmi-nand", not "gpmi-nand.0" as it would be expected, since the controller doesn't support multiple NANDs attached to it as of now. Rectify this flub by adjusting default mtdparts. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Stefano Babic Cc: Otavio Salvador Acked-by: Stefano Babic --- include/configs/m28evk.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index d0f2b48..9eb2a54 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -171,9 +171,9 @@ #define CONFIG_LZO #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nand0=gpmi-nand.0" +#define MTDIDS_DEFAULT "nand0=gpmi-nand" #define MTDPARTS_DEFAULT \ - "mtdparts=gpmi-nand.0:" \ + "mtdparts=gpmi-nand:" \ "3m(bootloader)ro," \ "512k(environment)," \ "512k(redundant-environment)," \ -- cgit v1.1 From 8aa09026588abb7222bc09c944db36312c263aad Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Aug 2012 15:15:52 +0000 Subject: MX28: Cleanup mxsboot within make mrproper Delete the "mxsboot" binary if make mrproper is called. Signed-off-by: Marek Vasut Cc: Wolfgang Denk Cc: Stefano Babic Cc: Fabio Estevam CC: Albert Aribaud Acked-by: Stefano Babic --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index d6d8ab2..e5f8d05 100644 --- a/Makefile +++ b/Makefile @@ -776,6 +776,7 @@ clean: $(obj)tools/gen_eth_addr $(obj)tools/img2srec \ $(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \ $(obj)tools/mk{smdk5250,}spl \ + $(obj)tools/mxsboot \ $(obj)tools/ncb $(obj)tools/ubsha1 @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \ $(obj)board/matrix_vision/*/bootscript.img \ -- cgit v1.1 From d82f05fcad3873dd6f5f06e042a28bacf2f0f950 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Aug 2012 15:15:53 +0000 Subject: MX28: Fixup the ad-hoc use of DIGCTL_MICROSECONDS Use proper struct-based access for this register in the SPL code. Signed-off-by: Marek Vasut Cc: Wolfgang Denk Cc: Stefano Babic Cc: Fabio Estevam Acked-by: Stefano Babic --- arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index ddafddb..ad66c57 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -38,12 +38,14 @@ * takes a few seconds to roll. The boot doesn't take that long, so to keep the * code simple, it doesn't take rolling into consideration. */ -#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0 void early_delay(int delay) { - uint32_t st = readl(HW_DIGCTRL_MICROSECONDS); + struct mxs_digctl_regs *digctl_regs = + (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; + + uint32_t st = readl(&digctl_regs->hw_digctl_microseconds); st += delay; - while (st > readl(HW_DIGCTRL_MICROSECONDS)) + while (st > readl(&digctl_regs->hw_digctl_microseconds)) ; } -- cgit v1.1 From 91dd7ca6ac9b9b760a1671ec845d4401a13df11e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 29 Aug 2012 06:20:03 +0000 Subject: mx28evk: Add USB Ethernet support Add USB Ethernet support. Signed-off-by: Fabio Estevam Reviewed-by: Marek Vasut --- include/configs/mx28evk.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index e34fd96..43b4002 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -184,6 +184,9 @@ #define CONFIG_EHCI_MXS_PORT 1 #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX #endif /* I2C */ -- cgit v1.1 From d812f4ad95d1f15c656c7f32d6077bc1224abf4a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 30 Aug 2012 13:41:15 +0000 Subject: SCSPS1: Enable caches Enable caches, make it faster! Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Detlev Zundel --- include/configs/sc_sps_1.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h index 0ebdfb8..f5dc393 100644 --- a/include/configs/sc_sps_1.h +++ b/include/configs/sc_sps_1.h @@ -39,8 +39,6 @@ #include #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MISC_INIT -- cgit v1.1 From 0d7d3830984012a8209bbf497f92add652082afb Mon Sep 17 00:00:00 2001 From: Matt Sealey Date: Thu, 23 Aug 2012 04:52:33 +0000 Subject: efikamx: refine USB support Because of the way USB pad settings are handled it doesn't make sense to be able to build the Efika MX board support without CONFIG_CMD_USB turned on. So, we change the build to always compile in USB support. We do not need to check for CONFIG_CMD_USB like we do with CONFIG_MXC_SPI since the USB subsystem will error out of the compile for us. Additionally, the following behaviors have changed; * Smartbook "preboot" should not set input and output to USB keyboard as there is no display support * board_eth_init is implemented such that it does not cause U-Boot to report an explicit failure ("CPU Net Initialization Failed"). Since Ethernet is implemented via USB (fixed on Smarttop, pluggable on Smartbook, and handled by "usb start") - the warning that is left ("No ethernet found") is perfectly reasonable at the point it is printed since the USB system hasn't been started and nothing has been probed yet. Signed-off-by: Matt Sealey Cc: Stefano Babic Cc: Marek Vasut --- board/genesi/mx51_efikamx/Makefile | 6 +----- board/genesi/mx51_efikamx/efikamx-usb.c | 12 ++++++++++++ board/genesi/mx51_efikamx/efikamx.c | 3 --- 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/board/genesi/mx51_efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile index bd2174f..f95356f 100644 --- a/board/genesi/mx51_efikamx/Makefile +++ b/board/genesi/mx51_efikamx/Makefile @@ -27,11 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := efikamx.o - -ifdef CONFIG_CMD_USB -COBJS += efikamx-usb.o -endif +COBJS := efikamx.o efikamx-usb.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c index e9273d0..cf020c3 100644 --- a/board/genesi/mx51_efikamx/efikamx-usb.c +++ b/board/genesi/mx51_efikamx/efikamx-usb.c @@ -214,3 +214,15 @@ void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) if (port) mdelay(10); } + +/* + * Ethernet on the Smarttop is on the USB bus. Rather than give an error about + * "CPU Net Initialization Failed", just pass this test since no other settings + * are required. Smartbook doesn't have built-in Ethernet but we will let it + * pass anyway considering someone may have plugged in a USB stick and all + * they need to do is run "usb start". + */ +int board_eth_init(bd_t *bis) +{ + return 0; +} diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 6d98c94..cfd2e93 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -492,9 +492,6 @@ int board_late_init(void) ARRAY_SIZE(efikamx_pata_pads)); setup_iomux_usb(); - if (machine_is_efikasb()) - setenv("preboot", "usb reset ; setenv stdin usbkbd\0"); - return 0; } -- cgit v1.1 From e7619554173a9d9f72dc19f97a804afea135f07f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 14 Aug 2012 10:32:54 +0000 Subject: mx35: Fix decode_pll MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- arch/arm/cpu/arm1136/mx35/generic.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index d435e8a..de7503c 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -24,6 +24,7 @@ */ #include +#include #include #include #include @@ -129,15 +130,17 @@ static int get_ahb_div(u32 pdr0) static u32 decode_pll(u32 reg, u32 infreq) { u32 mfi = (reg >> 10) & 0xf; - u32 mfn = reg & 0x3f; - u32 mfd = (reg >> 16) & 0x3f; + s32 mfn = reg & 0x3ff; + u32 mfd = (reg >> 16) & 0x3ff; u32 pd = (reg >> 26) & 0xf; mfi = mfi <= 5 ? 5 : mfi; + mfn = mfn >= 512 ? mfn - 1024 : mfn; mfd += 1; pd += 1; - return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; + return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), + mfd * pd); } static u32 get_mcu_main_clk(void) -- cgit v1.1 From 9ba81baabb3c370af9548348c24d326039589e7f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 14 Aug 2012 10:33:06 +0000 Subject: mx35: Add definitions for clock gate values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- arch/arm/include/asm/arch-mx35/crm_regs.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h index 7a2d1bb..fa71dea 100644 --- a/arch/arm/include/asm/arch-mx35/crm_regs.h +++ b/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -144,6 +144,12 @@ #define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) /* Bit definitions for Clock gating Register*/ +#define MXC_CCM_CGR_CG_MASK 0x3 +#define MXC_CCM_CGR_CG_OFF 0x0 +#define MXC_CCM_CGR_CG_RUN_ON 0x1 +#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2 +#define MXC_CCM_CGR_CG_ON 0x3 + #define MXC_CCM_CGR0_ASRC_OFFSET 0 #define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) #define MXC_CCM_CGR0_ATA_OFFSET 2 -- cgit v1.1 From 82e1b543b51fb514731992eeb2a6bdcdc279950e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 14 Aug 2012 10:33:27 +0000 Subject: mx35: Fix clock dividers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- arch/arm/cpu/arm1136/mx35/generic.c | 48 ++++++++++++------------------- arch/arm/include/asm/arch-mx35/crm_regs.h | 42 +++++++++------------------ 2 files changed, 31 insertions(+), 59 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index de7503c..e4b07d0 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -174,17 +174,14 @@ static u32 get_ipg_per_clk(void) u32 pdr4 = readl(&ccm->pdr4); u32 div; if (pdr0 & MXC_CCM_PDR0_PER_SEL) { - div = (CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_PER0_PRDF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * - (CCM_GET_DIVIDER(pdr4, + div = CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_PER0_PODF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; } else { div = CCM_GET_DIVIDER(pdr0, MXC_CCM_PDR0_PER_PODF_MASK, MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; - freq /= get_ahb_div(pdr0); + div *= get_ahb_div(pdr0); } return freq / div; } @@ -202,19 +199,16 @@ u32 imx_get_uartclk(void) freq = decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ); } - freq /= ((CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_UART_PRDF_MASK, - MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * - (CCM_GET_DIVIDER(pdr4, + freq /= CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_UART_PODF_MASK, - MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); + MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; return freq; } unsigned int mxc_get_main_clock(enum mxc_main_clock clk) { u32 nfc_pdf, hsp_podf; - u32 pll, ret_val = 0, usb_prdf, usb_podf; + u32 pll, ret_val = 0, usb_podf; struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; @@ -258,8 +252,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk) ret_val = pll / (nfc_pdf + 1); break; case USB_CLK: - usb_prdf = (reg4 >> 25) & 0x7; - usb_podf = (reg4 >> 22) & 0x7; + usb_podf = (reg4 >> 22) & 0x3F; if (reg4 & 0x200) { pll = get_mcu_main_clk(); } else { @@ -267,7 +260,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk) CONFIG_MX35_HCLK_FREQ); } - ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); + ret_val = pll / (usb_podf + 1); break; default: printf("Unknown clock: %d\n", clk); @@ -290,11 +283,10 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) case UART2_BAUD: case UART3_BAUD: clk_sel = mpdr3 & (1 << 14); - pre_pdf = (mpdr4 >> 13) & 0x7; - pdf = (mpdr4 >> 10) & 0x7; + pdf = (mpdr4 >> 10) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case SSI1_BAUD: pre_pdf = (mpdr2 >> 24) & 0x7; @@ -314,11 +306,10 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) break; case CSI_BAUD: clk_sel = mpdr2 & (1 << 7); - pre_pdf = (mpdr2 >> 16) & 0x7; - pdf = (mpdr2 >> 19) & 0x7; + pdf = (mpdr2 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case MSHC_CLK: pre_pdf = readl(&ccm->pdr1); @@ -331,27 +322,24 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) break; case ESDHC1_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = mpdr3 & 0x7; - pdf = (mpdr3>>3) & 0x7; + pdf = mpdr3 & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case ESDHC2_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = (mpdr3 >> 8) & 0x7; - pdf = (mpdr3 >> 11) & 0x7; + pdf = (mpdr3 >> 8) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case ESDHC3_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = (mpdr3 >> 16) & 0x7; - pdf = (mpdr3 >> 19) & 0x7; + pdf = (mpdr3 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case SPDIF_CLK: clk_sel = mpdr3 & 0x400000; diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h index fa71dea..3fcde0b 100644 --- a/arch/arm/include/asm/arch-mx35/crm_regs.h +++ b/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -32,8 +32,8 @@ #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) #define MXC_CCM_CCMR_ROMW_OFFSET 18 #define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) -#define MXC_CCM_CCMR_RAMW_OFFSET 21 -#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21) +#define MXC_CCM_CCMR_RAMW_OFFSET 16 +#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) #define MXC_CCM_CCMR_LPM_OFFSET 14 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) #define MXC_CCM_CCMR_UPE (1 << 9) @@ -47,7 +47,7 @@ #define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) #define MXC_CCM_PDR0_CKIL_SEL (1 << 15) #define MXC_CCM_PDR0_PER_PODF_OFFSET 12 -#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12) +#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) #define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) #define MXC_CCM_PDR0_AUTO_CON 0x1 @@ -62,10 +62,8 @@ #define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) #define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 #define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) -#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19 -#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19) #define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 -#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) #define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 #define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) #define MXC_CCM_PDR2_CSI_M_U (1 << 7) @@ -78,35 +76,23 @@ #define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 #define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) #define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) -#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19 -#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19) #define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 -#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16) -#define MXC_CCM_PDR3_UART_M_U (1 << 15) -#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11 -#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11) +#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) +#define MXC_CCM_PDR3_UART_M_U (1 << 14) #define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 -#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8) +#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) #define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) -#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3 -#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3) #define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 -#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7) +#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F) #define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 #define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) -#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25 -#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25) #define MXC_CCM_PDR4_USB_PODF_OFFSET 22 -#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22) -#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19 -#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22) #define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 -#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16) -#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13 -#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13) +#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) #define MXC_CCM_PDR4_UART_PODF_OFFSET 10 -#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10) +#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) #define MXC_CCM_PDR4_USB_M_U (1 << 9) /* Bit definitions for RCSR */ @@ -257,10 +243,8 @@ #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 #define MXC_CCM_COSR_CLKOEN (1 << 5) #define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) -#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10) -#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10 -#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13) -#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13 +#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) +#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) -- cgit v1.1 From 1b2080f3388b70c4c37b69830f73a61c50cdd505 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 21 Aug 2012 11:05:12 +0000 Subject: mx25: Define default SoC input clock frequencies MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define default SoC input clock frequencies for i.MX25 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Cc: Fabio Estevam Cc: Matthias Weisser --- arch/arm/cpu/arm926ejs/mx25/generic.c | 2 +- arch/arm/cpu/arm926ejs/mx25/timer.c | 16 ++++++++-------- arch/arm/include/asm/arch-mx25/clock.h | 14 ++++++++++++++ include/configs/mx25pdk.h | 1 - include/configs/zmx25.h | 1 - 5 files changed, 23 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index a412a8f..90e584a 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -64,7 +64,7 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) static ulong imx_get_mpllclk(void) { struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong fref = 24000000; + ulong fref = MXC_HCLK; return imx_decode_pll(readl(&ccm->mpctl), fref); } diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c index 1cfd02b..4dc4041 100644 --- a/arch/arm/cpu/arm926ejs/mx25/timer.c +++ b/arch/arm/cpu/arm926ejs/mx25/timer.c @@ -40,6 +40,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -55,28 +56,27 @@ DECLARE_GLOBAL_DATA_PTR; static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_MX25_CLK32); + do_div(tick, MXC_CLK32); return tick; } static inline unsigned long long time_to_tick(unsigned long long time) { - time *= CONFIG_MX25_CLK32; + time *= MXC_CLK32; do_div(time, CONFIG_SYS_HZ); return time; } static inline unsigned long long us_to_tick(unsigned long long us) { - us = us * CONFIG_MX25_CLK32 + 999999; + us = us * MXC_CLK32 + 999999; do_div(us, 1000000); return us; } #else /* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \ - CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / CONFIG_MX25_CLK32) +#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) +#define US_PER_TICK (1000000 / MXC_CLK32) static inline unsigned long long tick_to_time(unsigned long long tick) { @@ -144,7 +144,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -177,6 +177,6 @@ ulong get_tbclk(void) { ulong tbclk; - tbclk = CONFIG_MX25_CLK32; + tbclk = MXC_CLK32; return tbclk; } diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h index 0f47eaf..a313b80 100644 --- a/arch/arm/include/asm/arch-mx25/clock.h +++ b/arch/arm/include/asm/arch-mx25/clock.h @@ -26,6 +26,20 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include + +#ifdef CONFIG_MX25_HCLK_FREQ +#define MXC_HCLK CONFIG_MX25_HCLK_FREQ +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_MX25_CLK32 +#define MXC_CLK32 CONFIG_MX25_CLK32 +#else +#define MXC_CLK32 32768 +#endif + enum mxc_clock { MXC_CSI_CLK, MXC_EPIT_CLK, diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index 359a308..96c143e 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -17,7 +17,6 @@ /* High Level Configuration Options */ -#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TEXT_BASE 0x81200000 diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 072945a..447683a 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -28,7 +28,6 @@ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_MX25 -#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TEXT_BASE 0xA0000000 -- cgit v1.1 From 9c6c5c06764b7762a016b0ede002511139166fee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 21 Aug 2012 11:07:20 +0000 Subject: mx35: Define default SoC input clock frequencies MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define default SoC input clock frequencies for i.MX35 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Acked-by: Stefano Babic --- arch/arm/cpu/arm1136/mx35/generic.c | 43 +++++++++++++--------------------- arch/arm/cpu/arm1136/mx35/timer.c | 2 +- arch/arm/include/asm/arch-mx35/clock.h | 14 +++++++++++ include/configs/flea3.h | 1 - include/configs/mx35pdk.h | 1 - 5 files changed, 31 insertions(+), 30 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index e4b07d0..ef65176 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -149,9 +149,7 @@ static u32 get_mcu_main_clk(void) struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); - fi *= - decode_pll(readl(&ccm->mpctl), - CONFIG_MX35_HCLK_FREQ); + fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK); return fi / (arm_div * fd); } @@ -193,12 +191,10 @@ u32 imx_get_uartclk(void) (struct ccm_regs *)IMX_CCM_BASE; u32 pdr4 = readl(&ccm->pdr4); - if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) { + if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) freq = get_mcu_main_clk(); - } else { - freq = decode_pll(readl(&ccm->ppctl), - CONFIG_MX35_HCLK_FREQ); - } + else + freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK); freq /= CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_UART_PODF_MASK, MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; @@ -253,12 +249,10 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk) break; case USB_CLK: usb_podf = (reg4 >> 22) & 0x3F; - if (reg4 & 0x200) { + if (reg4 & 0x200) pll = get_mcu_main_clk(); - } else { - pll = decode_pll(readl(&ccm->ppctl), - CONFIG_MX35_HCLK_FREQ); - } + else + pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK); ret_val = pll / (usb_podf + 1); break; @@ -285,15 +279,14 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) clk_sel = mpdr3 & (1 << 14); pdf = (mpdr4 >> 10) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - (pdf + 1); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case SSI1_BAUD: pre_pdf = (mpdr2 >> 24) & 0x7; pdf = mpdr2 & 0x3F; clk_sel = mpdr2 & (1 << 6); ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case SSI2_BAUD: @@ -301,15 +294,14 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) pdf = (mpdr2 >> 8) & 0x3F; clk_sel = mpdr2 & (1 << 6); ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case CSI_BAUD: clk_sel = mpdr2 & (1 << 7); pdf = (mpdr2 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - (pdf + 1); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case MSHC_CLK: pre_pdf = readl(&ccm->pdr1); @@ -317,36 +309,33 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) pdf = (pre_pdf >> 22) & 0x3F; pre_pdf = (pre_pdf >> 28) & 0x7; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case ESDHC1_CLK: clk_sel = mpdr3 & 0x40; pdf = mpdr3 & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - (pdf + 1); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case ESDHC2_CLK: clk_sel = mpdr3 & 0x40; pdf = (mpdr3 >> 8) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - (pdf + 1); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case ESDHC3_CLK: clk_sel = mpdr3 & 0x40; pdf = (mpdr3 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - (pdf + 1); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case SPDIF_CLK: clk_sel = mpdr3 & 0x400000; pre_pdf = (mpdr3 >> 29) & 0x7; pdf = (mpdr3 >> 23) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; default: diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c index 04937a1..6000042 100644 --- a/arch/arm/cpu/arm1136/mx35/timer.c +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -101,7 +101,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h index e94f124..eb7458a 100644 --- a/arch/arm/include/asm/arch-mx35/clock.h +++ b/arch/arm/include/asm/arch-mx35/clock.h @@ -24,6 +24,20 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include + +#ifdef CONFIG_MX35_HCLK_FREQ +#define MXC_HCLK CONFIG_MX35_HCLK_FREQ +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_MX35_CLK32 +#define MXC_CLK32 CONFIG_MX35_CLK32 +#else +#define MXC_CLK32 32768 +#endif + enum mxc_clock { MXC_ARM_CLK, MXC_AHB_CLK, diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 4350518..16f2d2a 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -31,7 +31,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX35 -#define CONFIG_MX35_HCLK_FREQ 24000000 #define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 32 diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 9bc6bd4..834b97d 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -31,7 +31,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX35 -#define CONFIG_MX35_HCLK_FREQ 24000000 #define CONFIG_DISPLAY_CPUINFO -- cgit v1.1 From 543d247935f544acdd16f6dc136b8b8ceca2c2a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 21 Aug 2012 11:07:54 +0000 Subject: mx35 timer: Switch to 32-kHz source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switch the mx35 timer driver to the 32-kHz clock source to avoid calling mxc_get_clock() again and again, and to be consistent with the timer drivers of other i.MX SoCs. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Acked-by: Stefano Babic --- arch/arm/cpu/arm1136/mx35/timer.c | 44 ++++++++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c index 6000042..9680b7f 100644 --- a/arch/arm/cpu/arm1136/mx35/timer.c +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -27,6 +27,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -37,43 +38,52 @@ DECLARE_GLOBAL_DATA_PTR; /* General purpose timers bitfields */ #define GPTCR_SWR (1<<15) /* Software reset */ #define GPTCR_FRR (1<<9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ -#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ #define GPTCR_TEN (1) /* Timer enable */ -#define TIMER_FREQ_HZ mxc_get_clock(MXC_IPG_CLK) - +/* + * "time" is measured in 1 / CONFIG_SYS_HZ seconds, + * "tick" is internal timer period + */ +/* ~0.4% error - measured with stop-watch on 100s boot-delay */ static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, TIMER_FREQ_HZ); + do_div(tick, MXC_CLK32); return tick; } -static inline unsigned long long us_to_tick(unsigned long long usec) +static inline unsigned long long us_to_tick(unsigned long long us) { - usec *= TIMER_FREQ_HZ; - do_div(usec, 1000000); + us = us * MXC_CLK32 + 999999; + do_div(us, 1000000); - return usec; + return us; } +/* + * nothing really to do with interrupts, just starts up a counter. + * The 32KHz 32-bit timer overruns in 134217 seconds + */ int timer_init(void) { int i; struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR; /* setup GP Timer 1 */ writel(GPTCR_SWR, &gpt->ctrl); - for (i = 0; i < 100; i++) - writel(0, &gpt->ctrl); /* We have no udelay by now */ - writel(0, &gpt->pre); - /* Freerun Mode, PERCLK1 input */ - writel(readl(&gpt->ctrl) | - GPTCR_CLKSOURCE_IPG | GPTCR_TEN, - &gpt->ctrl); + writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1); + + for (i = 0; i < 100; i++) + writel(0, &gpt->ctrl); /* We have no udelay by now */ + writel(0, &gpt->pre); /* prescaler = 1 */ + /* Freerun Mode, 32KHz input */ + writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, + &gpt->ctrl); + writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl); return 0; } @@ -132,5 +142,5 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return TIMER_FREQ_HZ; + return MXC_CLK32; } -- cgit v1.1 From 697191d57fb2fae7b31cec9581fb7749f965d877 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 14 Aug 2012 08:43:47 +0000 Subject: Fix mx31_decode_pll MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- arch/arm/cpu/arm1136/mx31/generic.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 8873fb7..3a35bfa 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -22,6 +22,7 @@ */ #include +#include #include #include #include @@ -30,16 +31,17 @@ static u32 mx31_decode_pll(u32 reg, u32 infreq) { u32 mfi = GET_PLL_MFI(reg); - u32 mfn = GET_PLL_MFN(reg); + s32 mfn = GET_PLL_MFN(reg); u32 mfd = GET_PLL_MFD(reg); u32 pd = GET_PLL_PD(reg); mfi = mfi <= 5 ? 5 : mfi; + mfn = mfn >= 512 ? mfn - 1024 : mfn; mfd += 1; pd += 1; - return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) / - (mfd * pd)) << 10; + return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), + mfd * pd); } static u32 mx31_get_mpl_dpdgck_clk(void) -- cgit v1.1 From 88d155596879035532f8be05172d605965c733ed Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 31 Aug 2012 16:07:59 +0000 Subject: MX28: SPI: Fix the DMA DCache race condition This patch fixes dcache-related problem. The problem manifested when dcache was enabled and the following command issued twice: mw 0x42000000 0 0x4000 ; sf probe ; sf read 0x42000000 0x0 0x10000 ; sha1sum 0x42000000 0x10000 The SHA1 checksum was correct during the first call. Yet with every subsequent call of the above command, it differed and was wrong. It turns out this was because of a race condition. On the first time the command was called, no cacheline contained any data from the destination memory location. The DMA transfered data into the location and the cache above the location was invalidated. Then the checksum was computed, but that meant the data were loaded into data cache. On any subsequent call, the DMA again transfered data into the same destination. Yet during the transfer, some of the DCache lines were evicted and written back into the main memory. Once the DMA transfer completed, the data cache was invalidated over the memory location as usual. But the data that were to be loaded back into the data cache by subsequent SHA1 checksuming were corrupted. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic --- drivers/spi/mxs_spi.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 168dbe4..c399707 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -224,6 +224,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, struct mxs_dma_desc *dp; uint32_t ctrl0; uint32_t cache_data_count; + const uint32_t dstart = (uint32_t)data; int dmach; int tl; @@ -246,10 +247,12 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, else cache_data_count = length; + /* Flush data to DRAM so DMA can pick them up */ if (write) - /* Flush data to DRAM so DMA can pick them up */ - flush_dcache_range((uint32_t)data, - (uint32_t)(data + cache_data_count)); + flush_dcache_range(dstart, dstart + cache_data_count); + + /* Invalidate the area, so no writeback into the RAM races with DMA */ + invalidate_dcache_range(dstart, dstart + cache_data_count); dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus; @@ -310,10 +313,8 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, return -EINVAL; /* The data arrived into DRAM, invalidate cache over them */ - if (!write) { - invalidate_dcache_range((uint32_t)data, - (uint32_t)(data + cache_data_count)); - } + if (!write) + invalidate_dcache_range(dstart, dstart + cache_data_count); return 0; } -- cgit v1.1 From e9f7eafd3cc932d5d6e7e8acd96d5f15679e4a86 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 31 Aug 2012 16:08:00 +0000 Subject: MX28: SPI: Fix the DMA chaining It turns out that in order for the SPI DMA to properly support continuous transfers longer than 65280 bytes, there are some very important parts that were left out from the documentation. Firstly, the XFER_SIZE register is not written with the whole length of a transfer, but is written by each and every chained descriptor with the length of the descriptors data buffer. Next, unlike the demo code supplied by FSL, which only writes one PIO word per descriptor, this does not apply if the descriptors are chained, since the XFER_SIZE register must be written. Therefore, it is essential to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are written with zero, since they don't apply. The DMA programs the PIO words in an incrementing order, so four PIO words. Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC must not be set during the whole transfer, but it must be set only on the last descriptor in the chain. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic --- drivers/spi/mxs_spi.c | 43 +++++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index c399707..42e4c99 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -227,6 +227,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, const uint32_t dstart = (uint32_t)data; int dmach; int tl; + int ret = 0; ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count); @@ -240,8 +241,6 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, if (!write) ctrl0 |= SSP_CTRL0_READ; - writel(length, &ssp_regs->hw_ssp_xfer_size); - if (length % ARCH_DMA_MINALIGN) cache_data_count = roundup(length, ARCH_DMA_MINALIGN); else @@ -284,39 +283,47 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, tl = min(length, xfer_max_sz); dp->cmd.data |= - (tl << MXS_DMA_DESC_BYTES_OFFSET) | - (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | + ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) | + (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | MXS_DMA_DESC_HALT_ON_TERMINATE | MXS_DMA_DESC_TERMINATE_FLUSH; - dp->cmd.pio_words[0] = ctrl0; data += tl; length -= tl; + if (!length) { + dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; + + if (flags & SPI_XFER_END) { + ctrl0 &= ~SSP_CTRL0_LOCK_CS; + ctrl0 |= SSP_CTRL0_IGNORE_CRC; + } + } + + /* + * Write CTRL0, CMD0, CMD1, XFER_SIZE registers. It is + * essential that the XFER_SIZE register is written on + * a per-descriptor basis with the same size as is the + * descriptor! + */ + dp->cmd.pio_words[0] = ctrl0; + dp->cmd.pio_words[1] = 0; + dp->cmd.pio_words[2] = 0; + dp->cmd.pio_words[3] = tl; + mxs_dma_desc_append(dmach, dp); dp++; } - dp->address = (dma_addr_t)dp; - dp->cmd.address = (dma_addr_t)0; - dp->cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | - (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | - MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; - if (flags & SPI_XFER_END) { - ctrl0 &= ~SSP_CTRL0_LOCK_CS; - dp->cmd.pio_words[0] = ctrl0 | SSP_CTRL0_IGNORE_CRC; - } - mxs_dma_desc_append(dmach, dp); - if (mxs_dma_go(dmach)) - return -EINVAL; + ret = -EINVAL; /* The data arrived into DRAM, invalidate cache over them */ if (!write) invalidate_dcache_range(dstart, dstart + cache_data_count); - return 0; + return ret; } int spi_xfer(struct spi_slave *slave, unsigned int bitlen, -- cgit v1.1 From 97ed12cedf9cd47ddc4553c3fa9f3e8f92cba8c3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 31 Aug 2012 16:18:10 +0000 Subject: MX28: MMC: Avoid DMA DCache race condition This patch prevents dcache-related problem. The problem manifested itself on the SPI driver, this is just a port to the MMC driver. The scenario is the same. In case an "mmc read" is issued to a buffer which was written right before it and data cache is enabled, the cache eviction might happen during the DMA transfer into the buffer, therefore corrupting the buffer. Clear any cache lines that might contain the buffer to prevent such issue. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic --- drivers/mmc/mxsmmc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 9a98c6b..c80b41b 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -119,6 +119,10 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) (uint32_t)(priv->desc->cmd.address + cache_data_count)); } + /* Invalidate the area, so no writeback into the RAM races with DMA */ + invalidate_dcache_range((uint32_t)priv->desc->cmd.address, + (uint32_t)(priv->desc->cmd.address + cache_data_count)); + priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | (data_count << MXS_DMA_DESC_BYTES_OFFSET); -- cgit v1.1 From 0dc7b82e4ec7cb95738aebd368d06a5cd8e37595 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 21 Aug 2012 11:06:03 +0000 Subject: mx31: Define default SoC input clock frequencies MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define default SoC input clock frequencies for i.MX31 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Cc: Fabio Estevam Cc: Wolfgang Denk Cc: Helmut Raiger --- arch/arm/cpu/arm1136/mx31/generic.c | 4 ++-- arch/arm/cpu/arm1136/mx31/timer.c | 16 ++++++++-------- arch/arm/include/asm/arch-mx31/clock.h | 14 ++++++++++++++ include/configs/imx31_litekit.h | 1 - include/configs/imx31_phycore.h | 1 - include/configs/mx31ads.h | 2 -- include/configs/mx31pdk.h | 2 -- include/configs/qong.h | 2 -- include/configs/tt01.h | 2 -- 9 files changed, 24 insertions(+), 20 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 3a35bfa..93f429c 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -49,9 +49,9 @@ static u32 mx31_get_mpl_dpdgck_clk(void) u32 infreq; if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) - infreq = CONFIG_MX31_CLK32 * 1024; + infreq = MXC_CLK32 * 1024; else - infreq = CONFIG_MX31_HCLK_FREQ; + infreq = MXC_HCLK; return mx31_decode_pll(readl(CCM_MPCTL), infreq); } diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index 72081a8..36266da 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -23,6 +23,7 @@ #include #include +#include #include #include #include @@ -53,28 +54,27 @@ DECLARE_GLOBAL_DATA_PTR; static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_MX31_CLK32); + do_div(tick, MXC_CLK32); return tick; } static inline unsigned long long time_to_tick(unsigned long long time) { - time *= CONFIG_MX31_CLK32; + time *= MXC_CLK32; do_div(time, CONFIG_SYS_HZ); return time; } static inline unsigned long long us_to_tick(unsigned long long us) { - us = us * CONFIG_MX31_CLK32 + 999999; + us = us * MXC_CLK32 + 999999; do_div(us, 1000000); return us; } #else /* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \ - / CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) +#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) +#define US_PER_TICK (1000000 / MXC_CLK32) static inline unsigned long long tick_to_time(unsigned long long tick) { @@ -128,7 +128,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -159,7 +159,7 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return CONFIG_MX31_CLK32; + return MXC_CLK32; } void reset_cpu(ulong addr) diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index 852c19c..9468b45 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -24,6 +24,20 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include + +#ifdef CONFIG_MX31_HCLK_FREQ +#define MXC_HCLK CONFIG_MX31_HCLK_FREQ +#else +#define MXC_HCLK 26000000 +#endif + +#ifdef CONFIG_MX31_CLK32 +#define MXC_CLK32 CONFIG_MX31_CLK32 +#else +#define MXC_CLK32 32768 +#endif + enum mxc_clock { MXC_ARM_CLK, MXC_IPG_CLK, diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 8cca478..6ae764a 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -33,7 +33,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 #define CONFIG_MX31_CLK32 32000 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index b21621c..f36ceea 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -33,7 +33,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX31 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 #define CONFIG_MX31_CLK32 32000 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 081fbf6..9d9f4a7 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -27,8 +27,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */ -#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 17d3143..b272674 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -35,8 +35,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX31 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 -#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/qong.h b/include/configs/qong.h index 485e1b1..c2bd097 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -28,8 +28,6 @@ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX31 /* in a mx31 */ #define CONFIG_QONG -#define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */ -#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/tt01.h b/include/configs/tt01.h index cc68a42..f46efa5 100644 --- a/include/configs/tt01.h +++ b/include/configs/tt01.h @@ -31,8 +31,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 #define CONFIG_MX31 -#define CONFIG_MX31_HCLK_FREQ 26000000 -#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -- cgit v1.1 From b85705e60ec0f5ce2638ccf27a802e8df1a8d57c Mon Sep 17 00:00:00 2001 From: Ashok Kumar Reddy Date: Wed, 5 Sep 2012 22:09:37 +0530 Subject: ima3-mx53:Rename CONFIG_PRIME => CONFIG_ETHPRME, remove unused macro CONFIG_DISCOVER_PHY Signed-off-by: Ashok Kumar Reddy Acked-by: Stefano Babic --- include/configs/ima3-mx53.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h index 567061a..dbc59b9 100644 --- a/include/configs/ima3-mx53.h +++ b/include/configs/ima3-mx53.h @@ -64,7 +64,6 @@ /* Ethernet on FEC */ #define CONFIG_NET_MULTI #define CONFIG_MII -#define CONFIG_DISCOVER_PHY #define CONFIG_FEC_MXC #define IMX_FEC_BASE FEC_BASE_ADDR @@ -72,7 +71,7 @@ #define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR #define CONFIG_RESET_PHY_R #define CONFIG_FEC_MXC_NO_ANEG -#define CONFIG_PRIME "FEC0" +#define CONFIG_ETHPRIME "FEC0" /* SPI */ #define CONFIG_HARD_SPI -- cgit v1.1 From ea00e59be08989dae905076f4acf3eb297fce552 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 5 Sep 2012 20:16:36 +0000 Subject: MX: set a common place to share code for Freescale i.MX Up now only MX5 and MX6 can share code, because they have a common source directory in cpu/armv7. Other not armv7 i.MX can profit of the same shared code. Move these files into a directory accessible for all, similar to plat-mxc in linux. Signed-off-by: Stefano Babic --- Makefile | 7 +- arch/arm/cpu/armv7/imx-common/Makefile | 50 ---------- arch/arm/cpu/armv7/imx-common/cmd_bmode.c | 119 ------------------------ arch/arm/cpu/armv7/imx-common/cpu.c | 140 ---------------------------- arch/arm/cpu/armv7/imx-common/i2c.c | 99 -------------------- arch/arm/cpu/armv7/imx-common/iomux-v3.c | 70 -------------- arch/arm/cpu/armv7/imx-common/speed.c | 45 --------- arch/arm/cpu/armv7/imx-common/timer.c | 149 ------------------------------ arch/arm/imx-common/Makefile | 52 +++++++++++ arch/arm/imx-common/cmd_bmode.c | 119 ++++++++++++++++++++++++ arch/arm/imx-common/cpu.c | 140 ++++++++++++++++++++++++++++ arch/arm/imx-common/i2c-mxv7.c | 99 ++++++++++++++++++++ arch/arm/imx-common/iomux-v3.c | 70 ++++++++++++++ arch/arm/imx-common/speed.c | 45 +++++++++ arch/arm/imx-common/timer.c | 149 ++++++++++++++++++++++++++++++ 15 files changed, 676 insertions(+), 677 deletions(-) delete mode 100644 arch/arm/cpu/armv7/imx-common/Makefile delete mode 100644 arch/arm/cpu/armv7/imx-common/cmd_bmode.c delete mode 100644 arch/arm/cpu/armv7/imx-common/cpu.c delete mode 100644 arch/arm/cpu/armv7/imx-common/i2c.c delete mode 100644 arch/arm/cpu/armv7/imx-common/iomux-v3.c delete mode 100644 arch/arm/cpu/armv7/imx-common/speed.c delete mode 100644 arch/arm/cpu/armv7/imx-common/timer.c create mode 100644 arch/arm/imx-common/Makefile create mode 100644 arch/arm/imx-common/cmd_bmode.c create mode 100644 arch/arm/imx-common/cpu.c create mode 100644 arch/arm/imx-common/i2c-mxv7.c create mode 100644 arch/arm/imx-common/iomux-v3.c create mode 100644 arch/arm/imx-common/speed.c create mode 100644 arch/arm/imx-common/timer.c diff --git a/Makefile b/Makefile index e5f8d05..fe2f98c 100644 --- a/Makefile +++ b/Makefile @@ -306,11 +306,8 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif -ifeq ($(SOC),mx5) -LIBS-y += $(CPUDIR)/imx-common/libimx-common.o -endif -ifeq ($(SOC),mx6) -LIBS-y += $(CPUDIR)/imx-common/libimx-common.o +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) +LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif ifeq ($(SOC),s5pc1xx) diff --git a/arch/arm/cpu/armv7/imx-common/Makefile b/arch/arm/cpu/armv7/imx-common/Makefile deleted file mode 100644 index 16fba8d..0000000 --- a/arch/arm/cpu/armv7/imx-common/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)libimx-common.o - -COBJS-y = iomux-v3.o timer.o cpu.o speed.o -COBJS-$(CONFIG_I2C_MXC) += i2c.o -COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o -COBJS := $(sort $(COBJS-y)) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/armv7/imx-common/cmd_bmode.c b/arch/arm/cpu/armv7/imx-common/cmd_bmode.c deleted file mode 100644 index 02fe72e..0000000 --- a/arch/arm/cpu/armv7/imx-common/cmd_bmode.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (C) 2012 Boundary Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include - -static const struct boot_mode *modes[2]; - -static const struct boot_mode *search_modes(char *arg) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(modes); i++) { - const struct boot_mode *p = modes[i]; - if (p) { - while (p->name) { - if (!strcmp(p->name, arg)) - return p; - p++; - } - } - } - return NULL; -} - -static int create_usage(char *dest) -{ - int i; - int size = 0; - - for (i = 0; i < ARRAY_SIZE(modes); i++) { - const struct boot_mode *p = modes[i]; - if (p) { - while (p->name) { - int len = strlen(p->name); - if (dest) { - memcpy(dest, p->name, len); - dest += len; - *dest++ = '|'; - } - size += len + 1; - p++; - } - } - } - if (dest) - memcpy(dest - 1, " [noreset]", 11); /* include trailing 0 */ - size += 10; - return size; -} - -static int do_boot_mode(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - const struct boot_mode *p; - int reset_requested = 1; - - if (argc < 2) - return CMD_RET_USAGE; - p = search_modes(argv[1]); - if (!p) - return CMD_RET_USAGE; - if (argc == 3) { - if (strcmp(argv[2], "noreset")) - return CMD_RET_USAGE; - reset_requested = 0; - } - - boot_mode_apply(p->cfg_val); - if (reset_requested && p->cfg_val) - do_reset(NULL, 0, 0, NULL); - return 0; -} - -U_BOOT_CMD( - bmode, 3, 0, do_boot_mode, - NULL, - ""); - -void add_board_boot_modes(const struct boot_mode *p) -{ - int size; - char *dest; - - if (__u_boot_cmd_bmode.usage) { - free(__u_boot_cmd_bmode.usage); - __u_boot_cmd_bmode.usage = NULL; - } - - modes[0] = p; - modes[1] = soc_boot_modes; - size = create_usage(NULL); - dest = malloc(size); - if (dest) { - create_usage(dest); - __u_boot_cmd_bmode.usage = dest; - } -} diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c deleted file mode 100644 index fa1d468..0000000 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2007 - * Sascha Hauer, Pengutronix - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_FSL_ESDHC -#include -#endif - -char *get_reset_cause(void) -{ - u32 cause; - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - - cause = readl(&src_regs->srsr); - writel(cause, &src_regs->srsr); - - switch (cause) { - case 0x00001: - case 0x00011: - return "POR"; - case 0x00004: - return "CSU"; - case 0x00008: - return "IPP USER"; - case 0x00010: - return "WDOG"; - case 0x00020: - return "JTAG HIGH-Z"; - case 0x00040: - return "JTAG SW"; - case 0x10000: - return "WARM BOOT"; - default: - return "unknown reset"; - } -} - -#if defined(CONFIG_DISPLAY_CPUINFO) - -static const char *get_imx_type(u32 imxtype) -{ - switch (imxtype) { - case 0x63: - return "6Q"; /* Quad-core version of the mx6 */ - case 0x61: - return "6DS"; /* Dual/Solo version of the mx6 */ - case 0x60: - return "6SL"; /* Solo-Lite version of the mx6 */ - case 0x51: - return "51"; - case 0x53: - return "53"; - default: - return "??"; - } -} - -int print_cpuinfo(void) -{ - u32 cpurev; - - cpurev = get_cpu_rev(); - - printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", - get_imx_type((cpurev & 0xFF000) >> 12), - (cpurev & 0x000F0) >> 4, - (cpurev & 0x0000F) >> 0, - mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("Reset cause: %s\n", get_reset_cause()); - return 0; -} -#endif - -int cpu_eth_init(bd_t *bis) -{ - int rc = -ENODEV; - -#if defined(CONFIG_FEC_MXC) - rc = fecmxc_initialize(bis); -#endif - - return rc; -} - -#ifdef CONFIG_FSL_ESDHC -/* - * Initializes on-chip MMC controllers. - * to override, implement board_mmc_init() - */ -int cpu_mmc_init(bd_t *bis) -{ - return fsl_esdhc_mmc_init(bis); -} -#endif - -void reset_cpu(ulong addr) -{ - __raw_writew(4, WDOG1_BASE_ADDR); -} - -u32 get_ahb_clk(void) -{ - struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - u32 reg, ahb_podf; - - reg = __raw_readl(&imx_ccm->cbcdr); - reg &= MXC_CCM_CBCDR_AHB_PODF_MASK; - ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; - - return get_periph_clk() / (ahb_podf + 1); -} diff --git a/arch/arm/cpu/armv7/imx-common/i2c.c b/arch/arm/cpu/armv7/imx-common/i2c.c deleted file mode 100644 index da2b26f..0000000 --- a/arch/arm/cpu/armv7/imx-common/i2c.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2012 Boundary Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include - -static int force_idle_bus(void *priv) -{ - int i; - int sda, scl; - ulong elapsed, start_time; - struct i2c_pads_info *p = (struct i2c_pads_info *)priv; - int ret = 0; - - gpio_direction_input(p->sda.gp); - gpio_direction_input(p->scl.gp); - - imx_iomux_v3_setup_pad(p->sda.gpio_mode); - imx_iomux_v3_setup_pad(p->scl.gpio_mode); - - sda = gpio_get_value(p->sda.gp); - scl = gpio_get_value(p->scl.gp); - if ((sda & scl) == 1) - goto exit; /* Bus is idle already */ - - printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__, - sda, scl, p->sda.gp, p->scl.gp); - /* Send high and low on the SCL line */ - for (i = 0; i < 9; i++) { - gpio_direction_output(p->scl.gp, 0); - udelay(50); - gpio_direction_input(p->scl.gp); - udelay(50); - } - start_time = get_timer(0); - for (;;) { - sda = gpio_get_value(p->sda.gp); - scl = gpio_get_value(p->scl.gp); - if ((sda & scl) == 1) - break; - WATCHDOG_RESET(); - elapsed = get_timer(start_time); - if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */ - ret = -EBUSY; - printf("%s: failed to clear bus, sda=%d scl=%d\n", - __func__, sda, scl); - break; - } - } -exit: - imx_iomux_v3_setup_pad(p->sda.i2c_mode); - imx_iomux_v3_setup_pad(p->scl.i2c_mode); - return ret; -} - -static void * const i2c_bases[] = { - (void *)I2C1_BASE_ADDR, - (void *)I2C2_BASE_ADDR, -#ifdef I2C3_BASE_ADDR - (void *)I2C3_BASE_ADDR, -#endif -}; - -/* i2c_index can be from 0 - 2 */ -void setup_i2c(unsigned i2c_index, int speed, int slave_addr, - struct i2c_pads_info *p) -{ - if (i2c_index >= ARRAY_SIZE(i2c_bases)) - return; - /* Enable i2c clock */ - enable_i2c_clk(1, i2c_index); - /* Make sure bus is idle */ - force_idle_bus(p); - bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr, - force_idle_bus, p); -} diff --git a/arch/arm/cpu/armv7/imx-common/iomux-v3.c b/arch/arm/cpu/armv7/imx-common/iomux-v3.c deleted file mode 100644 index da093fb..0000000 --- a/arch/arm/cpu/armv7/imx-common/iomux-v3.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Based on the iomux-v3.c from Linux kernel: - * Copyright (C) 2008 by Sascha Hauer - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * - * - * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#include -#include -#include -#include - -static void *base = (void *)IOMUXC_BASE_ADDR; - -/* - * configures a single pad in the iomuxer - */ -int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) -{ - u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; - u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; - u32 sel_input_ofs = - (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; - u32 sel_input = - (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; - u32 pad_ctrl_ofs = - (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; - u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; - - if (mux_ctrl_ofs) - __raw_writel(mux_mode, base + mux_ctrl_ofs); - - if (sel_input_ofs) - __raw_writel(sel_input, base + sel_input_ofs); - - if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) - __raw_writel(pad_ctrl, base + pad_ctrl_ofs); - - return 0; -} - -int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) -{ - iomux_v3_cfg_t *p = pad_list; - int i; - int ret; - - for (i = 0; i < count; i++) { - ret = imx_iomux_v3_setup_pad(*p); - if (ret) - return ret; - p++; - } - return 0; -} diff --git a/arch/arm/cpu/armv7/imx-common/speed.c b/arch/arm/cpu/armv7/imx-common/speed.c deleted file mode 100644 index 80989c4..0000000 --- a/arch/arm/cpu/armv7/imx-common/speed.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_FSL_ESDHC -DECLARE_GLOBAL_DATA_PTR; -#endif - -int get_clocks(void) -{ -#ifdef CONFIG_FSL_ESDHC -#ifdef CONFIG_FSL_USDHC - gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); -#else - gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK); -#endif -#endif - return 0; -} diff --git a/arch/arm/cpu/armv7/imx-common/timer.c b/arch/arm/cpu/armv7/imx-common/timer.c deleted file mode 100644 index e2725e1..0000000 --- a/arch/arm/cpu/armv7/imx-common/timer.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2007 - * Sascha Hauer, Pengutronix - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* General purpose timers registers */ -struct mxc_gpt { - unsigned int control; - unsigned int prescaler; - unsigned int status; - unsigned int nouse[6]; - unsigned int counter; -}; - -static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; - -/* General purpose timers bitfields */ -#define GPTCR_SWR (1 << 15) /* Software reset */ -#define GPTCR_FRR (1 << 9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ -#define GPTCR_TEN 1 /* Timer enable */ -#define CLK_32KHZ 32768 /* 32Khz input */ - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp (gd->tbl) -#define lastinc (gd->lastinc) - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, CLK_32KHZ); - - return tick; -} - -static inline unsigned long long us_to_tick(unsigned long long usec) -{ - usec = usec * CLK_32KHZ + 999999; - do_div(usec, 1000000); - - return usec; -} - -int timer_init(void) -{ - int i; - ulong val; - - /* setup GP Timer 1 */ - __raw_writel(GPTCR_SWR, &cur_gpt->control); - - /* We have no udelay by now */ - for (i = 0; i < 100; i++) - __raw_writel(0, &cur_gpt->control); - - __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ - - /* Freerun Mode, PERCLK1 input */ - i = __raw_readl(&cur_gpt->control); - __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); - - val = __raw_readl(&cur_gpt->counter); - lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ); - timestamp = 0; - - return 0; -} - -unsigned long long get_ticks(void) -{ - ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */ - - if (now >= lastinc) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (now - lastinc); - } else { - /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - } - lastinc = now; - return timestamp; -} - -ulong get_timer_masked(void) -{ - /* - * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ - * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in - * 5 * 10^6 days - long enough. - */ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timstamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CLK_32KHZ; -} diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile new file mode 100644 index 0000000..b3e608e --- /dev/null +++ b/arch/arm/imx-common/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)libimx-common.o + +ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) +COBJS-y = iomux-v3.o timer.o cpu.o speed.o +COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o +endif +COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o +COBJS := $(sort $(COBJS-y)) + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/imx-common/cmd_bmode.c b/arch/arm/imx-common/cmd_bmode.c new file mode 100644 index 0000000..02fe72e --- /dev/null +++ b/arch/arm/imx-common/cmd_bmode.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2012 Boundary Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include + +static const struct boot_mode *modes[2]; + +static const struct boot_mode *search_modes(char *arg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(modes); i++) { + const struct boot_mode *p = modes[i]; + if (p) { + while (p->name) { + if (!strcmp(p->name, arg)) + return p; + p++; + } + } + } + return NULL; +} + +static int create_usage(char *dest) +{ + int i; + int size = 0; + + for (i = 0; i < ARRAY_SIZE(modes); i++) { + const struct boot_mode *p = modes[i]; + if (p) { + while (p->name) { + int len = strlen(p->name); + if (dest) { + memcpy(dest, p->name, len); + dest += len; + *dest++ = '|'; + } + size += len + 1; + p++; + } + } + } + if (dest) + memcpy(dest - 1, " [noreset]", 11); /* include trailing 0 */ + size += 10; + return size; +} + +static int do_boot_mode(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + const struct boot_mode *p; + int reset_requested = 1; + + if (argc < 2) + return CMD_RET_USAGE; + p = search_modes(argv[1]); + if (!p) + return CMD_RET_USAGE; + if (argc == 3) { + if (strcmp(argv[2], "noreset")) + return CMD_RET_USAGE; + reset_requested = 0; + } + + boot_mode_apply(p->cfg_val); + if (reset_requested && p->cfg_val) + do_reset(NULL, 0, 0, NULL); + return 0; +} + +U_BOOT_CMD( + bmode, 3, 0, do_boot_mode, + NULL, + ""); + +void add_board_boot_modes(const struct boot_mode *p) +{ + int size; + char *dest; + + if (__u_boot_cmd_bmode.usage) { + free(__u_boot_cmd_bmode.usage); + __u_boot_cmd_bmode.usage = NULL; + } + + modes[0] = p; + modes[1] = soc_boot_modes; + size = create_usage(NULL); + dest = malloc(size); + if (dest) { + create_usage(dest); + __u_boot_cmd_bmode.usage = dest; + } +} diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c new file mode 100644 index 0000000..fa1d468 --- /dev/null +++ b/arch/arm/imx-common/cpu.c @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_FSL_ESDHC +#include +#endif + +char *get_reset_cause(void) +{ + u32 cause; + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + + cause = readl(&src_regs->srsr); + writel(cause, &src_regs->srsr); + + switch (cause) { + case 0x00001: + case 0x00011: + return "POR"; + case 0x00004: + return "CSU"; + case 0x00008: + return "IPP USER"; + case 0x00010: + return "WDOG"; + case 0x00020: + return "JTAG HIGH-Z"; + case 0x00040: + return "JTAG SW"; + case 0x10000: + return "WARM BOOT"; + default: + return "unknown reset"; + } +} + +#if defined(CONFIG_DISPLAY_CPUINFO) + +static const char *get_imx_type(u32 imxtype) +{ + switch (imxtype) { + case 0x63: + return "6Q"; /* Quad-core version of the mx6 */ + case 0x61: + return "6DS"; /* Dual/Solo version of the mx6 */ + case 0x60: + return "6SL"; /* Solo-Lite version of the mx6 */ + case 0x51: + return "51"; + case 0x53: + return "53"; + default: + return "??"; + } +} + +int print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + + printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", + get_imx_type((cpurev & 0xFF000) >> 12), + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("Reset cause: %s\n", get_reset_cause()); + return 0; +} +#endif + +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + +#if defined(CONFIG_FEC_MXC) + rc = fecmxc_initialize(bis); +#endif + + return rc; +} + +#ifdef CONFIG_FSL_ESDHC +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ + return fsl_esdhc_mmc_init(bis); +} +#endif + +void reset_cpu(ulong addr) +{ + __raw_writew(4, WDOG1_BASE_ADDR); +} + +u32 get_ahb_clk(void) +{ + struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg, ahb_podf; + + reg = __raw_readl(&imx_ccm->cbcdr); + reg &= MXC_CCM_CBCDR_AHB_PODF_MASK; + ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; + + return get_periph_clk() / (ahb_podf + 1); +} diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c new file mode 100644 index 0000000..da2b26f --- /dev/null +++ b/arch/arm/imx-common/i2c-mxv7.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2012 Boundary Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include + +static int force_idle_bus(void *priv) +{ + int i; + int sda, scl; + ulong elapsed, start_time; + struct i2c_pads_info *p = (struct i2c_pads_info *)priv; + int ret = 0; + + gpio_direction_input(p->sda.gp); + gpio_direction_input(p->scl.gp); + + imx_iomux_v3_setup_pad(p->sda.gpio_mode); + imx_iomux_v3_setup_pad(p->scl.gpio_mode); + + sda = gpio_get_value(p->sda.gp); + scl = gpio_get_value(p->scl.gp); + if ((sda & scl) == 1) + goto exit; /* Bus is idle already */ + + printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__, + sda, scl, p->sda.gp, p->scl.gp); + /* Send high and low on the SCL line */ + for (i = 0; i < 9; i++) { + gpio_direction_output(p->scl.gp, 0); + udelay(50); + gpio_direction_input(p->scl.gp); + udelay(50); + } + start_time = get_timer(0); + for (;;) { + sda = gpio_get_value(p->sda.gp); + scl = gpio_get_value(p->scl.gp); + if ((sda & scl) == 1) + break; + WATCHDOG_RESET(); + elapsed = get_timer(start_time); + if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */ + ret = -EBUSY; + printf("%s: failed to clear bus, sda=%d scl=%d\n", + __func__, sda, scl); + break; + } + } +exit: + imx_iomux_v3_setup_pad(p->sda.i2c_mode); + imx_iomux_v3_setup_pad(p->scl.i2c_mode); + return ret; +} + +static void * const i2c_bases[] = { + (void *)I2C1_BASE_ADDR, + (void *)I2C2_BASE_ADDR, +#ifdef I2C3_BASE_ADDR + (void *)I2C3_BASE_ADDR, +#endif +}; + +/* i2c_index can be from 0 - 2 */ +void setup_i2c(unsigned i2c_index, int speed, int slave_addr, + struct i2c_pads_info *p) +{ + if (i2c_index >= ARRAY_SIZE(i2c_bases)) + return; + /* Enable i2c clock */ + enable_i2c_clk(1, i2c_index); + /* Make sure bus is idle */ + force_idle_bus(p); + bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr, + force_idle_bus, p); +} diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c new file mode 100644 index 0000000..da093fb --- /dev/null +++ b/arch/arm/imx-common/iomux-v3.c @@ -0,0 +1,70 @@ +/* + * Based on the iomux-v3.c from Linux kernel: + * Copyright (C) 2008 by Sascha Hauer + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * + * + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#include +#include +#include +#include + +static void *base = (void *)IOMUXC_BASE_ADDR; + +/* + * configures a single pad in the iomuxer + */ +int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) +{ + u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; + u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; + u32 sel_input_ofs = + (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; + u32 sel_input = + (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; + u32 pad_ctrl_ofs = + (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; + u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; + + if (mux_ctrl_ofs) + __raw_writel(mux_mode, base + mux_ctrl_ofs); + + if (sel_input_ofs) + __raw_writel(sel_input, base + sel_input_ofs); + + if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) + __raw_writel(pad_ctrl, base + pad_ctrl_ofs); + + return 0; +} + +int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) +{ + iomux_v3_cfg_t *p = pad_list; + int i; + int ret; + + for (i = 0; i < count; i++) { + ret = imx_iomux_v3_setup_pad(*p); + if (ret) + return ret; + p++; + } + return 0; +} diff --git a/arch/arm/imx-common/speed.c b/arch/arm/imx-common/speed.c new file mode 100644 index 0000000..80989c4 --- /dev/null +++ b/arch/arm/imx-common/speed.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR; +#endif + +int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC +#ifdef CONFIG_FSL_USDHC + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#else + gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK); +#endif +#endif + return 0; +} diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c new file mode 100644 index 0000000..e2725e1 --- /dev/null +++ b/arch/arm/imx-common/timer.c @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* General purpose timers registers */ +struct mxc_gpt { + unsigned int control; + unsigned int prescaler; + unsigned int status; + unsigned int nouse[6]; + unsigned int counter; +}; + +static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1 << 15) /* Software reset */ +#define GPTCR_FRR (1 << 9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ +#define GPTCR_TEN 1 /* Timer enable */ +#define CLK_32KHZ 32768 /* 32Khz input */ + +DECLARE_GLOBAL_DATA_PTR; + +#define timestamp (gd->tbl) +#define lastinc (gd->lastinc) + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, CLK_32KHZ); + + return tick; +} + +static inline unsigned long long us_to_tick(unsigned long long usec) +{ + usec = usec * CLK_32KHZ + 999999; + do_div(usec, 1000000); + + return usec; +} + +int timer_init(void) +{ + int i; + ulong val; + + /* setup GP Timer 1 */ + __raw_writel(GPTCR_SWR, &cur_gpt->control); + + /* We have no udelay by now */ + for (i = 0; i < 100; i++) + __raw_writel(0, &cur_gpt->control); + + __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ + + /* Freerun Mode, PERCLK1 input */ + i = __raw_readl(&cur_gpt->control); + __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); + + val = __raw_readl(&cur_gpt->counter); + lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ); + timestamp = 0; + + return 0; +} + +unsigned long long get_ticks(void) +{ + ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */ + + if (now >= lastinc) { + /* + * normal mode (non roll) + * move stamp forward with absolut diff ticks + */ + timestamp += (now - lastinc); + } else { + /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + } + lastinc = now; + return timestamp; +} + +ulong get_timer_masked(void) +{ + /* + * get_ticks() returns a long long (64 bit), it wraps in + * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in + * 5 * 10^6 days - long enough. + */ + return tick_to_time(get_ticks()); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* delay x useconds AND preserve advance timstamp value */ +void __udelay(unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = us_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CLK_32KHZ; +} -- cgit v1.1 From 5d20881eec7e25d453755a930cbee3ba441d9ec7 Mon Sep 17 00:00:00 2001 From: Ashok Kumar Reddy Date: Sat, 8 Sep 2012 17:56:51 +0530 Subject: mx6qsabrelite:Use IMX_GPIO_NR Macro Signed-off-by: Ashok Kumar Reddy --- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 909ccca..4b4e89b 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -197,18 +197,18 @@ static iomux_v3_cfg_t button_pads[] = { static void setup_iomux_enet(void) { - gpio_direction_output(87, 0); /* GPIO 3-23 */ - gpio_direction_output(190, 1); /* GPIO 6-30 */ - gpio_direction_output(185, 1); /* GPIO 6-25 */ - gpio_direction_output(187, 1); /* GPIO 6-27 */ - gpio_direction_output(188, 1); /* GPIO 6-28*/ - gpio_direction_output(189, 1); /* GPIO 6-29 */ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); - gpio_direction_output(184, 1); /* GPIO 6-24 */ + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); /* Need delay 10ms according to KSZ9021 spec */ udelay(1000 * 10); - gpio_set_value(87, 1); /* GPIO 3-23 */ + gpio_set_value(IMX_GPIO_NR(3, 23), 1); imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); } @@ -249,11 +249,11 @@ int board_mmc_getcd(struct mmc *mmc) int ret; if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(192); /*GPIO7_0*/ - ret = !gpio_get_value(192); + gpio_direction_input(IMX_GPIO_NR(7, 0)); + ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); } else { - gpio_direction_input(38); /*GPIO2_6*/ - ret = !gpio_get_value(38); + gpio_direction_input(IMX_GPIO_NR(2, 6)); + ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); } return ret; -- cgit v1.1 From 3292539e7dc347c2d8a8f307b3a1ffa67ca1d4fe Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 5 Sep 2012 21:47:42 +0000 Subject: MX35: mx35pdk: add support for MMC Add support for SD card and change the default environment due to increased u-boot size. Signed-off-by: Stefano Babic --- board/freescale/mx35pdk/mx35pdk.c | 25 +++++++++++++++++++++++++ include/configs/mx35pdk.h | 17 +++++++++++++++-- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index 787c923..7cb6b30 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -32,6 +32,8 @@ #include #include #include +#include +#include #include #include #include @@ -275,3 +277,26 @@ int board_eth_init(bd_t *bis) return rc; } + +#if defined(CONFIG_FSL_ESDHC) + +struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; + +int board_mmc_init(bd_t *bis) +{ + /* configure pins for SDHC1 only */ + mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC); + + return fsl_esdhc_initialize(bis, &esdhc_cfg); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4); +} +#endif diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 834b97d..38b1546 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -110,6 +110,12 @@ #define CONFIG_NET_RETRY_COUNT 100 #define CONFIG_CMD_DATE +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + #define CONFIG_BOOTDELAY 3 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ @@ -237,6 +243,13 @@ #define CONFIG_MXC_NAND_HWECC #define CONFIG_SYS_NAND_LARGEPAGE +/* mmc driver */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + /* * Default environment and default scripts * to update uboot and load kernel @@ -278,8 +291,8 @@ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "load=tftp ${loadaddr} ${u-boot}\0" \ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \ - "update=protect off ${uboot_addr} +40000;" \ - "erase ${uboot_addr} +40000;" \ + "update=protect off ${uboot_addr} +80000;" \ + "erase ${uboot_addr} +80000;" \ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ "upd=if run load;then echo Updating u-boot;if run update;" \ "then echo U-Boot updated;" \ -- cgit v1.1 From 19f59ea6db96fed898e6a25dc11a61437a2a429d Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 16 Sep 2012 14:52:10 +0200 Subject: MX6: drop binary constants from iomux header Constants set with binary value (0b...) are not compiled from old toolchain when used by the clrsetbits_le32 macro. Replaces them with the corresponding hex value. The error reported (for example with the mx6qsabrelite board) is something like: mx6qsabrelite.c:369:1: error: invalid suffix "b101" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10010" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b0000" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10001" on integer constant Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx6/iomux.h | 124 +++++++++++++++++----------------- 1 file changed, 62 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index a1255f9..d23abd7 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -34,21 +34,21 @@ #define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2) #define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (3<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (4<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (5<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (6<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (7<<24) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19) #define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15) #define IOMUXC_GPR13_SATA_SPEED_3G (1<<15) @@ -63,55 +63,55 @@ #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11) #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (1<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (2<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (3<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (4<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (5<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (6<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (7<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (8<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (9<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0xA<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0xB<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0xC<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0xD<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0xE<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0xF<<7) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (1<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (2<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (3<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (4<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (5<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (6<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (7<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (8<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (9<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0xA<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0xB<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0xC<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0xD<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0xE<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0xF<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0x10<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0x11<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0x12<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0x13<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0x14<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0x15<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0x16<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0x17<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0x18<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0x19<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0x1A<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0x1B<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0x1C<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0x1D<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0x1E<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0x1F<<2) #define IOMUXC_GPR13_SATA_PHY_1_FAST 0 #define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1 -- cgit v1.1 From f994dc5ecfbb702cc8041de246e7aa58c6ed0e9f Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 15 Sep 2012 08:26:17 +0000 Subject: mx28evk: extend default environment The environment has been based on mx53loco and m28evk but keeping the possibility to easy change the default console device as Freescale and mainline kernels differ on the device name. Signed-off-by: Otavio Salvador --- include/configs/mx28evk.h | 82 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 74 insertions(+), 8 deletions(-) diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 43b4002..dffb744 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -239,7 +239,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "run bootcmd_net" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_OF_LIBFDT @@ -248,13 +247,80 @@ * Extra Environments */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "console_fsl=console=ttyAM0" \ - "console_mainline=console=ttyAMA0" \ - "netargs=setenv bootargs console=${console_mainline}" \ + "update_nand_full_filename=u-boot.nand\0" \ + "update_nand_firmware_filename=u-boot.sb\0" \ + "update_sd_firmware_filename=u-boot.sd\0" \ + "update_nand_firmware_maxsz=0x100000\0" \ + "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ + "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ + "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \ + "nand device 0 ; " \ + "nand info ; " \ + "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ + "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ + "update_nand_full=" /* Update FCB, DBBT and FW */ \ + "if tftp ${update_nand_full_filename} ; then " \ + "run update_nand_get_fcb_size ; " \ + "nand scrub -y 0x0 ${filesize} ; " \ + "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \ + "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ + "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ + "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ + "fi\0" \ + "update_nand_firmware=" /* Update only firmware */ \ + "if tftp ${update_nand_firmware_filename} ; then " \ + "run update_nand_get_fcb_size ; " \ + "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \ + "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \ + "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \ + "nand erase ${fcb_sz} ${fw_sz} ; " \ + "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ + "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ + "fi\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if tftp ${update_sd_firmware_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console_fsl=ttyAM0\0" \ + "console_mainline=ttyAMA0\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm\0" \ + "netargs=setenv bootargs console=${console_mainline},${baudrate} " \ "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot}\0" \ - "bootcmd_net=echo Booting from net ...; " \ - "run netargs; " \ - "dhcp ${uimage}; bootm\0" \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "dhcp ${uimage}; bootm\0" + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" #endif /* __MX28EVK_CONFIG_H__ */ -- cgit v1.1 From 1d9b033269263a69f7402f508c17b242fc7fea43 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 14 Sep 2012 12:14:54 +0000 Subject: mx35pdk: README: Remove NAND references Booting from NAND is currently not supported, so remove its references. Signed-off-by: Fabio Estevam --- board/freescale/mx35pdk/README | 78 ++---------------------------------------- 1 file changed, 2 insertions(+), 76 deletions(-) diff --git a/board/freescale/mx35pdk/README b/board/freescale/mx35pdk/README index 3d69ed5..7232b53 100644 --- a/board/freescale/mx35pdk/README +++ b/board/freescale/mx35pdk/README @@ -71,91 +71,17 @@ exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nf Flashing U-Boot -------------------------------- -There are two options: the original bootloader in NAND can be replaced with -u-boot, or u-boot can be stored on the NOR flash without erasing -the delivered bootloader. +U-boot should be stored on the NOR flash. + The boot storage can be select using the switches on the personality board (SW1-SW2) and on the DEBUG board (SW4-SW10). -The second option is to be preferred if you have not a JTAG debugger. If something goes wrong flashing the bootloader, it is always possible to recover the board booting from the other device. -Replacing the bootloader on the NAND --------------------------------------- -To replace RedBoot with U-Boot, the easy way is to do this in linux. -Start the kernel with the suggested options. Make sure to have set the -mtdparts exactly as described, because this matches the layout on the -mx35pdk. - -You should see in your boot log the following entries for the NAND -flash: - -5 cmdlinepart partitions found on MTD device mxc_nand -Creating 5 MTD partitions on "mxc_nand": -0x000000000000-0x000000100000 : "boot" -0x000000100000-0x000000600000 : "linux" -0x000000600000-0x000006600000 : "root" -0x000006600000-0x000006e00000 : "cfg" -0x000006e00000-0x000080000000 : "user" - -You can use the utilities flash_eraseall and nandwrite to put -u-boot on the NAND. The bootloader is marked as "boot", and 1MB is -reserved. If everything is correct, this partition is accessed as -/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and -get the device node from the partition name: - -$ cat /proc/mtd | grep boot - -I suggest you try the utilities on a different partition to be sure -if everything works correctly. If not, and you remove RedBoot, you have to -reinstall it using the ATK tool as suggested by Freescale, or using a -JTAG debugger. - -I report the versions of the utilities I used (they are provided with ELDK): - --bash-3.2# nandwrite --version -nandwrite $Revision: 1.32 $ - -flash_eraseall --version -flash_eraseall $Revision: 1.22 $ - -nandwrite reports a warning if the file to be saved is not sector aligned. -This should have no consequences, but I preferred to pad u-boot.bin -to get no problem at all. -$ dd if=/dev/zero of=zeros bs=1 count=74800 -$ cat u-boot.bin zeros > u-boot-padded.bin - -To erase the partition: -$ flash_eraseall /dev/mtd4 - -Writing u-boot: - -$ nandwrite /dev/mtd4 u-boot-padded.bin - -Now U-Boot is stored on the booting partition. - -To boot from NAND, you have to select the switches as follows: - -Personality board - SW2 1, 4, 5 on - 2, 3, 6, 7, 8 off - SW1 all off - -Debug Board: - SW5 0 - SW6 0 - SW7 0 - SW8 1 - SW9 1 - SW10 0 - - Saving U-Boot in the NOR flash --------------------------------- -The procedure to save in the NOR flash is quite the same as to write into the NAND. - Check the partition for boot in the NOR flash. Setting the mtdparts as reported, the boot partition should be /dev/mtd0. -- cgit v1.1