From cd2004037c01be34ebd61f49755fd252d03131aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Fri, 10 Aug 2012 08:51:50 +0000 Subject: mxc_spi: Round up clock divider MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the input frequency of the API is a maximum that should not be exceeded in order for the devices to operate properly, the SPI clock divider should be rounded up, not truncated. Signed-off-by: Benoît Thébaudeau Cc: Wolfgang Denk Cc: Stefano Babic Acked-by: Stefano Babic --- drivers/spi/mxc_spi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 2e15318..cf1462f 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -96,7 +96,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, clk_src = mxc_get_clock(MXC_CSPI_CLK); - div = clk_src / max_hz; + div = DIV_ROUND_UP(clk_src, max_hz); div = get_cspi_div(div); debug("clk %d Hz, div %d, real clk %d Hz\n", @@ -147,7 +147,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, * The following computation is taken directly from Freescale's code. */ if (clk_src > max_hz) { - pre_div = clk_src / max_hz; + pre_div = DIV_ROUND_UP(clk_src, max_hz); if (pre_div > 16) { post_div = pre_div / 16; pre_div = 15; -- cgit v1.1