From c89cb2d535139b3824624123af0106bf35ca0288 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Wed, 26 Mar 2014 14:28:19 +0800 Subject: ENGR00305287 iMX6SX:ARM2 Add support for 19x19 LPDDR2 ARM2 board Add imximage_lpddr2.cfg for DDR controller settings of LPDDR2. Change the folder and files name of "mx6sx_19x19_ddr3_arm2" to "mx6sx_19x19_arm2" to be shared by LPDDR2 ARM2 board and DDR3 ARM2 board. Signed-off-by: Ye.Li --- board/freescale/mx6sx_19x19_arm2/Makefile | 33 ++ board/freescale/mx6sx_19x19_arm2/imximage.cfg | 123 +++++ .../freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg | 141 +++++ .../freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c | 569 +++++++++++++++++++++ board/freescale/mx6sx_19x19_arm2/plugin.S | 150 ++++++ board/freescale/mx6sx_19x19_ddr3_arm2/Makefile | 33 -- board/freescale/mx6sx_19x19_ddr3_arm2/imximage.cfg | 123 ----- .../mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c | 569 --------------------- board/freescale/mx6sx_19x19_ddr3_arm2/plugin.S | 150 ------ boards.cfg | 6 +- include/configs/mx6sx_19x19_arm2.h | 18 + include/configs/mx6sx_19x19_ddr3_arm2.h | 18 - 12 files changed, 1038 insertions(+), 895 deletions(-) create mode 100644 board/freescale/mx6sx_19x19_arm2/Makefile create mode 100644 board/freescale/mx6sx_19x19_arm2/imximage.cfg create mode 100644 board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg create mode 100755 board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c create mode 100644 board/freescale/mx6sx_19x19_arm2/plugin.S delete mode 100644 board/freescale/mx6sx_19x19_ddr3_arm2/Makefile delete mode 100644 board/freescale/mx6sx_19x19_ddr3_arm2/imximage.cfg delete mode 100755 board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c delete mode 100644 board/freescale/mx6sx_19x19_ddr3_arm2/plugin.S create mode 100644 include/configs/mx6sx_19x19_arm2.h delete mode 100644 include/configs/mx6sx_19x19_ddr3_arm2.h diff --git a/board/freescale/mx6sx_19x19_arm2/Makefile b/board/freescale/mx6sx_19x19_arm2/Makefile new file mode 100644 index 0000000..7ba3b30 --- /dev/null +++ b/board/freescale/mx6sx_19x19_arm2/Makefile @@ -0,0 +1,33 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mx6sx_19x19_arm2.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) plugin.bin + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +plugin.bin: plugin.o + $(OBJCOPY) -O binary --gap-fill 0xff $< $@ + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx6sx_19x19_arm2/imximage.cfg b/board/freescale/mx6sx_19x19_arm2/imximage.cfg new file mode 100644 index 0000000..b34d2f3 --- /dev/null +++ b/board/freescale/mx6sx_19x19_arm2/imximage.cfg @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_19x19_arm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +SECURE_BOOT +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 +DATA 4 0x020e0340 0x00000030 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030 +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x00270025 +DATA 4 0x021b0810 0x001B001E +DATA 4 0x021b083c 0x4144013C +DATA 4 0x021b0840 0x01300128 +DATA 4 0x021b0848 0x4044464A +DATA 4 0x021b0850 0x3A383C34 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000005f +DATA 4 0x021b0000 0x84190000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00068031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg b/board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg new file mode 100644 index 0000000..e93e7e9 --- /dev/null +++ b/board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_19x19_arm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +SECURE_BOOT +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020e0618 0x00080000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 +DATA 4 0x020e0340 0x00000030 +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000000 +DATA 4 0x020e0314 0x00000000 +DATA 4 0x020e0614 0x00000030 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00003030 +DATA 4 0x020e0334 0x00003030 +DATA 4 0x020e0338 0x00003030 +DATA 4 0x020e033c 0x00003030 +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b085c 0x1b4700c7 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b0890 0x00380000 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 +DATA 4 0x021b0848 0x3e42424a +DATA 4 0x021b0850 0x38363832 +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 +DATA 4 0x021b08b8 0x00000800 + +DATA 4 0x021b000c 0x33374133 +DATA 4 0x021b0004 0x00020024 +DATA 4 0x021b0010 0x00100A42 +DATA 4 0x021b0014 0x00000093 +DATA 4 0x021b0018 0x00001748 +DATA 4 0x021b002c 0x0f9f26d2 +DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0038 0x00190778 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0xc3110000 + +DATA 4 0x021b001c 0x003f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0x82018030 +DATA 4 0x021b001c 0x04028030 +DATA 4 0x021b001c 0x02038030 + +DATA 4 0x021b001c 0x003f8038 +DATA 4 0x021b001c 0xff0a8038 +DATA 4 0x021b001c 0x82018038 +DATA 4 0x021b001c 0x04028038 +DATA 4 0x021b001c 0x02038038 + +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b0818 0x00000000 +DATA 4 0x021b0800 0xa1310003 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c b/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c new file mode 100755 index 0000000..76f3948 --- /dev/null +++ b/board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c @@ -0,0 +1,569 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_I2C_MXC +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#ifdef CONFIG_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6SX_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6SX_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6SX_PAD_GPIO1_IO02__I2C2_SCL | PC, + .gpio_mode = MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6SX_PAD_GPIO1_IO03__I2C2_SDA | PC, + .gpio_mode = MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6SX_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6SX_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6SX_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX6SX_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + + /* AR8031 PHY Reset. For arm2 board, silder the resistance */ + MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec1(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + + /* Reset AR8031 PHY */ + gpio_direction_output(IMX_GPIO_NR(4, 22) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(4, 22), 1); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_QSPI + +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_34ohm) + +#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + /* just config QSPI2A */ + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; + +int board_qspi_init(void) +{ + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); + + /* Set the clock */ + enable_qspi_clk(1); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int mmc_get_env_devno(void) +{ + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + u32 dev_no; + + /* BOOT_CFG2[3] and BOOT_CFG2[4] */ + dev_no = (soc_sbmr & 0x00001800) >> 11; + + return dev_no; +} +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Assume boot SD always present */ +} +int board_mmc_init(bd_t *bis) +{ + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 (SDA) + */ + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +void board_late_mmc_init(void) +{ + char cmd[32]; + u32 dev_no = mmc_get_env_devno(); + + setenv_ulong("mmcdev", dev_no); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} + +#endif + +#ifdef CONFIG_SPLASH_SCREEN +extern int mmc_get_env_devno(void); +int setup_splash_img(void) +{ +#ifdef CONFIG_SPLASH_IS_IN_MMC + int mmc_dev = mmc_get_env_devno(); + ulong offset = CONFIG_SPLASH_IMG_OFFSET; + ulong size = CONFIG_SPLASH_IMG_SIZE; + ulong addr = 0; + char *s = NULL; + struct mmc *mmc = find_mmc_device(mmc_dev); + uint blk_start, blk_cnt, n; + + s = getenv("splashimage"); + + if (NULL == s) { + puts("env splashimage not found!\n"); + return -1; + } + addr = simple_strtoul(s, NULL, 16); + + if (!mmc) { + printf("MMC Device %d not found\n", mmc_dev); + return -1; + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + return -1; + } + + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; + n = mmc->block_dev.block_read(mmc_dev, blk_start, + blk_cnt, (u_char *)addr); + flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); + + return (n == blk_cnt) ? 0 : -1; +#endif + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec1(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + unsigned char value = 1; + +#ifdef CONFIG_FEC_CLOCK_FROM_ANATOP + /* clear gpr1[13], gpr1[17] to select anatop clock */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); +#else + /* Set gpr1[13], and clear gpr1[17] */ + setbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK); + clrbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); +#endif + + ret = enable_fec_clock(0); + if (ret) + return ret; + +#ifdef CONFIG_FEC_CLOCK_FROM_ANATOP + fec_set_rate(0, 125000000); +#endif + +#ifdef CONFIG_FEC_ENABLE_MAX7322 + /* This is needed to drive the pads to 1.8V instead of 1.5V */ + i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS); + + if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) { + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1)) + printf("MAX7322 write failed\n"); + } else { + printf("MAX7322 Not found\n"); + } +#endif + + return 0; +} + +#ifndef CONFIG_FEC_CLOCK_FROM_ANATOP +int mx6_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ +#ifndef CONFIG_FEC_CLOCK_FROM_ANATOP + mx6_rgmii_rework(phydev); +#endif + +#ifdef CONFIG_FEC_ENABLE_MAX7322 + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); +#endif + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_PFUZE100_PMIC_I2C +#define PFUZE100_DEVICEID 0x0 +#define PFUZE100_REVID 0x3 +#define PFUZE100_FABID 0x4 + +#define PFUZE100_SW1ABVOL 0x20 +#define PFUZE100_SW1ABSTBY 0x21 +#define PFUZE100_SW1ABCONF 0x24 +#define PFUZE100_SW1CVOL 0x2e +#define PFUZE100_SW1CSTBY 0x2f +#define PFUZE100_SW1CCONF 0x32 +#define PFUZE100_SW1ABC_SETP(x) ((x-3000)/250) + +static int setup_pmic_voltages(void) +{ + unsigned char value, rev_id = 0; + + i2c_set_bus_num(CONFIG_PMIC_I2C_BUS); + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_PMIC_I2C_SLAVE); + if (!i2c_probe(CONFIG_PMIC_I2C_SLAVE)) { + if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_DEVICEID, 1, &value, 1)) { + printf("Read device ID error!\n"); + return -1; + } + if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_REVID, 1, &rev_id, 1)) { + printf("Read Rev ID error!\n"); + return -1; + } + printf("Found PFUZE100! deviceid 0x%x, revid 0x%x\n", value, rev_id); + + /* set SW1AB staby volatage 0.975V */ + if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) { + printf("Read SW1ABSTBY error!\n"); + return -1; + } + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(9750); + if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) { + printf("Set SW1ABSTBY error!\n"); + return -1; + } + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) { + printf("Read SW1ABCONFIG error!\n"); + return -1; + } + value &= ~0xc0; + value |= 0x40; + if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) { + printf("Set SW1ABCONFIG error!\n"); + return -1; + } + + /* set SW1C staby volatage 0.975V */ + if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) { + printf("Read SW1CSTBY error!\n"); + return -1; + } + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(9750); + if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) { + printf("Set SW1CSTBY error!\n"); + return -1; + } + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) { + printf("Read SW1CCONFIG error!\n"); + return -1; + } + value &= ~0xc0; + value |= 0x40; + if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) { + printf("Set SW1CCONFIG error!\n"); + return -1; + } + } + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned char value; + /* swith to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.15V */ + if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) { + printf("Read SW1AB error!\n"); + return; + } + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(11500); + if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) { + printf("Set SW1AB error!\n"); + return; + } + /* increase VDDSOC to 1.15V */ + if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) { + printf("Read SW1C error!\n"); + return; + } + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(11500); + if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) { + printf("Set SW1C error!\n"); + return; + } + + set_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } + +} +#endif +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_QSPI + board_qspi_init(); +#endif + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_PFUZE100_PMIC_I2C + int ret = 0; + + ret = setup_pmic_voltages(); + if (ret) + return -1; +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6SX 19x19 DDR3 ARM2\n"); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +iomux_v3_cfg_t const usb_otg2_pads[] = { + MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, + ARRAY_SIZE(usb_otg1_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, + ARRAY_SIZE(usb_otg2_pads)); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + return 0; +} +#endif diff --git a/board/freescale/mx6sx_19x19_arm2/plugin.S b/board/freescale/mx6sx_19x19_arm2/plugin.S new file mode 100644 index 0000000..2531019 --- /dev/null +++ b/board/freescale/mx6sx_19x19_arm2/plugin.S @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define ROM_API_TABLE_BASE_ADDR 0x180 +#define ROM_API_HWCNFG_SETUP_OFFSET 0x08 + +/* DDR script */ +.macro imx6sx_19x19_ddr3_arm2_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000030 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + ldr r1, =0x00000030 + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00000030 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000030 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00270025 + str r2, [r0, #0x80c] + ldr r2, =0x001B001E + str r2, [r0, #0x810] + ldr r2, =0x4144013C + str r2, [r0, #0x83c] + ldr r2, =0x01300128 + str r2, [r0, #0x840] + ldr r2, =0x4044464A + str r2, [r0, #0x848] + ldr r2, =0x3A383C34 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x676b52f3 + str r2, [r0, #0x00c] + ldr r2, =0xb66d8b63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x0000005f + str r2, [r0, #0x040] + ldr r2, =0x84190000 + str r2, [r0, #0x000] + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00068031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x00000800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6sx_19x19_ddr3_arm2_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sx_19x19_ddr3_arm2/Makefile b/board/freescale/mx6sx_19x19_ddr3_arm2/Makefile deleted file mode 100644 index 674bd99..0000000 --- a/board/freescale/mx6sx_19x19_ddr3_arm2/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -# (C) Copyright 2014 Freescale Semiconductor, Inc. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx6sx_19x19_ddr3_arm2.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) plugin.bin - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -plugin.bin: plugin.o - $(OBJCOPY) -O binary --gap-fill 0xff $< $@ - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/mx6sx_19x19_ddr3_arm2/imximage.cfg b/board/freescale/mx6sx_19x19_ddr3_arm2/imximage.cfg deleted file mode 100644 index c396084..0000000 --- a/board/freescale/mx6sx_19x19_ddr3_arm2/imximage.cfg +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * Refer docs/README.imxmage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -#define __ASSEMBLY__ -#include - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi/sd/nand/onenand, qspi/nor - */ - -#ifdef CONFIG_SYS_BOOT_QSPI -BOOT_FROM qspi -#else -BOOT_FROM sd -#endif - -#ifdef CONFIG_USE_PLUGIN -/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ -PLUGIN board/freescale/mx6sx_19x19_ddr3_arm2/plugin.bin 0x00907000 -#else - -#ifdef CONFIG_SECURE_BOOT -SECURE_BOOT -#endif - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -DATA 4 0x020c4068 0xffffffff -DATA 4 0x020c406c 0xffffffff -DATA 4 0x020c4070 0xffffffff -DATA 4 0x020c4074 0xffffffff -DATA 4 0x020c4078 0xffffffff -DATA 4 0x020c407c 0xffffffff -DATA 4 0x020c4080 0xffffffff -DATA 4 0x020c4084 0xffffffff - -DATA 4 0x020e0618 0x000c0000 -DATA 4 0x020e05fc 0x00000000 -DATA 4 0x020e032c 0x00000030 - -DATA 4 0x020e0300 0x00000030 -DATA 4 0x020e02fc 0x00000030 -DATA 4 0x020e05f4 0x00000030 -DATA 4 0x020e0340 0x00000030 - -DATA 4 0x020e0320 0x00000000 -DATA 4 0x020e0310 0x00000030 -DATA 4 0x020e0314 0x00000030 -DATA 4 0x020e0614 0x00000030 - -DATA 4 0x020e05f8 0x00020000 -DATA 4 0x020e0330 0x00000030 -DATA 4 0x020e0334 0x00000030 -DATA 4 0x020e0338 0x00000030 -DATA 4 0x020e033c 0x00000030 -DATA 4 0x020e0608 0x00020000 -DATA 4 0x020e060c 0x00000030 -DATA 4 0x020e0610 0x00000030 -DATA 4 0x020e061c 0x00000030 -DATA 4 0x020e0620 0x00000030 -DATA 4 0x020e02ec 0x00000030 -DATA 4 0x020e02f0 0x00000030 -DATA 4 0x020e02f4 0x00000030 -DATA 4 0x020e02f8 0x00000030 -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b080c 0x00270025 -DATA 4 0x021b0810 0x001B001E -DATA 4 0x021b083c 0x4144013C -DATA 4 0x021b0840 0x01300128 -DATA 4 0x021b0848 0x4044464A -DATA 4 0x021b0850 0x3A383C34 -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b0004 0x0002002d -DATA 4 0x021b0008 0x00333030 -DATA 4 0x021b000c 0x676b52f3 -DATA 4 0x021b0010 0xb66d8b63 -DATA 4 0x021b0014 0x01ff00db -DATA 4 0x021b0018 0x00011740 -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b002c 0x000026d2 -DATA 4 0x021b0030 0x006b1023 -DATA 4 0x021b0040 0x0000005f -DATA 4 0x021b0000 0x84190000 -DATA 4 0x021b001c 0x04008032 -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x00068031 -DATA 4 0x021b001c 0x05208030 -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b0020 0x00000800 -DATA 4 0x021b0818 0x00011117 -DATA 4 0x021b001c 0x00000000 - -#endif diff --git a/board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c b/board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c deleted file mode 100755 index 76f3948..0000000 --- a/board/freescale/mx6sx_19x19_ddr3_arm2/mx6sx_19x19_ddr3_arm2.c +++ /dev/null @@ -1,569 +0,0 @@ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_I2C_MXC -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE) - -#ifdef CONFIG_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6SX_PAD_GPIO1_IO00__I2C1_SCL | PC, - .gpio_mode = MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, - .gp = IMX_GPIO_NR(1, 0), - }, - .sda = { - .i2c_mode = MX6SX_PAD_GPIO1_IO01__I2C1_SDA | PC, - .gpio_mode = MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, - .gp = IMX_GPIO_NR(1, 1), - }, -}; - -/* I2C2 */ -struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6SX_PAD_GPIO1_IO02__I2C2_SCL | PC, - .gpio_mode = MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, - .gp = IMX_GPIO_NR(1, 2), - }, - .sda = { - .i2c_mode = MX6SX_PAD_GPIO1_IO03__I2C2_SDA | PC, - .gpio_mode = MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, - .gp = IMX_GPIO_NR(1, 3), - }, -}; -#endif - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_SIZE; - - return 0; -} - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6SX_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6SX_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc1_pads[] = { - MX6SX_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6SX_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -#ifdef CONFIG_FEC_MXC -static iomux_v3_cfg_t const fec1_pads[] = { - MX6SX_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - - /* AR8031 PHY Reset. For arm2 board, silder the resistance */ - MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_iomux_fec1(void) -{ - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - - /* Reset AR8031 PHY */ - gpio_direction_output(IMX_GPIO_NR(4, 22) , 0); - udelay(500); - gpio_set_value(IMX_GPIO_NR(4, 22), 1); -} -#endif - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -#ifdef CONFIG_QSPI - -#define QSPI_PAD_CTRL1 \ - (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_34ohm) - -#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm) - -static iomux_v3_cfg_t const quadspi_pads[] = { - /* just config QSPI2A */ - MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), -}; - -int board_qspi_init(void) -{ - /* Set the iomux */ - imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); - - /* Set the clock */ - enable_qspi_clk(1); - - return 0; -} -#endif - -#ifdef CONFIG_FSL_ESDHC -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC1_BASE_ADDR, 0, 4}, -}; - -int mmc_get_env_devno(void) -{ - u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); - u32 dev_no; - - /* BOOT_CFG2[3] and BOOT_CFG2[4] */ - dev_no = (soc_sbmr & 0x00001800) >> 11; - - return dev_no; -} -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; /* Assume boot SD always present */ -} -int board_mmc_init(bd_t *bis) -{ - /* - * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) - * mmc0 USDHC1 (SDA) - */ - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - -void board_late_mmc_init(void) -{ - char cmd[32]; - u32 dev_no = mmc_get_env_devno(); - - setenv_ulong("mmcdev", dev_no); - - sprintf(cmd, "mmc dev %d", dev_no); - run_command(cmd, 0); -} - -#endif - -#ifdef CONFIG_SPLASH_SCREEN -extern int mmc_get_env_devno(void); -int setup_splash_img(void) -{ -#ifdef CONFIG_SPLASH_IS_IN_MMC - int mmc_dev = mmc_get_env_devno(); - ulong offset = CONFIG_SPLASH_IMG_OFFSET; - ulong size = CONFIG_SPLASH_IMG_SIZE; - ulong addr = 0; - char *s = NULL; - struct mmc *mmc = find_mmc_device(mmc_dev); - uint blk_start, blk_cnt, n; - - s = getenv("splashimage"); - - if (NULL == s) { - puts("env splashimage not found!\n"); - return -1; - } - addr = simple_strtoul(s, NULL, 16); - - if (!mmc) { - printf("MMC Device %d not found\n", mmc_dev); - return -1; - } - - if (mmc_init(mmc)) { - puts("MMC init failed\n"); - return -1; - } - - blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; - blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; - n = mmc->block_dev.block_read(mmc_dev, blk_start, - blk_cnt, (u_char *)addr); - flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); - - return (n == blk_cnt) ? 0 : -1; -#endif - - return 0; -} -#endif - -#ifdef CONFIG_FEC_MXC -int board_eth_init(bd_t *bis) -{ - int ret; - - setup_iomux_fec1(); - - ret = fecmxc_initialize_multi(bis, 0, - CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); - if (ret) - printf("FEC1 MXC: %s:failed\n", __func__); - - return 0; -} - -static int setup_fec(void) -{ - struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs - = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; - int ret; - unsigned char value = 1; - -#ifdef CONFIG_FEC_CLOCK_FROM_ANATOP - /* clear gpr1[13], gpr1[17] to select anatop clock */ - clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); -#else - /* Set gpr1[13], and clear gpr1[17] */ - setbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK); - clrbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); -#endif - - ret = enable_fec_clock(0); - if (ret) - return ret; - -#ifdef CONFIG_FEC_CLOCK_FROM_ANATOP - fec_set_rate(0, 125000000); -#endif - -#ifdef CONFIG_FEC_ENABLE_MAX7322 - /* This is needed to drive the pads to 1.8V instead of 1.5V */ - i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS); - - if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) { - /* Write 0x1 to enable O0 output, this device has no addr */ - /* hence addr length is 0 */ - value = 0x1; - if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1)) - printf("MAX7322 write failed\n"); - } else { - printf("MAX7322 Not found\n"); - } -#endif - - return 0; -} - -#ifndef CONFIG_FEC_CLOCK_FROM_ANATOP -int mx6_rgmii_rework(struct phy_device *phydev) -{ - unsigned short val; - - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - return 0; -} -#endif - -int board_phy_config(struct phy_device *phydev) -{ -#ifndef CONFIG_FEC_CLOCK_FROM_ANATOP - mx6_rgmii_rework(phydev); -#endif - -#ifdef CONFIG_FEC_ENABLE_MAX7322 - /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on - Phy control debug reg 0 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); -#endif - - /* rgmii tx clock delay enable */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} -#endif - -#ifdef CONFIG_PFUZE100_PMIC_I2C -#define PFUZE100_DEVICEID 0x0 -#define PFUZE100_REVID 0x3 -#define PFUZE100_FABID 0x4 - -#define PFUZE100_SW1ABVOL 0x20 -#define PFUZE100_SW1ABSTBY 0x21 -#define PFUZE100_SW1ABCONF 0x24 -#define PFUZE100_SW1CVOL 0x2e -#define PFUZE100_SW1CSTBY 0x2f -#define PFUZE100_SW1CCONF 0x32 -#define PFUZE100_SW1ABC_SETP(x) ((x-3000)/250) - -static int setup_pmic_voltages(void) -{ - unsigned char value, rev_id = 0; - - i2c_set_bus_num(CONFIG_PMIC_I2C_BUS); - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_PMIC_I2C_SLAVE); - if (!i2c_probe(CONFIG_PMIC_I2C_SLAVE)) { - if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_DEVICEID, 1, &value, 1)) { - printf("Read device ID error!\n"); - return -1; - } - if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_REVID, 1, &rev_id, 1)) { - printf("Read Rev ID error!\n"); - return -1; - } - printf("Found PFUZE100! deviceid 0x%x, revid 0x%x\n", value, rev_id); - - /* set SW1AB staby volatage 0.975V */ - if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) { - printf("Read SW1ABSTBY error!\n"); - return -1; - } - value &= ~0x3f; - value |= PFUZE100_SW1ABC_SETP(9750); - if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) { - printf("Set SW1ABSTBY error!\n"); - return -1; - } - - /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) { - printf("Read SW1ABCONFIG error!\n"); - return -1; - } - value &= ~0xc0; - value |= 0x40; - if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) { - printf("Set SW1ABCONFIG error!\n"); - return -1; - } - - /* set SW1C staby volatage 0.975V */ - if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) { - printf("Read SW1CSTBY error!\n"); - return -1; - } - value &= ~0x3f; - value |= PFUZE100_SW1ABC_SETP(9750); - if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) { - printf("Set SW1CSTBY error!\n"); - return -1; - } - - /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ - if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) { - printf("Read SW1CCONFIG error!\n"); - return -1; - } - value &= ~0xc0; - value |= 0x40; - if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) { - printf("Set SW1CCONFIG error!\n"); - return -1; - } - } - - return 0; -} - -#ifdef CONFIG_LDO_BYPASS_CHECK -void ldo_mode_set(int ldo_bypass) -{ - unsigned char value; - /* swith to ldo_bypass mode */ - if (ldo_bypass) { - /* decrease VDDARM to 1.15V */ - if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) { - printf("Read SW1AB error!\n"); - return; - } - value &= ~0x3f; - value |= PFUZE100_SW1ABC_SETP(11500); - if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) { - printf("Set SW1AB error!\n"); - return; - } - /* increase VDDSOC to 1.15V */ - if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) { - printf("Read SW1C error!\n"); - return; - } - value &= ~0x3f; - value |= PFUZE100_SW1ABC_SETP(11500); - if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) { - printf("Set SW1C error!\n"); - return; - } - - set_anatop_bypass(); - printf("switch to ldo_bypass mode!\n"); - } - -} -#endif -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); -#endif - -#ifdef CONFIG_FEC_MXC - setup_fec(); -#endif - -#ifdef CONFIG_QSPI - board_qspi_init(); -#endif - - return 0; -} - -int board_late_init(void) -{ -#ifdef CONFIG_PFUZE100_PMIC_I2C - int ret = 0; - - ret = setup_pmic_voltages(); - if (ret) - return -1; -#endif - -#ifdef CONFIG_ENV_IS_IN_MMC - board_late_mmc_init(); -#endif - - return 0; -} - -u32 get_board_rev(void) -{ - return get_cpu_rev(); -} - -int checkboard(void) -{ - puts("Board: MX6SX 19x19 DDR3 ARM2\n"); - - return 0; -} - -#ifdef CONFIG_USB_EHCI_MX6 -iomux_v3_cfg_t const usb_otg1_pads[] = { - MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL) -}; - -iomux_v3_cfg_t const usb_otg2_pads[] = { - MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -int board_ehci_hcd_init(int port) -{ - switch (port) { - case 0: - imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, - ARRAY_SIZE(usb_otg1_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, - ARRAY_SIZE(usb_otg2_pads)); - break; - default: - printf("MXC USB port %d not yet supported\n", port); - return 1; - } - return 0; -} -#endif diff --git a/board/freescale/mx6sx_19x19_ddr3_arm2/plugin.S b/board/freescale/mx6sx_19x19_ddr3_arm2/plugin.S deleted file mode 100644 index 2531019..0000000 --- a/board/freescale/mx6sx_19x19_ddr3_arm2/plugin.S +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#define ROM_API_TABLE_BASE_ADDR 0x180 -#define ROM_API_HWCNFG_SETUP_OFFSET 0x08 - -/* DDR script */ -.macro imx6sx_19x19_ddr3_arm2_ddr_setting - ldr r0, =IOMUXC_BASE_ADDR - ldr r1, =0x000c0000 - str r1, [r0, #0x618] - ldr r1, =0x00000000 - str r1, [r0, #0x5fc] - ldr r1, =0x00000030 - str r1, [r0, #0x32c] - - ldr r1, =0x00000030 - str r1, [r0, #0x300] - str r1, [r0, #0x2fc] - str r1, [r0, #0x5f4] - str r1, [r0, #0x340] - - ldr r1, =0x00000000 - str r1, [r0, #0x320] - ldr r1, =0x00000030 - str r1, [r0, #0x310] - str r1, [r0, #0x314] - str r1, [r0, #0x614] - - ldr r1, =0x00020000 - str r1, [r0, #0x5f8] - ldr r1, =0x00000030 - str r1, [r0, #0x330] - str r1, [r0, #0x334] - str r1, [r0, #0x338] - str r1, [r0, #0x33c] - ldr r1, =0x00020000 - str r1, [r0, #0x608] - ldr r1, =0x00000030 - str r1, [r0, #0x60c] - str r1, [r0, #0x610] - str r1, [r0, #0x61c] - str r1, [r0, #0x620] - str r1, [r0, #0x2ec] - str r1, [r0, #0x2f0] - str r1, [r0, #0x2f4] - str r1, [r0, #0x2f8] - - ldr r0, =MMDC_P0_BASE_ADDR - ldr r2, =0xa1390003 - str r2, [r0, #0x800] - ldr r2, =0x00270025 - str r2, [r0, #0x80c] - ldr r2, =0x001B001E - str r2, [r0, #0x810] - ldr r2, =0x4144013C - str r2, [r0, #0x83c] - ldr r2, =0x01300128 - str r2, [r0, #0x840] - ldr r2, =0x4044464A - str r2, [r0, #0x848] - ldr r2, =0x3A383C34 - str r2, [r0, #0x850] - - ldr r2, =0x33333333 - str r2, [r0, #0x81c] - str r2, [r0, #0x820] - str r2, [r0, #0x824] - str r2, [r0, #0x828] - - ldr r2, =0x00000800 - str r2, [r0, #0x8b8] - ldr r2, =0x0002002d - str r2, [r0, #0x004] - ldr r2, =0x00333030 - str r2, [r0, #0x008] - ldr r2, =0x676b52f3 - str r2, [r0, #0x00c] - ldr r2, =0xb66d8b63 - str r2, [r0, #0x010] - ldr r2, =0x01ff00db - str r2, [r0, #0x014] - ldr r2, =0x00011740 - str r2, [r0, #0x018] - ldr r2, =0x00008000 - str r2, [r0, #0x01c] - ldr r2, =0x000026d2 - str r2, [r0, #0x02c] - ldr r2, =0x006b1023 - str r2, [r0, #0x030] - ldr r2, =0x0000005f - str r2, [r0, #0x040] - ldr r2, =0x84190000 - str r2, [r0, #0x000] - ldr r2, =0x04008032 - str r2, [r0, #0x01c] - ldr r2, =0x00008033 - str r2, [r0, #0x01c] - ldr r2, =0x00068031 - str r2, [r0, #0x01c] - ldr r2, =0x05208030 - str r2, [r0, #0x01c] - ldr r2, =0x04008040 - str r2, [r0, #0x01c] - ldr r2, =0x00000800 - str r2, [r0, #0x020] - ldr r2, =0x00011117 - str r2, [r0, #0x818] - ldr r2, =0x00000000 - str r2, [r0, #0x01c] - -.endm -.macro imx6_clock_gating - ldr r0, =CCM_BASE_ADDR - ldr r1, =0xffffffff - str r1, [r0, #0x068] - str r1, [r0, #0x06c] - str r1, [r0, #0x070] - str r1, [r0, #0x074] - str r1, [r0, #0x078] - str r1, [r0, #0x07c] - str r1, [r0, #0x080] - str r1, [r0, #0x084] -.endm - -.macro imx6_qos_setting -.endm - -.macro imx6_ddr_setting - imx6sx_19x19_ddr3_arm2_ddr_setting -.endm - -/* include the common plugin code here */ -#include diff --git a/boards.cfg b/boards.cfg index 1d002e4..f322167 100644 --- a/boards.cfg +++ b/boards.cfg @@ -290,8 +290,10 @@ mx6slevk_spinor arm armv7 mx6slevk freescale mx6slevkandroid arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_USE_SPINOR,ANDROID_SUPPORT mx6sx_17x17_arm2 arm armv7 mx6sx_17x17_arm2 freescale mx6 mx6sx_17x17_arm2:IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" mx6sx_17x17_arm2_qspi2 arm armv7 mx6sx_17x17_arm2 freescale mx6 mx6sx_17x17_arm2:IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg,MX6SX,SYS_BOOT_QSPI,DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" -mx6sx_19x19_ddr3_arm2 arm armv7 mx6sx_19x19_ddr3_arm2 freescale mx6 mx6sx_19x19_ddr3_arm2:IMX_CONFIG=board/freescale/mx6sx_19x19_ddr3_arm2/imximage.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" -mx6sx_19x19_ddr3_arm2_qspi2 arm armv7 mx6sx_19x19_ddr3_arm2 freescale mx6 mx6sx_19x19_ddr3_arm2:IMX_CONFIG=board/freescale/mx6sx_19x19_ddr3_arm2/imximage.cfg,MX6SX,SYS_BOOT_QSPI,DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +mx6sx_19x19_ddr3_arm2 arm armv7 mx6sx_19x19_arm2 freescale mx6 mx6sx_19x19_arm2:IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +mx6sx_19x19_ddr3_arm2_qspi2 arm armv7 mx6sx_19x19_arm2 freescale mx6 mx6sx_19x19_arm2:IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg,MX6SX,SYS_BOOT_QSPI,DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +mx6sx_19x19_lpddr2_arm2 arm armv7 mx6sx_19x19_arm2 freescale mx6 mx6sx_19x19_arm2:IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" +mx6sx_19x19_lpddr2_arm2_qspi2 arm armv7 mx6sx_19x19_arm2 freescale mx6 mx6sx_19x19_arm2:IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg,MX6SX,SYS_BOOT_QSPI,DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" mx6sxsabresd arm armv7 mx6sxsabresd freescale mx6 mx6sxsabresd:IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX mx6sxsabresdandroid arm armv7 mx6sxsabresd freescale mx6 mx6sxsabresd:IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX,ANDROID_SUPPORT mx6sxsabresd_qspi2 arm armv7 mx6sxsabresd freescale mx6 mx6sxsabresd:IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX,SYS_BOOT_QSPI diff --git a/include/configs/mx6sx_19x19_arm2.h b/include/configs/mx6sx_19x19_arm2.h new file mode 100644 index 0000000..8506495 --- /dev/null +++ b/include/configs/mx6sx_19x19_arm2.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX 19x19 ARM2 board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ +#ifndef __MX6SX_19X19_DDR3_ARM2_CONFIG_H +#define __MX6SX_19X19_DDR3_ARM2_CONFIG_H + +#include "mx6sx_arm2.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif diff --git a/include/configs/mx6sx_19x19_ddr3_arm2.h b/include/configs/mx6sx_19x19_ddr3_arm2.h deleted file mode 100644 index 8506495..0000000 --- a/include/configs/mx6sx_19x19_ddr3_arm2.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6SX 19x19 ARM2 board. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ -#ifndef __MX6SX_19X19_DDR3_ARM2_CONFIG_H -#define __MX6SX_19X19_DDR3_ARM2_CONFIG_H - -#include "mx6sx_arm2.h" - -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -- cgit v1.1