From 97c9f29008579f56c3fb86785f29f04dd4f47f94 Mon Sep 17 00:00:00 2001 From: Felix Radensky Date: Sat, 23 Jan 2010 01:35:24 +0200 Subject: ppc4xx: Fix sending type 1 PCI transactions The list of 4xx SoCs that should send type 1 PCI transactions is not defined correctly. As a result PCI-PCI bridges and devices behind them are not identified. The following 4xx variants should send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT. Signed-off-by: Felix Radensky Signed-off-by: Stefan Roese --- drivers/pci/pci_indirect.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci_indirect.c b/drivers/pci/pci_indirect.c index ab51f8d..2070d01 100644 --- a/drivers/pci/pci_indirect.c +++ b/drivers/pci/pci_indirect.c @@ -59,7 +59,8 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ return 0; \ } -#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) +#elif defined(CONFIG_440GX) || defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ static int \ indirect_##rw##_config_##size(struct pci_controller *hose, \ -- cgit v1.1 From 9998b1366e7e42089c3f579b4d1d790d3c295387 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 21 Jan 2010 11:37:31 +0100 Subject: ppc4xx: Kilauea: Add CPLD version detection and EBC reconfiguration A newer CPLD version on the 405EX evaluation board requires a different EBC controller setup for the CPLD register access. This patch adds a CPLD version detection for Kilauea and code to reconfigure the EBC controller (chip select 2) for the old CPLD if no new version is found. Additionally the CPLD version is printed upon bootup: Board: Kilauea - AMCC PPC405EX Evaluation Board (CPLD rev. 0) Signed-off-by: Stefan Roese Acked-by: Wolfgang Denk Cc: Zhang Bao Quan --- board/amcc/kilauea/kilauea.c | 40 +++++++++++++++++++++++++++++++++++++++- include/configs/kilauea.h | 26 ++++++++++++++++++++++---- 2 files changed, 61 insertions(+), 5 deletions(-) diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 8ce2445..646f431 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -39,6 +39,37 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +static int board_cpld_version(void) +{ + u32 cpld; + + cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE); + if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) { + /* + * Magic not found -> "old" CPLD revision which needs + * the "old" EBC configuration + */ + mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) | + EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE | + EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) | + EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) | + EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED | + EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); + + /* + * Return 0 for "old" CPLD version + */ + return 0; + } + + /* + * Magic found -> "new" CPLD revision which needs no new + * EBC configuration + */ + return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8; +} + /* * Board early initialization function */ @@ -209,6 +240,13 @@ int board_early_init_f (void) mtsdr(SDR0_PFC1, val); /* + * The CPLD version detection has to be the first access to + * the CPLD, so we need to make this access this early and + * save the CPLD version for later. + */ + gd->board_type = board_cpld_version(); + + /* * Configure FPGA register with PCIe reset */ out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ @@ -280,7 +318,7 @@ int checkboard (void) puts(", serial# "); puts(s); } - putc('\n'); + printf(" (CPLD rev. %ld)\n", gd->board_type); return (0); } diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 8d4ce8d..a79feec 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -47,6 +47,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_TYPES #define CONFIG_BOARD_EMAC_COUNT /*----------------------------------------------------------------------- @@ -520,9 +521,22 @@ #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000) #endif -/* Memory Bank 2 (FPGA) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x9400C800 -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x18000) +/* Memory Bank 2 (FPGA) initialization */ +#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_ENABLED | \ + EBC_BXAP_FWT_ENCODE(6) | \ + EBC_BXAP_BWT_ENCODE(1) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(3) | \ + EBC_BXAP_WBF_ENCODE(1) | \ + EBC_BXAP_TH_ENCODE(4) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x18000) #define CONFIG_SYS_EBC_CFG 0x7FC00000 /* EBC0_CFG */ @@ -571,7 +585,7 @@ * Some Kilauea stuff..., mainly fpga registers */ #define CONFIG_SYS_FPGA_REG_BASE CONFIG_SYS_FPGA_BASE -#define CONFIG_SYS_FPGA_FIFO_BASE (in32(CONFIG_SYS_FPGA_BASE) | (1 << 10)) +#define CONFIG_SYS_FPGA_FIFO_BASE (CONFIG_SYS_FPGA_BASE | (1 << 10)) /* interrupt */ #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT 0x80000000 @@ -602,4 +616,8 @@ #define CONFIG_SYS_FPGA_USER_LED0 0x00000200 #define CONFIG_SYS_FPGA_USER_LED1 0x00000100 +#define CONFIG_SYS_FPGA_MAGIC_MASK 0xffff0000 +#define CONFIG_SYS_FPGA_MAGIC 0xabcd0000 +#define CONFIG_SYS_FPGA_VER_MASK 0x0000ff00 + #endif /* __CONFIG_H */ -- cgit v1.1 From 17ef9104ae11220979e1870f22dcaf535d9baacf Mon Sep 17 00:00:00 2001 From: Seunghyeon Rhee Date: Thu, 3 Dec 2009 09:41:49 +0900 Subject: samsung: fix DMC1_MEM_CFG for s3c64xx The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to control CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is observed that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases. Signed-off-by: Seunghyeon Rhee Signed-off-by: Minkyu Kang --- include/asm-arm/arch-s3c64xx/s3c6400.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/asm-arm/arch-s3c64xx/s3c6400.h b/include/asm-arm/arch-s3c64xx/s3c6400.h index e527c08..10b3324 100644 --- a/include/asm-arm/arch-s3c64xx/s3c6400.h +++ b/include/asm-arm/arch-s3c64xx/s3c6400.h @@ -817,9 +817,9 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ +#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */ #define DMC1_MEM_CFG2 0xB45 -#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ +#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */ #define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ /* Memory Parameters */ -- cgit v1.1 From d8e5f55475e621e793a15d93e2dd2549c5138735 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Fri, 18 Dec 2009 15:03:51 +0900 Subject: s5pc1xx: update cache routines Because of v7_flush_dcache_all is moved to omap3/cache.S and s5pc110 needs cache routines, update s5pc1xx cache routines. l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S and invalidate_dcache is modified for SoC specific. Signed-off-by: Minkyu Kang --- cpu/arm_cortexa8/s5pc1xx/Makefile | 4 +- cpu/arm_cortexa8/s5pc1xx/cache.S | 120 +++++++++++++++++++++++++++++++ cpu/arm_cortexa8/s5pc1xx/cache.c | 43 ----------- include/asm-arm/arch-s5pc1xx/sys_proto.h | 32 +++++++++ include/configs/smdkc100.h | 2 - 5 files changed, 154 insertions(+), 47 deletions(-) create mode 100644 cpu/arm_cortexa8/s5pc1xx/cache.S delete mode 100644 cpu/arm_cortexa8/s5pc1xx/cache.c create mode 100644 include/asm-arm/arch-s5pc1xx/sys_proto.h diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile index e08d9d8..4f922e6 100644 --- a/cpu/arm_cortexa8/s5pc1xx/Makefile +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile @@ -28,9 +28,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -SOBJS = reset.o +SOBJS = cache.o +SOBJS += reset.o -COBJS += cache.o COBJS += clock.o COBJS += cpu_info.o COBJS += timer.o diff --git a/cpu/arm_cortexa8/s5pc1xx/cache.S b/cpu/arm_cortexa8/s5pc1xx/cache.S new file mode 100644 index 0000000..23f527a --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/cache.S @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang + * + * based on cpu/arm_cortexa8/omap3/cache.S + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.align 5 +.global invalidate_dcache +.global l2_cache_enable +.global l2_cache_disable + +/* + * invalidate_dcache() + * Invalidate the whole D-cache. + * + * Corrupted registers: r0-r5, r7, r9-r11 + */ +invalidate_dcache: + stmfd r13!, {r0 - r5, r7, r9 - r12, r14} + + cmp r0, #0xC100 @ check if the cpu is s5pc100 + + beq finished_inval @ s5pc100 doesn't need this + @ routine + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished_inval @ if loc is 0, then no need to + @ clean + mov r10, #0 @ start clean at cache level 0 +inval_loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache + @ level + mov r1, r0, lsr r2 @ extract cache type bits from + @ clidr + and r1, r1, #7 @ mask of the bits for current + @ cache only + cmp r1, #2 @ see what cache we have at + @ this level + blt skip_inval @ skip if no cache, or just + @ i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mov r2, #0 @ operand for mcr SBZ + mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to + @ sych the new cssr&csidr, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the + @ cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the + @ way size + clz r5, r4 @ find bit position of way + @ size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the + @ index size +inval_loop2: + mov r9, r4 @ create working copy of max + @ way size +inval_loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number + @ into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge inval_loop3 + subs r7, r7, #1 @ decrement the index + bge inval_loop2 +skip_inval: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt inval_loop1 +finished_inval: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + + ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} + +l2_cache_enable: + push {r0, r1, r2, lr} + mrc 15, 0, r3, cr1, cr0, 1 + orr r3, r3, #2 + mcr 15, 0, r3, cr1, cr0, 1 + pop {r1, r2, r3, pc} + +l2_cache_disable: + push {r0, r1, r2, lr} + mrc 15, 0, r3, cr1, cr0, 1 + bic r3, r3, #2 + mcr 15, 0, r3, cr1, cr0, 1 + pop {r1, r2, r3, pc} diff --git a/cpu/arm_cortexa8/s5pc1xx/cache.c b/cpu/arm_cortexa8/s5pc1xx/cache.c deleted file mode 100644 index 8652a45..0000000 --- a/cpu/arm_cortexa8/s5pc1xx/cache.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electronics - * Minkyu Kang - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -void l2_cache_enable(void) -{ - unsigned long i; - - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); -} - -void l2_cache_disable(void) -{ - unsigned long i; - - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); -} diff --git a/include/asm-arm/arch-s5pc1xx/sys_proto.h b/include/asm-arm/arch-s5pc1xx/sys_proto.h new file mode 100644 index 0000000..3078aaf --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/sys_proto.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2009 Samsung Electrnoics + * Minkyu Kang + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +u32 get_device_type(void); +void invalidate_dcache(u32); +void l2_cache_disable(void); +void l2_cache_enable(void); + +#endif diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index bf0ee67..a8ba052 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -47,8 +47,6 @@ #undef CONFIG_SKIP_RELOCATE_UBOOT -#define CONFIG_L2_OFF - /* input clock of PLL: SMDKC100 has 12MHz input clock */ #define CONFIG_SYS_CLK_FREQ 12000000 -- cgit v1.1 From beca04dd2446fc9ec46ca17163dadb7f82420e7c Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Thu, 24 Dec 2009 02:55:23 +0530 Subject: Kirkwood: Upgated licencing for files imported from linux source to GPLv2 or later These are few files directly imported from Linux kernel source. Those are not modifyed at all ar per strategy. These files contains source with GPLv2 only whereas u-boot expects GPLv2 or latter These files are updated for the same from prior permission from original writes Acked-by: Nicolas Pitre Signed-off-by: Prafulla Wadaskar --- drivers/gpio/kw_gpio.c | 20 +++++++++++++++++--- drivers/i2c/kirkwood_i2c.c | 23 ++++++++++++++++++----- include/asm-arm/arch-kirkwood/gpio.h | 20 +++++++++++++++++--- include/asm-arm/arch-kirkwood/mpp.h | 20 +++++++++++++++++--- 4 files changed, 69 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/kw_gpio.c b/drivers/gpio/kw_gpio.c index 1c28834..56383c2 100644 --- a/drivers/gpio/kw_gpio.c +++ b/drivers/gpio/kw_gpio.c @@ -3,9 +3,23 @@ * * Marvell Orion SoC GPIO handling. * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* diff --git a/drivers/i2c/kirkwood_i2c.c b/drivers/i2c/kirkwood_i2c.c index 37b7d99..a4409be 100644 --- a/drivers/i2c/kirkwood_i2c.c +++ b/drivers/i2c/kirkwood_i2c.c @@ -5,16 +5,29 @@ * * Based on: * Author: Mark A. Greer + * 2005 (c) MontaVista, Software, Inc. * - * 2005 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA * * ported from Linux to u-boot * (C) Copyright 2009 * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * */ #include #include diff --git a/include/asm-arm/arch-kirkwood/gpio.h b/include/asm-arm/arch-kirkwood/gpio.h index b5bacde..cd1bc00 100644 --- a/include/asm-arm/arch-kirkwood/gpio.h +++ b/include/asm-arm/arch-kirkwood/gpio.h @@ -1,9 +1,23 @@ /* * arch/asm-arm/mach-kirkwood/include/mach/gpio.h * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* diff --git a/include/asm-arm/arch-kirkwood/mpp.h b/include/asm-arm/arch-kirkwood/mpp.h index bc74278..b3c090e 100644 --- a/include/asm-arm/arch-kirkwood/mpp.h +++ b/include/asm-arm/arch-kirkwood/mpp.h @@ -3,9 +3,23 @@ * * Copyright 2009: Marvell Technology Group Ltd. * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __KIRKWOOD_MPP_H -- cgit v1.1 From bfb6d510e9acbec97e4e1cc855ec1269538689f8 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 16 Nov 2009 18:29:25 +0530 Subject: Kirkwood: Makefile cleanup- fixed ordering (cosmetic change) As per coding guidlines, it is good to maintain proper ordering in the makefiles. This was missed during initial coding, corrected here. This was discovered during orion5x code review Thanks to Albert Aribaud for this. Signed-off-by: Prafulla Wadaskar --- cpu/arm926ejs/kirkwood/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/arm926ejs/kirkwood/Makefile b/cpu/arm926ejs/kirkwood/Makefile index d73e2104..fc2cc03 100644 --- a/cpu/arm926ejs/kirkwood/Makefile +++ b/cpu/arm926ejs/kirkwood/Makefile @@ -26,8 +26,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS-y = dram.o -COBJS-y += cpu.o +COBJS-y = cpu.o +COBJS-y += dram.o COBJS-y += mpp.o COBJS-y += timer.o -- cgit v1.1 From e4c43c20b87d5c9a7ac3b5250ca009311c62945c Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Wed, 20 Jan 2010 18:00:28 -0600 Subject: ARM Update mach-types Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 2045124ffd1a5e46d157349016a2c50f19c8c91d Signed-off-by: Tom Rix --- include/asm-arm/mach-types.h | 351 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 351 insertions(+) diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 2898618..3b46327 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -2594,6 +2594,33 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_ELTD100 2611 #define MACH_TYPE_CAPC7117 2612 #define MACH_TYPE_SWAN 2613 +#define MACH_TYPE_VEU 2614 +#define MACH_TYPE_RM2 2615 +#define MACH_TYPE_TT2100 2616 +#define MACH_TYPE_VENICE 2617 +#define MACH_TYPE_PC7323 2618 +#define MACH_TYPE_MASP 2619 +#define MACH_TYPE_FUJITSU_TVSTBSOC 2620 +#define MACH_TYPE_FUJITSU_TVSTBSOC1 2621 +#define MACH_TYPE_LEXIKON 2622 +#define MACH_TYPE_MINI2440V2 2623 +#define MACH_TYPE_ICONTROL 2624 +#define MACH_TYPE_SHEEVAD 2625 +#define MACH_TYPE_QSD8X50A_ST1_1 2626 +#define MACH_TYPE_QSD8X50A_ST1_5 2627 +#define MACH_TYPE_BEE 2628 +#define MACH_TYPE_MX23EVK 2629 +#define MACH_TYPE_AP4EVB 2630 +#define MACH_TYPE_STOCKHOLM 2631 +#define MACH_TYPE_LPC_H3131 2632 +#define MACH_TYPE_STINGRAY 2633 +#define MACH_TYPE_KRAKEN 2634 +#define MACH_TYPE_GW2388 2635 +#define MACH_TYPE_JADECPU 2636 +#define MACH_TYPE_CARLISLE 2637 +#define MACH_TYPE_LUX_SFT9 2638 +#define MACH_TYPE_NEMID_TB 2639 +#define MACH_TYPE_TERRIER 2640 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -33579,6 +33606,330 @@ extern unsigned int __machine_arch_type; # define machine_is_swan() (0) #endif +#ifdef CONFIG_MACH_VEU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VEU +# endif +# define machine_is_veu() (machine_arch_type == MACH_TYPE_VEU) +#else +# define machine_is_veu() (0) +#endif + +#ifdef CONFIG_MACH_RM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RM2 +# endif +# define machine_is_rm2() (machine_arch_type == MACH_TYPE_RM2) +#else +# define machine_is_rm2() (0) +#endif + +#ifdef CONFIG_MACH_TT2100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TT2100 +# endif +# define machine_is_tt2100() (machine_arch_type == MACH_TYPE_TT2100) +#else +# define machine_is_tt2100() (0) +#endif + +#ifdef CONFIG_MACH_VENICE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VENICE +# endif +# define machine_is_venice() (machine_arch_type == MACH_TYPE_VENICE) +#else +# define machine_is_venice() (0) +#endif + +#ifdef CONFIG_MACH_PC7323 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC7323 +# endif +# define machine_is_pc7323() (machine_arch_type == MACH_TYPE_PC7323) +#else +# define machine_is_pc7323() (0) +#endif + +#ifdef CONFIG_MACH_MASP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MASP +# endif +# define machine_is_masp() (machine_arch_type == MACH_TYPE_MASP) +#else +# define machine_is_masp() (0) +#endif + +#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJITSU_TVSTBSOC +# endif +# define machine_is_fujitsu_tvstbsoc0() (machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC) +#else +# define machine_is_fujitsu_tvstbsoc0() (0) +#endif + +#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJITSU_TVSTBSOC1 +# endif +# define machine_is_fujitsu_tvstbsoc1() (machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC1) +#else +# define machine_is_fujitsu_tvstbsoc1() (0) +#endif + +#ifdef CONFIG_MACH_LEXIKON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEXIKON +# endif +# define machine_is_lexikon() (machine_arch_type == MACH_TYPE_LEXIKON) +#else +# define machine_is_lexikon() (0) +#endif + +#ifdef CONFIG_MACH_MINI2440V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINI2440V2 +# endif +# define machine_is_mini2440v2() (machine_arch_type == MACH_TYPE_MINI2440V2) +#else +# define machine_is_mini2440v2() (0) +#endif + +#ifdef CONFIG_MACH_ICONTROL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICONTROL +# endif +# define machine_is_icontrol() (machine_arch_type == MACH_TYPE_ICONTROL) +#else +# define machine_is_icontrol() (0) +#endif + +#ifdef CONFIG_MACH_SHEEVAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHEEVAD +# endif +# define machine_is_sheevad() (machine_arch_type == MACH_TYPE_SHEEVAD) +#else +# define machine_is_sheevad() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_ST1_1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_1 +# endif +# define machine_is_qsd8x50a_st1_1() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_1) +#else +# define machine_is_qsd8x50a_st1_1() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_ST1_5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_5 +# endif +# define machine_is_qsd8x50a_st1_5() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_5) +#else +# define machine_is_qsd8x50a_st1_5() (0) +#endif + +#ifdef CONFIG_MACH_BEE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BEE +# endif +# define machine_is_bee() (machine_arch_type == MACH_TYPE_BEE) +#else +# define machine_is_bee() (0) +#endif + +#ifdef CONFIG_MACH_MX23EVK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX23EVK +# endif +# define machine_is_mx23evk() (machine_arch_type == MACH_TYPE_MX23EVK) +#else +# define machine_is_mx23evk() (0) +#endif + +#ifdef CONFIG_MACH_AP4EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AP4EVB +# endif +# define machine_is_ap4evb() (machine_arch_type == MACH_TYPE_AP4EVB) +#else +# define machine_is_ap4evb() (0) +#endif + +#ifdef CONFIG_MACH_STOCKHOLM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STOCKHOLM +# endif +# define machine_is_stockholm() (machine_arch_type == MACH_TYPE_STOCKHOLM) +#else +# define machine_is_stockholm() (0) +#endif + +#ifdef CONFIG_MACH_LPC_H3131 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC_H3131 +# endif +# define machine_is_lpc_h3131() (machine_arch_type == MACH_TYPE_LPC_H3131) +#else +# define machine_is_lpc_h3131() (0) +#endif + +#ifdef CONFIG_MACH_STINGRAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STINGRAY +# endif +# define machine_is_stingray() (machine_arch_type == MACH_TYPE_STINGRAY) +#else +# define machine_is_stingray() (0) +#endif + +#ifdef CONFIG_MACH_KRAKEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KRAKEN +# endif +# define machine_is_kraken() (machine_arch_type == MACH_TYPE_KRAKEN) +#else +# define machine_is_kraken() (0) +#endif + +#ifdef CONFIG_MACH_GW2388 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GW2388 +# endif +# define machine_is_gw2388() (machine_arch_type == MACH_TYPE_GW2388) +#else +# define machine_is_gw2388() (0) +#endif + +#ifdef CONFIG_MACH_JADECPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JADECPU +# endif +# define machine_is_jadecpu() (machine_arch_type == MACH_TYPE_JADECPU) +#else +# define machine_is_jadecpu() (0) +#endif + +#ifdef CONFIG_MACH_CARLISLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARLISLE +# endif +# define machine_is_carlisle() (machine_arch_type == MACH_TYPE_CARLISLE) +#else +# define machine_is_carlisle() (0) +#endif + +#ifdef CONFIG_MACH_LUX_SFT9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_SFT9 +# endif +# define machine_is_lux_sft9() (machine_arch_type == MACH_TYPE_LUX_SFT9) +#else +# define machine_is_lux_sft9() (0) +#endif + +#ifdef CONFIG_MACH_NEMID_TB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEMID_TB +# endif +# define machine_is_nemid_tb() (machine_arch_type == MACH_TYPE_NEMID_TB) +#else +# define machine_is_nemid_tb() (0) +#endif + +#ifdef CONFIG_MACH_TERRIER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TERRIER +# endif +# define machine_is_terrier() (machine_arch_type == MACH_TYPE_TERRIER) +#else +# define machine_is_terrier() (0) +#endif + /* * These have not yet been registered */ -- cgit v1.1 From 6fffcdf8c869a3d8436be8eff6428d8121aa76e6 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Fri, 15 Jan 2010 19:15:42 +0530 Subject: SPEAr : Adding README.spear in doc README.spear contains information about SPEAr architecture and build options etc Signed-off-by: Vipin --- doc/README.spear | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 doc/README.spear diff --git a/doc/README.spear b/doc/README.spear new file mode 100644 index 0000000..a8b1052 --- /dev/null +++ b/doc/README.spear @@ -0,0 +1,48 @@ + +SPEAr (Structured Processor Enhanced Architecture). + +SPEAr600 is also known as SPEArPlus and SPEAr300 is also known as SPEArBasic + +The SPEAr SoC family embeds a customizable logic that can be programmed +one-time by a customer at silicon mask level (i.e. not at runtime!). + +We are now adding the support in u-boot for two SoC: SPEAr600 and SPEAr3xx. + +All 4 SoCs share common peripherals. + +1. ARM926ejs core based (sp600 has two cores, the 2nd handled only in Linux) +2. FastEthernet (sp600 has Gbit version, but same controller - GMAC) +3. USB Host +4. USB Device +5. NAND controller (FSMC) +6. Serial NOR ctrl +7. I2C +8. SPI +9. CLCD +10. others .. + +Everything is supported in Linux. +u-boot is not currently supporting all peripeharls (just a few as listed below). +1. USB Device +2. NAND controller (FSMC) +3. Serial Memory Interface +4. EMI (Parallel NOR interface) +4. I2C +5. UART + +Build options + make spear600_config + make spear300_config + make spear310_config + make spear320_config + +Further options + make ENV=NAND (supported by all 4 SoCs) + - This option generates a uboot image that saves environment inn NAND + + make CONSOLE=USB (supported by all 4 SoCs) + - This option generates a uboot image for using usbdevice as a tty i/f + + make FLASH=PNOR (supported by SPEAr310 and SPEAr320) + - This option generates a uboot image that supports emi controller for + CFI compliant parallel NOR flash -- cgit v1.1 From 81c0ebf623ddbb6a4da8e051441c83e99a01b00b Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Fri, 15 Jan 2010 19:15:43 +0530 Subject: SPEAr : Adding basic SPEAr architecture support. SPEAr Architecture support added. It contains the support for following SPEAr blocks - Timer - System controller - Misc registers Signed-off-by: Vipin --- cpu/arm926ejs/spear/Makefile | 52 +++++++++++ cpu/arm926ejs/spear/reset.c | 54 +++++++++++ cpu/arm926ejs/spear/timer.c | 153 +++++++++++++++++++++++++++++++ include/asm-arm/arch-spear/hardware.h | 66 +++++++++++++ include/asm-arm/arch-spear/spr_gpt.h | 85 +++++++++++++++++ include/asm-arm/arch-spear/spr_misc.h | 130 ++++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_syscntl.h | 38 ++++++++ 7 files changed, 578 insertions(+) create mode 100755 cpu/arm926ejs/spear/Makefile create mode 100755 cpu/arm926ejs/spear/reset.c create mode 100755 cpu/arm926ejs/spear/timer.c create mode 100644 include/asm-arm/arch-spear/hardware.h create mode 100755 include/asm-arm/arch-spear/spr_gpt.h create mode 100644 include/asm-arm/arch-spear/spr_misc.h create mode 100644 include/asm-arm/arch-spear/spr_syscntl.h diff --git a/cpu/arm926ejs/spear/Makefile b/cpu/arm926ejs/spear/Makefile new file mode 100755 index 0000000..bf8dfa8 --- /dev/null +++ b/cpu/arm926ejs/spear/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS := reset.o \ + timer.o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/spear/reset.c b/cpu/arm926ejs/spear/reset.c new file mode 100755 index 0000000..73ad86d --- /dev/null +++ b/cpu/arm926ejs/spear/reset.c @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +void reset_cpu(ulong ignored) +{ + struct syscntl_regs *syscntl_regs_p = + (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE; + + printf("System is going to reboot ...\n"); + + /* + * This 1 second delay will allow the above message + * to be printed before reset + */ + udelay((1000 * 1000)); + + /* Going into slow mode before resetting SOC */ + writel(0x02, &syscntl_regs_p->scctrl); + + /* + * Writing any value to the system status register will + * reset the SoC + */ + writel(0x00, &syscntl_regs_p->scsysstat); + + /* system will restart */ + while (1) + ; +} diff --git a/cpu/arm926ejs/spear/timer.c b/cpu/arm926ejs/spear/timer.c new file mode 100755 index 0000000..06858b4 --- /dev/null +++ b/cpu/arm926ejs/spear/timer.c @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define GPT_RESOLUTION (CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ) +#define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING) + +static struct gpt_regs *const gpt_regs_p = + (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE; + +static struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + +static ulong timestamp; +static ulong lastdec; + +int timer_init(void) +{ + u32 synth; + + /* Prescaler setting */ +#if defined(CONFIG_SPEAR3XX) + writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg); + synth = MISC_GPT4SYNTH; +#elif defined(CONFIG_SPEAR600) + writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg); + synth = MISC_GPT3SYNTH; +#else +# error Incorrect config. Can only be spear{600|300|310|320} +#endif + + writel(readl(&misc_regs_p->periph_clk_cfg) | synth, + &misc_regs_p->periph_clk_cfg); + + /* disable timers */ + writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control); + + /* load value for free running */ + writel(GPT_FREE_RUNNING, &gpt_regs_p->compare); + + /* auto reload, start timer */ + writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control); + + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return (get_timer_masked() / GPT_RESOLUTION) - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void __udelay(unsigned long usec) +{ + ulong tmo; + ulong start = get_timer_masked(); + ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100); + ulong rndoff; + + rndoff = (usec % 10) ? 1 : 0; + + /* tenudelcnt timer tick gives 10 microsecconds delay */ + tmo = ((usec / 10) + rndoff) * tenudelcnt; + + while ((ulong) (get_timer_masked() - start) < tmo) + ; +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER(); + + if (now >= lastdec) { + /* normal mode */ + timestamp += now - lastdec; + } else { + /* we have an overflow ... */ + timestamp += now + GPT_FREE_RUNNING - lastdec; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked(unsigned long usec) +{ + return udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SPEAR_HZ; +} diff --git a/include/asm-arm/arch-spear/hardware.h b/include/asm-arm/arch-spear/hardware.h new file mode 100644 index 0000000..818f36c --- /dev/null +++ b/include/asm-arm/arch-spear/hardware.h @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#define CONFIG_SYS_USBD_BASE (0xE1100000) +#define CONFIG_SYS_PLUG_BASE (0xE1200000) +#define CONFIG_SYS_FIFO_BASE (0xE1000800) +#define CONFIG_SYS_SMI_BASE (0xFC000000) +#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) +#define CONFIG_SPEAR_TIMERBASE (0xFC800000) +#define CONFIG_SPEAR_MISCBASE (0xFCA80000) + +#define CONFIG_SYS_NAND_CLE (1 << 16) +#define CONFIG_SYS_NAND_ALE (1 << 17) + +#if defined(CONFIG_SPEAR600) +#define CONFIG_SYS_I2C_BASE (0xD0200000) +#define CONFIG_SPEAR_FSMCBASE (0xD1800000) + +#elif defined(CONFIG_SPEAR300) +#define CONFIG_SYS_I2C_BASE (0xD0180000) +#define CONFIG_SPEAR_FSMCBASE (0x94000000) + +#elif defined(CONFIG_SPEAR310) +#define CONFIG_SYS_I2C_BASE (0xD0180000) +#define CONFIG_SPEAR_FSMCBASE (0x44000000) + +#undef CONFIG_SYS_NAND_CLE +#undef CONFIG_SYS_NAND_ALE +#define CONFIG_SYS_NAND_CLE (1 << 17) +#define CONFIG_SYS_NAND_ALE (1 << 16) + +#define CONFIG_SPEAR_EMIBASE (0x4F000000) +#define CONFIG_SPEAR_RASBASE (0xB4000000) + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_I2C_BASE (0xD0180000) +#define CONFIG_SPEAR_FSMCBASE (0x4C000000) + +#define CONFIG_SPEAR_EMIBASE (0x40000000) +#define CONFIG_SPEAR_RASBASE (0xB3000000) + +#endif +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-spear/spr_gpt.h b/include/asm-arm/arch-spear/spr_gpt.h new file mode 100755 index 0000000..965b5ab --- /dev/null +++ b/include/asm-arm/arch-spear/spr_gpt.h @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_GPT_H +#define _SPR_GPT_H + +struct gpt_regs { + u8 reserved[0x80]; + u32 control; + u32 status; + u32 compare; + u32 count; + u32 capture_re; + u32 capture_fe; +}; + +/* + * TIMER_CONTROL register settings + */ + +#define GPT_PRESCALER_MASK 0x000F +#define GPT_PRESCALER_1 0x0000 +#define GPT_PRESCALER_2 0x0001 +#define GPT_PRESCALER_4 0x0002 +#define GPT_PRESCALER_8 0x0003 +#define GPT_PRESCALER_16 0x0004 +#define GPT_PRESCALER_32 0x0005 +#define GPT_PRESCALER_64 0x0006 +#define GPT_PRESCALER_128 0x0007 +#define GPT_PRESCALER_256 0x0008 + +#define GPT_MODE_SINGLE_SHOT 0x0010 +#define GPT_MODE_AUTO_RELOAD 0x0000 + +#define GPT_ENABLE 0x0020 + +#define GPT_CAPT_MODE_MASK 0x00C0 +#define GPT_CAPT_MODE_NONE 0x0000 +#define GPT_CAPT_MODE_RE 0x0040 +#define GPT_CAPT_MODE_FE 0x0080 +#define GPT_CAPT_MODE_BOTH 0x00C0 + +#define GPT_INT_MATCH 0x0100 +#define GPT_INT_FE 0x0200 +#define GPT_INT_RE 0x0400 + +/* + * TIMER_STATUS register settings + */ + +#define GPT_STS_MATCH 0x0001 +#define GPT_STS_FE 0x0002 +#define GPT_STS_RE 0x0004 + +/* + * TIMER_COMPARE register settings + */ + +#define GPT_FREE_RUNNING 0xFFFF + +/* Timer, HZ specific defines */ +#define CONFIG_SPEAR_HZ (1000) +#define CONFIG_SPEAR_HZ_CLOCK (8300000) + +#endif diff --git a/include/asm-arm/arch-spear/spr_misc.h b/include/asm-arm/arch-spear/spr_misc.h new file mode 100644 index 0000000..8b96d9b --- /dev/null +++ b/include/asm-arm/arch-spear/spr_misc.h @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_MISC_H +#define _SPR_MISC_H + +struct misc_regs { + u32 auto_cfg_reg; /* 0x0 */ + u32 armdbg_ctr_reg; /* 0x4 */ + u32 pll1_cntl; /* 0x8 */ + u32 pll1_frq; /* 0xc */ + u32 pll1_mod; /* 0x10 */ + u32 pll2_cntl; /* 0x14 */ + u32 pll2_frq; /* 0x18 */ + u32 pll2_mod; /* 0x1C */ + u32 pll_ctr_reg; /* 0x20 */ + u32 amba_clk_cfg; /* 0x24 */ + u32 periph_clk_cfg; /* 0x28 */ + u32 periph1_clken; /* 0x2C */ + u32 periph2_clken; /* 0x30 */ + u32 ras_clken; /* 0x34 */ + u32 periph1_rst; /* 0x38 */ + u32 periph2_rst; /* 0x3C */ + u32 ras_rst; /* 0x40 */ + u32 prsc1_clk_cfg; /* 0x44 */ + u32 prsc2_clk_cfg; /* 0x48 */ + u32 prsc3_clk_cfg; /* 0x4C */ + u32 amem_cfg_ctrl; /* 0x50 */ + u32 port_cfg_ctrl; /* 0x54 */ + u32 reserved_1; /* 0x58 */ + u32 clcd_synth_clk; /* 0x5C */ + u32 irda_synth_clk; /* 0x60 */ + u32 uart_synth_clk; /* 0x64 */ + u32 gmac_synth_clk; /* 0x68 */ + u32 ras_synth1_clk; /* 0x6C */ + u32 ras_synth2_clk; /* 0x70 */ + u32 ras_synth3_clk; /* 0x74 */ + u32 ras_synth4_clk; /* 0x78 */ + u32 arb_icm_ml1; /* 0x7C */ + u32 arb_icm_ml2; /* 0x80 */ + u32 arb_icm_ml3; /* 0x84 */ + u32 arb_icm_ml4; /* 0x88 */ + u32 arb_icm_ml5; /* 0x8C */ + u32 arb_icm_ml6; /* 0x90 */ + u32 arb_icm_ml7; /* 0x94 */ + u32 arb_icm_ml8; /* 0x98 */ + u32 arb_icm_ml9; /* 0x9C */ + u32 dma_src_sel; /* 0xA0 */ + u32 uphy_ctr_reg; /* 0xA4 */ + u32 gmac_ctr_reg; /* 0xA8 */ + u32 port_bridge_ctrl; /* 0xAC */ + u32 reserved_2[4]; /* 0xB0--0xBC */ + u32 prc1_ilck_ctrl_reg; /* 0xC0 */ + u32 prc2_ilck_ctrl_reg; /* 0xC4 */ + u32 prc3_ilck_ctrl_reg; /* 0xC8 */ + u32 prc4_ilck_ctrl_reg; /* 0xCC */ + u32 prc1_intr_ctrl_reg; /* 0xD0 */ + u32 prc2_intr_ctrl_reg; /* 0xD4 */ + u32 prc3_intr_ctrl_reg; /* 0xD8 */ + u32 prc4_intr_ctrl_reg; /* 0xDC */ + u32 powerdown_cfg_reg; /* 0xE0 */ + u32 ddr_1v8_compensation; /* 0xE4 */ + u32 ddr_2v5_compensation; /* 0xE8 */ + u32 core_3v3_compensation; /* 0xEC */ + u32 ddr_pad; /* 0xF0 */ + u32 bist1_ctr_reg; /* 0xF4 */ + u32 bist2_ctr_reg; /* 0xF8 */ + u32 bist3_ctr_reg; /* 0xFC */ + u32 bist4_ctr_reg; /* 0x100 */ + u32 bist5_ctr_reg; /* 0x104 */ + u32 bist1_rslt_reg; /* 0x108 */ + u32 bist2_rslt_reg; /* 0x10C */ + u32 bist3_rslt_reg; /* 0x110 */ + u32 bist4_rslt_reg; /* 0x114 */ + u32 bist5_rslt_reg; /* 0x118 */ + u32 syst_error_reg; /* 0x11C */ + u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */ + u32 ras_gpp1_in; /* 0x8000 */ + u32 ras_gpp2_in; /* 0x8004 */ + u32 ras_gpp1_out; /* 0x8008 */ + u32 ras_gpp2_out; /* 0x800C */ +}; + +/* AUTO_CFG_REG value */ +#define MISC_SOCCFGMSK 0x0000003F +#define MISC_SOCCFG30 0x0000000C +#define MISC_SOCCFG31 0x0000000D +#define MISC_NANDDIS 0x00020000 + +/* PERIPH_CLK_CFG value */ +#define MISC_GPT3SYNTH 0x00000400 +#define MISC_GPT4SYNTH 0x00000800 + +/* PRSC_CLK_CFG value */ +/* + * Fout = Fin / (2^(N+1) * (M + 1)) + */ +#define MISC_PRSC_N_1 0x00001000 +#define MISC_PRSC_M_9 0x00000009 +#define MISC_PRSC_N_4 0x00004000 +#define MISC_PRSC_M_399 0x0000018F +#define MISC_PRSC_N_6 0x00006000 +#define MISC_PRSC_M_2593 0x00000A21 +#define MISC_PRSC_M_124 0x0000007C +#define MISC_PRSC_CFG (MISC_PRSC_N_1 | MISC_PRSC_M_9) + +/* PERIPH1_CLKEN, PERIPH1_RST value */ +#define MISC_USBDENB 0x01000000 + +#endif diff --git a/include/asm-arm/arch-spear/spr_syscntl.h b/include/asm-arm/arch-spear/spr_syscntl.h new file mode 100644 index 0000000..3c92f09 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_syscntl.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2009 + * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +struct syscntl_regs { + u32 scctrl; + u32 scsysstat; + u32 scimctrl; + u32 scimsysstat; + u32 scxtalctrl; + u32 scpllctrl; + u32 scpllfctrl; + u32 scperctrl0; + u32 scperctrl1; + u32 scperen; + u32 scperdis; + const u32 scperclken; + const u32 scperstat; +}; -- cgit v1.1 From 2403f8f417b1b94701bb5949903d701f1f414a42 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Fri, 15 Jan 2010 19:15:44 +0530 Subject: SPEAr : i2c driver support added for SPEAr SoCs SPEAr SoCs contain a synopsys i2c controller. This patch adds the driver for this IP. Signed-off-by: Vipin --- drivers/i2c/Makefile | 1 + drivers/i2c/spr_i2c.c | 331 +++++++++++++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_i2c.h | 146 +++++++++++++++ 3 files changed, 478 insertions(+) mode change 100644 => 100755 drivers/i2c/Makefile create mode 100755 drivers/i2c/spr_i2c.c create mode 100755 include/asm-arm/arch-spear/spr_i2c.h diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile old mode 100644 new mode 100755 index b860e89..29bda85 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o +COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o COBJS := $(COBJS-y) diff --git a/drivers/i2c/spr_i2c.c b/drivers/i2c/spr_i2c.c new file mode 100755 index 0000000..eabfe84 --- /dev/null +++ b/drivers/i2c/spr_i2c.c @@ -0,0 +1,331 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +static struct i2c_regs *const i2c_regs_p = + (struct i2c_regs *)CONFIG_SYS_I2C_BASE; + +/* + * set_speed - Set the i2c speed mode (standard, high, fast) + * @i2c_spd: required i2c speed mode + * + * Set the i2c speed mode (standard, high, fast) + */ +static void set_speed(int i2c_spd) +{ + unsigned int cntl; + unsigned int hcnt, lcnt; + unsigned int high, low; + + cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK)); + + switch (i2c_spd) { + case IC_SPEED_MODE_MAX: + cntl |= IC_CON_SPD_HS; + high = MIN_HS_SCL_HIGHTIME; + low = MIN_HS_SCL_LOWTIME; + break; + + case IC_SPEED_MODE_STANDARD: + cntl |= IC_CON_SPD_SS; + high = MIN_SS_SCL_HIGHTIME; + low = MIN_SS_SCL_LOWTIME; + break; + + case IC_SPEED_MODE_FAST: + default: + cntl |= IC_CON_SPD_FS; + high = MIN_FS_SCL_HIGHTIME; + low = MIN_FS_SCL_LOWTIME; + break; + } + + writel(cntl, &i2c_regs_p->ic_con); + + hcnt = (IC_CLK * high) / NANO_TO_MICRO; + writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt); + + lcnt = (IC_CLK * low) / NANO_TO_MICRO; + writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt); +} + +/* + * i2c_set_bus_speed - Set the i2c speed + * @speed: required i2c speed + * + * Set the i2c speed. + */ +void i2c_set_bus_speed(int speed) +{ + if (speed >= I2C_MAX_SPEED) + set_speed(IC_SPEED_MODE_MAX); + else if (speed >= I2C_FAST_SPEED) + set_speed(IC_SPEED_MODE_FAST); + else + set_speed(IC_SPEED_MODE_STANDARD); +} + +/* + * i2c_get_bus_speed - Gets the i2c speed + * + * Gets the i2c speed. + */ +int i2c_get_bus_speed(void) +{ + u32 cntl; + + cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK); + + if (cntl == IC_CON_SPD_HS) + return I2C_MAX_SPEED; + else if (cntl == IC_CON_SPD_FS) + return I2C_FAST_SPEED; + else if (cntl == IC_CON_SPD_SS) + return I2C_STANDARD_SPEED; + + return 0; +} + +/* + * i2c_init - Init function + * @speed: required i2c speed + * @slaveadd: slave address for the spear device + * + * Initialization function. + */ +void i2c_init(int speed, int slaveadd) +{ + unsigned int enbl; + + /* Disable i2c */ + enbl = readl(&i2c_regs_p->ic_enable); + enbl &= ~IC_ENABLE_0B; + writel(enbl, &i2c_regs_p->ic_enable); + + writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con); + writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl); + writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl); + i2c_set_bus_speed(speed); + writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask); + writel(slaveadd, &i2c_regs_p->ic_sar); + + /* Enable i2c */ + enbl = readl(&i2c_regs_p->ic_enable); + enbl |= IC_ENABLE_0B; + writel(enbl, &i2c_regs_p->ic_enable); +} + +/* + * i2c_setaddress - Sets the target slave address + * @i2c_addr: target i2c address + * + * Sets the target slave address. + */ +static void i2c_setaddress(unsigned int i2c_addr) +{ + writel(i2c_addr, &i2c_regs_p->ic_tar); +} + +/* + * i2c_flush_rxfifo - Flushes the i2c RX FIFO + * + * Flushes the i2c RX FIFO + */ +static void i2c_flush_rxfifo(void) +{ + while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) + readl(&i2c_regs_p->ic_cmd_data); +} + +/* + * i2c_wait_for_bb - Waits for bus busy + * + * Waits for bus busy + */ +static int i2c_wait_for_bb(void) +{ + unsigned long start_time_bb = get_timer(0); + + while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) || + !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) { + + /* Evaluate timeout */ + if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB)) + return 1; + } + + return 0; +} + +/* check parameters for i2c_read and i2c_write */ +static int check_params(uint addr, int alen, uchar *buffer, int len) +{ + if (buffer == NULL) { + printf("Buffer is invalid\n"); + return 1; + } + + if (alen > 1) { + printf("addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > 256) { + printf("address out of range\n"); + return 1; + } + + return 0; +} + +static int i2c_xfer_init(uchar chip, uint addr) +{ + if (i2c_wait_for_bb()) { + printf("Timed out waiting for bus\n"); + return 1; + } + + i2c_setaddress(chip); + writel(addr, &i2c_regs_p->ic_cmd_data); + + return 0; +} + +static int i2c_xfer_finish(void) +{ + ulong start_stop_det = get_timer(0); + + while (1) { + if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) { + readl(&i2c_regs_p->ic_clr_stop_det); + break; + } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) { + break; + } + } + + if (i2c_wait_for_bb()) { + printf("Timed out waiting for bus\n"); + return 1; + } + + i2c_flush_rxfifo(); + + /* Wait for read/write operation to complete on actual memory */ + udelay(10000); + + return 0; +} + +/* + * i2c_read - Read from i2c memory + * @chip: target i2c address + * @addr: address to read from + * @alen: + * @buffer: buffer for read data + * @len: no of bytes to be read + * + * Read from i2c memory. + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + unsigned long start_time_rx; + + if (check_params(addr, alen, buffer, len)) + return 1; + + if (i2c_xfer_init(chip, addr)) + return 1; + + start_time_rx = get_timer(0); + while (len) { + writel(IC_CMD, &i2c_regs_p->ic_cmd_data); + + if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) { + *buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data); + len--; + start_time_rx = get_timer(0); + + } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { + printf("Timed out. i2c read Failed\n"); + return 1; + } + } + + return i2c_xfer_finish(); +} + +/* + * i2c_write - Write to i2c memory + * @chip: target i2c address + * @addr: address to read from + * @alen: + * @buffer: buffer for read data + * @len: no of bytes to be read + * + * Write to i2c memory. + */ +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int nb = len; + unsigned long start_time_tx; + + if (check_params(addr, alen, buffer, len)) + return 1; + + if (i2c_xfer_init(chip, addr)) + return 1; + + start_time_tx = get_timer(0); + while (len) { + if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) { + writel(*buffer, &i2c_regs_p->ic_cmd_data); + buffer++; + len--; + start_time_tx = get_timer(0); + + } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) { + printf("Timed out. i2c write Failed\n"); + return 1; + } + } + + return i2c_xfer_finish(); +} + +/* + * i2c_probe - Probe the i2c chip + */ +int i2c_probe(uchar chip) +{ + u32 tmp; + + /* + * Try to read the first location of the chip. + */ + return i2c_read(chip, 0, 1, (uchar *)&tmp, 1); +} diff --git a/include/asm-arm/arch-spear/spr_i2c.h b/include/asm-arm/arch-spear/spr_i2c.h new file mode 100755 index 0000000..7521ebc --- /dev/null +++ b/include/asm-arm/arch-spear/spr_i2c.h @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPR_I2C_H_ +#define __SPR_I2C_H_ + +struct i2c_regs { + u32 ic_con; + u32 ic_tar; + u32 ic_sar; + u32 ic_hs_maddr; + u32 ic_cmd_data; + u32 ic_ss_scl_hcnt; + u32 ic_ss_scl_lcnt; + u32 ic_fs_scl_hcnt; + u32 ic_fs_scl_lcnt; + u32 ic_hs_scl_hcnt; + u32 ic_hs_scl_lcnt; + u32 ic_intr_stat; + u32 ic_intr_mask; + u32 ic_raw_intr_stat; + u32 ic_rx_tl; + u32 ic_tx_tl; + u32 ic_clr_intr; + u32 ic_clr_rx_under; + u32 ic_clr_rx_over; + u32 ic_clr_tx_over; + u32 ic_clr_rd_req; + u32 ic_clr_tx_abrt; + u32 ic_clr_rx_done; + u32 ic_clr_activity; + u32 ic_clr_stop_det; + u32 ic_clr_start_det; + u32 ic_clr_gen_call; + u32 ic_enable; + u32 ic_status; + u32 ic_txflr; + u32 ix_rxflr; + u32 reserved_1; + u32 ic_tx_abrt_source; +}; + +#define IC_CLK 166 +#define NANO_TO_MICRO 1000 + +/* High and low times in different speed modes (in ns) */ +#define MIN_SS_SCL_HIGHTIME 4000 +#define MIN_SS_SCL_LOWTIME 5000 +#define MIN_FS_SCL_HIGHTIME 800 +#define MIN_FS_SCL_LOWTIME 1700 +#define MIN_HS_SCL_HIGHTIME 60 +#define MIN_HS_SCL_LOWTIME 160 + +/* Worst case timeout for 1 byte is kept as 2ms */ +#define I2C_BYTE_TO (CONFIG_SYS_HZ/500) +#define I2C_STOPDET_TO (CONFIG_SYS_HZ/500) +#define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16) + +/* i2c control register definitions */ +#define IC_CON_SD 0x0040 +#define IC_CON_RE 0x0020 +#define IC_CON_10BITADDRMASTER 0x0010 +#define IC_CON_10BITADDR_SLAVE 0x0008 +#define IC_CON_SPD_MSK 0x0006 +#define IC_CON_SPD_SS 0x0002 +#define IC_CON_SPD_FS 0x0004 +#define IC_CON_SPD_HS 0x0006 +#define IC_CON_MM 0x0001 + +/* i2c target address register definitions */ +#define TAR_ADDR 0x0050 + +/* i2c slave address register definitions */ +#define IC_SLAVE_ADDR 0x0002 + +/* i2c data buffer and command register definitions */ +#define IC_CMD 0x0100 + +/* i2c interrupt status register definitions */ +#define IC_GEN_CALL 0x0800 +#define IC_START_DET 0x0400 +#define IC_STOP_DET 0x0200 +#define IC_ACTIVITY 0x0100 +#define IC_RX_DONE 0x0080 +#define IC_TX_ABRT 0x0040 +#define IC_RD_REQ 0x0020 +#define IC_TX_EMPTY 0x0010 +#define IC_TX_OVER 0x0008 +#define IC_RX_FULL 0x0004 +#define IC_RX_OVER 0x0002 +#define IC_RX_UNDER 0x0001 + +/* fifo threshold register definitions */ +#define IC_TL0 0x00 +#define IC_TL1 0x01 +#define IC_TL2 0x02 +#define IC_TL3 0x03 +#define IC_TL4 0x04 +#define IC_TL5 0x05 +#define IC_TL6 0x06 +#define IC_TL7 0x07 +#define IC_RX_TL IC_TL0 +#define IC_TX_TL IC_TL0 + +/* i2c enable register definitions */ +#define IC_ENABLE_0B 0x0001 + +/* i2c status register definitions */ +#define IC_STATUS_SA 0x0040 +#define IC_STATUS_MA 0x0020 +#define IC_STATUS_RFF 0x0010 +#define IC_STATUS_RFNE 0x0008 +#define IC_STATUS_TFE 0x0004 +#define IC_STATUS_TFNF 0x0002 +#define IC_STATUS_ACT 0x0001 + +/* Speed Selection */ +#define IC_SPEED_MODE_STANDARD 1 +#define IC_SPEED_MODE_FAST 2 +#define IC_SPEED_MODE_MAX 3 + +#define I2C_MAX_SPEED 3400000 +#define I2C_FAST_SPEED 400000 +#define I2C_STANDARD_SPEED 100000 + +#endif /* __SPR_I2C_H_ */ -- cgit v1.1 From a6e34f76c51c8514f1b691fc60394f09ae4fb2ff Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Fri, 15 Jan 2010 19:15:45 +0530 Subject: SPEAr : smi driver support for SPEAr SoCs SPEAr SoCs contain a serial memory interface controller. This controller is used to interface with spi based memories. This patch adds the driver for this IP. Signed-off-by: Vipin --- drivers/mtd/Makefile | 1 + drivers/mtd/spr_smi.c | 523 +++++++++++++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_smi.h | 115 ++++++++ 3 files changed, 639 insertions(+) mode change 100644 => 100755 drivers/mtd/Makefile create mode 100755 drivers/mtd/spr_smi.c create mode 100755 include/asm-arm/arch-spear/spr_smi.h diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile old mode 100644 new mode 100755 index 754d648..cbf6f15 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o +COBJS-$(CONFIG_SPEARSMI) += spr_smi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/spr_smi.c new file mode 100755 index 0000000..9a70a19 --- /dev/null +++ b/drivers/mtd/spr_smi.c @@ -0,0 +1,523 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include +#include + +#if !defined(CONFIG_SYS_NO_FLASH) + +static struct smi_regs *const smicntl = + (struct smi_regs * const)CONFIG_SYS_SMI_BASE; +static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = + CONFIG_SYS_FLASH_ADDR_BASE; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +#define ST_M25Pxx_ID 0x00002020 + +static struct flash_dev flash_ids[] = { + {0x10, 0x10000, 2}, /* 64K Byte */ + {0x11, 0x20000, 4}, /* 128K Byte */ + {0x12, 0x40000, 4}, /* 256K Byte */ + {0x13, 0x80000, 8}, /* 512K Byte */ + {0x14, 0x100000, 16}, /* 1M Byte */ + {0x15, 0x200000, 32}, /* 2M Byte */ + {0x16, 0x400000, 64}, /* 4M Byte */ + {0x17, 0x800000, 128}, /* 8M Byte */ + {0x18, 0x1000000, 64}, /* 16M Byte */ + {0x00,} +}; + +/* + * smi_wait_xfer_finish - Wait until TFF is set in status register + * @timeout: timeout in milliseconds + * + * Wait until TFF is set in status register + */ +static void smi_wait_xfer_finish(int timeout) +{ + while (timeout--) { + if (readl(&smicntl->smi_sr) & TFF) + break; + udelay(1000); + } +} + +/* + * smi_read_id - Read flash id + * @info: flash_info structure pointer + * @banknum: bank number + * + * Read the flash id present at bank #banknum + */ +static unsigned int smi_read_id(flash_info_t *info, int banknum) +{ + unsigned int value; + + writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); + writel(READ_ID, &smicntl->smi_tr); + writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3, + &smicntl->smi_cr2); + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + value = (readl(&smicntl->smi_rr) & 0x00FFFFFF); + + writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr); + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); + + return value; +} + +/* + * flash_get_size - Detect the SMI flash by reading the ID. + * @base: Base address of the flash area bank #banknum + * @banknum: Bank number + * + * Detect the SMI flash by reading the ID. Initializes the flash_info structure + * with size, sector count etc. + */ +static ulong flash_get_size(ulong base, int banknum) +{ + flash_info_t *info = &flash_info[banknum]; + struct flash_dev *dev; + unsigned int value; + unsigned int density; + int i; + + value = smi_read_id(info, banknum); + density = (value >> 16) & 0xff; + + for (i = 0, dev = &flash_ids[0]; dev->density != 0x0; + i++, dev = &flash_ids[i]) { + if (dev->density == density) { + info->size = dev->size; + info->sector_count = dev->sector_count; + break; + } + } + + if (dev->density == 0x0) + return 0; + + info->flash_id = value & 0xffff; + info->start[0] = base; + + return info->size; +} + +/* + * smi_read_sr - Read status register of SMI + * @bank: bank number + * + * This routine will get the status register of the flash chip present at the + * given bank + */ +static unsigned int smi_read_sr(int bank) +{ + u32 ctrlreg1; + + /* store the CTRL REG1 state */ + ctrlreg1 = readl(&smicntl->smi_cr1); + + /* Program SMI in HW Mode */ + writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE), + &smicntl->smi_cr1); + + /* Performing a RSR instruction in HW mode */ + writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2); + + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + /* Restore the CTRL REG1 state */ + writel(ctrlreg1, &smicntl->smi_cr1); + + return readl(&smicntl->smi_sr); +} + +/* + * smi_wait_till_ready - Wait till last operation is over. + * @bank: bank number shifted. + * @timeout: timeout in milliseconds. + * + * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0) + * The routine checks for #timeout loops, each at interval of 1 milli-second. + * If successful the routine returns 0. + */ +static int smi_wait_till_ready(int bank, int timeout) +{ + int count; + unsigned int sr; + + /* One chip guarantees max 5 msec wait here after page writes, + but potentially three seconds (!) after page erase. */ + for (count = 0; count < timeout; count++) { + + sr = smi_read_sr(bank); + if (sr < 0) + break; + else if (!(sr & WIP_BIT)) + return 0; + + /* Try again after 1m-sec */ + udelay(1000); + } + printf("SMI controller is still in wait, timeout=%d\n", timeout); + return -EIO; +} + +/* + * smi_write_enable - Enable the flash to do write operation + * @bank: bank number + * + * Set write enable latch with Write Enable command. + * Returns negative if error occurred. + */ +static int smi_write_enable(int bank) +{ + u32 ctrlreg1; + int timeout = WMODE_TOUT; + + /* Store the CTRL REG1 state */ + ctrlreg1 = readl(&smicntl->smi_cr1); + + /* Program SMI in H/W Mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); + + /* Give the Flash, Write Enable command */ + writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2); + + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + /* Restore the CTRL REG1 state */ + writel(ctrlreg1, &smicntl->smi_cr1); + + while (timeout--) { + if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT))) + break; + udelay(1000); + } + + if (timeout) + return 0; + + return -1; +} + +/* + * smi_init - SMI initialization routine + * + * SMI initialization routine. Sets SMI control register1. + */ +static void smi_init(void) +{ + /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ + writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, + &smicntl->smi_cr1); +} + +/* + * smi_sector_erase - Erase flash sector + * @info: flash_info structure pointer + * @sector: sector number + * + * Set write enable latch with Write Enable command. + * Returns negative if error occurred. + */ +static int smi_sector_erase(flash_info_t *info, unsigned int sector) +{ + int bank; + unsigned int sect_add; + unsigned int instruction; + + switch (info->start[0]) { + case SMIBANK0_BASE: + bank = BANK0; + break; + case SMIBANK1_BASE: + bank = BANK1; + break; + case SMIBANK2_BASE: + bank = BANK2; + break; + case SMIBANK3_BASE: + bank = BANK3; + break; + default: + return -1; + } + + sect_add = sector * (info->size / info->sector_count); + instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE; + + writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr); + + if (info->flash_id == ST_M25Pxx_ID) { + /* Wait until finished previous write command. */ + if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) + return -EBUSY; + + /* Send write enable, before erase commands. */ + if (smi_write_enable(bank)) + return -EIO; + + /* Put SMI in SW mode */ + writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); + + /* Send Sector Erase command in SW Mode */ + writel(instruction, &smicntl->smi_tr); + writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, + &smicntl->smi_cr2); + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) + return -EBUSY; + + /* Put SMI in HW mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, + &smicntl->smi_cr1); + + return 0; + } else { + /* Put SMI in HW mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, + &smicntl->smi_cr1); + return -EINVAL; + } +} + +/* + * smi_write - Write to SMI flash + * @src_addr: source buffer + * @dst_addr: destination buffer + * @length: length to write in words + * @bank: bank base address + * + * Write to SMI flash + */ +static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, + unsigned int length, ulong bank_addr) +{ + int banknum; + unsigned int WM; + + switch (bank_addr) { + case SMIBANK0_BASE: + banknum = BANK0; + WM = WM0; + break; + case SMIBANK1_BASE: + banknum = BANK1; + WM = WM1; + break; + case SMIBANK2_BASE: + banknum = BANK2; + WM = WM2; + break; + case SMIBANK3_BASE: + banknum = BANK3; + WM = WM3; + break; + default: + return -1; + } + + if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) + return -EBUSY; + + /* Set SMI in Hardware Mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); + + if (smi_write_enable(banknum)) + return -EIO; + + /* Perform the write command */ + while (length--) { + if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) { + if (smi_wait_till_ready(banknum, + CONFIG_SYS_FLASH_WRITE_TOUT)) + return -EBUSY; + + if (smi_write_enable(banknum)) + return -EIO; + } + + *dst_addr++ = *src_addr++; + + if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2))) + return -EIO; + } + + if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) + return -EBUSY; + + writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr); + + return 0; +} + +/* + * write_buff - Write to SMI flash + * @info: flash info structure + * @src: source buffer + * @dest_addr: destination buffer + * @length: length to write in words + * + * Write to SMI flash + */ +int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length) +{ + return smi_write((unsigned int *)src, (unsigned int *)dest_addr, + (length + 3) / 4, info->start[0]); +} + +/* + * flash_init - SMI flash initialization + * + * SMI flash initialization + */ +unsigned long flash_init(void) +{ + unsigned long size = 0; + int i, j; + + smi_init(); + + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + size += flash_info[i].size = flash_get_size(bank_base[i], i); + } + + for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) { + for (i = 1; i < flash_info[j].sector_count; i++) + flash_info[j].start[i] = + flash_info[j].start[i - 1] + + flash_info->size / flash_info->sector_count; + + } + + return size; +} + +/* + * flash_print_info - Print SMI flash information + * + * Print SMI flash information + */ +void flash_print_info(flash_info_t *info) +{ + int i; + if (info->flash_id == FLASH_UNKNOWN) { + puts("missing or unknown FLASH type\n"); + return; + } + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + puts(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { +#ifdef CONFIG_SYS_FLASH_EMPTY_INFO + int size; + int erased; + u32 *flash; + + /* + * Check if whole sector is erased + */ + size = (info->size) / (info->sector_count); + flash = (u32 *) info->start[i]; + size = size / sizeof(int); + + while ((size--) && (*flash++ == ~0)) + ; + + size++; + if (size) + erased = 0; + else + erased = 1; + + if ((i % 5) == 0) + printf("\n"); + + printf(" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO) " : " "); +#endif + } + putc('\n'); + return; +} + +/* + * flash_erase - Erase SMI flash + * + * Erase SMI flash + */ +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot = 0; + flash_sect_t sect; + + if (info->flash_id != ST_M25Pxx_ID) { + puts("Can't erase unknown flash type - aborted\n"); + return 1; + } + + if ((s_first < 0) || (s_first > s_last)) { + puts("- no sectors to erase\n"); + return 1; + } + + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + putc('\n'); + } + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { + if (smi_sector_erase(info, sect)) + rcode = 1; + else + putc('.'); + } + } + puts(" done\n"); + return rcode; +} +#endif diff --git a/include/asm-arm/arch-spear/spr_smi.h b/include/asm-arm/arch-spear/spr_smi.h new file mode 100755 index 0000000..06df745 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_smi.h @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef SPR_SMI_H +#define SPR_SMI_H + +/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ +/* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ + +#define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE +#define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE + +#define SMIBANK0_BASE (FLASH_START_ADDRESS) +#define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) +#define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) +#define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) + +#define BANK0 0 +#define BANK1 1 +#define BANK2 2 +#define BANK3 3 + +struct smi_regs { + u32 smi_cr1; + u32 smi_cr2; + u32 smi_sr; + u32 smi_tr; + u32 smi_rr; +}; + +/* CONTROL REG 1 */ +#define BANK_EN 0x0000000F /* enables all banks */ +#define DSEL_TIME 0x00000060 /* Deselect time */ +#define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ +#define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ +#define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ +#define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ +#define SW_MODE 0x10000000 /* enables SW Mode */ +#define WB_MODE 0x20000000 /* Write Burst Mode */ +#define FAST_MODE 0x00008000 /* Fast Mode */ +#define HOLD1 0x00010000 + +/* CONTROL REG 2 */ +#define RD_STATUS_REG 0x00000400 /* reads status reg */ +#define WE 0x00000800 /* Write Enable */ +#define BANK0_SEL 0x00000000 /* Select Banck0 */ +#define BANK1_SEL 0x00001000 /* Select Banck1 */ +#define BANK2_SEL 0x00002000 /* Select Banck2 */ +#define BANK3_SEL 0x00003000 /* Select Banck3 */ +#define BANKSEL_SHIFT 12 +#define SEND 0x00000080 /* Send data */ +#define TX_LEN_1 0x00000001 /* data length = 1 byte */ +#define TX_LEN_2 0x00000002 /* data length = 2 byte */ +#define TX_LEN_3 0x00000003 /* data length = 3 byte */ +#define TX_LEN_4 0x00000004 /* data length = 4 byte */ +#define RX_LEN_1 0x00000010 /* data length = 1 byte */ +#define RX_LEN_2 0x00000020 /* data length = 2 byte */ +#define RX_LEN_3 0x00000030 /* data length = 3 byte */ +#define RX_LEN_4 0x00000040 /* data length = 4 byte */ +#define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ +#define WCIE 0x00000200 /* WCF Interrupt Enable */ + +/* STATUS_REG */ +#define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ +#define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ +#define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ +#define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ +#define RSR 0x00000005 /* Read Status regiser */ +#define TFF 0x00000100 /* Transfer Finished FLag */ +#define WCF 0x00000200 /* Transfer Finished FLag */ +#define ERF1 0x00000400 /* Error Flag 1 */ +#define ERF2 0x00000800 /* Error Flag 2 */ +#define WM0 0x00001000 /* WM Bank 0 */ +#define WM1 0x00002000 /* WM Bank 1 */ +#define WM2 0x00004000 /* WM Bank 2 */ +#define WM3 0x00008000 /* WM Bank 3 */ +#define WM_SHIFT 12 + +/* TR REG */ +#define READ_ID 0x0000009F /* Read Identification */ +#define BULK_ERASE 0x000000C7 /* BULK erase */ +#define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ +#define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ + +struct flash_dev { + u32 density; + ulong size; + ushort sector_count; +}; + +#define SFLASH_PAGE_SIZE 0x100 /* flash page size */ +#define XFER_FINISH_TOUT 2 /* xfer finish timeout */ +#define WMODE_TOUT 2 /* write enable timeout */ + +#endif -- cgit v1.1 From 165fa406ad8c39c0c32a31476a8a9bda3db72851 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Fri, 15 Jan 2010 19:15:46 +0530 Subject: SPEAr : nand driver support for SPEAr SoCs SPEAr SoCs contain an FSMC controller which can be used to interface with a range of memories eg. NAND, SRAM, NOR. Currently, this driver supports interfacing FSMC with NAND memories Signed-off-by: Vipin --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/spr_nand.c | 124 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_nand.h | 57 ++++++++++++++++ 3 files changed, 182 insertions(+) create mode 100755 drivers/mtd/nand/spr_nand.c create mode 100644 include/asm-arm/arch-spear/spr_nand.h diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 02449ee..28f27da 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_NAND_NDFC) += ndfc.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o +COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o endif diff --git a/drivers/mtd/nand/spr_nand.c b/drivers/mtd/nand/spr_nand.c new file mode 100755 index 0000000..097d0c6 --- /dev/null +++ b/drivers/mtd/nand/spr_nand.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +static struct fsmc_regs *const fsmc_regs_p = + (struct fsmc_regs *)CONFIG_SPEAR_FSMCBASE; + +static struct nand_ecclayout spear_nand_ecclayout = { + .eccbytes = 24, + .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, + 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, + .oobfree = { + {.offset = 8, .length = 8}, + {.offset = 24, .length = 8}, + {.offset = 40, .length = 8}, + {.offset = 56, .length = 8}, + {.offset = 72, .length = 8}, + {.offset = 88, .length = 8}, + {.offset = 104, .length = 8}, + {.offset = 120, .length = 8} + } +}; + +static void spear_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W = (ulong)this->IO_ADDR_W; + + IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE); + if (ctrl & NAND_CLE) + IO_ADDR_W |= CONFIG_SYS_NAND_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= CONFIG_SYS_NAND_ALE; + + if (ctrl & NAND_NCE) { + writel(readl(&fsmc_regs_p->genmemctrl_pc) | + FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc); + } else { + writel(readl(&fsmc_regs_p->genmemctrl_pc) & + ~FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc); + } + this->IO_ADDR_W = (void *)IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int spear_read_hwecc(struct mtd_info *mtd, + const u_char *data, u_char ecc[3]) +{ + u_int ecc_tmp; + + /* read the h/w ECC */ + ecc_tmp = readl(&fsmc_regs_p->genmemctrl_ecc); + + ecc[0] = (u_char) (ecc_tmp & 0xFF); + ecc[1] = (u_char) ((ecc_tmp & 0xFF00) >> 8); + ecc[2] = (u_char) ((ecc_tmp & 0xFF0000) >> 16); + + return 0; +} + +void spear_enable_hwecc(struct mtd_info *mtd, int mode) +{ + writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~0x80, + &fsmc_regs_p->genmemctrl_pc); + writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~FSMC_ECCEN, + &fsmc_regs_p->genmemctrl_pc); + writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_ECCEN, + &fsmc_regs_p->genmemctrl_pc); +} + +int spear_nand_init(struct nand_chip *nand) +{ + writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, + &fsmc_regs_p->genmemctrl_pc); + writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_TCLR_1 | FSMC_TAR_1, + &fsmc_regs_p->genmemctrl_pc); + writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, + &fsmc_regs_p->genmemctrl_comm); + writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, + &fsmc_regs_p->genmemctrl_attrib); + + nand->options = 0; + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &spear_nand_ecclayout; + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.calculate = spear_read_hwecc; + nand->ecc.hwctl = spear_enable_hwecc; + nand->ecc.correct = nand_correct_data; + nand->cmd_ctrl = spear_nand_hwcontrol; + return 0; +} diff --git a/include/asm-arm/arch-spear/spr_nand.h b/include/asm-arm/arch-spear/spr_nand.h new file mode 100644 index 0000000..2b63dc7 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_nand.h @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPR_NAND_H__ +#define __SPR_NAND_H__ + +struct fsmc_regs { + u32 reserved_1[0x10]; + u32 genmemctrl_pc; + u32 reserved_2; + u32 genmemctrl_comm; + u32 genmemctrl_attrib; + u32 reserved_3; + u32 genmemctrl_ecc; +}; + +/* genmemctrl_pc register definitions */ +#define FSMC_RESET (1 << 0) +#define FSMC_WAITON (1 << 1) +#define FSMC_ENABLE (1 << 2) +#define FSMC_DEVTYPE_NAND (1 << 3) +#define FSMC_DEVWID_8 (0 << 4) +#define FSMC_DEVWID_16 (1 << 4) +#define FSMC_ECCEN (1 << 6) +#define FSMC_ECCPLEN_512 (0 << 7) +#define FSMC_ECCPLEN_256 (1 << 7) +#define FSMC_TCLR_1 (1 << 9) +#define FSMC_TAR_1 (1 << 13) + +/* genmemctrl_comm register definitions */ +#define FSMC_TSET_0 (0 << 0) +#define FSMC_TWAIT_6 (6 << 8) +#define FSMC_THOLD_4 (4 << 16) +#define FSMC_THIZ_1 (1 << 24) + +extern int spear_nand_init(struct nand_chip *nand); +#endif -- cgit v1.1 From 62db1c0d79f1fd75961eec81edc8c0a1bc1f09a6 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Fri, 15 Jan 2010 19:15:47 +0530 Subject: SPEAr : usbd driver support for SPEAr SoCs SPEAr SoCs contain a synopsys usb device controller. USB Device IP can work in 2 modes - DMA mode - Slave mode The driver adds support only for slave mode operation of usb device IP. This driver is used along with standard USBTTY driver to obtain a tty interface over USB on the host Signed-off-by: Vipin --- drivers/serial/usbtty.h | 2 + drivers/usb/gadget/Makefile | 1 + drivers/usb/gadget/spr_udc.c | 998 +++++++++++++++++++++++++++++++++++++++++++ include/usb/spr_udc.h | 230 ++++++++++ 4 files changed, 1231 insertions(+) mode change 100644 => 100755 drivers/serial/usbtty.h mode change 100644 => 100755 drivers/usb/gadget/Makefile create mode 100755 drivers/usb/gadget/spr_udc.c create mode 100755 include/usb/spr_udc.h diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h old mode 100644 new mode 100755 index 6b6c4a1..a23169a --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -33,6 +33,8 @@ #include #elif defined(CONFIG_PXA27X) #include +#elif defined(CONFIG_SPEAR3XX) || defined(CONFIG_SPEAR600) +#include #endif #include diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile old mode 100644 new mode 100755 index 2a19b1e..1d7362d --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -32,6 +32,7 @@ COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o COBJS-$(CONFIG_PXA27X) += pxa27x_udc.o +COBJS-$(CONFIG_SPEARUDC) += spr_udc.o endif COBJS := $(COBJS-y) diff --git a/drivers/usb/gadget/spr_udc.c b/drivers/usb/gadget/spr_udc.c new file mode 100755 index 0000000..f2b06d6 --- /dev/null +++ b/drivers/usb/gadget/spr_udc.c @@ -0,0 +1,998 @@ +/* + * Based on drivers/usb/gadget/omap1510_udc.c + * TI OMAP1510 USB bus interface driver + * + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include "ep0.h" +#include +#include +#include + +#define UDC_INIT_MDELAY 80 /* Device settle delay */ + +/* Some kind of debugging output... */ +#ifndef DEBUG_SPRUSBTTY +#define UDCDBG(str) +#define UDCDBGA(fmt, args...) +#else +#define UDCDBG(str) serial_printf(str "\n") +#define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args) +#endif + +static struct urb *ep0_urb; +static struct usb_device_instance *udc_device; + +static struct plug_regs *const plug_regs_p = + (struct plug_regs * const)CONFIG_SYS_PLUG_BASE; +static struct udc_regs *const udc_regs_p = + (struct udc_regs * const)CONFIG_SYS_USBD_BASE; +static struct udc_endp_regs *const outep_regs_p = + &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->out_regs[0]; +static struct udc_endp_regs *const inep_regs_p = + &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->in_regs[0]; + +/* + * udc_state_transition - Write the next packet to TxFIFO. + * @initial: Initial state. + * @final: Final state. + * + * Helper function to implement device state changes. The device states and + * the events that transition between them are: + * + * STATE_ATTACHED + * || /\ + * \/ || + * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET + * || /\ + * \/ || + * STATE_POWERED + * || /\ + * \/ || + * DEVICE_RESET DEVICE_POWER_INTERRUPTION + * || /\ + * \/ || + * STATE_DEFAULT + * || /\ + * \/ || + * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET + * || /\ + * \/ || + * STATE_ADDRESSED + * || /\ + * \/ || + * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED + * || /\ + * \/ || + * STATE_CONFIGURED + * + * udc_state_transition transitions up (in the direction from STATE_ATTACHED + * to STATE_CONFIGURED) from the specified initial state to the specified final + * state, passing through each intermediate state on the way. If the initial + * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then + * no state transitions will take place. + * + * udc_state_transition also transitions down (in the direction from + * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the + * specified final state, passing through each intermediate state on the way. + * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final + * state, then no state transitions will take place. + * + * This function must only be called with interrupts disabled. + */ +static void udc_state_transition(usb_device_state_t initial, + usb_device_state_t final) +{ + if (initial < final) { + switch (initial) { + case STATE_ATTACHED: + usbd_device_event_irq(udc_device, + DEVICE_HUB_CONFIGURED, 0); + if (final == STATE_POWERED) + break; + case STATE_POWERED: + usbd_device_event_irq(udc_device, DEVICE_RESET, 0); + if (final == STATE_DEFAULT) + break; + case STATE_DEFAULT: + usbd_device_event_irq(udc_device, + DEVICE_ADDRESS_ASSIGNED, 0); + if (final == STATE_ADDRESSED) + break; + case STATE_ADDRESSED: + usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0); + case STATE_CONFIGURED: + break; + default: + break; + } + } else if (initial > final) { + switch (initial) { + case STATE_CONFIGURED: + usbd_device_event_irq(udc_device, + DEVICE_DE_CONFIGURED, 0); + if (final == STATE_ADDRESSED) + break; + case STATE_ADDRESSED: + usbd_device_event_irq(udc_device, DEVICE_RESET, 0); + if (final == STATE_DEFAULT) + break; + case STATE_DEFAULT: + usbd_device_event_irq(udc_device, + DEVICE_POWER_INTERRUPTION, 0); + if (final == STATE_POWERED) + break; + case STATE_POWERED: + usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0); + case STATE_ATTACHED: + break; + default: + break; + } + } +} + +/* Stall endpoint */ +static void udc_stall_ep(u32 ep_num) +{ + writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, + &inep_regs_p[ep_num].endp_cntl); + + writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, + &outep_regs_p[ep_num].endp_cntl); +} + +static void *get_fifo(int ep_num, int in) +{ + u32 *fifo_ptr = (u32 *)CONFIG_SYS_FIFO_BASE; + + switch (ep_num) { + case UDC_EP3: + fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn); + /* break intentionally left out */ + + case UDC_EP1: + fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn); + /* break intentionally left out */ + + case UDC_EP0: + default: + if (in) { + fifo_ptr += + readl(&outep_regs_p[2].endp_maxpacksize) >> 16; + /* break intentionally left out */ + } else { + break; + } + + case UDC_EP2: + fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16; + /* break intentionally left out */ + } + + return (void *)fifo_ptr; +} + +static int usbgetpckfromfifo(int epNum, u8 *bufp, u32 len) +{ + u8 *fifo_ptr = (u8 *)get_fifo(epNum, 0); + u32 i, nw, nb; + u32 *wrdp; + u8 *bytp; + + if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY) + return -1; + + nw = len / sizeof(u32); + nb = len % sizeof(u32); + + wrdp = (u32 *)bufp; + for (i = 0; i < nw; i++) { + writel(readl(fifo_ptr), wrdp); + wrdp++; + } + + bytp = (u8 *)wrdp; + for (i = 0; i < nb; i++) { + writeb(readb(fifo_ptr), bytp); + fifo_ptr++; + bytp++; + } + readl(&outep_regs_p[epNum].write_done); + + return 0; +} + +static void usbputpcktofifo(int epNum, u8 *bufp, u32 len) +{ + u32 i, nw, nb; + u32 *wrdp; + u8 *bytp; + u8 *fifo_ptr = get_fifo(epNum, 1); + + nw = len / sizeof(int); + nb = len % sizeof(int); + wrdp = (u32 *)bufp; + for (i = 0; i < nw; i++) { + writel(*wrdp, fifo_ptr); + wrdp++; + } + + bytp = (u8 *)wrdp; + for (i = 0; i < nb; i++) { + writeb(*bytp, fifo_ptr); + fifo_ptr++; + bytp++; + } +} + +/* + * spear_write_noniso_tx_fifo - Write the next packet to TxFIFO. + * @endpoint: Endpoint pointer. + * + * If the endpoint has an active tx_urb, then the next packet of data from the + * URB is written to the tx FIFO. The total amount of data in the urb is given + * by urb->actual_length. The maximum amount of data that can be sent in any + * one packet is given by endpoint->tx_packetSize. The number of data bytes + * from this URB that have already been transmitted is given by endpoint->sent. + * endpoint->last is updated by this routine with the number of data bytes + * transmitted in this packet. + * + */ +static void spear_write_noniso_tx_fifo(struct usb_endpoint_instance + *endpoint) +{ + struct urb *urb = endpoint->tx_urb; + int align; + + if (urb) { + u32 last; + + UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d", + urb->buffer, urb->buffer_length, urb->actual_length); + + last = MIN(urb->actual_length - endpoint->sent, + endpoint->tx_packetSize); + + if (last) { + u8 *cp = urb->buffer + endpoint->sent; + + /* + * This ensures that USBD packet fifo is accessed + * - through word aligned pointer or + * - through non word aligned pointer but only + * with a max length to make the next packet + * word aligned + */ + + align = ((ulong)cp % sizeof(int)); + if (align) + last = MIN(last, sizeof(int) - align); + + UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d", + endpoint->sent, endpoint->tx_packetSize, last); + + usbputpcktofifo(endpoint->endpoint_address & + USB_ENDPOINT_NUMBER_MASK, cp, last); + } + endpoint->last = last; + } +} + +/* + * Handle SETUP USB interrupt. + * This function implements TRM Figure 14-14. + */ +static void spear_udc_setup(struct usb_endpoint_instance *endpoint) +{ + u8 *datap = (u8 *)&ep0_urb->device_request; + int ep_addr = endpoint->endpoint_address; + + UDCDBG("-> Entering device setup"); + usbgetpckfromfifo(ep_addr, datap, 8); + + /* Try to process setup packet */ + if (ep0_recv_setup(ep0_urb)) { + /* Not a setup packet, stall next EP0 transaction */ + udc_stall_ep(0); + UDCDBG("can't parse setup packet, still waiting for setup"); + return; + } + + /* Check direction */ + if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) + == USB_REQ_HOST2DEVICE) { + UDCDBG("control write on EP0"); + if (le16_to_cpu(ep0_urb->device_request.wLength)) { + /* Stall this request */ + UDCDBG("Stalling unsupported EP0 control write data " + "stage."); + udc_stall_ep(0); + } + } else { + + UDCDBG("control read on EP0"); + /* + * The ep0_recv_setup function has already placed our response + * packet data in ep0_urb->buffer and the packet length in + * ep0_urb->actual_length. + */ + endpoint->tx_urb = ep0_urb; + endpoint->sent = 0; + /* + * Write packet data to the FIFO. spear_write_noniso_tx_fifo + * will update endpoint->last with the number of bytes written + * to the FIFO. + */ + spear_write_noniso_tx_fifo(endpoint); + + writel(0x0, &inep_regs_p[ep_addr].write_done); + } + + udc_unset_nak(endpoint->endpoint_address); + + UDCDBG("<- Leaving device setup"); +} + +/* + * Handle endpoint 0 RX interrupt + */ +static void spear_udc_ep0_rx(struct usb_endpoint_instance *endpoint) +{ + u8 dummy[64]; + + UDCDBG("RX on EP0"); + + /* Check direction */ + if ((ep0_urb->device_request.bmRequestType + & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) { + /* + * This rx interrupt must be for a control write data + * stage packet. + * + * We don't support control write data stages. + * We should never end up here. + */ + + UDCDBG("Stalling unexpected EP0 control write " + "data stage packet"); + udc_stall_ep(0); + } else { + /* + * This rx interrupt must be for a control read status + * stage packet. + */ + UDCDBG("ACK on EP0 control read status stage packet"); + u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff; + usbgetpckfromfifo(0, dummy, len); + } +} + +/* + * Handle endpoint 0 TX interrupt + */ +static void spear_udc_ep0_tx(struct usb_endpoint_instance *endpoint) +{ + struct usb_device_request *request = &ep0_urb->device_request; + int ep_addr; + + UDCDBG("TX on EP0"); + + /* Check direction */ + if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) == + USB_REQ_HOST2DEVICE) { + /* + * This tx interrupt must be for a control write status + * stage packet. + */ + UDCDBG("ACK on EP0 control write status stage packet"); + } else { + /* + * This tx interrupt must be for a control read data + * stage packet. + */ + int wLength = le16_to_cpu(request->wLength); + + /* + * Update our count of bytes sent so far in this + * transfer. + */ + endpoint->sent += endpoint->last; + + /* + * We are finished with this transfer if we have sent + * all of the bytes in our tx urb (urb->actual_length) + * unless we need a zero-length terminating packet. We + * need a zero-length terminating packet if we returned + * fewer bytes than were requested (wLength) by the host, + * and the number of bytes we returned is an exact + * multiple of the packet size endpoint->tx_packetSize. + */ + if ((endpoint->sent == ep0_urb->actual_length) && + ((ep0_urb->actual_length == wLength) || + (endpoint->last != endpoint->tx_packetSize))) { + /* Done with control read data stage. */ + UDCDBG("control read data stage complete"); + } else { + /* + * We still have another packet of data to send + * in this control read data stage or else we + * need a zero-length terminating packet. + */ + UDCDBG("ACK control read data stage packet"); + spear_write_noniso_tx_fifo(endpoint); + + ep_addr = endpoint->endpoint_address; + writel(0x0, &inep_regs_p[ep_addr].write_done); + } + } +} + +static struct usb_endpoint_instance *spear_find_ep(int ep) +{ + int i; + + for (i = 0; i < udc_device->bus->max_endpoints; i++) { + if ((udc_device->bus->endpoint_array[i].endpoint_address & + USB_ENDPOINT_NUMBER_MASK) == ep) + return &udc_device->bus->endpoint_array[i]; + } + return NULL; +} + +/* + * Handle RX transaction on non-ISO endpoint. + * The ep argument is a physical endpoint number for a non-ISO IN endpoint + * in the range 1 to 15. + */ +static void spear_udc_epn_rx(int ep) +{ + int nbytes = 0; + struct urb *urb; + struct usb_endpoint_instance *endpoint = spear_find_ep(ep); + + if (endpoint) { + urb = endpoint->rcv_urb; + + if (urb) { + u8 *cp = urb->buffer + urb->actual_length; + + nbytes = (readl(&outep_regs_p[ep].endp_status) >> 11) & + 0xfff; + usbgetpckfromfifo(ep, cp, nbytes); + usbd_rcv_complete(endpoint, nbytes, 0); + } + } +} + +/* + * Handle TX transaction on non-ISO endpoint. + * The ep argument is a physical endpoint number for a non-ISO IN endpoint + * in the range 16 to 30. + */ +static void spear_udc_epn_tx(int ep) +{ + struct usb_endpoint_instance *endpoint = spear_find_ep(ep); + + /* + * We need to transmit a terminating zero-length packet now if + * we have sent all of the data in this URB and the transfer + * size was an exact multiple of the packet size. + */ + if (endpoint && endpoint->tx_urb && endpoint->tx_urb->actual_length) { + if (endpoint->last == endpoint->tx_packetSize) { + /* handle zero length packet here */ + writel(0x0, &inep_regs_p[ep].write_done); + } + /* retire the data that was just sent */ + usbd_tx_complete(endpoint); + /* + * Check to see if we have more data ready to transmit + * now. + */ + if (endpoint->tx_urb && endpoint->tx_urb->actual_length) { + /* write data to FIFO */ + spear_write_noniso_tx_fifo(endpoint); + writel(0x0, &inep_regs_p[ep].write_done); + + } else if (endpoint->tx_urb + && (endpoint->tx_urb->actual_length == 0)) { + /* udc_set_nak(ep); */ + } + } +} + +/* + * Start of public functions. + */ + +/* Called to start packet transmission. */ +int udc_endpoint_write(struct usb_endpoint_instance *endpoint) +{ + udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK); + return 0; +} + +/* Start to initialize h/w stuff */ +int udc_init(void) +{ + int i; + u32 plug_st; + + udc_device = NULL; + + UDCDBG("starting"); + + readl(&plug_regs_p->plug_pending); + + udc_disconnect(); + + for (i = 0; i < UDC_INIT_MDELAY; i++) + udelay(1000); + + plug_st = readl(&plug_regs_p->plug_state); + writel(plug_st | PLUG_STATUS_EN, &plug_regs_p->plug_state); + + writel(~0x0, &udc_regs_p->endp_int); + writel(~0x0, &udc_regs_p->dev_int_mask); + writel(~0x0, &udc_regs_p->endp_int_mask); + + writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW | + /* Dev_Conf_SYNCFRAME | */ + DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf); + + writel(0x0, &udc_regs_p->dev_cntl); + + /* Clear all interrupts pending */ + writel(DEV_INT_MSK, &udc_regs_p->dev_int); + + return 0; +} + +/* + * udc_setup_ep - setup endpoint + * Associate a physical endpoint with endpoint_instance + */ +void udc_setup_ep(struct usb_device_instance *device, + u32 ep, struct usb_endpoint_instance *endpoint) +{ + UDCDBGA("setting up endpoint addr %x", endpoint->endpoint_address); + int ep_addr; + int ep_num, ep_type; + int packet_size; + int buffer_size; + int attributes; + char *tt; + u32 endp_intmask; + + tt = getenv("usbtty"); + if (!tt) + tt = "generic"; + + ep_addr = endpoint->endpoint_address; + ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; + + if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + /* IN endpoint */ + packet_size = endpoint->tx_packetSize; + buffer_size = packet_size * 2; + attributes = endpoint->tx_attributes; + } else { + /* OUT endpoint */ + packet_size = endpoint->rcv_packetSize; + buffer_size = packet_size * 2; + attributes = endpoint->rcv_attributes; + } + + switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) { + case USB_ENDPOINT_XFER_CONTROL: + ep_type = ENDP_EPTYPE_CNTL; + break; + case USB_ENDPOINT_XFER_BULK: + default: + ep_type = ENDP_EPTYPE_BULK; + break; + case USB_ENDPOINT_XFER_INT: + ep_type = ENDP_EPTYPE_INT; + break; + case USB_ENDPOINT_XFER_ISOC: + ep_type = ENDP_EPTYPE_ISO; + break; + } + + struct udc_endp_regs *out_p = &outep_regs_p[ep_num]; + struct udc_endp_regs *in_p = &inep_regs_p[ep_num]; + + if (!ep_addr) { + /* Setup endpoint 0 */ + buffer_size = packet_size; + + writel(readl(&in_p->endp_cntl) | ENDP_CNTL_CNAK, + &in_p->endp_cntl); + + writel(readl(&out_p->endp_cntl) | ENDP_CNTL_CNAK, + &out_p->endp_cntl); + + writel(ENDP_CNTL_CONTROL | ENDP_CNTL_FLUSH, &in_p->endp_cntl); + + writel(buffer_size / sizeof(int), &in_p->endp_bsorfn); + + writel(packet_size, &in_p->endp_maxpacksize); + + writel(ENDP_CNTL_CONTROL | ENDP_CNTL_RRDY, &out_p->endp_cntl); + + writel(packet_size | ((buffer_size / sizeof(int)) << 16), + &out_p->endp_maxpacksize); + + writel((packet_size << 19) | ENDP_EPTYPE_CNTL, + &udc_regs_p->udc_endp_reg[ep_num]); + + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + /* Setup the IN endpoint */ + writel(0x0, &in_p->endp_status); + writel((ep_type << 4) | ENDP_CNTL_RRDY, &in_p->endp_cntl); + writel(buffer_size / sizeof(int), &in_p->endp_bsorfn); + writel(packet_size, &in_p->endp_maxpacksize); + + if (!strcmp(tt, "cdc_acm")) { + if (ep_type == ENDP_EPTYPE_INT) { + /* Conf no. 1 Interface no. 0 */ + writel((packet_size << 19) | + ENDP_EPDIR_IN | (1 << 7) | + (0 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } else { + /* Conf no. 1 Interface no. 1 */ + writel((packet_size << 19) | + ENDP_EPDIR_IN | (1 << 7) | + (1 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } + } else { + /* Conf no. 1 Interface no. 0 */ + writel((packet_size << 19) | + ENDP_EPDIR_IN | (1 << 7) | + (0 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } + + } else { + /* Setup the OUT endpoint */ + writel(0x0, &out_p->endp_status); + writel((ep_type << 4) | ENDP_CNTL_RRDY, &out_p->endp_cntl); + writel(packet_size | ((buffer_size / sizeof(int)) << 16), + &out_p->endp_maxpacksize); + + if (!strcmp(tt, "cdc_acm")) { + writel((packet_size << 19) | + ENDP_EPDIR_OUT | (1 << 7) | + (1 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } else { + writel((packet_size << 19) | + ENDP_EPDIR_OUT | (1 << 7) | + (0 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } + + } + + endp_intmask = readl(&udc_regs_p->endp_int_mask); + endp_intmask &= ~((1 << ep_num) | 0x10000 << ep_num); + writel(endp_intmask, &udc_regs_p->endp_int_mask); +} + +/* Turn on the USB connection by enabling the pullup resistor */ +void udc_connect(void) +{ + u32 plug_st; + + plug_st = readl(&plug_regs_p->plug_state); + plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); + writel(plug_st, &plug_regs_p->plug_state); +} + +/* Turn off the USB connection by disabling the pullup resistor */ +void udc_disconnect(void) +{ + u32 plug_st; + + plug_st = readl(&plug_regs_p->plug_state); + plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); + writel(plug_st, &plug_regs_p->plug_state); +} + +/* Switch on the UDC */ +void udc_enable(struct usb_device_instance *device) +{ + UDCDBGA("enable device %p, status %d", device, device->status); + + /* Save the device structure pointer */ + udc_device = device; + + /* Setup ep0 urb */ + if (!ep0_urb) { + ep0_urb = + usbd_alloc_urb(udc_device, udc_device->bus->endpoint_array); + } else { + serial_printf("udc_enable: ep0_urb already allocated %p\n", + ep0_urb); + } + + writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask); +} + +/** + * udc_startup - allow udc code to do any additional startup + */ +void udc_startup_events(struct usb_device_instance *device) +{ + /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ + usbd_device_event_irq(device, DEVICE_INIT, 0); + + /* + * The DEVICE_CREATE event puts the USB device in the state + * STATE_ATTACHED. + */ + usbd_device_event_irq(device, DEVICE_CREATE, 0); + + /* + * Some USB controller driver implementations signal + * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. + * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, + * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. + * The SPEAr USB client controller has the capability to detect when the + * USB cable is connected to a powered USB bus, so we will defer the + * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later. + */ + + udc_enable(device); +} + +/* + * Plug detection interrupt handling + */ +void spear_udc_plug_irq(void) +{ + if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) { + /* + * USB cable attached + * Turn off PHY reset bit (PLUG detect). + * Switch PHY opmode to normal operation (PLUG detect). + */ + udc_connect(); + writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask); + + UDCDBG("device attached and powered"); + udc_state_transition(udc_device->device_state, STATE_POWERED); + } else { + /* + * USB cable detached + * Reset the PHY and switch the mode. + */ + udc_disconnect(); + writel(~0x0, &udc_regs_p->dev_int_mask); + + UDCDBG("device detached or unpowered"); + udc_state_transition(udc_device->device_state, STATE_ATTACHED); + } +} + +/* + * Device interrupt handling + */ +void spear_udc_dev_irq(void) +{ + if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) { + writel(~0x0, &udc_regs_p->endp_int_mask); + + udc_connect(); + + writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH, + &inep_regs_p[0].endp_cntl); + + writel(DEV_INT_USBRESET, &udc_regs_p->dev_int); + + UDCDBG("device reset in progess"); + udc_state_transition(udc_device->device_state, STATE_DEFAULT); + } + + /* Device Enumeration completed */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_ENUM) { + writel(DEV_INT_ENUM, &udc_regs_p->dev_int); + + /* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */ + writel(readl(&udc_regs_p->endp_int_mask) & ~0x10001, + &udc_regs_p->endp_int_mask); + + UDCDBG("default -> addressed"); + udc_state_transition(udc_device->device_state, STATE_ADDRESSED); + } + + /* The USB will be in SUSPEND in 3 ms */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_INACTIVE) { + writel(DEV_INT_INACTIVE, &udc_regs_p->dev_int); + + UDCDBG("entering inactive state"); + /* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */ + } + + /* SetConfiguration command received */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_SETCFG) { + writel(DEV_INT_SETCFG, &udc_regs_p->dev_int); + + UDCDBG("entering configured state"); + udc_state_transition(udc_device->device_state, + STATE_CONFIGURED); + } + + /* SetInterface command received */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_SETINTF) + writel(DEV_INT_SETINTF, &udc_regs_p->dev_int); + + /* USB Suspend detected on cable */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_SUSPUSB) { + writel(DEV_INT_SUSPUSB, &udc_regs_p->dev_int); + + UDCDBG("entering suspended state"); + usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); + } + + /* USB Start-Of-Frame detected on cable */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_SOF) + writel(DEV_INT_SOF, &udc_regs_p->dev_int); +} + +/* + * Endpoint interrupt handling + */ +void spear_udc_endpoint_irq(void) +{ + while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) { + + writel(ENDP0_INT_CTRLOUT, &udc_regs_p->endp_int); + + if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK) + == ENDP_STATUS_OUT_SETUP) { + spear_udc_setup(udc_device->bus->endpoint_array + 0); + writel(ENDP_STATUS_OUT_SETUP, + &outep_regs_p[0].endp_status); + + } else if ((readl(&outep_regs_p[0].endp_status) & + ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) { + spear_udc_ep0_rx(udc_device->bus->endpoint_array + 0); + writel(ENDP_STATUS_OUT_DATA, + &outep_regs_p[0].endp_status); + + } else if ((readl(&outep_regs_p[0].endp_status) & + ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) { + /* NONE received */ + } + + writel(0x0, &outep_regs_p[0].endp_status); + } + + if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) { + spear_udc_ep0_tx(udc_device->bus->endpoint_array + 0); + + writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status); + writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int); + } + + while (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) { + u32 epnum = 0; + u32 ep_int = readl(&udc_regs_p->endp_int) & + ENDP_INT_NONISOOUT_MSK; + + ep_int >>= 16; + while (0x0 == (ep_int & 0x1)) { + ep_int >>= 1; + epnum++; + } + + writel((1 << 16) << epnum, &udc_regs_p->endp_int); + + if ((readl(&outep_regs_p[epnum].endp_status) & + ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) { + + spear_udc_epn_rx(epnum); + writel(ENDP_STATUS_OUT_DATA, + &outep_regs_p[epnum].endp_status); + } else if ((readl(&outep_regs_p[epnum].endp_status) & + ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) { + writel(0x0, &outep_regs_p[epnum].endp_status); + } + } + + if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOIN_MSK) { + u32 epnum = 0; + u32 ep_int = readl(&udc_regs_p->endp_int) & + ENDP_INT_NONISOIN_MSK; + + while (0x0 == (ep_int & 0x1)) { + ep_int >>= 1; + epnum++; + } + + if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) { + writel(ENDP_STATUS_IN, + &outep_regs_p[epnum].endp_status); + spear_udc_epn_tx(epnum); + + writel(ENDP_STATUS_IN, + &outep_regs_p[epnum].endp_status); + } + + writel((1 << epnum), &udc_regs_p->endp_int); + } +} + +/* + * UDC interrupts + */ +void udc_irq(void) +{ + /* + * Loop while we have interrupts. + * If we don't do this, the input chain + * polling delay is likely to miss + * host requests. + */ + while (readl(&plug_regs_p->plug_pending)) + spear_udc_plug_irq(); + + while (readl(&udc_regs_p->dev_int)) + spear_udc_dev_irq(); + + if (readl(&udc_regs_p->endp_int)) + spear_udc_endpoint_irq(); +} + +/* Flow control */ +void udc_set_nak(int epid) +{ + writel(readl(&inep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK, + &inep_regs_p[epid].endp_cntl); + + writel(readl(&outep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK, + &outep_regs_p[epid].endp_cntl); +} + +void udc_unset_nak(int epid) +{ + u32 val; + + val = readl(&inep_regs_p[epid].endp_cntl); + val &= ~ENDP_CNTL_SNAK; + val |= ENDP_CNTL_CNAK; + writel(val, &inep_regs_p[epid].endp_cntl); + + val = readl(&outep_regs_p[epid].endp_cntl); + val &= ~ENDP_CNTL_SNAK; + val |= ENDP_CNTL_CNAK; + writel(val, &outep_regs_p[epid].endp_cntl); +} diff --git a/include/usb/spr_udc.h b/include/usb/spr_udc.h new file mode 100755 index 0000000..2c332d5 --- /dev/null +++ b/include/usb/spr_udc.h @@ -0,0 +1,230 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPR_UDC_H +#define __SPR_UDC_H + +/* + * Defines for USBD + * + * The udc_ahb controller has three AHB slaves: + * + * 1. THe UDC registers + * 2. The plug detect + * 3. The RX/TX FIFO + */ + +#define MAX_ENDPOINTS 16 + +struct udc_endp_regs { + u32 endp_cntl; + u32 endp_status; + u32 endp_bsorfn; + u32 endp_maxpacksize; + u32 reserved_1; + u32 endp_desc_point; + u32 reserved_2; + u32 write_done; +}; + +/* Endpoint Control Register definitions */ + +#define ENDP_CNTL_STALL 0x00000001 +#define ENDP_CNTL_FLUSH 0x00000002 +#define ENDP_CNTL_SNOOP 0x00000004 +#define ENDP_CNTL_POLL 0x00000008 +#define ENDP_CNTL_CONTROL 0x00000000 +#define ENDP_CNTL_ISO 0x00000010 +#define ENDP_CNTL_BULK 0x00000020 +#define ENDP_CNTL_INT 0x00000030 +#define ENDP_CNTL_NAK 0x00000040 +#define ENDP_CNTL_SNAK 0x00000080 +#define ENDP_CNTL_CNAK 0x00000100 +#define ENDP_CNTL_RRDY 0x00000200 + +/* Endpoint Satus Register definitions */ + +#define ENDP_STATUS_PIDMSK 0x0000000f +#define ENDP_STATUS_OUTMSK 0x00000030 +#define ENDP_STATUS_OUT_NONE 0x00000000 +#define ENDP_STATUS_OUT_DATA 0x00000010 +#define ENDP_STATUS_OUT_SETUP 0x00000020 +#define ENDP_STATUS_IN 0x00000040 +#define ENDP_STATUS_BUFFNAV 0x00000080 +#define ENDP_STATUS_FATERR 0x00000100 +#define ENDP_STATUS_HOSTBUSERR 0x00000200 +#define ENDP_STATUS_TDC 0x00000400 +#define ENDP_STATUS_RXPKTMSK 0x003ff800 + +struct udc_regs { + struct udc_endp_regs in_regs[MAX_ENDPOINTS]; + struct udc_endp_regs out_regs[MAX_ENDPOINTS]; + u32 dev_conf; + u32 dev_cntl; + u32 dev_stat; + u32 dev_int; + u32 dev_int_mask; + u32 endp_int; + u32 endp_int_mask; + u32 reserved_3[0x39]; + u32 reserved_4; /* offset 0x500 */ + u32 udc_endp_reg[MAX_ENDPOINTS]; +}; + +/* Device Configuration Register definitions */ + +#define DEV_CONF_HS_SPEED 0x00000000 +#define DEV_CONF_LS_SPEED 0x00000002 +#define DEV_CONF_FS_SPEED 0x00000003 +#define DEV_CONF_REMWAKEUP 0x00000004 +#define DEV_CONF_SELFPOW 0x00000008 +#define DEV_CONF_SYNCFRAME 0x00000010 +#define DEV_CONF_PHYINT_8 0x00000020 +#define DEV_CONF_PHYINT_16 0x00000000 +#define DEV_CONF_UTMI_BIDIR 0x00000040 +#define DEV_CONF_STATUS_STALL 0x00000080 + +/* Device Control Register definitions */ + +#define DEV_CNTL_RESUME 0x00000001 +#define DEV_CNTL_TFFLUSH 0x00000002 +#define DEV_CNTL_RXDMAEN 0x00000004 +#define DEV_CNTL_TXDMAEN 0x00000008 +#define DEV_CNTL_DESCRUPD 0x00000010 +#define DEV_CNTL_BIGEND 0x00000020 +#define DEV_CNTL_BUFFILL 0x00000040 +#define DEV_CNTL_TSHLDEN 0x00000080 +#define DEV_CNTL_BURSTEN 0x00000100 +#define DEV_CNTL_DMAMODE 0x00000200 +#define DEV_CNTL_SOFTDISCONNECT 0x00000400 +#define DEV_CNTL_SCALEDOWN 0x00000800 +#define DEV_CNTL_BURSTLENU 0x00010000 +#define DEV_CNTL_BURSTLENMSK 0x00ff0000 +#define DEV_CNTL_TSHLDLENU 0x01000000 +#define DEV_CNTL_TSHLDLENMSK 0xff000000 + +/* Device Status Register definitions */ + +#define DEV_STAT_CFG 0x0000000f +#define DEV_STAT_INTF 0x000000f0 +#define DEV_STAT_ALT 0x00000f00 +#define DEV_STAT_SUSP 0x00001000 +#define DEV_STAT_ENUM 0x00006000 +#define DEV_STAT_ENUM_SPEED_HS 0x00000000 +#define DEV_STAT_ENUM_SPEED_FS 0x00002000 +#define DEV_STAT_ENUM_SPEED_LS 0x00004000 +#define DEV_STAT_RXFIFO_EMPTY 0x00008000 +#define DEV_STAT_PHY_ERR 0x00010000 +#define DEV_STAT_TS 0xf0000000 + +/* Device Interrupt Register definitions */ + +#define DEV_INT_MSK 0x0000007f +#define DEV_INT_SETCFG 0x00000001 +#define DEV_INT_SETINTF 0x00000002 +#define DEV_INT_INACTIVE 0x00000004 +#define DEV_INT_USBRESET 0x00000008 +#define DEV_INT_SUSPUSB 0x00000010 +#define DEV_INT_SOF 0x00000020 +#define DEV_INT_ENUM 0x00000040 + +/* Endpoint Interrupt Register definitions */ + +#define ENDP0_INT_CTRLIN 0x00000001 +#define ENDP1_INT_BULKIN 0x00000002 +#define ENDP_INT_NONISOIN_MSK 0x0000AAAA +#define ENDP2_INT_BULKIN 0x00000004 +#define ENDP0_INT_CTRLOUT 0x00010000 +#define ENDP1_INT_BULKOUT 0x00020000 +#define ENDP2_INT_BULKOUT 0x00040000 +#define ENDP_INT_NONISOOUT_MSK 0x55540000 + +/* Endpoint Register definitions */ +#define ENDP_EPDIR_OUT 0x00000000 +#define ENDP_EPDIR_IN 0x00000010 +#define ENDP_EPTYPE_CNTL 0x0 +#define ENDP_EPTYPE_ISO 0x1 +#define ENDP_EPTYPE_BULK 0x2 +#define ENDP_EPTYPE_INT 0x3 + +/* + * Defines for Plug Detect + */ + +struct plug_regs { + u32 plug_state; + u32 plug_pending; +}; + +/* Plug State Register definitions */ +#define PLUG_STATUS_EN 0x1 +#define PLUG_STATUS_ATTACHED 0x2 +#define PLUG_STATUS_PHY_RESET 0x4 +#define PLUG_STATUS_PHY_MODE 0x8 + +/* + * Defines for UDC FIFO (Slave Mode) + */ +struct udcfifo_regs { + u32 *fifo_p; +}; + +/* + * USBTTY definitions + */ +#define EP0_MAX_PACKET_SIZE 64 +#define UDC_INT_ENDPOINT 1 +#define UDC_INT_PACKET_SIZE 64 +#define UDC_OUT_ENDPOINT 2 +#define UDC_BULK_PACKET_SIZE 64 +#define UDC_IN_ENDPOINT 3 +#define UDC_OUT_PACKET_SIZE 64 +#define UDC_IN_PACKET_SIZE 64 + +/* + * UDC endpoint definitions + */ +#define UDC_EP0 0 +#define UDC_EP1 1 +#define UDC_EP2 2 +#define UDC_EP3 3 + +/* + * Function declarations + */ + +void udc_irq(void); + +void udc_set_nak(int epid); +void udc_unset_nak(int epid); +int udc_endpoint_write(struct usb_endpoint_instance *endpoint); +int udc_init(void); +void udc_enable(struct usb_device_instance *device); +void udc_disable(void); +void udc_connect(void); +void udc_disconnect(void); +void udc_startup_events(struct usb_device_instance *device); +void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, + struct usb_endpoint_instance *endpoint); + +#endif /* __SPR_UDC_H */ -- cgit v1.1 From 566c9c16fe4e501c3193ae6605bc9c663c6ea706 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Fri, 15 Jan 2010 19:15:48 +0530 Subject: SPEAr : Support added for SPEAr600 board SPEAr600 SoC support contains basic spear600 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver Signed-off-by: Vipin --- MAKEALL | 1 + Makefile | 3 + board/spear/common/Makefile | 54 +++++++ board/spear/common/spr_lowlevel_init.S | 195 ++++++++++++++++++++++ board/spear/common/spr_misc.c | 171 ++++++++++++++++++++ board/spear/spear600/Makefile | 51 ++++++ board/spear/spear600/config.mk | 39 +++++ board/spear/spear600/spear600.c | 53 ++++++ include/asm-arm/arch-spear/spr_defs.h | 38 +++++ include/asm-arm/arch-spear/spr_xloader_table.h | 67 ++++++++ include/configs/spear-common.h | 213 +++++++++++++++++++++++++ include/configs/spear6xx.h | 43 +++++ 12 files changed, 928 insertions(+) create mode 100644 board/spear/common/Makefile create mode 100755 board/spear/common/spr_lowlevel_init.S create mode 100755 board/spear/common/spr_misc.c create mode 100755 board/spear/spear600/Makefile create mode 100755 board/spear/spear600/config.mk create mode 100755 board/spear/spear600/spear600.c create mode 100644 include/asm-arm/arch-spear/spr_defs.h create mode 100755 include/asm-arm/arch-spear/spr_xloader_table.h create mode 100644 include/configs/spear-common.h create mode 100755 include/configs/spear6xx.h diff --git a/MAKEALL b/MAKEALL index dd635bd..342ae96 100755 --- a/MAKEALL +++ b/MAKEALL @@ -574,6 +574,7 @@ LIST_ARM9=" \ sheevaplug \ smdk2400 \ smdk2410 \ + spear600 \ trab \ VCMA9 \ versatile \ diff --git a/Makefile b/Makefile index 2403ad9..193d0bb 100644 --- a/Makefile +++ b/Makefile @@ -3036,6 +3036,9 @@ smdk2400_config : unconfig smdk2410_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0 +spear600_config : unconfig + @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx arm arm926ejs $(@:_config=) spear spear + SX1_stdout_serial_config \ SX1_config: unconfig @mkdir -p $(obj)include diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile new file mode 100644 index 0000000..4f8959f --- /dev/null +++ b/board/spear/common/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS := spr_misc.o +SOBJS := spr_lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/common/spr_lowlevel_init.S b/board/spear/common/spr_lowlevel_init.S new file mode 100755 index 0000000..6fbe579 --- /dev/null +++ b/board/spear/common/spr_lowlevel_init.S @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2006 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * platform specific initializations are already done in Xloader + * Initializations already done include + * DDR, PLLs, IP's clock enable and reset release etc + */ +.globl lowlevel_init +lowlevel_init: + /* By default, U-Boot switches CPU to low-vector */ + /* Revert this as we work in high vector even in U-Boot */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00002000 + mcr p15, 0, r0, c1, c0, 0 + mov pc, lr + +/* void setfreq(unsigned int device, unsigned int frequency) */ +.global setfreq +setfreq: + stmfd sp!,{r14} + stmfd sp!,{r0-r12} + + mov r8,sp + ldr sp,SRAM_STACK_V + + /* Saving the function arguements for later use */ + mov r4,r0 + mov r5,r1 + + /* Putting DDR into self refresh */ + ldr r0,DDR_07_V + ldr r1,[r0] + ldr r2,DDR_ACTIVE_V + bic r1, r1, r2 + str r1,[r0] + ldr r0,DDR_57_V + ldr r1,[r0] + ldr r2,CYCLES_MASK_V + bic r1, r1, r2 + ldr r2,REFRESH_CYCLES_V + orr r1, r1, r2, lsl #16 + str r1,[r0] + ldr r0,DDR_07_V + ldr r1,[r0] + ldr r2,SREFRESH_MASK_V + orr r1, r1, r2 + str r1,[r0] + + /* flush pipeline */ + b flush + .align 5 +flush: + /* Delay to ensure self refresh mode */ + ldr r0,SREFRESH_DELAY_V +delay: + sub r0,r0,#1 + cmp r0,#0 + bne delay + + /* Putting system in slow mode */ + ldr r0,SCCTRL_V + mov r1,#2 + str r1,[r0] + + /* Changing PLL(1/2) frequency */ + mov r0,r4 + mov r1,r5 + + cmp r4,#0 + beq pll1_freq + + /* Change PLL2 (DDR frequency) */ + ldr r6,PLL2_FREQ_V + ldr r7,PLL2_CNTL_V + b pll2_freq + +pll1_freq: + /* Change PLL1 (CPU frequency) */ + ldr r6,PLL1_FREQ_V + ldr r7,PLL1_CNTL_V + +pll2_freq: + mov r0,r6 + ldr r1,[r0] + ldr r2,PLLFREQ_MASK_V + bic r1,r1,r2 + mov r2,r5,lsr#1 + orr r1,r1,r2,lsl#24 + str r1,[r0] + + mov r0,r7 + ldr r1,P1C0A_V + str r1,[r0] + ldr r1,P1C0E_V + str r1,[r0] + ldr r1,P1C06_V + str r1,[r0] + ldr r1,P1C0E_V + str r1,[r0] + +lock: + ldr r1,[r0] + and r1,r1,#1 + cmp r1,#0 + beq lock + + /* Putting system back to normal mode */ + ldr r0,SCCTRL_V + mov r1,#4 + str r1,[r0] + + /* Putting DDR back to normal */ + ldr r0,DDR_07_V + ldr r1,[R0] + ldr r2,SREFRESH_MASK_V + bic r1, r1, r2 + str r1,[r0] + ldr r2,DDR_ACTIVE_V + orr r1, r1, r2 + str r1,[r0] + + /* Delay to ensure self refresh mode */ + ldr r0,SREFRESH_DELAY_V +1: + sub r0,r0,#1 + cmp r0,#0 + bne 1b + + mov sp,r8 + /* Resuming back to code */ + ldmia sp!,{r0-r12} + ldmia sp!,{pc} + +SCCTRL_V: + .word 0xfca00000 +PLL1_FREQ_V: + .word 0xfca8000C +PLL1_CNTL_V: + .word 0xfca80008 +PLL2_FREQ_V: + .word 0xfca80018 +PLL2_CNTL_V: + .word 0xfca80014 +PLLFREQ_MASK_V: + .word 0xff000000 +P1C0A_V: + .word 0x1C0A +P1C0E_V: + .word 0x1C0E +P1C06_V: + .word 0x1C06 + +SREFRESH_DELAY_V: + .word 0x9999 +SRAM_STACK_V: + .word 0xD2800600 +DDR_07_V: + .word 0xfc60001c +DDR_ACTIVE_V: + .word 0x01000000 +DDR_57_V: + .word 0xfc6000e4 +CYCLES_MASK_V: + .word 0xffff0000 +REFRESH_CYCLES_V: + .word 0xf0f0 +SREFRESH_MASK_V: + .word 0x00010000 + +.global setfreq_sz +setfreq_sz: + .word setfreq_sz - setfreq diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c new file mode 100755 index 0000000..dfa3ece --- /dev/null +++ b/board/spear/common/spr_misc.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define CPU 0 +#define DDR 1 +#define SRAM_REL 0xD2801000 + +DECLARE_GLOBAL_DATA_PTR; +static struct chip_data chip_data; + +int dram_init(void) +{ + struct xloader_table *xloader_tb = + (struct xloader_table *)XLOADER_TABLE_ADDRESS; + struct xloader_table_1_1 *table_1_1; + struct xloader_table_1_2 *table_1_2; + struct chip_data *chip = &chip_data; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1, + PHYS_SDRAM_1_MAXSIZE); + + if (XLOADER_TABLE_VERSION_1_1 == xloader_tb->table_version) { + table_1_1 = &xloader_tb->table.table_1_1; + chip->dramfreq = table_1_1->ddrfreq; + chip->dramtype = table_1_1->ddrtype; + + } else if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) { + table_1_2 = &xloader_tb->table.table_1_2; + chip->dramfreq = table_1_2->ddrfreq; + chip->dramtype = table_1_2->ddrtype; + } else { + chip->dramfreq = -1; + } + + return 0; +} + +int misc_init_r(void) +{ + setenv("verify", "n"); + +#if defined(CONFIG_SPEAR_USBTTY) + setenv("stdin", "usbtty"); + setenv("stdout", "usbtty"); + setenv("stderr", "usbtty"); +#endif + return 0; +} + +int spear_board_init(ulong mach_type) +{ + struct xloader_table *xloader_tb = + (struct xloader_table *)XLOADER_TABLE_ADDRESS; + struct xloader_table_1_2 *table_1_2; + struct chip_data *chip = &chip_data; + + gd->bd->bi_arch_number = mach_type; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR; + + /* CPU is initialized to work at 333MHz in Xloader */ + chip->cpufreq = 333; + + if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) { + table_1_2 = &xloader_tb->table.table_1_2; + memcpy(chip->version, table_1_2->version, + sizeof(chip->version)); + } + + return 0; +} + +int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + void (*sram_setfreq) (unsigned int, unsigned int); + struct chip_data *chip = &chip_data; + unsigned char mac[6]; + unsigned int frequency; + + if ((argc > 3) || (argc < 2)) { + cmd_usage(cmdtp); + return 1; + } + + if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) { + + frequency = simple_strtoul(argv[2], NULL, 0); + + if (frequency > 333) { + printf("Frequency is limited to 333MHz\n"); + return 1; + } + + sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz); + + if (!strcmp(argv[1], "cpufreq")) { + sram_setfreq(CPU, frequency); + printf("CPU frequency changed to %u\n", frequency); + + chip->cpufreq = frequency; + } else { + sram_setfreq(DDR, frequency); + printf("DDR frequency changed to %u\n", frequency); + + chip->dramfreq = frequency; + } + + return 0; + } else if (!strcmp(argv[1], "print")) { + + if (chip->cpufreq == -1) + printf("CPU Freq = Not Known\n"); + else + printf("CPU Freq = %d MHz\n", chip->cpufreq); + + if (chip->dramfreq == -1) + printf("DDR Freq = Not Known\n"); + else + printf("DDR Freq = %d MHz\n", chip->dramfreq); + + if (chip->dramtype == DDRMOBILE) + printf("DDR Type = MOBILE\n"); + else if (chip->dramtype == DDR2) + printf("DDR Type = DDR2\n"); + else + printf("DDR Type = Not Known\n"); + + printf("Xloader Rev = %s\n", chip->version); + + return 0; + } + + cmd_usage(cmdtp); + return 1; +} + +U_BOOT_CMD(chip_config, 3, 1, do_chip_config, + "configure chip", + "chip_config cpufreq/ddrfreq frequency\n" + "chip_config print"); diff --git a/board/spear/spear600/Makefile b/board/spear/spear600/Makefile new file mode 100755 index 0000000..1978002 --- /dev/null +++ b/board/spear/spear600/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := spear600.o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk new file mode 100755 index 0000000..35646f2 --- /dev/null +++ b/board/spear/spear600/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2009 +# Vipin Kumar, ST Microelectronics +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +TEXT_BASE = 0x00700000 + +ALL += $(obj)u-boot.img + +# Environment variables in NAND +ifeq ($(ENV),NAND) +PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND +else +PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH +endif + +ifeq ($(CONSOLE),USB) +PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY +endif diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c new file mode 100755 index 0000000..eef9a37 --- /dev/null +++ b/board/spear/spear600/spear600.c @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +int board_init(void) +{ + return spear_board_init(MACH_TYPE_SPEAR600); +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +int board_nand_init(struct nand_chip *nand) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) + return spear_nand_init(nand); + + return -1; +} diff --git a/include/asm-arm/arch-spear/spr_defs.h b/include/asm-arm/arch-spear/spr_defs.h new file mode 100644 index 0000000..9dde54a --- /dev/null +++ b/include/asm-arm/arch-spear/spr_defs.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPR_DEFS_H__ +#define __SPR_DEFS_H__ + +extern int spear_board_init(ulong); +extern void setfreq(unsigned int, unsigned int); +extern unsigned int setfreq_sz; + +struct chip_data { + int cpufreq; + int dramfreq; + int dramtype; + uchar version[32]; +}; + +#endif diff --git a/include/asm-arm/arch-spear/spr_xloader_table.h b/include/asm-arm/arch-spear/spr_xloader_table.h new file mode 100755 index 0000000..7e3da18 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_xloader_table.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_XLOADER_TABLE_H +#define _SPR_XLOADER_TABLE_H + +#define XLOADER_TABLE_VERSION_1_1 2 +#define XLOADER_TABLE_VERSION_1_2 3 + +#define XLOADER_TABLE_ADDRESS 0xD2801FF0 + +#define DDRMOBILE 1 +#define DDR2 2 + +#define REV_BA 1 +#define REV_AA 2 +#define REV_AB 3 + +struct xloader_table_1_1 { + unsigned short ddrfreq; + unsigned char ddrsize; + unsigned char ddrtype; + + unsigned char soc_rev; +} __attribute__ ((packed)); + +struct xloader_table_1_2 { + unsigned const char *version; + + unsigned short ddrfreq; + unsigned char ddrsize; + unsigned char ddrtype; + + unsigned char soc_rev; +} __attribute__ ((packed)); + +union table_contents { + struct xloader_table_1_1 table_1_1; + struct xloader_table_1_2 table_1_2; +}; + +struct xloader_table { + unsigned char table_version; + union table_contents table; +} __attribute__ ((packed)); + +#endif diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h new file mode 100644 index 0000000..cc52e39 --- /dev/null +++ b/include/configs/spear-common.h @@ -0,0 +1,213 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPEAR_COMMON_H +#define _SPEAR_COMMON_H +/* + * Common configurations used for both spear3xx as well as spear6xx + */ + +/* USBD driver configuration */ +#define CONFIG_SPEARUDC +#define CONFIG_USB_DEVICE +#define CONFIG_USB_TTY + +#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" +#define CONFIG_USBD_MANUFACTURER "ST Microelectronics" + +#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" + +/* I2C driver configuration */ +#define CONFIG_HARD_I2C +#define CONFIG_SPEAR_I2C +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x02 + +#define CONFIG_I2C_CHIPADDRESS 0x50 + +/* Timer, HZ specific defines */ +#define CONFIG_SYS_HZ (1000) +#define CONFIG_SYS_HZ_CLOCK (8300000) + +/* Flash configuration */ +#if defined(CONFIG_FLASH_PNOR) +#define CONFIG_SPEAR_EMI 1 +#else +#define CONFIG_SPEARSMI 1 +#endif + +#if defined(CONFIG_SPEARSMI) + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BASE (0xF8000000) +#define CONFIG_SYS_CS1_FLASH_BASE (0xF9000000) +#define CONFIG_SYS_FLASH_BANK_SIZE (0x01000000) +#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) + +#endif + +/* + * Serial Configuration (PL011) + * CONFIG_PL01x_PORTS is defined in specific files + */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ + 57600, 115200 } + +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* NAND FLASH Configuration */ +#define CONFIG_NAND_SPEAR 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 + +/* + * Command support defines + */ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NAND +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVES + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +/* + * Default Environment Varible definitions + */ +#if defined(CONFIG_SPEAR_USBTTY) +#define CONFIG_BOOTDELAY -1 +#else +#define CONFIG_BOOTDELAY 1 +#endif + +#define CONFIG_ENV_OVERWRITE + +/* + * U-Boot Environment placing definitions. + */ +#if defined(CONFIG_ENV_IS_IN_FLASH) +#ifdef CONFIG_SPEARSMI +/* + * Environment is in serial NOR flash + */ +#define CONFIG_SYS_MONITOR_LEN 0x00040000 +#define CONFIG_ENV_SECT_SIZE 0x00010000 +#define CONFIG_FSMTDBLK "/dev/mtdblock8 " + +#define CONFIG_BOOTCOMMAND "bootm 0xf8050000" + +#elif defined(CONFIG_SPEAR_EMI) +/* + * Environment is in parallel NOR flash + */ +#define CONFIG_SYS_MONITOR_LEN 0x00060000 +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#define CONFIG_FSMTDBLK "/dev/mtdblock3 " + +#define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 " \ + "0x4C0000; bootm 0x1600000" +#endif + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#elif defined(CONFIG_ENV_IS_IN_NAND) +/* + * Environment is in NAND + */ + +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_RANGE 0x10000 +#define CONFIG_FSMTDBLK "/dev/mtdblock12 " + +#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \ + "0x80000 0x4C0000; " \ + "bootm 0x1600000" +#endif + +#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \ + "console=ttyS0 init=/bin/sh" +#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \ + "root="CONFIG_FSMTDBLK \ + "rootfstype=jffs2" + +#define CONFIG_ENV_SIZE 0x02000 + +/* Miscellaneous configurable options */ +#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_PROMPT \ + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay + +#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x04000000 +#define CONFIG_SYS_MALLOC_LEN (1024*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_IDENT_STRING "-SPEAr" +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "u-boot> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 +#define CONFIG_SYS_64BIT_VSPRINTF 1 + +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY + +/* Stack sizes */ +#define CONFIG_STACKSIZE (128*1024) + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) +#define CONFIG_STACKSIZE_FIQ (4*1024) +#endif + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_MAXSIZE 0x40000000 + +#endif diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx.h new file mode 100755 index 0000000..2ad5beb --- /dev/null +++ b/include/configs/spear6xx.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SPEAR600 1 + +#include + +/* Serial Configuration (PL011) */ +#define CONFIG_SYS_SERIAL0 0xD0000000 +#define CONFIG_SYS_SERIAL1 0xD0080000 +#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1 } + +#define CONFIG_SYS_NAND_BASE (0xD2000000) + +#endif /* __CONFIG_H */ -- cgit v1.1 From f92994f0f7403b84366ce04e554e461f624e6868 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Fri, 15 Jan 2010 19:15:49 +0530 Subject: SPEAr : Support for HW mac id read/write from i2c mem This patch adds the support to read and write mac id from i2c memory. For reading: if (env contains ethaddr) pick env ethaddr else pick ethaddr from i2c memory For writing: chip_config ethaddr XX:XX:XX:XX:XX:XX writes the mac id in i2c memory Signed-off-by: Vipin --- board/spear/common/spr_misc.c | 68 ++++++++++++++++++++++++++++++++++- include/asm-arm/arch-spear/spr_defs.h | 8 +++++ 2 files changed, 75 insertions(+), 1 deletion(-) diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index dfa3ece..204ccf2 100755 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -67,6 +67,12 @@ int dram_init(void) int misc_init_r(void) { +#if defined(CONFIG_CMD_NET) + uchar mac_id[6]; + + if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id)) + eth_setenv_enetaddr("ethaddr", mac_id); +#endif setenv("verify", "n"); #if defined(CONFIG_SPEAR_USBTTY) @@ -101,12 +107,54 @@ int spear_board_init(ulong mach_type) return 0; } +static int i2c_read_mac(uchar *buffer) +{ + u8 buf[2]; + + i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); + + /* Check if mac in i2c memory is valid */ + if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) { + /* Valid mac address is saved in i2c eeprom */ + i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN); + return 0; + } + + return -1; +} + +static int write_mac(uchar *mac) +{ + u8 buf[2]; + + buf[0] = (u8)MAGIC_BYTE0; + buf[1] = (u8)MAGIC_BYTE1; + i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); + + buf[0] = (u8)~MAGIC_BYTE0; + buf[1] = (u8)~MAGIC_BYTE1; + + i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); + + /* check if valid MAC address is saved in I2C EEPROM or not? */ + if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) { + i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN); + puts("I2C EEPROM written with mac address \n"); + return 0; + } + + puts("I2C EEPROM writing failed \n"); + return -1; +} + int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { void (*sram_setfreq) (unsigned int, unsigned int); struct chip_data *chip = &chip_data; unsigned char mac[6]; - unsigned int frequency; + unsigned int reg, frequency; + char *s, *e; + char i2c_mac[20]; if ((argc > 3) || (argc < 2)) { cmd_usage(cmdtp); @@ -137,6 +185,17 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } return 0; + } else if (!strcmp(argv[1], "ethaddr")) { + + s = argv[2]; + for (reg = 0; reg < 6; ++reg) { + mac[reg] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + write_mac(mac); + + return 0; } else if (!strcmp(argv[1], "print")) { if (chip->cpufreq == -1) @@ -156,6 +215,13 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else printf("DDR Type = Not Known\n"); + if (!i2c_read_mac(mac)) { + sprintf(i2c_mac, "%pM", mac); + printf("Ethaddr (from i2c mem) = %s\n", i2c_mac); + } else { + printf("Ethaddr (from i2c mem) = Not set\n"); + } + printf("Xloader Rev = %s\n", chip->version); return 0; diff --git a/include/asm-arm/arch-spear/spr_defs.h b/include/asm-arm/arch-spear/spr_defs.h index 9dde54a..fa8412c 100644 --- a/include/asm-arm/arch-spear/spr_defs.h +++ b/include/asm-arm/arch-spear/spr_defs.h @@ -35,4 +35,12 @@ struct chip_data { uchar version[32]; }; +/* HW mac id in i2c memory definitions */ +#define MAGIC_OFF 0x0 +#define MAGIC_LEN 0x2 +#define MAGIC_BYTE0 0x55 +#define MAGIC_BYTE1 0xAA +#define MAC_OFF 0x2 +#define MAC_LEN 0x6 + #endif -- cgit v1.1 From 7e074158ce239380259c5fc97e87be2896169973 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Fri, 15 Jan 2010 19:15:50 +0530 Subject: SPEAr : Support added for SPEAr300 board SPEAr300 SoC support contains basic spear300 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver Signed-off-by: Vipin --- MAKEALL | 1 + Makefile | 3 +++ board/spear/spear300/Makefile | 51 ++++++++++++++++++++++++++++++++++++ board/spear/spear300/config.mk | 39 +++++++++++++++++++++++++++ board/spear/spear300/spear300.c | 58 +++++++++++++++++++++++++++++++++++++++++ include/configs/spear3xx.h | 42 +++++++++++++++++++++++++++++ 6 files changed, 194 insertions(+) create mode 100755 board/spear/spear300/Makefile create mode 100755 board/spear/spear300/config.mk create mode 100755 board/spear/spear300/spear300.c create mode 100755 include/configs/spear3xx.h diff --git a/MAKEALL b/MAKEALL index 342ae96..deeebd9 100755 --- a/MAKEALL +++ b/MAKEALL @@ -574,6 +574,7 @@ LIST_ARM9=" \ sheevaplug \ smdk2400 \ smdk2410 \ + spear300 \ spear600 \ trab \ VCMA9 \ diff --git a/Makefile b/Makefile index 193d0bb..ca863d1 100644 --- a/Makefile +++ b/Makefile @@ -3036,6 +3036,9 @@ smdk2400_config : unconfig smdk2410_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0 +spear300_config : unconfig + @$(MKCONFIG) -n $@ -t $(@:_config=) spear3xx arm arm926ejs $(@:_config=) spear spear + spear600_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx arm arm926ejs $(@:_config=) spear spear diff --git a/board/spear/spear300/Makefile b/board/spear/spear300/Makefile new file mode 100755 index 0000000..b5168ff --- /dev/null +++ b/board/spear/spear300/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := spear300.o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/spear300/config.mk b/board/spear/spear300/config.mk new file mode 100755 index 0000000..35646f2 --- /dev/null +++ b/board/spear/spear300/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2009 +# Vipin Kumar, ST Microelectronics +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +TEXT_BASE = 0x00700000 + +ALL += $(obj)u-boot.img + +# Environment variables in NAND +ifeq ($(ENV),NAND) +PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND +else +PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH +endif + +ifeq ($(CONSOLE),USB) +PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY +endif diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c new file mode 100755 index 0000000..60ee544 --- /dev/null +++ b/board/spear/spear300/spear300.c @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +int board_init(void) +{ + return spear_board_init(MACH_TYPE_SPEAR300); +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +int board_nand_init(struct nand_chip *nand) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG30) || + ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG31)) { + + return spear_nand_init(nand); + } + + return -1; +} diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h new file mode 100755 index 0000000..012a840 --- /dev/null +++ b/include/configs/spear3xx.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SPEAR300 1 +#define CONFIG_SPEAR3XX 1 + +#include + +/* Serial Configuration (PL011) */ +#define CONFIG_SYS_SERIAL0 0xD0000000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} + +#define CONFIG_SYS_NAND_BASE (0x80000000) + +#endif /* __CONFIG_H */ -- cgit v1.1 From 4bfacad4e796f2e121ee7432705ecc9c61e7b6ca Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Fri, 15 Jan 2010 19:15:51 +0530 Subject: SPEAr : emi controller initialization for CFI driver support SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface Paraller NOR flashes. This patch adds the support for this IP The standard CFI driver is used to interface with NOR flashes Signed-off-by: Vipin --- board/spear/common/spr_misc.c | 59 ++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_emi.h | 54 +++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 include/asm-arm/arch-spear/spr_emi.h diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 204ccf2..e356912 100755 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -83,6 +84,61 @@ int misc_init_r(void) return 0; } +#ifdef CONFIG_SPEAR_EMI +struct cust_emi_para { + unsigned int tap; + unsigned int tsdp; + unsigned int tdpw; + unsigned int tdpr; + unsigned int tdcs; +}; + +/* EMI timing setting of m28w640hc of linux kernel */ +const struct cust_emi_para emi_timing_m28w640hc = { + .tap = 0x10, + .tsdp = 0x05, + .tdpw = 0x0a, + .tdpr = 0x0a, + .tdcs = 0x05, +}; + +/* EMI timing setting of bootrom */ +const struct cust_emi_para emi_timing_bootrom = { + .tap = 0xf, + .tsdp = 0x0, + .tdpw = 0xff, + .tdpr = 0x111, + .tdcs = 0x02, +}; + +void spear_emi_init(void) +{ + const struct cust_emi_para *p = &emi_timing_m28w640hc; + struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE; + unsigned int cs; + unsigned int val, tmp; + + val = readl(CONFIG_SPEAR_RASBASE); + + if (val & EMI_ACKMSK) + tmp = 0x3f; + else + tmp = 0x0; + + writel(tmp, &emi_regs_p->ack); + + for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) { + writel(p->tap, &emi_regs_p->bank_regs[cs].tap); + writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp); + writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw); + writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr); + writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs); + writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3), + &emi_regs_p->bank_regs[cs].control); + } +} +#endif + int spear_board_init(ulong mach_type) { struct xloader_table *xloader_tb = @@ -104,6 +160,9 @@ int spear_board_init(ulong mach_type) sizeof(chip->version)); } +#ifdef CONFIG_SPEAR_EMI + spear_emi_init(); +#endif return 0; } diff --git a/include/asm-arm/arch-spear/spr_emi.h b/include/asm-arm/arch-spear/spr_emi.h new file mode 100644 index 0000000..c1f1c2a --- /dev/null +++ b/include/asm-arm/arch-spear/spr_emi.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2009 + * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPEAR_EMI_H__ +#define __SPEAR_EMI_H__ + +#ifdef CONFIG_SPEAR_EMI + +struct emi_bank_regs { + u32 tap; + u32 tsdp; + u32 tdpw; + u32 tdpr; + u32 tdcs; + u32 control; +}; + +struct emi_regs { + struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS]; + u32 tout; + u32 ack; + u32 irq; +}; + +#define EMI_ACKMSK 0x40 + +/* control register definitions */ +#define EMI_CNTL_ENBBYTEW (1 << 2) +#define EMI_CNTL_ENBBYTER (1 << 3) +#define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW) + +#endif + +#endif -- cgit v1.1 From 080cfee71459588fd6312e475bb5115bdbda1cb3 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Fri, 15 Jan 2010 19:15:52 +0530 Subject: SPEAr : Support added for SPEAr310 board SPEAr310 SoC support contains basic spear310 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver - emi driver(cfi support) Signed-off-by: Vipin --- MAKEALL | 1 + Makefile | 3 ++- board/spear/spear310/Makefile | 51 +++++++++++++++++++++++++++++++++++ board/spear/spear310/config.mk | 44 ++++++++++++++++++++++++++++++ board/spear/spear310/spear310.c | 59 ++++++++++++++++++++++++++++++++++++++++ include/configs/spear3xx.h | 60 +++++++++++++++++++++++++++++++++++++++++ 6 files changed, 217 insertions(+), 1 deletion(-) create mode 100755 board/spear/spear310/Makefile create mode 100755 board/spear/spear310/config.mk create mode 100755 board/spear/spear310/spear310.c diff --git a/MAKEALL b/MAKEALL index deeebd9..263081a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -575,6 +575,7 @@ LIST_ARM9=" \ smdk2400 \ smdk2410 \ spear300 \ + spear310 \ spear600 \ trab \ VCMA9 \ diff --git a/Makefile b/Makefile index ca863d1..0cb4b05 100644 --- a/Makefile +++ b/Makefile @@ -3036,7 +3036,8 @@ smdk2400_config : unconfig smdk2410_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0 -spear300_config : unconfig +spear300_config \ +spear310_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear3xx arm arm926ejs $(@:_config=) spear spear spear600_config : unconfig diff --git a/board/spear/spear310/Makefile b/board/spear/spear310/Makefile new file mode 100755 index 0000000..e67e941 --- /dev/null +++ b/board/spear/spear310/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := spear310.o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/spear310/config.mk b/board/spear/spear310/config.mk new file mode 100755 index 0000000..cba8436 --- /dev/null +++ b/board/spear/spear310/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2009 +# Vipin Kumar, ST Microelectronics +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +TEXT_BASE = 0x00700000 + +ALL += $(obj)u-boot.img + +# Environment variables in NAND +ifeq ($(ENV),NAND) +PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND +else +PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH +endif + +# Support parallel flash +ifeq ($(FLASH),PNOR) +PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR +endif + +ifeq ($(CONSOLE),USB) +PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY +endif diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c new file mode 100755 index 0000000..756aa56 --- /dev/null +++ b/board/spear/spear310/spear310.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2009 + * Ryan Chen, ST Micoelectronics, ryan.chen@st.com. + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +int board_init(void) +{ + return spear_board_init(MACH_TYPE_SPEAR300); +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +int board_nand_init(struct nand_chip *nand) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG30) || + ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG31)) { + + return spear_nand_init(nand); + } + + return -1; +} diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index 012a840..d25f12a 100755 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -28,15 +28,75 @@ * High Level Configuration Options * (easy to change) */ +#if defined(CONFIG_MK_spear300) +#define CONFIG_SPEAR3XX 1 #define CONFIG_SPEAR300 1 +#elif defined(CONFIG_MK_spear310) #define CONFIG_SPEAR3XX 1 +#define CONFIG_SPEAR310 1 +#endif #include /* Serial Configuration (PL011) */ #define CONFIG_SYS_SERIAL0 0xD0000000 + +#if defined(CONFIG_SPEAR300) #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} +#elif defined(CONFIG_SPEAR310) + +#if (CONFIG_CONS_INDEX) +#undef CONFIG_PL011_CLOCK +#define CONFIG_PL011_CLOCK (83 * 1000 * 1000) +#endif + +#define CONFIG_SYS_SERIAL1 0xB2000000 +#define CONFIG_SYS_SERIAL2 0xB2080000 +#define CONFIG_SYS_SERIAL3 0xB2100000 +#define CONFIG_SYS_SERIAL4 0xB2180000 +#define CONFIG_SYS_SERIAL5 0xB2200000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2, \ + (void *)CONFIG_SYS_SERIAL3, \ + (void *)CONFIG_SYS_SERIAL4, \ + (void *)CONFIG_SYS_SERIAL5 } +#endif + +#if defined(CONFIG_SPEAR_EMI) + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +#if defined(CONFIG_SPEAR310) +#define CONFIG_SYS_FLASH_BASE 0x50000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0x60000000 +#define CONFIG_SYS_CS2_FLASH_BASE 0x70000000 +#define CONFIG_SYS_CS3_FLASH_BASE 0x80000000 +#define CONFIG_SYS_CS4_FLASH_BASE 0x90000000 +#define CONFIG_SYS_CS5_FLASH_BASE 0xA0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE, \ + CONFIG_SYS_CS2_FLASH_BASE, \ + CONFIG_SYS_CS3_FLASH_BASE, \ + CONFIG_SYS_CS4_FLASH_BASE, \ + CONFIG_SYS_CS5_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 6 + +#endif + +#define CONFIG_SYS_MAX_FLASH_SECT (127 + 8) +#define CONFIG_SYS_FLASH_QUIET_TEST 1 + +#endif + +#if defined(CONFIG_SPEAR300) #define CONFIG_SYS_NAND_BASE (0x80000000) +#elif defined(CONFIG_SPEAR310) +#define CONFIG_SYS_NAND_BASE (0x40000000) + +#endif + #endif /* __CONFIG_H */ -- cgit v1.1 From 7da692360414d07027c6cf564a15d79cd9dcf488 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Fri, 15 Jan 2010 19:15:53 +0530 Subject: SPEAr : Support added for SPEAr320 board SPEAr320 SoC support contains basic spear320 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver - emi driver(cfi support) Signed-off-by: Vipin --- MAKEALL | 1 + Makefile | 3 ++- board/spear/spear320/Makefile | 51 +++++++++++++++++++++++++++++++++++ board/spear/spear320/config.mk | 44 ++++++++++++++++++++++++++++++ board/spear/spear320/spear320.c | 59 +++++++++++++++++++++++++++++++++++++++++ include/configs/spear3xx.h | 29 ++++++++++++++++++++ 6 files changed, 186 insertions(+), 1 deletion(-) create mode 100755 board/spear/spear320/Makefile create mode 100755 board/spear/spear320/config.mk create mode 100755 board/spear/spear320/spear320.c diff --git a/MAKEALL b/MAKEALL index 263081a..afdc1b5 100755 --- a/MAKEALL +++ b/MAKEALL @@ -576,6 +576,7 @@ LIST_ARM9=" \ smdk2410 \ spear300 \ spear310 \ + spear320 \ spear600 \ trab \ VCMA9 \ diff --git a/Makefile b/Makefile index 0cb4b05..0f60925 100644 --- a/Makefile +++ b/Makefile @@ -3037,7 +3037,8 @@ smdk2410_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0 spear300_config \ -spear310_config : unconfig +spear310_config \ +spear320_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear3xx arm arm926ejs $(@:_config=) spear spear spear600_config : unconfig diff --git a/board/spear/spear320/Makefile b/board/spear/spear320/Makefile new file mode 100755 index 0000000..1b80586 --- /dev/null +++ b/board/spear/spear320/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := spear320.o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk new file mode 100755 index 0000000..cba8436 --- /dev/null +++ b/board/spear/spear320/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2009 +# Vipin Kumar, ST Microelectronics +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +TEXT_BASE = 0x00700000 + +ALL += $(obj)u-boot.img + +# Environment variables in NAND +ifeq ($(ENV),NAND) +PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND +else +PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH +endif + +# Support parallel flash +ifeq ($(FLASH),PNOR) +PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR +endif + +ifeq ($(CONSOLE),USB) +PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY +endif diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c new file mode 100755 index 0000000..756aa56 --- /dev/null +++ b/board/spear/spear320/spear320.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2009 + * Ryan Chen, ST Micoelectronics, ryan.chen@st.com. + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +int board_init(void) +{ + return spear_board_init(MACH_TYPE_SPEAR300); +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +int board_nand_init(struct nand_chip *nand) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG30) || + ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG31)) { + + return spear_nand_init(nand); + } + + return -1; +} diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index d25f12a..0248aba 100755 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -34,6 +34,9 @@ #elif defined(CONFIG_MK_spear310) #define CONFIG_SPEAR3XX 1 #define CONFIG_SPEAR310 1 +#elif defined(CONFIG_MK_spear320) +#define CONFIG_SPEAR3XX 1 +#define CONFIG_SPEAR320 1 #endif #include @@ -62,6 +65,18 @@ (void *)CONFIG_SYS_SERIAL3, \ (void *)CONFIG_SYS_SERIAL4, \ (void *)CONFIG_SYS_SERIAL5 } +#elif defined(CONFIG_SPEAR320) + +#if (CONFIG_CONS_INDEX) +#undef CONFIG_PL011_CLOCK +#define CONFIG_PL011_CLOCK (83 * 1000 * 1000) +#endif + +#define CONFIG_SYS_SERIAL1 0xA3000000 +#define CONFIG_SYS_SERIAL2 0xA4000000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2 } #endif #if defined(CONFIG_SPEAR_EMI) @@ -84,6 +99,17 @@ CONFIG_SYS_CS5_FLASH_BASE } #define CONFIG_SYS_MAX_FLASH_BANKS 6 +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_FLASH_BASE 0x44000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0x45000000 +#define CONFIG_SYS_CS2_FLASH_BASE 0x46000000 +#define CONFIG_SYS_CS3_FLASH_BASE 0x47000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE, \ + CONFIG_SYS_CS2_FLASH_BASE, \ + CONFIG_SYS_CS3_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 4 + #endif #define CONFIG_SYS_MAX_FLASH_SECT (127 + 8) @@ -97,6 +123,9 @@ #elif defined(CONFIG_SPEAR310) #define CONFIG_SYS_NAND_BASE (0x40000000) +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_NAND_BASE (0x50000000) + #endif #endif /* __CONFIG_H */ -- cgit v1.1 From a3f3897bfda9b4729785bdd328b3b7f30417a67f Mon Sep 17 00:00:00 2001 From: Daniel Gorsulowski Date: Wed, 20 Jan 2010 08:00:11 +0100 Subject: at91: Enable slow master clock on meesc board Normally the processor clock has a divisor of 2. In some cases this this needs to be set to 4. Check the user has set environment mdiv to 4 to change the divisor. Signed-off-by: Daniel Gorsulowski --- board/esd/meesc/meesc.c | 26 ++++++++++++++++++++++++++ include/configs/meesc.h | 1 + 2 files changed, 27 insertions(+) diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index efba60d..a1b66cb 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -219,6 +219,32 @@ u32 get_board_rev(void) } #endif +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + char *str; + char buf[32]; + + /* + * Normally the processor clock has a divisor of 2. + * In some cases this this needs to be set to 4. + * Check the user has set environment mdiv to 4 to change the divisor. + */ + if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) { + at91_sys_write(AT91_PMC_MCKR, + (at91_sys_read(AT91_PMC_MCKR) & ~AT91_PMC_MDIV) | + AT91SAM9_PMC_MDIV_4); + at91_clock_init(0); + serial_setbrg(); + /* Notify the user that the clock is not default */ + printf("Setting master clock to %s MHz\n", + strmhz(buf, get_mck_clk_rate())); + } + + return 0; +} +#endif /* CONFIG_MISC_INIT_R */ + int board_init(void) { /* Peripheral Clock Enable Register */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index ab5cbca..c3255fa 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -48,6 +48,7 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_MISC_INIT_R /* Call misc_init_r */ #define CONFIG_ARCH_CPU_INIT -- cgit v1.1 From 82826d5422331e9c99e5408dcf0348c8e0c257a6 Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Fri, 22 Jan 2010 14:47:59 +0100 Subject: mpc512x: Add display of reset status register Content of the RSR is put into gd early so we can output it together with the CPU info. The clearing of gd in board_init_f is redundant for this architecture as it is done in cpu_init_f so we remove it. Signed-off-by: Detlev Zundel --- cpu/mpc512x/cpu.c | 5 +++-- lib_ppc/board.c | 7 ++++--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index f96a4c8..09cbd20 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -66,9 +66,10 @@ int checkcpu (void) default: puts ("unknown "); } - printf ("at %s MHz, CSB at %s MHz\n", + printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n", strmhz(buf1, clock), - strmhz(buf2, gd->csb_clk) ); + strmhz(buf2, gd->csb_clk), + gd->reset_status & 0xffff); return 0; } diff --git a/lib_ppc/board.c b/lib_ppc/board.c index dd22f99..2889b2c 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2006 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -378,8 +378,9 @@ void board_init_f (ulong bootflag) /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); -#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83xx) && \ - !defined(CONFIG_MPC85xx) && !defined(CONFIG_MPC86xx) +#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \ + !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \ + !defined(CONFIG_MPC86xx) /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); #endif -- cgit v1.1 From a21fb981d533ac6d323a01c7fa2cda20f2d36de5 Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Wed, 20 Jan 2010 14:28:48 +0100 Subject: mpc5xxx: Support CPU internal watchdog. Signed-off-by: Detlev Zundel --- cpu/mpc5xxx/cpu.c | 20 +++++++++++++++++++- cpu/mpc5xxx/cpu_init.c | 14 +++++++++++++- include/watchdog.h | 5 +++++ 3 files changed, 37 insertions(+), 2 deletions(-) diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 2a28df4..edfb828 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2003 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -192,3 +192,21 @@ int cpu_eth_init(bd_t *bis) return mpc5xxx_fec_initialize(bis); } #endif + +#if defined(CONFIG_WATCHDOG) +void watchdog_reset(void) +{ + int re_enable = disable_interrupts(); + reset_5xxx_watchdog(); + if (re_enable) enable_interrupts(); +} + +void reset_5xxx_watchdog(void) +{ + volatile struct mpc5xxx_gpt *gpt0 = + (struct mpc5xxx_gpt *) MPC5XXX_GPT; + + /* Trigger TIMER_0 by writing A5 to OCPW */ + clrsetbits_be32(&gpt0->emsr, 0xff000000, 0xa5000000); +} +#endif /* CONFIG_WATCHDOG */ diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c index acff5f5..b151464 100644 --- a/cpu/mpc5xxx/cpu_init.c +++ b/cpu/mpc5xxx/cpu_init.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2009 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -24,6 +24,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -45,6 +46,8 @@ void cpu_init_f (void) (struct mpc5xxx_gpio *) MPC5XXX_GPIO; volatile struct mpc5xxx_xlb *xlb = (struct mpc5xxx_xlb *) MPC5XXX_XLBARB; + volatile struct mpc5xxx_gpt *gpt0 = + (struct mpc5xxx_gpt *) MPC5XXX_GPT; unsigned long addecr = (1 << 25); /* Boot_CS */ #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100) addecr |= (1 << 22); /* SDRAM enable */ @@ -206,6 +209,15 @@ void cpu_init_f (void) /* Enable piplining */ clrbits_be32(&xlb->config, (1 << 31)); # endif + +#if defined(CONFIG_WATCHDOG) + /* Charge the watchdog timer - prescaler = 64k, count = 64k*/ + out_be32(&gpt0->cir, 0x0000ffff); + out_be32(&gpt0->emsr, 0x9004); /* wden|ce|timer_ms */ + + reset_5xxx_watchdog(); +#endif /* CONFIG_WATCHDOG */ + #endif /* CONFIG_MPC5200 */ } diff --git a/include/watchdog.h b/include/watchdog.h index 9265be9..ef2f5aa 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -84,6 +84,11 @@ void reset_5xx_watchdog(volatile immap_t *immr); #endif +/* MPC 5xxx */ +#if defined(CONFIG_MPC5xxx) && !defined(__ASSEMBLY__) + void reset_5xxx_watchdog(void); +#endif + /* AMCC 4xx */ #if defined(CONFIG_4xx) && !defined(__ASSEMBLY__) void reset_4xx_watchdog(void); -- cgit v1.1 From 8edcde5e4e2e7f6bc7e277011fed71e64fd9d294 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 20 Jan 2010 18:19:10 +0100 Subject: mkimage: Add Freescale imx Boot Image support (imximage) This patch adds support for "imximage" (MX Boot Image) to the mkimage utility. The imximage is used on the Freescales's MX.25, MX.35 and MX.51 processors. Further details under doc/README.imximage. This patch was tested on a Freescale mx51evk board. Signed-off-by: Stefano Babic --- Makefile | 4 + common/image.c | 1 + doc/README.imximage | 188 ++++++++++++++++++++++++++++++ include/image.h | 1 + tools/Makefile | 2 + tools/imximage.c | 324 ++++++++++++++++++++++++++++++++++++++++++++++++++++ tools/imximage.h | 105 +++++++++++++++++ tools/mkimage.c | 2 + tools/mkimage.h | 1 + 9 files changed, 628 insertions(+) create mode 100644 doc/README.imximage create mode 100644 tools/imximage.c create mode 100644 tools/imximage.h diff --git a/Makefile b/Makefile index 0f60925..722b976 100644 --- a/Makefile +++ b/Makefile @@ -324,6 +324,10 @@ $(obj)u-boot.img: $(obj)u-boot.bin sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -d $< $@ +$(obj)u-boot.imx: $(obj)u-boot.bin + $(obj)tools/mkimage -n $(IMX_CONFIG) -T imximage \ + -e $(TEXT_BASE) -d $< $@ + $(obj)u-boot.kwb: $(obj)u-boot.bin $(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \ -a $(TEXT_BASE) -e $(TEXT_BASE) -d $< $@ diff --git a/common/image.c b/common/image.c index 82e7aa4..9e49713 100644 --- a/common/image.c +++ b/common/image.c @@ -140,6 +140,7 @@ static table_entry_t uimage_type[] = { { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, + { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, { -1, "", "", }, }; diff --git a/doc/README.imximage b/doc/README.imximage new file mode 100644 index 0000000..9048ef6 --- /dev/null +++ b/doc/README.imximage @@ -0,0 +1,188 @@ +--------------------------------------------- +Imximage Boot Image generation using mkimage +--------------------------------------------- + +This document describes how to set up a U-Boot image +that can be booted by Freescale MX25, MX35 and MX51 +processors via internal boot mode. + +These processors can boot directly from NAND, SPI flash and SD card flash +using its internal boot ROM support. They can boot from an internal +UART, if booting from device media fails. +Booting from NOR flash does not require to use this image type. + +For more details refer Chapter 2 - System Boot and section 2.14 +(flash header description) of the processor's manual. + +This implementation does not use at the moment the secure boot feature +of the processor. The image is generated disabling all security fields. + +Command syntax: +-------------- +./tools/mkimage -l + to list the imx image file details + +./tools/mkimage -T imximage \ + -n \ + -e -d + +For example, for the mx51evk board: +./tools/mkimage -n ./board/freescale/mx51evk/imximage.cfg \ + -T imximage -e 0x97800000 \ + -d u-boot.bin u-boot.imx + +You can generate directly the image when you compile u-boot with: + +$ make u-boot.imx + +The output image can be flashed on the board SPI flash or on a SD card. +In both cases, you have to copy the image at the offset required for the +chosen media devices (0x400 for both SPI flash or SD card). + +Please check Freescale documentation for further details. + +Board specific configuration file specifications: +------------------------------------------------- +1. This file must present in the $(BOARDDIR) and the name should be + imximage.cfg (since this is used in Makefile). +2. This file can have empty lines and lines starting with "#" as first + character to put comments. +3. This file can have configuration command lines as mentioned below, + any other information in this file is treated as invalid. + +Configuration command line syntax: +--------------------------------- +1. Each command line is must have two strings, first one command or address + and second one data string +2. Following are the valid command strings and associated data strings:- + Command string data string + -------------- ----------- + BOOT_FROM nand/spi/sd/onenand + Example: + BOOT_FROM spi + DATA type address value + + type: word=4, halfword=2, byte=1 + address: physycal register address + value: value to be set in register + All values are in in hexadecimal. + Example (write to IOMUXC): + DATA 4 0x73FA88a0 0x200 + +The processor support up to 60 register programming commands. An error +is generated if more commands are found in the configuration file. + +3. All commands are optional to program. + +Setup a SD Card for booting +-------------------------------- + +The following example prepare a SD card with u-boot and a FAT partition +to be used to stored the kernel to be booted. +I will set the SD in the most compatible mode, setting it with +255 heads and 63 sectors, as suggested from several documentation and +howto on line (I took as reference the preparation of a SD Card for the +Beagleboard, running u-boot as bootloader). + +You should start clearing the partitions table on the SD card. Because +the u-boot image must be stored at the offset 0x400, it must be assured +that there is no partition at that address. A new SD card is already +formatted with FAT filesystem and the partition starts from the first +cylinder, so we need to change it. + +You can do all steps with fdisk. If the device for the SD card is +/dev/mmcblk0, the following commands make the job: + +1. Start the fdisk utility (as superuser) + fdisk /dev/mmcblk0 + +2. Clear the actual partition + +Command (m for help): o + +3. Print card info: + +Command (m for help): p +Disk /dev/mmcblk0: 1981 MB, 1981284352 bytes + +In my case, I have a 2 GB card. I need the size to set later the correct value +for the cylinders. + +4. Go to expert mode: + +Command (m for help): x + +5. Set card geometry + +Expert command (m for help): h +Number of heads (1-256, default 4): 255 + +Expert command (m for help): s +Number of sectors (1-63, default 16): 63 +Warning: setting sector offset for DOS compatiblity + +We have set 255 heads, 63 sector. We have to set the cylinder. +The value to be set can be calculated with: + + cilynder = / / / + +in this example, + 1981284352 / 255 / 63 / 512 = 239.x = 239 + + +Expert command (m for help): c +Number of cylinders (1-1048576, default 60032): 239 + +6. Leave the expert mode +Expert command (m for help): r + +7. Set up a partition + +Now set a partition table to store the kernel or whatever you want. Of course, +you can set additional partitions to store rootfs, data, etc. +In my example I want to set a single partition. I must take care +to not overwrite the space where I will put u-boot. + +Command (m for help): n +Command action + e extended + p primary partition (1-4) +p +Partition number (1-4): 1 +First cylinder (1-239, default 1): 3 +Last cylinder, +cylinders or +size{K,M,G} (3-239, default 239): +100M + +Command (m for help): p + +Disk /dev/mmcblk0: 1967 MB, 1967128576 bytes +255 heads, 63 sectors/track, 239 cylinders +Units = cylinders of 16065 * 512 = 8225280 bytes +Disk identifier: 0xb712a870 + + Device Boot Start End Blocks Id System +/dev/mmcblk0p1 3 16 112455 83 Linux + +I have set 100MB, leaving the first 2 sectors free. I will copy u-boot +there. + +8. Write the partition table and exit. + +Command (m for help): w +The partition table has been altered! + +Calling ioctl() to re-read partition table. + +9. Copy u-boot.imx on the SD card + +I use dd: + +dd if=u-boot.imx of=/dev/mmcblk0 bs=512 seek=2 + +This command copies the u-boot image at the address 0x400, as required +by the processor. + +Now remove your card from the PC and go to the target. If evrything went right, +the u-boot prompt should come after power on. + +------------------------------------------------ +Author: Stefano babic diff --git a/include/image.h b/include/image.h index acc553c..541cac9 100644 --- a/include/image.h +++ b/include/image.h @@ -156,6 +156,7 @@ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ #define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */ +#define IH_TYPE_IMXIMAGE 10 /* Freescale IMXBoot Image */ /* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index d3b1518..f8b69de 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -82,6 +82,7 @@ OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o NOPED_OBJ_FILES-y += kwbimage.o +NOPED_OBJ_FILES-y += imximage.o NOPED_OBJ_FILES-y += mkimage.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o NOPED_OBJ_FILES-y += os_support.o @@ -167,6 +168,7 @@ $(obj)mkimage$(SFX): $(obj)crc32.o \ $(obj)default_image.o \ $(obj)fit_image.o \ $(obj)image.o \ + $(obj)imximage.o \ $(obj)kwbimage.o \ $(obj)md5.o \ $(obj)mkimage.o \ diff --git a/tools/imximage.c b/tools/imximage.c new file mode 100644 index 0000000..c1fdafb --- /dev/null +++ b/tools/imximage.c @@ -0,0 +1,324 @@ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "mkimage.h" +#include +#include "imximage.h" + +/* + * Supported commands for configuration file + */ +static table_entry_t imximage_cmds[] = { + {CMD_BOOT_FROM, "BOOT_FROM", "boot comand", }, + {CMD_DATA, "DATA", "Reg Write Data", }, + {-1, "", "", }, +}; + +/* + * Supported Boot options for configuration file + * this is needed to set the correct flash offset + */ +static table_entry_t imximage_bootops[] = { + {FLASH_OFFSET_SPI, "spi", "SPI Flash", }, + {FLASH_OFFSET_NAND, "nand", "NAND Flash", }, + {FLASH_OFFSET_SD, "sd", "SD Card", }, + {FLASH_OFFSET_ONENAND, "onenand", "OneNAND Flash",}, + {-1, "", "Invalid", }, +}; + + +static struct imx_header imximage_header; + +static uint32_t get_cfg_value(char *token, char *name, int linenr) +{ + char *endptr; + uint32_t value; + + errno = 0; + value = strtoul(token, &endptr, 16); + if (errno || (token == endptr)) { + fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n", + name, linenr, token); + exit(EXIT_FAILURE); + } + return value; +} + +static int imximage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_IMXIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static int imximage_verify_header(unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + + struct imx_header *imx_hdr = (struct imx_header *) ptr; + flash_header_t *hdr = &imx_hdr->fhdr; + + /* Only a few checks can be done: search for magic numbers */ + if (hdr->app_code_barker != APP_CODE_BARKER) + return -FDT_ERR_BADSTRUCTURE; + + if (imx_hdr->dcd_table.preamble.barker != DCD_BARKER) + return -FDT_ERR_BADSTRUCTURE; + + return 0; +} + +static void imximage_print_header(const void *ptr) +{ + struct imx_header *imx_hdr = (struct imx_header *) ptr; + flash_header_t *hdr = &imx_hdr->fhdr; + uint32_t size; + flash_cfg_parms_t *ext_header; + + size = imx_hdr->dcd_table.preamble.length; + if (size > (MAX_HW_CFG_SIZE * sizeof(dcd_type_addr_data_t))) { + fprintf(stderr, + "Error: Image corrupt DCD size %d exceed maximum %d\n", + size / sizeof(dcd_type_addr_data_t), MAX_HW_CFG_SIZE); + exit(EXIT_FAILURE); + } + + ext_header = (flash_cfg_parms_t *) ((uint32_t)&imx_hdr->dcd_table + + sizeof(dcd_preamble_t) + size); + + printf("Image Type: Freescale IMX Boot Image\n"); + printf("Data Size: "); + genimg_print_size(ext_header->length); + printf("Load Address: %08x\n", (unsigned int)hdr->app_dest_ptr); + printf("Entry Point: %08x\n", (unsigned int)hdr->app_code_jump_vector); +} + +static uint32_t imximage_parse_cfg_file(struct imx_header *imxhdr, char *name) +{ + FILE *fd = NULL; + char *line = NULL; + char *token, *saveptr1, *saveptr2; + int lineno = 0; + int fld, value; + uint32_t len; + int dcd_len = 0; + dcd_t *dcd = &imxhdr->dcd_table; + int32_t cmd; + + fd = fopen(name, "r"); + if (fd == 0) { + fprintf(stderr, "Error: %s - Can't open DCD file\n", name); + exit(EXIT_FAILURE); + } + + /* Very simple parsing, line starting with # are comments + * and are dropped + */ + while ((getline(&line, &len, fd)) > 0) { + lineno++; + + token = strtok_r(line, "\r\n", &saveptr1); + if (token == NULL) + continue; + + /* Check inside the single line */ + for (fld = CFG_COMMAND, cmd = CMD_INVALID, + line = token; ; line = NULL, fld++) { + token = strtok_r(line, " \t", &saveptr2); + if (token == NULL) + break; + + /* Drop all text starting with '#' as comments */ + if (token[0] == '#') + break; + + /* parse all fields in a single line */ + switch (fld) { + case CFG_COMMAND: + cmd = get_table_entry_id(imximage_cmds, + "imximage commands", token); + if (cmd < 0) { + fprintf(stderr, + "Error: %s[%d] - " + "Invalid command (%s)\n", + name, lineno, token); + exit(EXIT_FAILURE); + } + break; + case CFG_REG_SIZE: + switch (cmd) { + case CMD_BOOT_FROM: + /* Get flash header offset */ + imxhdr->flash_offset = + get_table_entry_id( + imximage_bootops, + "imximage boot option", + token); + if (imxhdr->flash_offset == -1) { + fprintf(stderr, + "Error: %s[%d] -" + "Invalid boot device" + "(%s)\n", + name, lineno, token); + exit(EXIT_FAILURE); + } + break; + case CMD_DATA: + value = get_cfg_value(token, + name, lineno); + + /* Byte, halfword, word */ + if ((value != 1) && + (value != 2) && (value != 4)) { + fprintf(stderr, + "Error: %s[%d] - " + "Invalid register size " + "(%d)\n", + name, lineno, value); + exit(EXIT_FAILURE); + } + dcd->addr_data[dcd_len].type = value; + break; + } + + case CFG_REG_ADDRESS: + if (cmd == CMD_DATA) + dcd->addr_data[dcd_len].addr = + get_cfg_value(token, + name, lineno); + break; + case CFG_REG_VALUE: + if (cmd == CMD_DATA) { + dcd->addr_data[dcd_len].value = + get_cfg_value(token, + name, lineno); + dcd_len++; + } + break; + } + } + + if (dcd_len > MAX_HW_CFG_SIZE) { + fprintf(stderr, + "Error: %s[%d] -" + "DCD table exceeds maximum size(%d)\n", + name, lineno, MAX_HW_CFG_SIZE); + } + } + dcd->preamble.barker = DCD_BARKER; + dcd->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t); + fclose(fd); + + return dcd->preamble.length; +} + +static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + struct imx_header *hdr = (struct imx_header *)ptr; + flash_header_t *fhdr = &hdr->fhdr; + int dcd_len; + flash_cfg_parms_t *ext_header; + uint32_t base_offset; + + /* Set default offset */ + hdr->flash_offset = FLASH_OFFSET_STANDARD; + + /* Set magic number */ + fhdr->app_code_barker = APP_CODE_BARKER; + + /* Parse dcd configuration file */ + dcd_len = imximage_parse_cfg_file(hdr, params->imagename); + + fhdr->app_dest_ptr = params->addr; + fhdr->app_dest_ptr = params->ep - hdr->flash_offset - + sizeof(struct imx_header); + fhdr->app_code_jump_vector = params->ep; + + base_offset = fhdr->app_dest_ptr + hdr->flash_offset ; + fhdr->dcd_ptr_ptr = (uint32_t) ((uint32_t)&fhdr->dcd_ptr - + (uint32_t)&fhdr->app_code_jump_vector) + base_offset ; + + fhdr->dcd_ptr = base_offset + + ((uint32_t)&hdr->dcd_table - + (uint32_t)&hdr->fhdr); + + /* The external flash header must be at the end of the DCD table */ + ext_header = (flash_cfg_parms_t *) ((uint32_t)&hdr->dcd_table + + dcd_len + + sizeof(dcd_preamble_t)); + ext_header->length = sbuf->st_size + + hdr->flash_offset + + sizeof(struct imx_header); + + /* Security feature are not supported */ + fhdr->app_code_csf = 0; + fhdr->super_root_key = NULL; + +} + +int imximage_check_params(struct mkimage_params *params) +{ + if (!params) + return CFG_INVALID; + if (!strlen(params->imagename)) { + fprintf(stderr, "Error: %s - Configuration file not specified, " + "it is needed for imximage generation\n", + params->cmdname); + return CFG_INVALID; + } + /* + * Check parameters: + * XIP is not allowed and verify that incompatible + * parameters are not sent at the same time + * For example, if list is required a data image must not be provided + */ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)) || + (params->xflag) || !(strlen(params->imagename)); +} + +/* + * imximage parameters + */ +static struct image_type_params imximage_params = { + .name = "Freescale i.MX 51 Boot Image support", + .header_size = sizeof(struct imx_header), + .hdr = (void *)&imximage_header, + .check_image_type = imximage_check_image_types, + .verify_header = imximage_verify_header, + .print_header = imximage_print_header, + .set_header = imximage_set_header, + .check_params = imximage_check_params, +}; + +void init_imx_image_type(void) +{ + mkimage_register(&imximage_params); +} diff --git a/tools/imximage.h b/tools/imximage.h new file mode 100644 index 0000000..c579f51 --- /dev/null +++ b/tools/imximage.h @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMXIMAGE_H_ +#define _IMXIMAGE_H_ + +#define MAX_HW_CFG_SIZE 60 /* Max number of registers imx can set */ +#define MAX_EXP_SIZE 4 +#define APP_CODE_BARKER 0xB1 +#define DCD_BARKER 0xB17219E9 +#define HEADER_OFFSET 0x400 + + +#define CMD_DATA_STR "DATA" +#define FLASH_OFFSET_STANDARD 0x400 +#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_ONENAND 0x100 + +enum imximage_cmd { + CMD_INVALID, + CMD_BOOT_FROM, + CMD_DATA +}; + +enum imximage_fld_types { + CFG_INVALID = -1, + CFG_COMMAND, + CFG_REG_SIZE, + CFG_REG_ADDRESS, + CFG_REG_VALUE +}; + +typedef struct { + uint8_t rsa_exponent[MAX_EXP_SIZE]; /* RSA public exponent */ + uint8_t *rsa_modulus; /* RSA modulus pointer */ + uint16_t exponent_size; /* Exponent size (bytes) */ + uint16_t modulus_size; /* Modulus size (bytes) */ + uint8_t init_flag; /* key initialized */ +} hab_rsa_public_key; + +typedef struct { + uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */ + uint32_t addr; /* Address to write to */ + uint32_t value; /* Data to write */ +} dcd_type_addr_data_t; + +typedef struct { + uint32_t barker; /* Barker for sanity check */ + uint32_t length; /* Device configuration length (without preamble) */ +} dcd_preamble_t; + +typedef struct { + dcd_preamble_t preamble; + dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE]; +} dcd_t; + +typedef struct { + uint32_t app_code_jump_vector; + uint32_t app_code_barker; + uint32_t app_code_csf; + uint32_t dcd_ptr_ptr; + hab_rsa_public_key *super_root_key; + uint32_t dcd_ptr; + uint32_t app_dest_ptr; +} flash_header_t; + +typedef struct { + uint32_t length; /* Length of data to be read from flash */ +} flash_cfg_parms_t; + +struct imx_header { + flash_header_t fhdr; + dcd_t dcd_table; + flash_cfg_parms_t ext_header; + uint32_t flash_offset; +}; + +struct reg_config { + uint32_t raddr; + uint32_t rdata; +}; + +#endif /* _IMXIMAGE_H_ */ diff --git a/tools/mkimage.c b/tools/mkimage.c index 1bed933..cf4b754 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -150,6 +150,8 @@ main (int argc, char **argv) /* Init Kirkwood Boot image generation/list support */ init_kwb_image_type (); + /* Init Freescale imx Boot image generation/list support */ + init_imx_image_type (); /* Init FIT image generation/list support */ init_fit_image_type (); /* Init Default image generation/list support */ diff --git a/tools/mkimage.h b/tools/mkimage.h index ec67336..9033a7d 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -140,6 +140,7 @@ void mkimage_register (struct image_type_params *tparams); * Supported image types init functions */ void init_kwb_image_type (void); +void init_imx_image_type (void); void init_default_image_type (void); void init_fit_image_type (void); -- cgit v1.1 From 44431cabbb66e81a2d77642b6f7d39c6230ea4ba Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 21 Jan 2010 19:30:36 -0500 Subject: gzip/zlib: make features optional If you really want to slim down U-Boot and you would rather use a higher compression scheme (like LZMA), it'd be nice to disable gzip/zlib since these code bases take up a significant amount of space. Signed-off-by: Mike Frysinger --- common/cmd_bootm.c | 2 ++ include/config_defaults.h | 3 +++ lib_generic/Makefile | 4 ++-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index f28e88f..23ab0c4 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -352,6 +352,7 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress) *load_end = load + image_len; puts("OK\n"); break; +#ifdef CONFIG_GZIP case IH_COMP_GZIP: printf (" Uncompressing %s ... ", type_name); if (gunzip ((void *)load, unc_len, @@ -365,6 +366,7 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress) *load_end = load + image_len; break; +#endif /* CONFIG_GZIP */ #ifdef CONFIG_BZIP2 case IH_COMP_BZIP2: printf (" Uncompressing %s ... ", type_name); diff --git a/include/config_defaults.h b/include/config_defaults.h index 08b6ede..0337163 100644 --- a/include/config_defaults.h +++ b/include/config_defaults.h @@ -14,4 +14,7 @@ #define CONFIG_BOOTM_NETBSD 1 #define CONFIG_BOOTM_RTEMS 1 +#define CONFIG_GZIP 1 +#define CONFIG_ZLIB 1 + #endif diff --git a/lib_generic/Makefile b/lib_generic/Makefile index 4e4496a..c45f07c 100644 --- a/lib_generic/Makefile +++ b/lib_generic/Makefile @@ -37,7 +37,7 @@ COBJS-y += crc32.o COBJS-y += ctype.o COBJS-y += display_options.o COBJS-y += div64.o -COBJS-y += gunzip.o +COBJS-$(CONFIG_GZIP) += gunzip.o COBJS-$(CONFIG_LMB) += lmb.o COBJS-y += ldiv.o COBJS-$(CONFIG_MD5) += md5.o @@ -48,7 +48,7 @@ COBJS-y += string.o COBJS-y += strmhz.o COBJS-y += time.o COBJS-y += vsprintf.o -COBJS-y += zlib.o +COBJS-$(CONFIG_ZLIB) += zlib.o COBJS-$(CONFIG_RBTREE) += rbtree.o COBJS := $(COBJS-y) -- cgit v1.1 From e852d36a1e12864ab0656729c45c846e65efa4ee Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 21 Jan 2010 19:59:04 -0500 Subject: tools: give explicit libfdt paths The current libfdt object rules hard depend implicitly on the .depend file being correct. If it isn't, then it is unable to properly compile the objects. Give it a full path like all the other implicit rules here so it will always work in face of .depend issues. Signed-off-by: Mike Frysinger --- tools/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/Makefile b/tools/Makefile index f8b69de..266306e 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -196,7 +196,7 @@ $(obj)%.o: $(SRCTREE)/common/%.c $(obj)%.o: $(SRCTREE)/lib_generic/%.c $(HOSTCC) -g $(HOSTCFLAGS) -c -o $@ $< -$(LIBFDT_OBJS): +$(obj)%.o: $(SRCTREE)/libfdt/%.c $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< subdirs: -- cgit v1.1 From 64b150213365db6be97a98d25884f87d83caacaf Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 8 Jan 2010 02:48:03 -0500 Subject: getline: split out for darwin systems At least on OS X 10.5 and older, getline does not exist. So split out the function from the mingw code so that we can pull it in for Darwin systems. Signed-off-by: Mike Frysinger --- tools/getline.c | 101 ++++++++++++++++++++++++++++++++++++++++++++++++++ tools/getline.h | 1 + tools/mingw_support.c | 99 +------------------------------------------------ tools/mingw_support.h | 2 +- tools/os_support.c | 3 ++ tools/os_support.h | 4 ++ 6 files changed, 111 insertions(+), 99 deletions(-) create mode 100644 tools/getline.c create mode 100644 tools/getline.h diff --git a/tools/getline.c b/tools/getline.c new file mode 100644 index 0000000..3ba52a3 --- /dev/null +++ b/tools/getline.c @@ -0,0 +1,101 @@ +/* getline.c -- Replacement for GNU C library function getline + +Copyright (C) 1993, 1996, 2001, 2002 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2 of the +License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* Written by Jan Brittenson, bson@gnu.ai.mit.edu. */ + +#include +#include + +/* Always add at least this many bytes when extending the buffer. */ +#define MIN_CHUNK 64 + +/* Read up to (and including) a TERMINATOR from STREAM into *LINEPTR + + OFFSET (and null-terminate it). *LINEPTR is a pointer returned from + malloc (or NULL), pointing to *N characters of space. It is realloc'd + as necessary. Return the number of characters read (not including the + null terminator), or -1 on error or EOF. + NOTE: There is another getstr() function declared in . */ +static int getstr(char **lineptr, size_t *n, FILE *stream, + char terminator, size_t offset) +{ + int nchars_avail; /* Allocated but unused chars in *LINEPTR. */ + char *read_pos; /* Where we're reading into *LINEPTR. */ + int ret; + + if (!lineptr || !n || !stream) + return -1; + + if (!*lineptr) { + *n = MIN_CHUNK; + *lineptr = malloc(*n); + if (!*lineptr) + return -1; + } + + nchars_avail = *n - offset; + read_pos = *lineptr + offset; + + for (;;) { + register int c = getc(stream); + + /* We always want at least one char left in the buffer, since we + always (unless we get an error while reading the first char) + NUL-terminate the line buffer. */ + + assert(*n - nchars_avail == read_pos - *lineptr); + if (nchars_avail < 2) { + if (*n > MIN_CHUNK) + *n *= 2; + else + *n += MIN_CHUNK; + + nchars_avail = *n + *lineptr - read_pos; + *lineptr = realloc(*lineptr, *n); + if (!*lineptr) + return -1; + read_pos = *n - nchars_avail + *lineptr; + assert(*n - nchars_avail == read_pos - *lineptr); + } + + if (c == EOF || ferror (stream)) { + /* Return partial line, if any. */ + if (read_pos == *lineptr) + return -1; + else + break; + } + + *read_pos++ = c; + nchars_avail--; + + if (c == terminator) + /* Return the line. */ + break; + } + + /* Done - NUL terminate and return the number of chars read. */ + *read_pos = '\0'; + + ret = read_pos - (*lineptr + offset); + return ret; +} + +int getline (char **lineptr, size_t *n, FILE *stream) +{ + return getstr(lineptr, n, stream, '\n', 0); +} diff --git a/tools/getline.h b/tools/getline.h new file mode 100644 index 0000000..a2f35b9 --- /dev/null +++ b/tools/getline.h @@ -0,0 +1 @@ +int getline(char **lineptr, size_t *n, FILE *stream); diff --git a/tools/mingw_support.c b/tools/mingw_support.c index 6379710..18b69bb 100644 --- a/tools/mingw_support.c +++ b/tools/mingw_support.c @@ -136,101 +136,4 @@ char *strtok_r(char *s, const char *delim, char **save_ptr) return token; } -/* getline.c -- Replacement for GNU C library function getline - -Copyright (C) 1993, 1996, 2001, 2002 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or -modify it under the terms of the GNU General Public License as -published by the Free Software Foundation; either version 2 of the -License, or (at your option) any later version. - -This program is distributed in the hope that it will be useful, but -WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* Written by Jan Brittenson, bson@gnu.ai.mit.edu. */ - -/* Always add at least this many bytes when extending the buffer. */ -#define MIN_CHUNK 64 - -/* Read up to (and including) a TERMINATOR from STREAM into *LINEPTR - + OFFSET (and null-terminate it). *LINEPTR is a pointer returned from - malloc (or NULL), pointing to *N characters of space. It is realloc'd - as necessary. Return the number of characters read (not including the - null terminator), or -1 on error or EOF. - NOTE: There is another getstr() function declared in . */ -static int getstr(char **lineptr, size_t *n, FILE *stream, - char terminator, size_t offset) -{ - int nchars_avail; /* Allocated but unused chars in *LINEPTR. */ - char *read_pos; /* Where we're reading into *LINEPTR. */ - int ret; - - if (!lineptr || !n || !stream) - return -1; - - if (!*lineptr) { - *n = MIN_CHUNK; - *lineptr = malloc(*n); - if (!*lineptr) - return -1; - } - - nchars_avail = *n - offset; - read_pos = *lineptr + offset; - - for (;;) { - register int c = getc(stream); - - /* We always want at least one char left in the buffer, since we - always (unless we get an error while reading the first char) - NUL-terminate the line buffer. */ - - assert(*n - nchars_avail == read_pos - *lineptr); - if (nchars_avail < 2) { - if (*n > MIN_CHUNK) - *n *= 2; - else - *n += MIN_CHUNK; - - nchars_avail = *n + *lineptr - read_pos; - *lineptr = realloc(*lineptr, *n); - if (!*lineptr) - return -1; - read_pos = *n - nchars_avail + *lineptr; - assert(*n - nchars_avail == read_pos - *lineptr); - } - - if (c == EOF || ferror (stream)) { - /* Return partial line, if any. */ - if (read_pos == *lineptr) - return -1; - else - break; - } - - *read_pos++ = c; - nchars_avail--; - - if (c == terminator) - /* Return the line. */ - break; - } - - /* Done - NUL terminate and return the number of chars read. */ - *read_pos = '\0'; - - ret = read_pos - (*lineptr + offset); - return ret; -} - -int getline (char **lineptr, size_t *n, FILE *stream) -{ - return getstr(lineptr, n, stream, '\n', 0); -} +#include "getline.c" diff --git a/tools/mingw_support.h b/tools/mingw_support.h index 2793674..ee07290 100644 --- a/tools/mingw_support.h +++ b/tools/mingw_support.h @@ -45,6 +45,6 @@ int fsync(int fd); void *mmap(void *, size_t, int, int, int, int); int munmap(void *, size_t); char *strtok_r(char *s, const char *delim, char **save_ptr); -int getline(char **lineptr, size_t *n, FILE *stream); +#include "getline.h" #endif /* __MINGW_SUPPORT_H_ */ diff --git a/tools/os_support.c b/tools/os_support.c index 5b919aa..1ed89e6 100644 --- a/tools/os_support.c +++ b/tools/os_support.c @@ -23,3 +23,6 @@ #ifdef __MINGW32__ #include "mingw_support.c" #endif +#ifdef __APPLE__ +#include "getline.c" +#endif diff --git a/tools/os_support.h b/tools/os_support.h index 7bf930e..7dcbee4 100644 --- a/tools/os_support.h +++ b/tools/os_support.h @@ -28,4 +28,8 @@ #include "mingw_support.h" #endif +#ifdef __APPLE__ +#include "getline.h" +#endif + #endif /* __OS_SUPPORT_H_ */ -- cgit v1.1 From 2903ad33a71251a3a87485b5b185852c8998f209 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 8 Jan 2010 08:03:06 -0500 Subject: jffs2: fix hangs/crashs when not using CONFIG_JFFS2_PART_SIZE Commit b5b004ad8a0ac6f98bd5708ec8b22fbddd1c1042 caused the sector_size to be calculated incorrectly when the part size was not hardcoded. This is because the new code relied on part->size but tried to do the calculation before it was initialized properly, and it did not take into consideration the magic SIZE_REMAINING define. Signed-off-by: Mike Frysinger --- common/cmd_jffs2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c index 372ccb2..6799cca 100644 --- a/common/cmd_jffs2.c +++ b/common/cmd_jffs2.c @@ -406,8 +406,6 @@ int mtdparts_init(void) part->offset = 0x00000000; #endif - part->sector_size = get_part_sector_size(id, part); - part->dev = current_mtd_dev; INIT_LIST_HEAD(&part->link); @@ -415,6 +413,8 @@ int mtdparts_init(void) if (part->size == SIZE_REMAINING) part->size = id->size - part->offset; + part->sector_size = get_part_sector_size(id, part); + DEBUGF("part : name = %s, size = 0x%08lx, offset = 0x%08lx\n", part->name, part->size, part->offset); -- cgit v1.1 From 93cedc71647b4b72ac9b48e11997eb2f91645001 Mon Sep 17 00:00:00 2001 From: James Yang Date: Tue, 12 Jan 2010 15:50:18 -0600 Subject: ppc/p4080: Fix mask width of RCW fields MEM_PLL_RAT, SYS_PLL_RAT The masks for MEM_PLL_RAT and SYS_PLL_RAT should have been 5-bits instead of 4. Signed-off-by: James Yang Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 2103e2e..8dab8d1 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -80,8 +80,8 @@ void get_sys_info (sys_info_t * sysInfo) freqCC_PLL[2] = sysclk; freqCC_PLL[3] = sysclk; - sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf; - sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf); + sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f); freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; -- cgit v1.1 From 693416fe01d324472d270ac28389022eb82c7217 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 25 Jan 2010 11:01:51 -0600 Subject: Revert "ppc/p4080: Fix reporting of PME & FM clock frequencies" This reverts commit bc20f9a9527afe8ae406a74f74765d4323f04922. The original code was correct. I clearly need glasses or a brown paper bag. Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 8dab8d1..9193992 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -103,21 +103,21 @@ void get_sys_info (sys_info_t * sysInfo) #ifdef CONFIG_SYS_DPAA_PME if (rcw_tmp & PME_CLK_SEL) - sysInfo->freqPME = sysInfo->freqSystemBus / 2; - else sysInfo->freqPME = freqCC_PLL[2] / 2; + else + sysInfo->freqPME = sysInfo->freqSystemBus / 2; #endif #ifdef CONFIG_SYS_DPAA_FMAN if (rcw_tmp & FM1_CLK_SEL) - sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; - else sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; #if (CONFIG_SYS_NUM_FMAN) == 2 if (rcw_tmp & FM2_CLK_SEL) - sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; - else sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; #endif #endif -- cgit v1.1 From 1118cdbfeb8fc3acfe542d08703153ac188f9dbd Mon Sep 17 00:00:00 2001 From: Li Yang Date: Thu, 7 Jan 2010 16:00:13 +0800 Subject: fsl_esdhc: fix wrong clock mask Fix typo in SYSCTL_CLOCK_MASK, which caused residual in high bits of SDCLKFS. Signed-off-by: Jin Qing Signed-off-by: Li Yang Signed-off-by: Kumar Gala --- include/fsl_esdhc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 89b8304..eac6a2b 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -32,7 +32,7 @@ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 -#define SYSCTL_CLOCK_MASK 0x00000fff +#define SYSCTL_CLOCK_MASK 0x0000fff0 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 -- cgit v1.1 From d91803826985bfdf151eed66543ce3b1a301682f Mon Sep 17 00:00:00 2001 From: Liu Yu Date: Fri, 27 Nov 2009 15:31:51 +0800 Subject: ppc/85xx: Add PIB/ATM support for MPC8569mds Signed-off-by: Liu Yu Signed-off-by: Kumar Gala --- board/freescale/common/pq-mds-pib.c | 2 +- board/freescale/mpc8569mds/mpc8569mds.c | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index 6c72aa1..5f7a67d 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -63,7 +63,7 @@ int pib_init(void) #endif #if defined(CONFIG_PQ_MDS_PIB_ATM) -#if defined(CONFIG_MPC8360EMDS) +#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS) val8 = 0; i2c_write(0x20, 0x6, 1, &val8, 1); i2c_write(0x20, 0x7, 1, &val8, 1); diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 1c76b84..1eddeef 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -39,6 +39,9 @@ #include #include "bcsr.h" +#if defined(CONFIG_PQ_MDS_PIB) +#include "../common/pq-mds-pib.h" +#endif phys_size_t fixed_sdram(void); @@ -545,6 +548,10 @@ void pci_init_board(void) debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); +#if defined(CONFIG_PQ_MDS_PIB) + pib_init(); +#endif + #ifdef CONFIG_PCIE1 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); -- cgit v1.1 From c95d541e4b46cb3ba19bf35e34b1dc3ca32f7b4b Mon Sep 17 00:00:00 2001 From: Liu Yu Date: Fri, 27 Nov 2009 15:31:52 +0800 Subject: ppc/85xx: Add ATM config for MPC8569MDS Signed-off-by: Liu Yu Signed-off-by: Kumar Gala --- MAKEALL | 1 + Makefile | 3 ++- include/configs/MPC8569MDS.h | 5 +++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/MAKEALL b/MAKEALL index afdc1b5..15e93cf 100755 --- a/MAKEALL +++ b/MAKEALL @@ -403,6 +403,7 @@ LIST_85xx=" \ MPC8560ADS \ MPC8568MDS \ MPC8569MDS \ + MPC8569MDS_ATM \ MPC8572DS \ MPC8572DS_36BIT \ P2020DS \ diff --git a/Makefile b/Makefile index 722b976..69b963f 100644 --- a/Makefile +++ b/Makefile @@ -2489,8 +2489,9 @@ MPC8555CDS_config: unconfig MPC8568MDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale +MPC8569MDS_ATM_config \ MPC8569MDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8569mds freescale + @$(MKCONFIG) -t $(@:_config=) MPC8569MDS ppc mpc85xx mpc8569mds freescale MPC8572DS_36BIT_config \ MPC8572DS_config: unconfig diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index e16f0e1..ae2fc19 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -51,6 +51,11 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CLK_FREQ 66666666 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_MK_ATM +#define CONFIG_PQ_MDS_PIB +#define CONFIG_PQ_MDS_PIB_ATM +#endif + /* * These can be toggled for performance analysis, otherwise use default. */ -- cgit v1.1 From 0fd2fa6cce6eb91271ebf9733878d0f1fcbc9b32 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 17 Nov 2009 20:49:05 +0800 Subject: Fix the local bus divider mapping The real clock divider is 4 times of the bits LCRR[CLKDIV], according the latest RevF RM. Signed-off-by: Dave Liu Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 9193992..268edbc 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -170,7 +170,12 @@ void get_sys_info (sys_info_t * sysInfo) } #endif if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { -#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ +#if defined(CONFIG_FSL_CORENET) + /* If this is corenet based SoC, bit-representation + * for four times the clock divider values. + */ + lcrr_div *= 4; +#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) /* * Yes, the entire PQ38 family use the same -- cgit v1.1 From 46df64f22c471b010161aa68bfdbfe94ea46e7bd Mon Sep 17 00:00:00 2001 From: Liu Yu Date: Fri, 15 Jan 2010 14:58:40 +0800 Subject: qe: fixup the snum for MPC8569 Rev2.0 Since 1.0 and 2.0 use different snum table, we fixup the snum value according to SPRN_SVR. Signed-off-by: Liu Yu Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index af0e78e..1d11ab4 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -331,6 +331,23 @@ static void ft_fixup_dpaa_clks(void *blob) #define ft_fixup_dpaa_clks(x) #endif +#ifdef CONFIG_QE +static void ft_fixup_qe_snum(void *blob) +{ + unsigned int svr; + + svr = mfspr(SPRN_SVR); + if (SVR_SOC_VER(svr) == SVR_8569_E) { + if(IS_SVR_REV(svr, 1, 0)) + do_fixup_by_compat_u32(blob, "fsl,qe", + "fsl,qe-num-snums", 46, 1); + else + do_fixup_by_compat_u32(blob, "fsl,qe", + "fsl,qe-num-snums", 76, 1); + } +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { int off; @@ -367,6 +384,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) "bus-frequency", gd->lbc_clk, 1); #ifdef CONFIG_QE ft_qe_setup(blob); + ft_fixup_qe_snum(blob); #endif #ifdef CONFIG_SYS_NS16550 -- cgit v1.1 From 66e821ebe96123b3a81ec9ca25cec9c0560fe232 Mon Sep 17 00:00:00 2001 From: Vivek Mahajan Date: Thu, 7 Jan 2010 14:27:14 +0530 Subject: 85xx/p1_p2_rdb: enable hwconfig Signed-off-by: Vivek Mahajan Signed-off-by: Kumar Gala --- include/configs/P1_P2_RDB.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 15bfeef..405e6d5 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -203,6 +203,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_HWCONFIG #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -- cgit v1.1 From fc4e188789b01dc9f18c80869c43fdd7d1a51378 Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Tue, 19 Jan 2010 14:41:55 +0100 Subject: ppc: Loose GOT access in IRQ Using the GOT in IRQ handlers requires r14 to be -ffixed-r14. Avoid this by relocatate transfer_to_handler too. This will allow to free up r14 later on. Signed-off-by: Joakim Tjernlund --- cpu/74xx_7xx/start.S | 36 +++--------------------------------- cpu/mpc512x/start.S | 35 +++-------------------------------- cpu/mpc5xx/start.S | 37 +++---------------------------------- cpu/mpc5xxx/start.S | 35 +++-------------------------------- cpu/mpc8220/start.S | 35 +++-------------------------------- cpu/mpc824x/start.S | 33 +++------------------------------ cpu/mpc8260/start.S | 35 +++-------------------------------- cpu/mpc83xx/start.S | 34 +++------------------------------- cpu/mpc85xx/start.S | 33 +++------------------------------ cpu/mpc86xx/start.S | 36 +++--------------------------------- cpu/mpc8xx/start.S | 36 +++--------------------------------- cpu/ppc4xx/start.S | 33 +++------------------------------ include/ppc_asm.tmpl | 47 ++++++++++++++++++++++------------------------- lib_ppc/Makefile | 1 + lib_ppc/reloc.S | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 15 files changed, 108 insertions(+), 407 deletions(-) create mode 100644 lib_ppc/reloc.S diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index 23381a3..efcd95f 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -132,28 +132,15 @@ Alignment: mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) /* Program check exception */ . = 0x700 ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) /* No FPU on MPC8xx. This exception is not supposed to happen. */ @@ -837,23 +824,6 @@ trap_init: mtlr r4 /* restore link register */ blr - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - sync - isync - - blr - #ifdef CONFIG_SYS_INIT_RAM_LOCK lock_ram_in_cache: /* Allocate Initial RAM in data cache. diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 4edc8e9..46c5efa 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -127,30 +127,15 @@ Alignment: mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) /* Program check exception */ . = 0x700 ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) /* Floating Point Unit unavailable exception */ STD_EXCEPTION(0x800, FPUnavailable, UnknownException) @@ -723,17 +708,3 @@ trap_init: mtlr r4 /* restore link register */ blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S index 85ea7a8..be980a1 100644 --- a/cpu/mpc5xx/start.S +++ b/cpu/mpc5xx/start.S @@ -217,28 +217,15 @@ Alignment: mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) /* Program check exception */ . = 0x700 ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) /* FPU on MPC5xx available. We will use it later. */ @@ -563,24 +550,6 @@ trap_init: mtlr r4 /* restore link register */ blr - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - sync - isync - - blr - - #if defined(CONFIG_PATI) /* Program the PLL */ pll_prog_code_start: diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index eb42939..075a7dd 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -215,30 +215,15 @@ Alignment: mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) /* Program check exception */ . = 0x700 ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) STD_EXCEPTION(0x800, FPUnavailable, UnknownException) @@ -797,17 +782,3 @@ trap_init: mtlr r4 /* restore link register */ blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S index af9472d..5218c85 100644 --- a/cpu/mpc8220/start.S +++ b/cpu/mpc8220/start.S @@ -176,30 +176,15 @@ Alignment: mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) /* Program check exception */ . = 0x700 ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) STD_EXCEPTION(0x800, FPUnavailable, UnknownException) @@ -762,17 +747,3 @@ trap_init: mtlr r4 /* restore link register */ blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S index 750457b..7f40648 100644 --- a/cpu/mpc824x/start.S +++ b/cpu/mpc824x/start.S @@ -227,28 +227,15 @@ Alignment: mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) /* Program check exception */ . = EXC_OFF_PROGRAM ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) /* No FPU on MPC8xx. This exception is not supposed to happen. */ @@ -695,20 +682,6 @@ trap_init: mtlr r4 /* restore link register */ blr - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr - /* Setup the BAT registers. */ setup_bats: diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index edb95e6..7d80af5 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -286,30 +286,15 @@ Alignment: mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) /* Program check exception */ . = 0x700 ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) STD_EXCEPTION(0x800, FPUnavailable, UnknownException) @@ -1033,17 +1018,3 @@ trap_init: mtlr r4 /* restore link register */ blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index ee4b862..5a50b09 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -338,30 +338,15 @@ Alignment: mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) /* Program check exception */ . = 0x700 ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) STD_EXCEPTION(0x800, FPUnavailable, UnknownException) @@ -1086,19 +1071,6 @@ trap_init: mtlr r4 /* restore link register */ blr - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr #endif /* !CONFIG_NAND_SPL */ #ifdef CONFIG_SYS_INIT_RAM_LOCK diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 7e60e67..d73c5c2 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -415,28 +415,15 @@ Alignment: mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + _START_OFFSET - .long int_return - _start + _START_OFFSET + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) /* Program check exception */ . = 0x0700 ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + _START_OFFSET - .long int_return - _start + _START_OFFSET + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) /* No FPU on MPC85xx. This exception is not supposed to happen. */ @@ -1089,20 +1076,6 @@ trap_init: mtlr r4 /* restore link register */ blr - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0,0(r7) /* hdlr ... */ - add r0,r0,r3 /* ... += dest_addr */ - stw r0,0(r7) - - lwz r0,4(r7) /* int_return ... */ - add r0,r0,r3 /* ... += dest_addr */ - stw r0,4(r7) - - blr - .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index e65f1c0..eaa2657 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -121,28 +121,15 @@ Alignment: mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) /* Program check exception */ . = 0x700 ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) STD_EXCEPTION(0x800, FPUnavailable, UnknownException) @@ -848,23 +835,6 @@ trap_init: mtlr r4 /* restore link register */ blr - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - sync - isync - - blr - .globl enable_ext_addr enable_ext_addr: mfspr r0, HID0 diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S index e84326e..24e9053 100644 --- a/cpu/mpc8xx/start.S +++ b/cpu/mpc8xx/start.S @@ -231,28 +231,15 @@ Alignment: mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) /* Program check exception */ . = 0x700 ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) /* No FPU on MPC8xx. This exception is not supposed to happen. */ @@ -694,20 +681,3 @@ trap_init: mtlr r4 /* restore link register */ blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - sync - isync - - blr diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 46f65aa..2eb21fa 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -574,28 +574,15 @@ Alignment: mfspr r5,DSISR stw r5,_DSISR(r21) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + _START_OFFSET - .long int_return - _start + _START_OFFSET + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) /* Program check exception */ . = 0x700 ProgramCheck: EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + _START_OFFSET - .long int_return - _start + _START_OFFSET + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) #ifdef CONFIG_440 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) @@ -1742,20 +1729,6 @@ __440_msr_continue: mtlr r4 /* restore link register */ blr - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr - #if defined(CONFIG_440) /*----------------------------------------------------------------------------+ | dcbz_area. diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 0019d46..fa5c5f6 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -257,46 +257,43 @@ * OFFSET values only; they must be relocated first before they can * be used! */ -#define STD_EXCEPTION(n, label, hdlr) \ - . = n; \ -label: \ - EXCEPTION_PROLOG(SRR0, SRR1); \ - lwz r3,GOT(transfer_to_handler); \ - mtlr r3; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - li r20,MSR_KERNEL; \ +#define COPY_EE(d, s) rlwimi d,s,0,16,16 +#define NOCOPY(d, s) +#define EXC_XFER_TEMPLATE(label, hdlr, msr, copyee) \ + bl 1f; \ +1: mflr r20; \ + lwz r20,(.L_ ## label)-1b+8(r20); \ + mtlr r20; \ + li r20,msr; \ + copyee(r20,r23); \ rlwimi r20,r23,0,25,25; \ blrl; \ .L_ ## label : \ .long hdlr - _start + _START_OFFSET; \ - .long int_return - _start + _START_OFFSET + .long int_return - _start + _START_OFFSET; \ + .long transfer_to_handler - _start + _START_OFFSET + +#define STD_EXCEPTION(n, label, hdlr) \ + . = n; \ +label: \ + EXCEPTION_PROLOG(SRR0, SRR1); \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + EXC_XFER_TEMPLATE(label, hdlr, MSR_KERNEL, NOCOPY) \ #define CRIT_EXCEPTION(n, label, hdlr) \ . = n; \ label: \ EXCEPTION_PROLOG(CSRR0, CSRR1); \ - lwz r3,GOT(transfer_to_handler); \ - mtlr r3; \ addi r3,r1,STACK_FRAME_OVERHEAD; \ - li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ - rlwimi r20,r23,0,25,25; \ - blrl; \ -.L_ ## label : \ - .long hdlr - _start + _START_OFFSET; \ - .long crit_return - _start + _START_OFFSET + EXC_XFER_TEMPLATE(label, hdlr, \ + MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \ #define MCK_EXCEPTION(n, label, hdlr) \ . = n; \ label: \ EXCEPTION_PROLOG(MCSRR0, MCSRR1); \ - lwz r3,GOT(transfer_to_handler); \ - mtlr r3; \ addi r3,r1,STACK_FRAME_OVERHEAD; \ - li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ - rlwimi r20,r23,0,25,25; \ - blrl; \ -.L_ ## label : \ - .long hdlr - _start + _START_OFFSET; \ - .long mck_return - _start + _START_OFFSET + EXC_XFER_TEMPLATE(label, hdlr, \ + MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \ #endif /* __PPC_ASM_TMPL__ */ diff --git a/lib_ppc/Makefile b/lib_ppc/Makefile index 60a7625..334e457 100644 --- a/lib_ppc/Makefile +++ b/lib_ppc/Makefile @@ -28,6 +28,7 @@ LIB = $(obj)lib$(ARCH).a SOBJS-y += ppccache.o SOBJS-y += ppcstring.o SOBJS-y += ticks.o +SOBJS-y += reloc.o COBJS-y += bat_rw.o COBJS-y += board.o diff --git a/lib_ppc/reloc.S b/lib_ppc/reloc.S new file mode 100644 index 0000000..50f9a83 --- /dev/null +++ b/lib_ppc/reloc.S @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2009 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + .file "reloc.S" + + .text +#ifndef CONFIG_NAND_SPL + /* + * Function: relocate entries for one exception vector + */ + .globl trap_reloc + .type trap_reloc, @function +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + lwz r0, 8(r7) /* transfer_to_handler ...*/ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 8(r7) + + blr + .size trap_reloc, .-trap_reloc +#endif -- cgit v1.1 From 0f8aa159175385ddd77bc91d11b9568583fbbd0c Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Tue, 19 Jan 2010 14:41:56 +0100 Subject: ppc: Use r12 instead of r14 as GOT pointer. r14 is not supposed to be clobbered by functions. Switch to r12 and call GET_GOT when needed. This will allow u-boot to loose the -ffixed-r14 gcc option. Signed-off-by: Joakim Tjernlund --- cpu/74xx_7xx/start.S | 11 ++++++----- cpu/mpc512x/start.S | 11 ++++++----- cpu/mpc5xx/start.S | 11 ++++++----- cpu/mpc5xxx/start.S | 11 ++++++----- cpu/mpc8220/start.S | 11 ++++++----- cpu/mpc824x/start.S | 11 ++++++----- cpu/mpc8260/start.S | 15 +++++++++------ cpu/mpc83xx/start.S | 11 ++++++----- cpu/mpc85xx/start.S | 11 ++++++----- cpu/mpc86xx/start.S | 11 ++++++----- cpu/mpc8xx/start.S | 11 ++++++----- cpu/ppc4xx/start.S | 11 ++++++----- include/ppc_asm.tmpl | 8 ++++---- 13 files changed, 79 insertions(+), 65 deletions(-) diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index efcd95f..88fdf88 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -63,7 +63,7 @@ /* * Set up GOT: Global Offset Table * - * Use r14 to access the GOT + * Use r12 to access the GOT */ START_GOT GOT_ENTRY(_GOT2_TABLE_) @@ -599,6 +599,7 @@ relocate_code: mr r9, r4 /* Save copy of Global Data pointer */ mr r10, r5 /* Save copy of Destination Address */ + GET_GOT mr r3, r5 /* Destination Address */ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l @@ -616,7 +617,7 @@ relocate_code: sub r15, r10, r4 /* First our own GOT */ - add r14, r14, r15 + add r12, r12, r15 /* then the one used by the C code */ add r30, r30, r15 @@ -691,7 +692,7 @@ in_ram: bl board_init_ecc #endif /* - * Relocation Function, r14 point to got2+0x8000 + * Relocation Function, r12 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. @@ -765,6 +766,8 @@ in_ram: */ .globl trap_init trap_init: + mflr r4 /* save link register */ + GET_GOT lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) @@ -772,8 +775,6 @@ trap_init: cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ 1: lwz r0, 0(r7) stw r0, 0(r9) diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 46c5efa..d26b617 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -65,7 +65,7 @@ /* * Set up GOT: Global Offset Table * - * Use r14 to access the GOT + * Use r12 to access the GOT */ START_GOT GOT_ENTRY(_GOT2_TABLE_) @@ -486,6 +486,7 @@ relocate_code: mr r9, r4 /* Save copy of Global Data pointer */ mr r10, r5 /* Save copy of Destination Address */ + GET_GOT mr r3, r5 /* Destination Address */ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l @@ -504,7 +505,7 @@ relocate_code: sub r15, r10, r4 /* First our own GOT */ - add r14, r14, r15 + add r12, r12, r15 /* then the one used by the C code */ add r30, r30, r15 @@ -584,7 +585,7 @@ relocate_code: in_ram: /* - * Relocation Function, r14 point to got2+0x8000 + * Relocation Function, r12 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. @@ -648,6 +649,8 @@ clear_bss: */ .globl trap_init trap_init: + mflr r4 /* save link register */ + GET_GOT lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) @@ -655,8 +658,6 @@ trap_init: cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ 1: lwz r0, 0(r7) stw r0, 0(r9) diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S index be980a1..0af879e 100644 --- a/cpu/mpc5xx/start.S +++ b/cpu/mpc5xx/start.S @@ -56,7 +56,7 @@ /* * Set up GOT: Global Offset Table * - * Use r14 to access the GOT + * Use r12 to access the GOT */ START_GOT GOT_ENTRY(_GOT2_TABLE_) @@ -372,6 +372,7 @@ relocate_code: mr r9, r4 /* Save copy of global data pointer in SRAM */ mr r10, r5 /* Save copy of monitor destination Address in SRAM */ + GET_GOT mr r3, r5 /* Destination Address */ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l @@ -388,7 +389,7 @@ relocate_code: sub r15, r10, r4 /* First our own GOT */ - add r14, r14, r15 + add r12, r12, r15 /* the the one used by the C code */ add r30, r30, r15 @@ -433,7 +434,7 @@ relocate_code: in_ram: /* - * Relocation Function, r14 point to got2+0x8000 + * Relocation Function, r12 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. @@ -497,6 +498,8 @@ clear_bss: */ .globl trap_init trap_init: + mflr r4 /* save link register */ + GET_GOT lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) @@ -504,8 +507,6 @@ trap_init: cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ 1: lwz r0, 0(r7) stw r0, 0(r9) diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index 075a7dd..d499da5 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -56,7 +56,7 @@ /* * Set up GOT: Global Offset Table * - * Use r14 to access the GOT + * Use r12 to access the GOT */ START_GOT GOT_ENTRY(_GOT2_TABLE_) @@ -567,6 +567,7 @@ relocate_code: mr r9, r4 /* Save copy of Global Data pointer */ mr r10, r5 /* Save copy of Destination Address */ + GET_GOT mr r3, r5 /* Destination Address */ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l @@ -584,7 +585,7 @@ relocate_code: sub r15, r10, r4 /* First our own GOT */ - add r14, r14, r15 + add r12, r12, r15 /* then the one used by the C code */ add r30, r30, r15 @@ -657,7 +658,7 @@ relocate_code: in_ram: /* - * Relocation Function, r14 point to got2+0x8000 + * Relocation Function, r12 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. @@ -722,6 +723,8 @@ clear_bss: */ .globl trap_init trap_init: + mflr r4 /* save link register */ + GET_GOT lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) @@ -729,8 +732,6 @@ trap_init: cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ 1: lwz r0, 0(r7) stw r0, 0(r9) diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S index 5218c85..e28999d 100644 --- a/cpu/mpc8220/start.S +++ b/cpu/mpc8220/start.S @@ -55,7 +55,7 @@ /* * Set up GOT: Global Offset Table * - * Use r14 to access the GOT + * Use r12 to access the GOT */ START_GOT GOT_ENTRY(_GOT2_TABLE_) @@ -532,6 +532,7 @@ relocate_code: mr r9, r4 /* Save copy of Global Data pointer */ mr r10, r5 /* Save copy of Destination Address */ + GET_GOT mr r3, r5 /* Destination Address */ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l @@ -549,7 +550,7 @@ relocate_code: sub r15, r10, r4 /* First our own GOT */ - add r14, r14, r15 + add r12, r12, r15 /* then the one used by the C code */ add r30, r30, r15 @@ -622,7 +623,7 @@ relocate_code: in_ram: /* - * Relocation Function, r14 point to got2+0x8000 + * Relocation Function, r12 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. @@ -687,6 +688,8 @@ clear_bss: */ .globl trap_init trap_init: + mflr r4 /* save link register */ + GET_GOT lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) @@ -694,8 +697,6 @@ trap_init: cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ 1: lwz r0, 0(r7) stw r0, 0(r9) diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S index 7f40648..f3f595a 100644 --- a/cpu/mpc824x/start.S +++ b/cpu/mpc824x/start.S @@ -63,7 +63,7 @@ /* * Set up GOT: Global Offset Table * - * Use r14 to access the GOT + * Use r12 to access the GOT */ START_GOT GOT_ENTRY(_GOT2_TABLE_) @@ -462,6 +462,7 @@ relocate_code: mr r9, r4 /* Save copy of Global Data pointer */ mr r10, r5 /* Save copy of Destination Address */ + GET_GOT mr r3, r5 /* Destination Address */ #ifdef CONFIG_SYS_RAMBOOT lis r4, CONFIG_SYS_SDRAM_BASE@h /* Source Address */ @@ -484,7 +485,7 @@ relocate_code: sub r15, r10, r4 /* First our own GOT */ - add r14, r14, r15 + add r12, r12, r15 /* the the one used by the C code */ add r30, r30, r15 @@ -564,7 +565,7 @@ relocate_code: in_ram: /* - * Relocation Function, r14 point to got2+0x8000 + * Relocation Function, r12 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. @@ -629,6 +630,8 @@ clear_bss: */ .globl trap_init trap_init: + mflr r4 /* save link register */ + GET_GOT lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) @@ -636,8 +639,6 @@ trap_init: cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ 1: lwz r0, 0(r7) stw r0, 0(r9) diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index 7d80af5..1fc70bc 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -56,7 +56,7 @@ /* * Set up GOT: Global Offset Table * - * Use r14 to access the GOT + * Use r12 to access the GOT */ START_GOT GOT_ENTRY(_GOT2_TABLE_) @@ -650,7 +650,9 @@ init_debug: /* RAM should now be operational */ #define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4) - + mflr r3 + GET_GOT + mtlr r3 lwz r3, GOT(_end_of_vectors) rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */ lis r5, VEC_WRD_CNT@h @@ -792,6 +794,7 @@ relocate_code: mr r9, r4 /* Save copy of Global Data pointer */ mr r10, r5 /* Save copy of Destination Address */ + GET_GOT mr r3, r5 /* Destination Address */ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l @@ -809,7 +812,7 @@ relocate_code: sub r15, r10, r4 /* First our own GOT */ - add r14, r14, r15 + add r12, r12, r15 /* then the one used by the C code */ add r30, r30, r15 @@ -882,7 +885,7 @@ relocate_code: in_ram: /* - * Relocation Function, r14 point to got2+0x8000 + * Relocation Function, r12 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. @@ -958,6 +961,8 @@ clear_bss: */ .globl trap_init trap_init: + mflr r4 /* save link register */ + GET_GOT lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) @@ -965,8 +970,6 @@ trap_init: cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ 1: lwz r0, 0(r7) stw r0, 0(r9) diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 5a50b09..68bb620 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -65,7 +65,7 @@ /* * Set up GOT: Global Offset Table * - * Use r14 to access the GOT + * Use r12 to access the GOT */ START_GOT GOT_ENTRY(_GOT2_TABLE_) @@ -830,6 +830,7 @@ relocate_code: mr r9, r4 /* Save copy of Global Data pointer */ mr r10, r5 /* Save copy of Destination Address */ + GET_GOT mr r3, r5 /* Destination Address */ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l @@ -848,7 +849,7 @@ relocate_code: sub r15, r10, r4 /* First our own GOT */ - add r14, r14, r15 + add r12, r12, r15 /* then the one used by the C code */ add r30, r30, r15 @@ -930,7 +931,7 @@ relocate_code: in_ram: /* - * Relocation Function, r14 point to got2+0x8000 + * Relocation Function, r12 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. @@ -1010,6 +1011,8 @@ clear_bss: */ .globl trap_init trap_init: + mflr r4 /* save link register */ + GET_GOT lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) @@ -1017,8 +1020,6 @@ trap_init: cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ 1: lwz r0, 0(r7) stw r0, 0(r9) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index d73c5c2..386fa81 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -51,7 +51,7 @@ /* * Set up GOT: Global Offset Table * - * Use r14 to access the GOT + * Use r12 to access the GOT */ START_GOT GOT_ENTRY(_GOT2_TABLE_) @@ -871,6 +871,7 @@ relocate_code: mr r9,r4 /* Save copy of Init Data pointer */ mr r10,r5 /* Save copy of Destination Address */ + GET_GOT mr r3,r5 /* Destination Address */ lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4,r4,CONFIG_SYS_MONITOR_BASE@l @@ -888,7 +889,7 @@ relocate_code: sub r15,r10,r4 /* First our own GOT */ - add r14,r14,r15 + add r12,r12,r15 /* the the one used by the C code */ add r30,r30,r15 @@ -958,7 +959,7 @@ relocate_code: in_ram: /* - * Relocation Function, r14 point to got2+0x8000 + * Relocation Function, r12 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. @@ -1024,6 +1025,8 @@ clear_bss: */ .globl trap_init trap_init: + mflr r4 /* save link register */ + GET_GOT lwz r7,GOT(_start_of_vectors) lwz r8,GOT(_end_of_vectors) @@ -1031,8 +1034,6 @@ trap_init: cmplw 0,r7,r8 bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ 1: lwz r0,0(r7) stw r0,0(r9) diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index eaa2657..ed1e4ca 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -52,7 +52,7 @@ /* * Set up GOT: Global Offset Table * - * Use r14 to access the GOT + * Use r12 to access the GOT */ START_GOT GOT_ENTRY(_GOT2_TABLE_) @@ -630,6 +630,7 @@ relocate_code: mr r9, r4 /* Save copy of Global Data pointer */ mr r10, r5 /* Save copy of Destination Address */ + GET_GOT mr r3, r5 /* Destination Address */ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l @@ -647,7 +648,7 @@ relocate_code: sub r15, r10, r4 /* First our own GOT */ - add r14, r14, r15 + add r12, r12, r15 /* then the one used by the C code */ add r30, r30, r15 @@ -708,7 +709,7 @@ relocate_code: in_ram: /* - * Relocation Function, r14 point to got2+0x8000 + * Relocation Function, r12 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. @@ -775,6 +776,8 @@ in_ram: */ .globl trap_init trap_init: + mflr r4 /* save link register */ + GET_GOT lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) @@ -782,8 +785,6 @@ trap_init: cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ 1: lwz r0, 0(r7) stw r0, 0(r9) diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S index 24e9053..7cf602f 100644 --- a/cpu/mpc8xx/start.S +++ b/cpu/mpc8xx/start.S @@ -63,7 +63,7 @@ /* * Set up GOT: Global Offset Table * - * Use r14 to access the GOT + * Use r12 to access the GOT */ START_GOT GOT_ENTRY(_GOT2_TABLE_) @@ -482,6 +482,7 @@ relocate_code: mr r9, r4 /* Save copy of Global Data pointer */ mr r10, r5 /* Save copy of Destination Address */ + GET_GOT mr r3, r5 /* Destination Address */ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l @@ -499,7 +500,7 @@ relocate_code: sub r15, r10, r4 /* First our own GOT */ - add r14, r14, r15 + add r12, r12, r15 /* then the one used by the C code */ add r30, r30, r15 @@ -564,7 +565,7 @@ relocate_code: in_ram: /* - * Relocation Function, r14 point to got2+0x8000 + * Relocation Function, r12 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. @@ -629,6 +630,8 @@ clear_bss: */ .globl trap_init trap_init: + mflr r4 /* save link register */ + GET_GOT lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) @@ -636,8 +639,6 @@ trap_init: cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ 1: lwz r0, 0(r7) stw r0, 0(r9) diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 2eb21fa..927c88c 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -228,7 +228,7 @@ /* * Set up GOT: Global Offset Table * - * Use r14 to access the GOT + * Use r12 to access the GOT */ #if !defined(CONFIG_NAND_SPL) START_GOT @@ -1489,6 +1489,7 @@ relocate_code: mr r9, r4 /* Save copy of Init Data pointer */ mr r10, r5 /* Save copy of Destination Address */ + GET_GOT mr r3, r5 /* Destination Address */ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l @@ -1506,7 +1507,7 @@ relocate_code: sub r15, r10, r4 /* First our own GOT */ - add r14, r14, r15 + add r12, r12, r15 /* then the one used by the C code */ add r30, r30, r15 @@ -1571,7 +1572,7 @@ relocate_code: in_ram: /* - * Relocation Function, r14 point to got2+0x8000 + * Relocation Function, r12 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. @@ -1645,6 +1646,8 @@ clear_bss: */ .globl trap_init trap_init: + mflr r4 /* save link register */ + GET_GOT lwz r7, GOT(_start_of_vectors) lwz r8, GOT(_end_of_vectors) @@ -1652,8 +1655,6 @@ trap_init: cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ 1: lwz r0, 0(r7) stw r0, 0(r9) diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index fa5c5f6..84de146 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -50,13 +50,13 @@ .text 2 ; \ 0: .long .LCTOC1-1f ; \ .text ; \ -1: mflr r14 ; \ - lwz r0,0b-1b(r14) ; \ - add r14,r0,r14 ; +1: mflr r12 ; \ + lwz r0,0b-1b(r12) ; \ + add r12,r0,r12 ; #define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME -#define GOT(NAME) .L_ ## NAME (r14) +#define GOT(NAME) .L_ ## NAME (r12) /*************************************************************************** -- cgit v1.1 From e6bee80814c3a0d7eab89d28142fe68c4a670f31 Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Tue, 19 Jan 2010 14:41:58 +0100 Subject: ppc: Update README about the new GOT ptr. r14 is no longer used as non volatile GOT ptr. Instead the volatile r12 is used so be sure to do GET_GOT in asm code when you need to access global data. Signed-off-by: Joakim Tjernlund --- README | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/README b/README index 7affe10..263bb05 100644 --- a/README +++ b/README @@ -3922,7 +3922,9 @@ For PowerPC, the following registers have specific use: R30: GOT pointer R31: frame pointer - (U-Boot also uses R14 as internal GOT pointer.) + (U-Boot also uses R12 as internal GOT pointer. r12 + is a volatile register so r12 needs to be reset when + going back and forth between asm and C) ==> U-Boot will use R2 to hold a pointer to the global data -- cgit v1.1 From a16e9a5b5f23106665dde15d974db17e8aeb83f1 Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Tue, 19 Jan 2010 14:41:57 +0100 Subject: ppc: remove -ffixed-r14 gcc option. This is no loger needed, free up r14 for general usage. Signed-off-by: Joakim Tjernlund --- cpu/74xx_7xx/config.mk | 2 +- cpu/mpc512x/config.mk | 2 +- cpu/mpc5xx/config.mk | 2 +- cpu/mpc5xxx/config.mk | 2 +- cpu/mpc8220/config.mk | 2 +- cpu/mpc824x/config.mk | 2 +- cpu/mpc8260/config.mk | 2 +- cpu/mpc83xx/config.mk | 2 +- cpu/mpc85xx/config.mk | 2 +- cpu/mpc86xx/config.mk | 2 +- cpu/mpc8xx/config.mk | 2 +- cpu/ppc4xx/config.mk | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/cpu/74xx_7xx/config.mk b/cpu/74xx_7xx/config.mk index d589210..df1f6ac 100644 --- a/cpu/74xx_7xx/config.mk +++ b/cpu/74xx_7xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk index 6ab34b1..fb0a563 100644 --- a/cpu/mpc512x/config.mk +++ b/cpu/mpc512x/config.mk @@ -19,7 +19,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ -ffixed-r2 -msoft-float -mcpu=603e diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk index 157ddc5..7854924 100644 --- a/cpu/mpc5xx/config.mk +++ b/cpu/mpc5xx/config.mk @@ -28,7 +28,7 @@ # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float diff --git a/cpu/mpc5xxx/config.mk b/cpu/mpc5xxx/config.mk index b0ce2ee..5e82f67 100644 --- a/cpu/mpc5xxx/config.mk +++ b/cpu/mpc5xxx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \ -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc8220/config.mk b/cpu/mpc8220/config.mk index 5819048..3ce40c0 100644 --- a/cpu/mpc8220/config.mk +++ b/cpu/mpc8220/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \ -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk index b607fee..940474b 100644 --- a/cpu/mpc824x/config.mk +++ b/cpu/mpc824x/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float diff --git a/cpu/mpc8260/config.mk b/cpu/mpc8260/config.mk index 2cb0270..39d81ee 100644 --- a/cpu/mpc8260/config.mk +++ b/cpu/mpc8260/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \ -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk index d619426..e80919b 100644 --- a/cpu/mpc83xx/config.mk +++ b/cpu/mpc83xx/config.mk @@ -20,7 +20,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 \ -ffixed-r2 -msoft-float diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk index 84651b8..408184a 100644 --- a/cpu/mpc85xx/config.mk +++ b/cpu/mpc85xx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string diff --git a/cpu/mpc86xx/config.mk b/cpu/mpc86xx/config.mk index 13da2cf..ca2f837 100644 --- a/cpu/mpc86xx/config.mk +++ b/cpu/mpc86xx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -ffixed-r2 -mstring PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float diff --git a/cpu/mpc8xx/config.mk b/cpu/mpc8xx/config.mk index 2b3d545..5540d65 100644 --- a/cpu/mpc8xx/config.mk +++ b/cpu/mpc8xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk index 979004b..c1de1e9 100644 --- a/cpu/ppc4xx/config.mk +++ b/cpu/ppc4xx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -- cgit v1.1 From 5912d3650740468329a0df014109132431d2140d Mon Sep 17 00:00:00 2001 From: Wolfgang Wegner Date: Thu, 10 Dec 2009 10:11:21 +0100 Subject: add ability to handle compressed images to imxtract imxtract currently can not handle compressed images. This patch adds handling for bzip2 and zip compression. In both cases, a destination address has to be specified for extraction. Signed-off-by: Wolfgang Wegner --- common/cmd_ximg.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 85 insertions(+), 7 deletions(-) diff --git a/common/cmd_ximg.c b/common/cmd_ximg.c index 5593b2d..3e5fb44 100644 --- a/common/cmd_ximg.c +++ b/common/cmd_ximg.c @@ -31,8 +31,17 @@ #include #include #include +#include +#if defined(CONFIG_BZIP2) +#include +#endif #include +#ifndef CONFIG_SYS_XIMG_LEN +/* use 8MByte as default max gunzip size */ +#define CONFIG_SYS_XIMG_LEN 0x800000 +#endif + int do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { @@ -50,6 +59,8 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) const void *fit_data; size_t fit_len; #endif + uint unc_len = CONFIG_SYS_XIMG_LEN; + uint8_t comp; verify = getenv_yesno ("verify"); @@ -92,8 +103,10 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } - if (image_get_comp (hdr) != IH_COMP_NONE) { - printf("Wrong Compression Type for %s command\n", + comp = image_get_comp (hdr); + if ((comp != IH_COMP_NONE) && (argc < 4)) { + printf("Must specify load address for %s command " + "with compressed image\n", cmdtp->name); return 1; } @@ -138,9 +151,11 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } - if (fit_image_check_comp (fit_hdr, noffset, IH_COMP_NONE)) { - printf("Wrong Compression Type for %s command\n", - cmdtp->name); + if (fit_image_check_comp (fit_hdr, noffset, IH_COMP_NONE) + && (argc < 4)) { + printf("Must specify load address for %s command " + "with compressed image\n", + cmdtp->name); return 1; } @@ -153,11 +168,18 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } /* get subimage data address and length */ - if (fit_image_get_data (fit_hdr, noffset, &fit_data, &fit_len)) { + if (fit_image_get_data (fit_hdr, noffset, + &fit_data, &fit_len)) { puts ("Could not find script subimage data\n"); return 1; } + if (fit_image_get_comp (fit_hdr, noffset, &comp)) { + puts ("Could not find script subimage " + "compression type\n"); + return 1; + } + data = (ulong)fit_data; len = (ulong)fit_len; break; @@ -168,7 +190,63 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } if (argc > 3) { - memcpy((char *) dest, (char *) data, len); + switch (comp) { + case IH_COMP_NONE: +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + { + size_t l = len; + size_t tail; + void *to = (void *) dest; + void *from = (void *)data; + + printf (" Loading part %d ... ", part); + + while (l > 0) { + tail = (l > CHUNKSZ) ? CHUNKSZ : l; + WATCHDOG_RESET(); + memmove (to, from, tail); + to += tail; + from += tail; + l -= tail; + } + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + printf (" Loading part %d ... ", part); + memmove ((char *) dest, (char *)data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + break; + case IH_COMP_GZIP: + printf (" Uncompressing part %d ... ", part); + if (gunzip ((void *) dest, unc_len, + (uchar *) data, &len) != 0) { + puts ("GUNZIP ERROR - image not loaded\n"); + return 1; + } + break; +#if defined(CONFIG_BZIP2) + case IH_COMP_BZIP2: + printf (" Uncompressing part %d ... ", part); + /* + * If we've got less than 4 MB of malloc() space, + * use slower decompression algorithm which requires + * at most 2300 KB of memory. + */ + i = BZ2_bzBuffToBuffDecompress + ((char*)ntohl(hdr->ih_load), + &unc_len, (char *)data, len, + CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0); + if (i != BZ_OK) { + printf ("BUNZIP2 ERROR %d - " + "image not loaded\n", i); + return 1; + } + break; +#endif /* CONFIG_BZIP2 */ + default: + printf ("Unimplemented compression type %d\n", comp); + return 1; + } + puts ("OK\n"); } sprintf(pbuf, "%8lx", data); -- cgit v1.1 From 8b1760ed9a35a5fd71d1f64981068ca2979f1e3d Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 20 Jan 2010 09:05:32 +0100 Subject: 83xx, kmeter1: fix compile error - delete double MTDIDS_DEFAULT and MTDPARTS_DEFAULT defines in board config file. - add mising CONFIG_KM_UBI_PARTITION_NAME define Signed-off-by: Heiko Schocher Signed-off-by: Kim Phillips --- include/configs/kmeter1.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 71658d8..0327b97 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -33,6 +33,8 @@ /* include common defines/options for all Keymile boards */ #include "keymile-common.h" +#define CONFIG_KM_UBI_PARTITION_NAME "ubi0" + #define MTDIDS_DEFAULT "nor0=boot" #define MTDPARTS_DEFAULT \ "mtdparts=boot:768k(u-boot),128k(env),128k(envred)," \ @@ -449,11 +451,6 @@ #define CONFIG_PRAM 512 /* protected RAM [KBytes] */ -#define MTDIDS_DEFAULT "nor2=app" -#define MTDPARTS_DEFAULT \ - "mtdparts=app:256k(u-boot),128k(env),128k(envred)," \ - "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)" - /* * Environment Configuration */ -- cgit v1.1 From 4194b3668a93eee18dd1f7eb1309ca7b05003aa7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 12 Jan 2010 11:42:43 -0600 Subject: Add support to disable cpu's in multicore processors Add a disable sub-command to the cpu command that allows for disabling cores in multicore processors. This can be useful for systems that are using multicore chips but aren't utilizing all the cores as a way to reduce power and possibly improve performance. Also updated an added missing copyright. Signed-off-by: Kumar Gala --- common/cmd_mp.c | 3 +++ cpu/mpc85xx/mp.c | 8 +++++++- cpu/mpc86xx/mp.c | 28 ++++++++++++++++++++++++++++ include/common.h | 1 + 4 files changed, 39 insertions(+), 1 deletion(-) diff --git a/common/cmd_mp.c b/common/cmd_mp.c index 71e4303..d78c209 100644 --- a/common/cmd_mp.c +++ b/common/cmd_mp.c @@ -46,6 +46,8 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) cpu_reset(cpuid); } else if (strncmp(argv[2], "status", 6) == 0) { cpu_status(cpuid); + } else if (strncmp(argv[2], "disable", 7) == 0) { + return cpu_disable(cpuid); } else { cmd_usage(cmdtp); return 1; @@ -86,6 +88,7 @@ U_BOOT_CMD( "Multiprocessor CPU boot manipulation and release", " reset - Reset cpu \n" "cpu status - Status of cpu \n" + "cpu disable - Disable cpu \n" "cpu release [args] - Release cpu at with [args]" #ifdef CPU_ARCH_HELP "\n" diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 6530cb1..6ae7f0a 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -68,6 +68,12 @@ int cpu_status(int nr) return 0; } +int cpu_disable(int nr) +{ + /* dummy function so common/cmd_mp.c will build */ + return 1; +} + static u8 boot_entry_map[4] = { 0, BOOT_ENTRY_PIR, diff --git a/cpu/mpc86xx/mp.c b/cpu/mpc86xx/mp.c index 2940673..ecdf2fb 100644 --- a/cpu/mpc86xx/mp.c +++ b/cpu/mpc86xx/mp.c @@ -1,3 +1,25 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #include #include #include @@ -24,6 +46,12 @@ int cpu_status(int nr) return 0; } +int cpu_disable(int nr) +{ + /* dummy function so common/cmd_mp.c will build */ + return 1; +} + int cpu_release(int nr, int argc, char *argv[]) { /* dummy function so common/cmd_mp.c will build diff --git a/include/common.h b/include/common.h index 391790a..81f2b59 100644 --- a/include/common.h +++ b/include/common.h @@ -712,6 +712,7 @@ void show_boot_progress(int val); #ifdef CONFIG_MP int cpu_status(int nr); int cpu_reset(int nr); +int cpu_disable(int nr); int cpu_release(int nr, int argc, char *argv[]); #endif -- cgit v1.1 From c894852b7aa2ac5f04ca70a073f803aa665c3ec1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 12 Jan 2010 11:51:52 -0600 Subject: 86xx: Add support for 'cpu disable' command Support disabling of a core via user command 'cpu disable'. Signed-off-by: Kumar Gala --- cpu/mpc86xx/mp.c | 18 ++++++++++++++++-- include/asm-ppc/immap_86xx.h | 33 ++++++++++++++++++--------------- 2 files changed, 34 insertions(+), 17 deletions(-) diff --git a/cpu/mpc86xx/mp.c b/cpu/mpc86xx/mp.c index ecdf2fb..b4a0faa 100644 --- a/cpu/mpc86xx/mp.c +++ b/cpu/mpc86xx/mp.c @@ -48,8 +48,22 @@ int cpu_status(int nr) int cpu_disable(int nr) { - /* dummy function so common/cmd_mp.c will build */ - return 1; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + + switch (nr) { + case 0: + setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0); + break; + case 1: + setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1); + break; + default: + printf("Invalid cpu number for disable %d\n", nr); + return 1; + } + + return 0; } int cpu_release(int nr, int argc, char *argv[]) diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 098f253..fd7acdb 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -1186,17 +1186,8 @@ typedef struct ccsr_rio { typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ uint porbmsr; /* 0xe0004 - POR boot mode status register */ -#define MPC8610_PORBMSR_HA 0x00070000 -#define MPC8610_PORBMSR_HA_SHIFT 16 -#define MPC8641_PORBMSR_HA 0x00060000 -#define MPC8641_PORBMSR_HA_SHIFT 17 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ -#define MPC8610_PORDEVSR_IO_SEL 0x00380000 -#define MPC8610_PORDEVSR_IO_SEL_SHIFT 19 -#define MPC8641_PORDEVSR_IO_SEL 0x000F0000 -#define MPC8641_PORDEVSR_IO_SEL_SHIFT 16 -#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */ uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ char res1[12]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ @@ -1210,11 +1201,6 @@ typedef struct ccsr_gur { uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ -#define MPC86xx_DEVDISR_PCIEX1 0x80000000 -#define MPC86xx_DEVDISR_PCIEX2 0x40000000 -#define MPC86xx_DEVDISR_PCI1 0x80000000 -#define MPC86xx_DEVDISR_PCIE1 0x40000000 -#define MPC86xx_DEVDISR_PCIE2 0x20000000 char res7[12]; uint powmgtcsr; /* 0xe0080 - Power management status and control register */ char res8[12]; @@ -1225,7 +1211,6 @@ typedef struct ccsr_gur { uint svr; /* 0xe00a4 - System version register */ char res10a[8]; uint rstcr; /* 0xe00b0 - Reset control register */ -#define MPC86xx_RSTCR_HRST_REQ 0x00000002 char res10b[1868]; uint clkdvdr; /* 0xe0800 - Clock Divide register */ char res10c[796]; @@ -1250,6 +1235,24 @@ typedef struct ccsr_gur { char res16[184]; } ccsr_gur_t; +#define MPC8610_PORBMSR_HA 0x00070000 +#define MPC8610_PORBMSR_HA_SHIFT 16 +#define MPC8641_PORBMSR_HA 0x00060000 +#define MPC8641_PORBMSR_HA_SHIFT 17 +#define MPC8610_PORDEVSR_IO_SEL 0x00380000 +#define MPC8610_PORDEVSR_IO_SEL_SHIFT 19 +#define MPC8641_PORDEVSR_IO_SEL 0x000F0000 +#define MPC8641_PORDEVSR_IO_SEL_SHIFT 16 +#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */ +#define MPC86xx_DEVDISR_PCIEX1 0x80000000 +#define MPC86xx_DEVDISR_PCIEX2 0x40000000 +#define MPC86xx_DEVDISR_PCI1 0x80000000 +#define MPC86xx_DEVDISR_PCIE1 0x40000000 +#define MPC86xx_DEVDISR_PCIE2 0x20000000 +#define MPC86xx_DEVDISR_CPU0 0x00008000 +#define MPC86xx_DEVDISR_CPU1 0x00004000 +#define MPC86xx_RSTCR_HRST_REQ 0x00000002 + /* * Watchdog register block(0xe_4000-0xe_4fff) */ -- cgit v1.1 From a9c3ac78d81d7ff4fe239e292e11e0f78ac5d461 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 12 Jan 2010 12:56:05 -0600 Subject: 85xx: Add support for 'cpu disable' command Support disabling of a core via user command 'cpu disable'. Signed-off-by: Kumar Gala --- cpu/mpc85xx/mp.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 6ae7f0a..826bf32 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -68,11 +68,35 @@ int cpu_status(int nr) return 0; } +#ifdef CONFIG_FSL_CORENET +int cpu_disable(int nr) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->coredisrl, 1 << nr); + + return 0; +} +#else int cpu_disable(int nr) { - /* dummy function so common/cmd_mp.c will build */ - return 1; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + switch (nr) { + case 0: + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0); + break; + case 1: + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1); + break; + default: + printf("Invalid cpu number for disable %d\n", nr); + return 1; + } + + return 0; } +#endif static u8 boot_entry_map[4] = { 0, -- cgit v1.1 From 249d4dec69e8d41ca58fe6cb3c56ea6f0480ef16 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 27 Jan 2010 10:16:56 -0600 Subject: Fix compiler warning in imximage.c due to getline prototype imximage.c: In function 'imximage_parse_cfg_file': imximage.c:142: warning: implicit declaration of function 'getline' Signed-off-by: Kumar Gala --- tools/imximage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/imximage.c b/tools/imximage.c index c1fdafb..59923ff 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -25,6 +25,9 @@ * MA 02111-1307 USA */ +/* Required to obtain the getline prototype from stdio.h */ +#define _GNU_SOURCE + #include "mkimage.h" #include #include "imximage.h" -- cgit v1.1 From 1be2890d8b5ce629cd0b0ce4ff35d05495749c7e Mon Sep 17 00:00:00 2001 From: Daniel Gorsulowski Date: Mon, 25 Jan 2010 10:50:41 +0100 Subject: at91: Add esd gmbh OTC570 board support This patch adds support for esd gmbh OTC570 board. The OTC570 is based on an Atmel AT91SAM9263 SoC. Signed-off-by: Daniel Gorsulowski --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/esd/otc570/Makefile | 55 +++++++ board/esd/otc570/config.mk | 1 + board/esd/otc570/otc570.c | 365 +++++++++++++++++++++++++++++++++++++++++++ board/esd/otc570/partition.c | 37 +++++ include/configs/otc570.h | 246 +++++++++++++++++++++++++++++ tools/Makefile | 3 + tools/logos/esd.bmp | Bin 0 -> 35078 bytes 10 files changed, 712 insertions(+) create mode 100644 board/esd/otc570/Makefile create mode 100644 board/esd/otc570/config.mk create mode 100644 board/esd/otc570/otc570.c create mode 100644 board/esd/otc570/partition.c create mode 100644 include/configs/otc570.h create mode 100644 tools/logos/esd.bmp diff --git a/MAINTAINERS b/MAINTAINERS index e8ba4bc..0c2b1b1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -574,6 +574,7 @@ Peter Figuli Daniel Gorsulowski meesc ARM926EJS (AT91SAM9263 SoC) + otc570 ARM926EJS (AT91SAM9263 SoC) Sedji Gaouaou at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC) diff --git a/MAKEALL b/MAKEALL index 15e93cf..506dc78 100755 --- a/MAKEALL +++ b/MAKEALL @@ -659,6 +659,7 @@ LIST_at91=" \ meesc \ mp2usb \ m501sk \ + otc570 \ pm9261 \ pm9263 \ SBC35_A9G20 \ diff --git a/Makefile b/Makefile index 69b963f..628bcdb 100644 --- a/Makefile +++ b/Makefile @@ -2872,6 +2872,9 @@ at91sam9g45ekes_config : unconfig fi; @$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91 +otc570_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs otc570 esd at91 + pm9263_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91 diff --git a/board/esd/otc570/Makefile b/board/esd/otc570/Makefile new file mode 100644 index 0000000..755c5ee --- /dev/null +++ b/board/esd/otc570/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/esd/otc570/config.mk b/board/esd/otc570/config.mk new file mode 100644 index 0000000..ff2cfd1 --- /dev/null +++ b/board/esd/otc570/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c new file mode 100644 index 0000000..056df37 --- /dev/null +++ b/board/esd/otc570/otc570.c @@ -0,0 +1,365 @@ +/* + * (C) Copyright 2010 + * Daniel Gorsulowski + * esd electronic system design gmbh + * + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_LCD_INFO +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ + +static int hw_rev = -1; /* hardware revision */ + +int get_hw_rev(void) +{ + if (hw_rev >= 0) + return hw_rev; + + hw_rev = at91_get_gpio_value(AT91_PIN_PB19); + hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1; + hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2; + hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3; + + if (hw_rev == 15) + hw_rev = 0; + + return hw_rev; +} + +#ifdef CONFIG_CMD_NAND +static void otc570_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBI0CSA); + at91_sys_write(AT91_MATRIX_EBI0CSA, + csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_DBW_8 | + AT91_SMC_TDF_(2)); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif /* CONFIG_CMD_NAND */ + +#ifdef CONFIG_MACB +static void otc570_macb_hw_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + at91_macb_hw_init(); +} +#endif + +/* + * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT + * controller debugging + * The ET1100 is located at physical address 0x70000000 + * Its process memory is located at physical address 0x70001000 + */ +static void otc570_ethercat_hw_init(void) +{ + /* Configure SMC EBI1_CS0 for EtherCAT */ + at91_sys_write(AT91_SMC1_SETUP(0), + AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC1_PULSE(0), + AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) | + AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(9)); + at91_sys_write(AT91_SMC1_CYCLE(0), + AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(6)); + /* + * Configure behavior at external wait signal, byte-select mode, 16 bit + * data bus width, none data float wait states and TDF optimization + */ + at91_sys_write(AT91_SMC1_MODE(0), + AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY | + AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) | + AT91_SMC_TDFMODE); + + /* Configure RDY/BSY */ + at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */ +} + +#ifdef CONFIG_LCD +/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */ +vidinfo_t panel_info = { + .vl_col = 640, + .vl_row = 480, + .vl_clk = 25175000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + + .vl_bpix = 3, /* Bits per pixel, 0 = 1bit, 3 = 8bit */ + .vl_tft = 1, /* 0 = passive, 1 = TFT */ + .vl_vsync_len = 1, /* Length of vertical sync in NOL */ + .vl_upper_margin = 35, /* Idle lines at the frame start */ + .vl_lower_margin = 5, /* Idle lines at the end of the frame */ + .vl_hsync_len = 5, /* Width of the LCDHSYNC pulse */ + .vl_left_margin = 112, /* Idle cycles at the line beginning */ + .vl_right_margin = 1, /* Idle cycles at the end of the line */ + + .mmio = AT91SAM9263_LCDC_BASE, +}; + +void lcd_enable(void) +{ + at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ +} + +static void otc570_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ + at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ + at91_set_gpio_output(AT91_PIN_PA30, 1); /* PCI */ + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC); + + gd->fb_base = CONFIG_OTC570_LCD_BASE; +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; + + lcd_printf("\n%s\n", U_BOOT_VERSION); + lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME, + strmhz(temp, get_cpu_clk_rate())); + lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, + nand_size >> 20 ); + lcd_printf(" Board : esd ARM9 HMI Panel - OTC570\n"); + lcd_printf(" Hardware-revision: 1.%d\n", get_hw_rev()); + lcd_printf(" Mach-type : %lu\n", gd->bd->bi_arch_number); +} +#endif /* CONFIG_LCD_INFO */ +#endif /* CONFIG_LCD */ + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27)); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); +#endif + return rc; +} + +int checkboard(void) +{ + char str[32]; + + puts("Board: esd ARM9 HMI Panel - OTC570"); + if (getenv_r("serial#", str, sizeof(str)) > 0) { + puts(", serial# "); + puts(str); + } + printf("\nHardware-revision: 1.%d\n", get_hw_rev()); + printf("Mach-type: %lu\n", gd->bd->bi_arch_number); + return 0; +} + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *str; + + char *serial = getenv("serial#"); + if (serial) { + str = strchr(serial, '_'); + if (str && (strlen(str) >= 4)) { + serialnr->high = (*(str + 1) << 8) | *(str + 2); + serialnr->low = simple_strtoul(str + 3, NULL, 16); + } + } else { + serialnr->high = 0; + serialnr->low = 0; + } +} +#endif + +#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void) +{ + return hw_rev | 0x100; +} +#endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + char str[64]; + + at91_set_gpio_output(AT91_PIN_PA29, 1); + at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0); + /* Set USART_MODE = 1 (RS485) */ + at91_sys_write((0xFFF8C004 - AT91_BASE_SYS), 1); + + printf("USART0: "); + + if (getenv_r("usart0", str, sizeof(str)) == -1) { + printf("No entry - assuming 1-wire\n"); + /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */ + at91_set_gpio_output(AT91_PIN_PA29, 0); + } else { + if (strcmp(str, "1-wire") == 0) { + printf("%s\n", str); + at91_set_gpio_output(AT91_PIN_PA29, 0); + } else if (strcmp(str, "rs485") == 0) { + printf("%s\n", str); + at91_set_gpio_output(AT91_PIN_PA29, 1); + } else { + printf("Wrong entry - assuming 1-wire "); + printf("(valid values are '1-wire' or 'rs485')\n"); + at91_set_gpio_output(AT91_PIN_PA29, 0); + } + } + printf("Display memory address: 0x%08lX\n", gd->fb_base); + + return 0; +} +#endif /* CONFIG_MISC_INIT_R */ + +int board_init(void) +{ + /* Peripheral Clock Enable Register */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | + 1 << AT91SAM9263_ID_PIOB | + 1 << AT91SAM9263_ID_PIOCDE | + 1 << AT91SAM9263_ID_TWI | + 1 << AT91SAM9263_ID_SPI0 | + 1 << AT91SAM9263_ID_LCDC | + 1 << AT91SAM9263_ID_UHP); + + /* arch number of OTC570-Board */ + gd->bd->bi_arch_number = MACH_TYPE_OTC570; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + otc570_nand_hw_init(); +#endif + otc570_ethercat_hw_init(); +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_MACB + otc570_macb_hw_init(); +#endif +#ifdef CONFIG_AT91_CAN + at91_can_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif +#ifdef CONFIG_LCD + otc570_lcd_hw_init(); +#endif + return 0; +} diff --git a/board/esd/otc570/partition.c b/board/esd/otc570/partition.c new file mode 100644 index 0000000..df0e1db --- /dev/null +++ b/board/esd/otc570/partition.c @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2008 + * Ulf Samuelsson + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include +#include +#include + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/* define the area offsets */ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, +}; diff --git a/include/configs/otc570.h b/include/configs/otc570.h new file mode 100644 index 0000000..bedaf13 --- /dev/null +++ b/include/configs/otc570.h @@ -0,0 +1,246 @@ +/* + * (C) Copyright 2010 + * Daniel Gorsulowski + * esd electronic system design gmbh + * + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the esd OTC570 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Common stuff */ +#define CONFIG_OTC570 1 /* Board is esd OTC570 */ +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq */ +#define CONFIG_DISPLAY_BOARDINFO 1 +#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_SERIAL_TAG 1 +#define CONFIG_REVISION_TAG 1 +#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */ + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +#define CONFIG_ARCH_CPU_INIT + +/* + * Hardware drivers + */ + +/* Console output */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 + +#undef CONFIG_SPLASH_SCREEN + +#ifndef CONFIG_SPLASH_SCREEN +#define CONFIG_LCD_LOGO 1 +#define CONFIG_LCD_INFO 1 +#undef CONFIG_LCD_INFO_BELOW_LOGO +#endif /* CONFIG_SPLASH_SCREEN */ + +#undef LCD_TEST_PATTERN +#define CONFIG_SYS_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#define CONFIG_OTC570_LCD_BASE 0x23E00000 /* LCD is in SDRAM */ +#define CONFIG_CMD_BMP 1 + +/* RTC and I2C stuff */ +#define CONFIG_RTC_DS1338 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#undef CONFIG_HARD_I2C +#define CONFIG_SOFT_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x7F + +#ifdef CONFIG_SOFT_I2C +#define CONFIG_I2C_CMD_TREE 1 +#define CONFIG_I2C_MULTI_BUS 1 +/* Enable peripheral clock and configure data and clock pins for pio */ +#define I2C_INIT { \ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB | \ + 1 << AT91SAM9263_ID_PIOCDE); \ + at91_set_gpio_output(AT91_PIN_PB4, 0); \ + at91_set_gpio_output(AT91_PIN_PB5, 0); \ +} +/* Configure data pin as output */ +#define I2C_ACTIVE at91_set_gpio_output(AT91_PIN_PB4, 0) +/* Configure data pin as input */ +#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PB4, 0) +/* Read data pin */ +#define I2C_READ at91_get_gpio_value(AT91_PIN_PB4) +/* Set data pin */ +#define I2C_SDA(bit) at91_set_gpio_value(AT91_PIN_PB4, bit) +/* Set clock pin */ +#define I2C_SCL(bit) at91_set_gpio_value(AT91_PIN_PB5, bit) +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_I2C 1 +#define CONFIG_CMD_DATE 1 + +/* LED */ +#define CONFIG_AT91_LED 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 + +/* DataFlash */ +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NOR flash is not populated, disable it */ +#define CONFIG_SYS_NO_FLASH 1 + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#undef CONFIG_RESET_PHY_R + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_CMD_FAT 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +#define CONFIG_SYS_USE_DATAFLASH 1 +#undef CONFIG_SYS_USE_NANDFLASH + +/* CAN */ +#define CONFIG_AT91_CAN 1 + +/* hw-controller addresses */ +#define CONFIG_ET1100_BASE 0x70000000 + +/* bootstrap + u-boot + env in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ + 0x8400) +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x4200 + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ + 128*1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/tools/Makefile b/tools/Makefile index 266306e..743505f 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -112,6 +112,9 @@ endif ifeq ($(VENDOR),atmel) LOGO_BMP= logos/atmel.bmp endif +ifeq ($(VENDOR),esd) +LOGO_BMP= logos/esd.bmp +endif ifeq ($(VENDOR),ronetix) LOGO_BMP= logos/ronetix.bmp endif diff --git a/tools/logos/esd.bmp b/tools/logos/esd.bmp new file mode 100644 index 0000000..a6b4030 Binary files /dev/null and b/tools/logos/esd.bmp differ -- cgit v1.1 From d01b384f7c2dfedebbeadd94abf61ccaf5349ceb Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Wed, 27 Jan 2010 11:10:40 -0500 Subject: TI DaVinci: Driver for the davinci SPI controller This adds a driver for the SPI controller found on davinci based SoCs from Texas Instruments. Signed-off-by: Sekhar Nori Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Sandeep Paulraj --- drivers/spi/Makefile | 1 + drivers/spi/davinci_spi.c | 223 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/davinci_spi.h | 101 +++++++++++++++++++++ 3 files changed, 325 insertions(+) create mode 100644 drivers/spi/davinci_spi.c create mode 100644 drivers/spi/davinci_spi.h diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 824d8e7..f112ed0 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o COBJS-$(CONFIG_CF_SPI) += cf_spi.o +COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c new file mode 100644 index 0000000..ebc7f80 --- /dev/null +++ b/drivers/spi/davinci_spi.c @@ -0,0 +1,223 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Driver for SPI controller on DaVinci. Based on atmel_spi.c + * by Atmel Corporation + * + * Copyright (C) 2007 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include "davinci_spi.h" + +void spi_init() +{ + /* do nothing */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct davinci_spi_slave *ds; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ds = malloc(sizeof(*ds)); + if (!ds) + return NULL; + + ds->slave.bus = bus; + ds->slave.cs = cs; + ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE; + ds->freq = max_hz; + + return &ds->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + + free(ds); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + unsigned int scalar, data1_reg_val = 0; + + /* Enable the SPI hardware */ + writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); + udelay(1000); + writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0); + + /* Set master mode, powered up and not activated */ + writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); + + /* CS, CLK, SIMO and SOMI are functional pins */ + writel((SPIPC0_EN0FUN_MASK | SPIPC0_CLKFUN_MASK | + SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); + + /* setup format */ + scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; + + /* + * Use following format: + * character length = 8, + * clock signal delayed by half clk cycle, + * clock low in idle state - Mode 0, + * MSB shifted out first + */ + writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) | + (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0); + + /* hold cs active at end of transfer until explicitly de-asserted */ + data1_reg_val = (1 << SPIDAT1_CSHOLD_SHIFT) | + (slave->cs << SPIDAT1_CSNR_SHIFT); + writel(data1_reg_val, &ds->regs->dat1); + + /* + * Including a minor delay. No science here. Should be good even with + * no delay + */ + writel((50 << SPI_C2TDELAY_SHIFT) | + (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay); + + /* default chip select register */ + writel(SPIDEF_CSDEF0_MASK, &ds->regs->def); + + /* no interrupts */ + writel(0, &ds->regs->int0); + writel(0, &ds->regs->lvl); + + /* enable SPI */ + writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + + /* Disable the SPI hardware */ + writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + unsigned int len, data1_reg_val = readl(&ds->regs->dat1); + int ret, i; + const u8 *txp = dout; /* dout can be NULL for read operation */ + u8 *rxp = din; /* din can be NULL for write operation */ + + ret = 0; + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + /* + * It's not clear how non-8-bit-aligned transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface - here we terminate on receiving such a + * transfer request. + */ + if (bitlen % 8) { + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + /* do an empty read to clear the current contents */ + readl(&ds->regs->buf); + + /* keep writing and reading 1 byte until done */ + for (i = 0; i < len; i++) { + /* wait till TXFULL is asserted */ + while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK); + + /* write the data */ + data1_reg_val &= ~0xFFFF; + if (txp) { + data1_reg_val |= *txp; + txp++; + } + + /* + * Write to DAT1 is required to keep the serial transfer going. + * We just terminate when we reach the end. + */ + if ((i == (len - 1)) && (flags & SPI_XFER_END)) { + /* clear CS hold */ + writel(data1_reg_val & + ~(1 << SPIDAT1_CSHOLD_SHIFT), &ds->regs->dat1); + } else { + /* enable CS hold */ + data1_reg_val |= ((1 << SPIDAT1_CSHOLD_SHIFT) | + (slave->cs << SPIDAT1_CSNR_SHIFT)); + writel(data1_reg_val, &ds->regs->dat1); + } + + /* read the data - wait for data availability */ + while (readl(&ds->regs->buf) & SPIBUF_RXEMPTY_MASK); + + if (rxp) { + *rxp = readl(&ds->regs->buf) & 0xFF; + rxp++; + } else { + /* simply drop the read character */ + readl(&ds->regs->buf); + } + } + return 0; + +out: + if (flags & SPI_XFER_END) { + writel(data1_reg_val & + ~(1 << SPIDAT1_CSHOLD_SHIFT), &ds->regs->dat1); + } + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* do nothing */ +} + diff --git a/drivers/spi/davinci_spi.h b/drivers/spi/davinci_spi.h new file mode 100644 index 0000000..8d36a42 --- /dev/null +++ b/drivers/spi/davinci_spi.h @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Register definitions for the DaVinci SPI Controller + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DAVINCI_SPI_H_ +#define _DAVINCI_SPI_H_ + +struct davinci_spi_regs { + dv_reg gcr0; /* 0x00 */ + dv_reg gcr1; /* 0x04 */ + dv_reg int0; /* 0x08 */ + dv_reg lvl; /* 0x0c */ + dv_reg flg; /* 0x10 */ + dv_reg pc0; /* 0x14 */ + dv_reg pc1; /* 0x18 */ + dv_reg pc2; /* 0x1c */ + dv_reg pc3; /* 0x20 */ + dv_reg pc4; /* 0x24 */ + dv_reg pc5; /* 0x28 */ + dv_reg rsvd[3]; + dv_reg dat0; /* 0x38 */ + dv_reg dat1; /* 0x3c */ + dv_reg buf; /* 0x40 */ + dv_reg emu; /* 0x44 */ + dv_reg delay; /* 0x48 */ + dv_reg def; /* 0x4c */ + dv_reg fmt0; /* 0x50 */ + dv_reg fmt1; /* 0x54 */ + dv_reg fmt2; /* 0x58 */ + dv_reg fmt3; /* 0x5c */ + dv_reg intvec0; /* 0x60 */ + dv_reg intvec1; /* 0x64 */ +}; + +#define BIT(x) (1 << (x)) + +/* SPIGCR0 */ +#define SPIGCR0_SPIENA_MASK 0x1 +#define SPIGCR0_SPIRST_MASK 0x0 + +/* SPIGCR0 */ +#define SPIGCR1_CLKMOD_MASK BIT(1) +#define SPIGCR1_MASTER_MASK BIT(0) +#define SPIGCR1_SPIENA_MASK BIT(24) + +/* SPIPC0 */ +#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */ +#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */ +#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ +#define SPIPC0_EN0FUN_MASK BIT(0) + +/* SPIFMT0 */ +#define SPIFMT_SHIFTDIR_SHIFT 20 +#define SPIFMT_POLARITY_SHIFT 17 +#define SPIFMT_PHASE_SHIFT 16 +#define SPIFMT_PRESCALE_SHIFT 8 + +/* SPIDAT1 */ +#define SPIDAT1_CSHOLD_SHIFT 28 +#define SPIDAT1_CSNR_SHIFT 16 + +/* SPIDELAY */ +#define SPI_C2TDELAY_SHIFT 24 +#define SPI_T2CDELAY_SHIFT 16 + +/* SPIBUF */ +#define SPIBUF_RXEMPTY_MASK BIT(31) +#define SPIBUF_TXFULL_MASK BIT(29) + +/* SPIDEF */ +#define SPIDEF_CSDEF0_MASK BIT(0) + +struct davinci_spi_slave { + struct spi_slave slave; + struct davinci_spi_regs *regs; + unsigned int freq; +}; + +static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) +{ + return container_of(slave, struct davinci_spi_slave, slave); +} + +#endif /* _DAVINCI_SPI_H_ */ -- cgit v1.1 From e0f2318f85780c9f4fd5ea0bb5da475b33ebdf78 Mon Sep 17 00:00:00 2001 From: Nick Thompson Date: Wed, 27 Jan 2010 11:11:28 -0500 Subject: da830evm: Use table driven pin mux configuration Tidyup the pin muxer configuration using the Davinci table driven pinmux configuration function and data tables. Signed-off-by: Nick Thompson Signed-off-by: Sandeep Paulraj --- board/davinci/da830evm/da830evm.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da830evm/da830evm.c index 7cf6013..12df1f8 100644 --- a/board/davinci/da830evm/da830evm.c +++ b/board/davinci/da830evm/da830evm.c @@ -42,34 +42,43 @@ DECLARE_GLOBAL_DATA_PTR; #define pinmux &davinci_syscfg_regs->pinmux -#ifdef CONFIG_SPI_FLASH /* SPI0 pin muxer settings */ -const struct pinmux_config spi0_pins[] = { +static const struct pinmux_config spi0_pins[] = { { pinmux[7], 1, 3 }, { pinmux[7], 1, 4 }, { pinmux[7], 1, 5 }, { pinmux[7], 1, 6 }, { pinmux[7], 1, 7 } }; -#endif /* UART pin muxer settings */ -const struct pinmux_config uart_pins[] = { +static const struct pinmux_config uart_pins[] = { { pinmux[8], 2, 7 }, { pinmux[9], 2, 0 } }; /* I2C pin muxer settings */ -const struct pinmux_config i2c_pins[] = { +static const struct pinmux_config i2c_pins[] = { { pinmux[9], 2, 3 }, { pinmux[9], 2, 4 } }; /* USB0_DRVVBUS pin muxer settings */ -const struct pinmux_config usb_pins[] = { +static const struct pinmux_config usb_pins[] = { { pinmux[9], 1, 1 } }; +static const struct pinmux_resource pinmuxes[] = { +#ifdef CONFIG_SPI_FLASH + PINMUX_ITEM(spi0_pins), +#endif + PINMUX_ITEM(uart_pins), + PINMUX_ITEM(i2c_pins), +#ifdef CONFIG_USB_DA8XX + PINMUX_ITEM(usb_pins), +#endif +}; + int board_init(void) { #ifndef CONFIG_USE_IRQ @@ -112,18 +121,8 @@ int board_init(void) DAVINCI_SYSCFG_SUSPSRC_UART2), &davinci_syscfg_regs->suspsrc); -#ifdef CONFIG_SPI_FLASH - if (davinci_configure_pin_mux(spi0_pins, ARRAY_SIZE(spi0_pins)) != 0) - return 1; -#endif - - if (davinci_configure_pin_mux(uart_pins, ARRAY_SIZE(uart_pins)) != 0) - return 1; - - if (davinci_configure_pin_mux(i2c_pins, ARRAY_SIZE(i2c_pins)) != 0) - return 1; - - if (davinci_configure_pin_mux(usb_pins, ARRAY_SIZE(usb_pins)) != 0) + /* configure pinmux settings */ + if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) return 1; /* enable the console UART */ -- cgit v1.1 From 7dd866ae926a69cd09605b29c5e115568a6131bb Mon Sep 17 00:00:00 2001 From: Scott Ellis Date: Wed, 27 Jan 2010 11:11:46 -0500 Subject: Overo GPMC registers Use appropriate GPMC timings for the LAN9221 controller on the Gumstix Overo expansion boards not the values in arch-omap3/mem.h which are for a different ethernet controller. Signed-off-by: Scott Ellis Signed-off-by: Sandeep Paulraj --- board/overo/overo.c | 14 +++++++------- board/overo/overo.h | 9 +++++++++ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/board/overo/overo.c b/board/overo/overo.c index f363281..e85be7d 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -100,13 +100,13 @@ static void setup_net_chip(void) struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; /* Configure GPMC registers */ - writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); - writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); - writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); - writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); - writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); - writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); - writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); + writel(NET_LAN9221_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); + writel(NET_LAN9221_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); + writel(NET_LAN9221_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); + writel(NET_LAN9221_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); + writel(NET_LAN9221_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); + writel(NET_LAN9221_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); + writel(NET_LAN9221_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); diff --git a/board/overo/overo.h b/board/overo/overo.h index 4c7ac27..1873523 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -33,6 +33,15 @@ const omap3_sysinfo sysinfo = { #endif }; +/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */ +#define NET_LAN9221_GPMC_CONFIG1 0x00001000 +#define NET_LAN9221_GPMC_CONFIG2 0x00080701 +#define NET_LAN9221_GPMC_CONFIG3 0x00020201 +#define NET_LAN9221_GPMC_CONFIG4 0x08030703 +#define NET_LAN9221_GPMC_CONFIG5 0x00060908 +#define NET_LAN9221_GPMC_CONFIG6 0x87030000 +#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c + /* * IEN - Input Enable * IDIS - Input Disable -- cgit v1.1 From 274fafef68b28b5ab5f8542dd2a836bedb2ea8d5 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Wed, 27 Jan 2010 11:11:55 -0500 Subject: OMAP3 Move declaration of gpmc_cfg. Every omap3 board config file declared the global variable gpmc_cfg. This changes moves the declaration to a better location in the arch dependent header file cpu.h. Signed-off-by: Tom Rix Signed-off-by: Sandeep Paulraj --- include/asm-arm/arch-omap3/cpu.h | 4 ++++ include/configs/devkit8000.h | 1 - include/configs/omap3_beagle.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/omap3_overo.h | 1 - include/configs/omap3_pandora.h | 1 - include/configs/omap3_sdp3430.h | 1 - include/configs/omap3_zoom1.h | 1 - include/configs/omap3_zoom2.h | 1 - 9 files changed, 4 insertions(+), 8 deletions(-) diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index e51c4f3..aa8de32 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -136,6 +136,10 @@ struct gpmc { u32 ecc8_result; /* 0x21C */ u32 ecc9_result; /* 0x220 */ }; + +/* Used for board specific gpmc initialization */ +extern struct gpmc *gpmc_cfg; + #else /* __ASSEMBLY__ */ #define GPMC_CONFIG1 0x00 #define GPMC_CONFIG2 0x04 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index e81da67..7d1332f 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -297,7 +297,6 @@ #define CONFIG_ENV_OFFSET boot_flash_off #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index a8abb0e..08d79ac 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -326,7 +326,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1 #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index a8d4105..0d99f7d 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -330,7 +330,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1 #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index c72fb9d..a43500b 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -295,7 +295,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1 #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index f22fab5..945c053 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -287,7 +287,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1 #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 4d01933..b4919db 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -361,7 +361,6 @@ /*--------------------------------------------------------------------------*/ #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index cdf95c0..ae7ebf9 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -311,7 +311,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1 #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 7a8beb8..c88c732 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -270,7 +270,6 @@ #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; -- cgit v1.1 From d9657ac848ab647a1309d76d848eb41cda613560 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Wed, 27 Jan 2010 11:12:08 -0500 Subject: NetStar: Disable CONFIG_CMD_JFFS2 This patch removes "CONFIG_CMD_JFFS" from the board config Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- include/configs/netstar.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/netstar.h b/include/configs/netstar.h index 20b423b..884dc09 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -149,7 +149,6 @@ #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_LOADB #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NAND @@ -158,8 +157,6 @@ #define CONFIG_CMD_RUN -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ - /* * BOOTP options */ -- cgit v1.1 From c2dccef33ac0c0c678e9aa3fb16d1ccac1e385d6 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Wed, 27 Jan 2010 11:12:23 -0500 Subject: NetStar: make crcit utility more readable This patch makes the crcit utility more readable Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- board/netstar/crcit.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c index e0cea9b..0eef41a 100644 --- a/board/netstar/crcit.c +++ b/board/netstar/crcit.c @@ -56,13 +56,14 @@ static int do_crc(char *path, unsigned version) fprintf(stderr, "File too large\n"); return EXIT_FAILURE; } - size = (size + 3) & ~3; /* round up to 4 bytes */ - data[0] = size + 4; /* add size of version field */ + size = (size + 3) & ~3; /* round up to 4 bytes */ + size += 4; /* add size of version field */ + data[0] = size; data[1] = version; - data[2 + (size >> 2)] = crc32(0, (unsigned char *)(data + 1), data[0]); + data[size/4 + 1] = crc32(0, (unsigned char *)(data + 1), size); close(fd); - if (write(STDOUT_FILENO, data, size + 3*4) == -1) { + if (write(STDOUT_FILENO, data, size + 4 /*size*/ + 4 /*crc*/) == -1) { perror("Error writing file"); return EXIT_FAILURE; } -- cgit v1.1 From 7f5a9c237e1ab2488518953442bcde882c5edd66 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Wed, 27 Jan 2010 11:12:28 -0500 Subject: NetStar: Remove debug junk leaked into eeprom utility This patch removes debug junk leaked into eeprom utility. Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- board/netstar/eeprom.c | 8 +-- board/netstar/eeprom_start.S | 166 +------------------------------------------ 2 files changed, 2 insertions(+), 172 deletions(-) diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c index 1366457..adb01b9 100644 --- a/board/netstar/eeprom.c +++ b/board/netstar/eeprom.c @@ -22,8 +22,6 @@ * Some code shamelessly stolen back from Robin Getz. */ -#define DEBUG - #include #include #include @@ -142,8 +140,6 @@ static int parse_element(char *s, unsigned char *buf, int len) return cnt; } -extern int crcek(void); - int eeprom(int argc, char *argv[]) { int i, len, ret; @@ -161,8 +157,6 @@ int eeprom(int argc, char *argv[]) return 1; } - return crcek(); - if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) { printf("SMSC91111 not found.\n"); return 2; @@ -176,7 +170,7 @@ int eeprom(int argc, char *argv[]) /* Print help message */ if (argv[1][1] == 'h') { - printf("VoiceBlue EEPROM writer\n"); + printf("NetStar EEPROM writer\n"); printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); printf("Usage:\n\t [] [<...>]\n"); return 0; diff --git a/board/netstar/eeprom_start.S b/board/netstar/eeprom_start.S index 1306485..3609382 100644 --- a/board/netstar/eeprom_start.S +++ b/board/netstar/eeprom_start.S @@ -8,170 +8,6 @@ */ .globl _start -_start: b eeprom - -#include "crcek.h" - -/** - * do_crc32 - calculate CRC32 of given buffer - * r0 - crc - * r1 - pointer to buffer - * r2 - buffer len - */ - .macro do_crc32 - ldr r5, FFFFFFFF - eor r0, r0, r5 - adr r3, CRC32_TABLE -1: - ldrb r4, [r1], #1 - eor r4, r4, r0 - and r4, r4, #0xff - ldr r4, [r3, r4, lsl#2] - eor r0, r4, r0, lsr#8 - subs r2, r2, #0x1 - bne 1b - eor r0, r0, r5 - .endm - - .macro crcuj, offset, size - ldr r1, \offset - ldr r2, [r1] - cmp r2, #0 @ no data, no problem - beq 2f - mov r7, #1 - tst r2, #3 @ unaligned size - bne 2f - mov r7, #2 - ldr r0, \size - cmp r2, r0 @ bogus size - bhi 2f - mov r7, #3 - add r1, r1, #4 - mov r0, #0 - do_crc32 - ldr r1, [r1] -2: - cmp r0, r1 - .endm - - .macro wait, reg - mov \reg, #0x1000 -3: - subs \reg, \reg, #0x1 - bne 3b - - .endm -.text -.globl crcek -crcek: - mov r6, #0 -@ crcuj _LOADER1_OFFSET, _LOADER_SIZE -@ bne crc1_bad -@ orr r6, r6, #1 -crc1_bad: - crcuj _LOADER2_OFFSET, _LOADER_SIZE - bne crc2_bad - orr r6, r6, #2 -crc2_bad: -@ mov r0, r6 - mov pc, lr - ldr r3, _LOADER1_OFFSET - ldr r4, _LOADER2_OFFSET - tst r6, #3 - beq one_is_bad @ one of them (or both) has bad crc - ldr r1, [r3, #4] - ldr r2, [r4, #4] - cmp r1, r2 @ boot 2nd loader if versions differ - beq boot_1st - b boot_2nd -one_is_bad: - tst r6, #1 - bne boot_1st - tst r6, #2 - bne boot_2nd -@ We are doomed, so let user know. - ldr r0, GPIO_BASE @ configure GPIO pins - ldr r1, GPIO_DIRECTION - strh r1, [r0, #0x08] -blink_loop: - mov r1, #0x08 - strh r1, [r0, #0x04] - wait r3 - mov r1, #0x10 - strh r1, [r0, #0x04] - wait r3 - b blink_loop -boot_1st: - add pc, r3, #8 -boot_2nd: - add pc, r4, #8 - -_LOADER_SIZE: - .word LOADER_SIZE - 8 @ minus size and crc32 -_LOADER1_OFFSET: - .word LOADER1_OFFSET -_LOADER2_OFFSET: - .word LOADER2_OFFSET - -FFFFFFFF: - .word 0xffffffff -CRC32_TABLE: - .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 - .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 - .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 - .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de - .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 - .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 - .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 - .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b - .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 - .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a - .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 - .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 - .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 - .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f - .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e - .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 - .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed - .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 - .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 - .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 - .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a - .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 - .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 - .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f - .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 - .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 - .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 - .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 - .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 - .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb - .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a - .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 - .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 - .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c - .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef - .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 - .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe - .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 - .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c - .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 - .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b - .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 - .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 - .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c - .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 - .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 - .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 - .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 - .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 - .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 - .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b - .word 0x2d02ef8d - -GPIO_BASE: - .word 0xfffce000 -GPIO_DIRECTION: - .word 0x0000ffe7 +_start: b eeprom .end -- cgit v1.1 From 8ed0f6108ff771ea605c896ce6e416b502f2cb55 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 1 Feb 2010 21:29:48 +0100 Subject: Add support for EDB93xx boards Added support for the following EDB93xx boards: EDB9301 EDB9302 EDB9302A EDB9307 EDB9307A EDB93012 EDB9315 EDB9315A Signed-off-by: Matthias Kaehlcke --- MAINTAINERS | 10 ++ MAKEALL | 8 ++ Makefile | 10 ++ board/edb93xx/Makefile | 50 ++++++++ board/edb93xx/config.mk | 33 ++++++ board/edb93xx/early_udelay.h | 34 ++++++ board/edb93xx/edb93xx.c | 104 +++++++++++++++++ board/edb93xx/flash_cfg.c | 38 ++++++ board/edb93xx/pll_cfg.c | 58 ++++++++++ board/edb93xx/pll_cfg.h | 72 ++++++++++++ board/edb93xx/sdram_cfg.c | 123 ++++++++++++++++++++ board/edb93xx/sdram_cfg.h | 144 +++++++++++++++++++++++ include/configs/edb93xx.h | 270 +++++++++++++++++++++++++++++++++++++++++++ 13 files changed, 954 insertions(+) create mode 100644 board/edb93xx/Makefile create mode 100644 board/edb93xx/config.mk create mode 100644 board/edb93xx/early_udelay.h create mode 100644 board/edb93xx/edb93xx.c create mode 100644 board/edb93xx/flash_cfg.c create mode 100644 board/edb93xx/pll_cfg.c create mode 100644 board/edb93xx/pll_cfg.h create mode 100644 board/edb93xx/sdram_cfg.c create mode 100644 board/edb93xx/sdram_cfg.h create mode 100644 include/configs/edb93xx.h diff --git a/MAINTAINERS b/MAINTAINERS index 0c2b1b1..1721ecb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -599,6 +599,16 @@ Gary Jennejohn smdk2400 ARM920T trab ARM920T +Matthias Kaehlcke + edb9301 ARM920T (EP9301) + edb9302 ARM920T (EP9302) + edb9302a ARM920T (EP9302) + edb9307 ARM920T (EP9307) + edb9307a ARM920T (EP9307) + edb9312 ARM920T (EP9312) + edb9315 ARM920T (EP9315) + edb9315a ARM920T (EP9315) + Konstantin Kletschke scb9328 ARM920T diff --git a/MAKEALL b/MAKEALL index 506dc78..549cc56 100755 --- a/MAKEALL +++ b/MAKEALL @@ -555,6 +555,14 @@ LIST_ARM9=" \ cp946es \ cp966 \ da830evm \ + edb9301 \ + edb9302 \ + edb9302a \ + edb9307 \ + edb9307a \ + edb9312 \ + edb9315 \ + edb9315a \ imx27lite \ lpd7a400 \ mv88f6281gtw_ge \ diff --git a/Makefile b/Makefile index 628bcdb..327aa8c 100644 --- a/Makefile +++ b/Makefile @@ -2416,6 +2416,16 @@ caddy2_config \ vme8349_config: unconfig @$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd +edb9301_config \ +edb9302_config \ +edb9302a_config \ +edb9307_config \ +edb9307a_config \ +edb9312_config \ +edb9315_config \ +edb9315a_config: unconfig + @$(MKCONFIG) -t $(@:_config=) edb93xx arm arm920t edb93xx NULL ep93xx + ######################################################################### ## MPC85xx Systems ######################################################################### diff --git a/board/edb93xx/Makefile b/board/edb93xx/Makefile new file mode 100644 index 0000000..e2e2636 --- /dev/null +++ b/board/edb93xx/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/edb93xx/config.mk b/board/edb93xx/config.mk new file mode 100644 index 0000000..b2fc6fa --- /dev/null +++ b/board/edb93xx/config.mk @@ -0,0 +1,33 @@ +LDSCRIPT := $(SRCTREE)/cpu/arm920t/ep93xx/u-boot.lds + +ifdef CONFIG_EDB9301 +TEXT_BASE = 0x05700000 +endif + +ifdef CONFIG_EDB9302 +TEXT_BASE = 0x05700000 +endif + +ifdef CONFIG_EDB9302A +TEXT_BASE = 0xc5700000 +endif + +ifdef CONFIG_EDB9307 +TEXT_BASE = 0x01f00000 +endif + +ifdef CONFIG_EDB9307A +TEXT_BASE = 0xc1f00000 +endif + +ifdef CONFIG_EDB9312 +TEXT_BASE = 0x01f00000 +endif + +ifdef CONFIG_EDB9315 +TEXT_BASE = 0x01f00000 +endif + +ifdef CONFIG_EDB9315A +TEXT_BASE = 0xc1f00000 +endif diff --git a/board/edb93xx/early_udelay.h b/board/edb93xx/early_udelay.h new file mode 100644 index 0000000..3b26b3f --- /dev/null +++ b/board/edb93xx/early_udelay.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* delay execution before timers are initialized */ +static inline void early_udelay(uint32_t usecs) +{ + /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */ + register uint32_t loops = (usecs * 1000) / 20; + + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} diff --git a/board/edb93xx/edb93xx.c b/board/edb93xx/edb93xx.c new file mode 100644 index 0000000..4df2246 --- /dev/null +++ b/board/edb93xx/edb93xx.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke + * + * (C) Copyright 2002 2003 + * Network Audio Technologies, Inc. + * Adam Bezanson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MAX_BANK_SIZE 0x04000000 /* 64 MB */ + +static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = { + PHYS_SDRAM_1, +#ifdef PHYS_SDRAM_2 + PHYS_SDRAM_2, +#endif +#ifdef PHYS_SDRAM_3 + PHYS_SDRAM_3, +#endif +#ifdef PHYS_SDRAM_4 + PHYS_SDRAM_4 +#endif +}; + +int board_init(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + + icache_enable(); + +#ifdef USE_920T_MMU + dcache_enable(); +#endif + + /* + * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of + * 14.7456/2 MHz + */ + uint32_t value = readl(&syscon->pwrcnt); + value |= SYSCON_PWRCNT_UART_BAUD; + writel(value, &syscon->pwrcnt); + + /* Machine number, as defined in linux/arch/arm/tools/mach-types */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* We have a console */ + gd->have_console = 1; + + return 0; +} + +int board_eth_init(bd_t *bd) +{ + return ep93xx_eth_initialize(0, MAC_BASE); +} + +int dram_init(void) +{ + unsigned int *src, *dst; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + const ulong bank_size = get_ram_size((long *)bank_addr[i], + MAX_BANK_SIZE); + if (bank_size) { + gd->bd->bi_dram[i].start = bank_addr[i]; + gd->bd->bi_dram[i].size = bank_size; + } + } + + /* copy exception vectors */ + src = (unsigned int *)_armboot_start; + dst = (unsigned int *)PHYS_SDRAM_1; + memcpy(dst, src, 16 * sizeof(unsigned int)); + + return 0; +} diff --git a/board/edb93xx/flash_cfg.c b/board/edb93xx/flash_cfg.c new file mode 100644 index 0000000..a4c2048 --- /dev/null +++ b/board/edb93xx/flash_cfg.c @@ -0,0 +1,38 @@ +/* + * Flash setup for Cirrus edb93xx boards + * + * Copyright (C) 2009 Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \ + SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \ + 1 << SMC_BCR_MW_SHIFT) + +void flash_cfg(void) +{ + struct smc_regs *smc = (struct smc_regs *)SMC_BASE; + + writel(SMC_BCR6_VALUE, &smc->bcr6); +} diff --git a/board/edb93xx/pll_cfg.c b/board/edb93xx/pll_cfg.c new file mode 100644 index 0000000..a687af0 --- /dev/null +++ b/board/edb93xx/pll_cfg.c @@ -0,0 +1,58 @@ +/* + * PLL setup for Cirrus edb93xx boards + * + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2006 Dominic Rath + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "pll_cfg.h" +#include "early_udelay.h" + +void pll_cfg(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + + /* setup PLL1 */ + writel(CLKSET1_VAL, &syscon->clkset1); + + /* + * flush the pipeline + * writing to CLKSET1 causes the EP93xx to enter standby for between + * 8 ms to 16 ms, until PLL1 stabilizes + */ + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + + /* setup PLL2 */ + writel(CLKSET2_VAL, &syscon->clkset2); + + /* + * the user's guide recommends to wait at least 1 ms for PLL2 to + * stabilize + */ + early_udelay(1000); +} diff --git a/board/edb93xx/pll_cfg.h b/board/edb93xx/pll_cfg.h new file mode 100644 index 0000000..0b6f469 --- /dev/null +++ b/board/edb93xx/pll_cfg.h @@ -0,0 +1,72 @@ +/* + * PLL register values for Cirrus edb93xx boards + * + * Copyright (C) 2009 Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ + defined(CONFIG_EDB9302A) +/* + * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2 + * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000, + * pll1_x2: 331776000.000000, pll1_out: 331776000.000000 + */ +#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ + 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ + 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ + 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \ + 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ + SYSCON_CLKSET1_NBYP1 | \ + 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) +#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \ + defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \ + defined(CONFIG_EDB9315A) +/* + * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2 + * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000, + * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000 + */ +#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ + 30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ + 20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ + 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \ + 2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ + SYSCON_CLKSET1_NBYP1 | \ + 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) +#else +#error "Undefined board" +#endif + +/* + * usb_div: 4, nbyp2: 1, pll2_en: 1 + * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000, + * pll2_x2: 384000000.000000, pll2_out: 192000000.000000 + */ +#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ + 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ + 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ + 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \ + SYSCON_CLKSET2_PLL2_EN | \ + SYSCON_CLKSET2_NBYP2 | \ + 3 << SYSCON_CLKSET2_USB_DIV_SHIFT) diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c new file mode 100644 index 0000000..6155f0e --- /dev/null +++ b/board/edb93xx/sdram_cfg.c @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2006 Dominic Rath + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "sdram_cfg.h" +#include "early_udelay.h" + +#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \ + (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL)) + +#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \ + (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) + +static void force_precharge(void); +static void setup_refresh_timer(void); +static void program_mode_registers(void); + +void sdram_cfg(void) +{ + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; + + writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG); + + /* Issue continous NOP commands */ + writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); + + early_udelay(200); + + force_precharge(); + + setup_refresh_timer(); + + program_mode_registers(); + + /* Select normal operation mode */ + writel(GLCONFIG_CKE, &sdram->glconfig); +} + +static void force_precharge(void) +{ + /* + * Errata most EP93xx revisions say that PRECHARGE ALL isn't always + * issued. + * + * Do a read from each bank to make sure they're precharged + */ + + PRECHARGE_BANK(0); + PRECHARGE_BANK(1); + PRECHARGE_BANK(2); + PRECHARGE_BANK(3); +} + +static void setup_refresh_timer(void) +{ + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; + + /* Load refresh timer with 10 to issue refresh every 10 cycles */ + writel(0x0a, &sdram->refrshtimr); + + /* + * Wait at least 80 clock cycles to provide 8 refresh cycles + * to all SDRAMs + */ + early_udelay(1); + + /* + * Program refresh timer with normal value + * We need 8192 refresh cycles every 64ms + * at 15ns (HCLK >= 66MHz) per cycle: + * 64ms / 8192 = 7.8125us + * 7.8125us / 15ns = 520 (0x208) + */ + /* + * TODO: redboot uses 0x1e0 for the slowest possible device + * but i don't understand how this value is calculated + */ + writel(0x208, &sdram->refrshtimr); +} + +static void program_mode_registers(void) +{ + /* + * The mode registers are programmed by performing a read from each + * SDRAM bank. The value of the address that is read defines the value + * that is written into the mode register + */ + + PROGRAM_MODE_REG(0); + +#if (CONFIG_NR_DRAM_BANKS >= 2) + PROGRAM_MODE_REG(1); +#endif + +#if (CONFIG_NR_DRAM_BANKS >= 3) + PROGRAM_MODE_REG(2); +#endif + +#if (CONFIG_NR_DRAM_BANKS == 4) + PROGRAM_MODE_REG(3); +#endif +} diff --git a/board/edb93xx/sdram_cfg.h b/board/edb93xx/sdram_cfg.h new file mode 100644 index 0000000..757b63c --- /dev/null +++ b/board/edb93xx/sdram_cfg.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2006 Dominic Rath + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define SDRAM_BASE_ADDR PHYS_SDRAM_1 + +#ifdef CONFIG_EDB93XX_SDCS0 +#define SDRAM_DEVCFG_REG devcfg0 +#elif defined(CONFIG_EDB93XX_SDCS3) +#define SDRAM_DEVCFG_REG devcfg3 +#else +#error "SDRAM bank configuration" +#endif + +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ + defined(CONFIG_EDB9302A) +/* + * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM + * + * CLK cycle time min: + * @ CAS latency = 3: 7.5ns + * @ CAS latency = 2: 10ns + * We're running at 66MHz (15ns cycle time) external bus speed (HCLK), + * so it's safe to use CAS latency = 2 + * + * RAS-to-CAS delay min: + * 20ns + * At 15ns cycle time, we use RAS-to-CAS delay = 2 + * + * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear + * as four blocks of 8MB size, instead of eight blocks of 4MB size: + * + * EDB9301/EDB9302: + * + * 0x00000000 - 0x007fffff + * 0x01000000 - 0x017fffff + * 0x04000000 - 0x047fffff + * 0x05000000 - 0x057fffff + * + * + * EDB9302a: + * + * 0xc0000000 - 0xc07fffff + * 0xc1000000 - 0xc17fffff + * 0xc4000000 - 0xc47fffff + * 0xc5000000 - 0xc57fffff + * + * BANKCOUNT = 1: This is a device with four banks + */ + +#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ + SDRAM_DEVCFG_SROMLL | \ + SDRAM_DEVCFG_CASLAT_2 | \ + SDRAM_DEVCFG_RASTOCAS_2 | \ + SDRAM_DEVCFG_EXTBUSWIDTH) + +/* + * 16 bit ext. bus + * + * A[22:09] is output as SYA[13:0] + * CAS latency: 2 + * Burst type: sequential + * Burst length: 8 (required for 16 bit ext. bus) + * SYA[13:0] = 0x0023 + */ +#define SDRAM_MODE_REG_VAL 0x4600 + +#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */ +#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */ +#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */ +#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */ + +#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \ + defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \ + defined(CONFIG_EDB9315A) +/* + * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM + * + * CLK cycle time min: + * @ CAS latency = 3: 7.5ns + * @ CAS latency = 2: 10ns + * We're running at 100MHz (10ns cycle time) external bus speed (HCLK), + * so it's safe to use CAS latency = 2 + * + * RAS-to-CAS delay min: + * 20ns + * At 10ns cycle time, we use RAS-to-CAS delay = 2 + * + * EDB9307, EDB9312, EDB9315: + * + * 0x00000000 - 0x01ffffff + * 0x04000000 - 0x05ffffff + * + * + * EDB9307a, EDB9315a: + * + * 0xc0000000 - 0xc1ffffff + * 0xc4000000 - 0xc5ffffff + */ + +#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ + SDRAM_DEVCFG_SROMLL | \ + SDRAM_DEVCFG_CASLAT_2 | \ + SDRAM_DEVCFG_RASTOCAS_2) + +/* + * 32 bit ext. bus + * + * A[23:10] is output as SYA[13:0] + * CAS latency: 2 + * Burst type: sequential + * Burst length: 4 + * SYA[13:0] = 0x0022 + */ +#define SDRAM_MODE_REG_VAL 0x8800 + +#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */ +#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */ +#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */ +#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */ +#endif diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h new file mode 100644 index 0000000..4b00391 --- /dev/null +++ b/include/configs/edb93xx.h @@ -0,0 +1,270 @@ +/* + * U-boot - Configuration file for Cirrus Logic EDB93xx boards + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_MK_edb9301 +#define CONFIG_EDB9301 +#elif defined(CONFIG_MK_edb9302) +#define CONFIG_EDB9302 +#elif defined(CONFIG_MK_edb9302a) +#define CONFIG_EDB9302A +#elif defined(CONFIG_MK_edb9307) +#define CONFIG_EDB9307 +#elif defined(CONFIG_MK_edb9307a) +#define CONFIG_EDB9307A +#elif defined(CONFIG_MK_edb9312) +#define CONFIG_EDB9312 +#elif defined(CONFIG_MK_edb9315) +#define CONFIG_EDB9315 +#elif defined(CONFIG_MK_edb9315a) +#define CONFIG_EDB9315A +#else +#error "no board defined" +#endif + +/* Initial environment and monitor configuration options. */ +#define CONFIG_BOOTDELAY 2 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp" +#define CONFIG_BOOTFILE "edb93xx.img" + +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#ifdef CONFIG_EDB9301 +#define CONFIG_EP9301 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301 +#define CONFIG_SYS_PROMPT "EDB9301> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9302) +#define CONFIG_EP9302 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302 +#define CONFIG_SYS_PROMPT "EDB9302> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9302A) +#define CONFIG_EP9302 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A +#define CONFIG_SYS_PROMPT "EDB9302A> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9307) +#define CONFIG_EP9307 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307 +#define CONFIG_SYS_PROMPT "EDB9307> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9307A) +#define CONFIG_EP9307 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A +#define CONFIG_SYS_PROMPT "EDB9307A> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9312) +#define CONFIG_EP9312 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312 +#define CONFIG_SYS_PROMPT "EDB9312> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9315) +#define CONFIG_EP9315 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315 +#define CONFIG_SYS_PROMPT "EDB9315> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9315A) +#define CONFIG_EP9315 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A +#define CONFIG_SYS_PROMPT "EDB9315A> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#else +#error "no board defined" +#endif + +/* High-level configuration options */ +#define CONFIG_ARM920T 1 /* This is an ARM920T core... */ +#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */ + +#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ +#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */ +#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ + +/* Monitor configuration */ +#include +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#undef CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 + +#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +/* Print buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +/* Boot argument buffer size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ + +/* Serial port hardware configuration */ +#define CONFIG_PL010_SERIAL +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_SERIAL0 0x808C0000 +#define CONFIG_SYS_SERIAL1 0x808D0000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} + +/* Status LED */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 +#define STATUS_LED_GREEN 0 +#define STATUS_LED_RED 1 +/* Green */ +#define STATUS_LED_BIT STATUS_LED_GREEN +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +/* Red */ +#define STATUS_LED_BIT1 STATUS_LED_RED +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* Optional value */ +#define STATUS_LED_BOOT STATUS_LED_BIT + +/* Network hardware configuration */ +#define CONFIG_DRIVER_EP93XX_MAC +#define CONFIG_MII_SUPPRESS_PREAMBLE +#define CONFIG_MII +#define CONFIG_PHY_ADDR 1 +#define CONFIG_NET_MULTI +#undef CONFIG_NETCONSOLE + +/* SDRAM configuration */ +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) +/* + * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + */ +#define CONFIG_NR_DRAM_BANKS 4 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_SIZE_1 0x00800000 +#define PHYS_SDRAM_2 0x01000000 +#define PHYS_SDRAM_SIZE_2 0x00800000 +#define PHYS_SDRAM_3 0x04000000 +#define PHYS_SDRAM_SIZE_3 0x00800000 +#define PHYS_SDRAM_4 0x05000000 +#define PHYS_SDRAM_SIZE_4 0x00800000 +#define CONFIG_EDB93XX_SDCS3 +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x007fffff + +#elif defined(CONFIG_EDB9302A) +/* + * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + */ +#define CONFIG_NR_DRAM_BANKS 4 +#define PHYS_SDRAM_1 0xc0000000 +#define PHYS_SDRAM_SIZE_1 0x00800000 +#define PHYS_SDRAM_2 0xc1000000 +#define PHYS_SDRAM_SIZE_2 0x00800000 +#define PHYS_SDRAM_3 0xc4000000 +#define PHYS_SDRAM_SIZE_3 0x00800000 +#define PHYS_SDRAM_4 0xc5000000 +#define PHYS_SDRAM_SIZE_4 0x00800000 +#define CONFIG_EDB93XX_SDCS0 +#define CONFIG_SYS_MEMTEST_START 0xc0100000 +#define CONFIG_SYS_MEMTEST_END 0xc07fffff + +#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \ + defined(CONFIG_EDB9315) +/* + * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of + * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of + * 64 MB of SDRAM. + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_SIZE_1 0x02000000 +#define PHYS_SDRAM_2 0x04000000 +#define PHYS_SDRAM_SIZE_2 0x02000000 +#define CONFIG_EDB93XX_SDCS3 +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x01e00000 + +#elif defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A) +/* + * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung + * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM. + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 0xc0000000 +#define PHYS_SDRAM_SIZE_1 0x02000000 +#define PHYS_SDRAM_2 0xc4000000 +#define PHYS_SDRAM_SIZE_2 0x02000000 +#define CONFIG_EDB93XX_SDCS0 +#define CONFIG_SYS_MEMTEST_START 0xc0100000 +#define CONFIG_SYS_MEMTEST_END 0xc1e00000 +#endif + +/* Default load address */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x01000000) + +/* Must match kernel config */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) + +/* Run-time memory allocatons */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_STACKSIZE (128 * 1024) + +#if defined(CONFIG_USE_IRQ) +#define CONFIG_STACKSIZE_IRQ (4 * 1024) +#define CONFIG_STACKSIZE_FIQ (4 * 1024) +#endif + +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) + +/* ----------------------------------------------------------------------------- + * FLASH and environment organization + * + * The EDB9301 and EDB9302(a) have 1 bank of flash memory at 0x60000000 + * consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus, + * for a total of 16 MB of CFI-compatible flash. + * + * The EDB9307(a), EDB9312, and EDB9315(a) have 1 bank of flash memory at + * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit + * data bus, for a total of 32 MB of CFI-compatible flash. + * + * EDB9301/02(a) EDB9307(a)/12/15(a) + * 0x60000000 - 0x0003FFFF u-boot u-boot + * 0x60040000 - 0x0005FFFF environment #1 environment #1 + * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued) + * 0x60080000 - 0x0009FFFF unused environment #2 + * 0x600A0000 - 0x000BFFFF unused environment #2 (continued) + * 0x600C0000 - 0x00FFFFFF unused unused + * 0x61000000 - 0x01FFFFFF not present unused + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +#define PHYS_FLASH_1 0x60000000 +#define CONFIG_SYS_FLASH_BASE (PHYS_FLASH_1) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR 0x60040000 + +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) + +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#endif /* !defined (__CONFIG_H) */ -- cgit v1.1 From a62921468d652a2f158852ac11ce7c5cab7859f0 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 1 Feb 2010 21:29:39 +0100 Subject: ARM: Add support for EP93xx SoCs Add support for the Cirrus EP93xx platform Signed-off-by: Matthias Kaehlcke Acked-by: Tom --- cpu/arm920t/ep93xx/Makefile | 56 ++++ cpu/arm920t/ep93xx/cpu.c | 51 +++ cpu/arm920t/ep93xx/led.c | 101 ++++++ cpu/arm920t/ep93xx/lowlevel_init.S | 65 ++++ cpu/arm920t/ep93xx/speed.c | 110 +++++++ cpu/arm920t/ep93xx/timer.c | 168 ++++++++++ cpu/arm920t/ep93xx/u-boot.lds | 59 ++++ include/asm-arm/arch-ep93xx/ep93xx.h | 595 +++++++++++++++++++++++++++++++++++ include/common.h | 3 +- 9 files changed, 1207 insertions(+), 1 deletion(-) create mode 100644 cpu/arm920t/ep93xx/Makefile create mode 100644 cpu/arm920t/ep93xx/cpu.c create mode 100644 cpu/arm920t/ep93xx/led.c create mode 100644 cpu/arm920t/ep93xx/lowlevel_init.S create mode 100644 cpu/arm920t/ep93xx/speed.c create mode 100644 cpu/arm920t/ep93xx/timer.c create mode 100644 cpu/arm920t/ep93xx/u-boot.lds create mode 100644 include/asm-arm/arch-ep93xx/ep93xx.h diff --git a/cpu/arm920t/ep93xx/Makefile b/cpu/arm920t/ep93xx/Makefile new file mode 100644 index 0000000..30e12af --- /dev/null +++ b/cpu/arm920t/ep93xx/Makefile @@ -0,0 +1,56 @@ +# +# Cirrus Logic EP93xx CPU-specific Makefile +# +# Copyright (C) 2009 Matthias Kaehlcke +# +# Copyright (C) 2004, 2005 +# Cory T. Tusar, Videon Central, Inc., +# +# Copyright (C) 2006 +# Dominic Rath +# +# Based on an original Makefile, which is +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 675 Mass Ave, Cambridge, MA 02139, USA. +# +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = cpu.o led.o speed.o timer.o +SOBJS = lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/cpu/arm920t/ep93xx/cpu.c b/cpu/arm920t/ep93xx/cpu.c new file mode 100644 index 0000000..1abb9c6 --- /dev/null +++ b/cpu/arm920t/ep93xx/cpu.c @@ -0,0 +1,51 @@ +/* + * Cirrus Logic EP93xx CPU-specific support. + * + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */ +extern void reset_cpu(ulong addr) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + uint32_t value; + + /* Unlock DeviceCfg and set SWRST */ + writel(0xAA, &syscon->sysswlock); + value = readl(&syscon->devicecfg); + value |= SYSCON_DEVICECFG_SWRST; + writel(value, &syscon->devicecfg); + + /* Unlock DeviceCfg and clear SWRST */ + writel(0xAA, &syscon->sysswlock); + value = readl(&syscon->devicecfg); + value &= ~SYSCON_DEVICECFG_SWRST; + writel(value, &syscon->devicecfg); + + /* Dying... */ + while (1) + ; /* noop */ +} diff --git a/cpu/arm920t/ep93xx/led.c b/cpu/arm920t/ep93xx/led.c new file mode 100644 index 0000000..7e2c897 --- /dev/null +++ b/cpu/arm920t/ep93xx/led.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2010, 2009 Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; +static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN, + 1 << STATUS_LED_RED}; + +inline void switch_LED_on(uint8_t led) +{ + register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; + + writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr); + saved_state[led] = STATUS_LED_ON; +} + +inline void switch_LED_off(uint8_t led) +{ + register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; + + writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr); + saved_state[led] = STATUS_LED_OFF; +} + +void red_LED_on(void) +{ + switch_LED_on(STATUS_LED_RED); +} + +void red_LED_off(void) +{ + switch_LED_off(STATUS_LED_RED); +} + +void green_LED_on(void) +{ + switch_LED_on(STATUS_LED_GREEN); +} + +void green_LED_off(void) +{ + switch_LED_off(STATUS_LED_GREEN); +} + +void __led_init(led_id_t mask, int state) +{ + __led_set(mask, state); +} + +void __led_toggle(led_id_t mask) +{ + if (STATUS_LED_RED == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_RED]) + red_LED_off(); + else + red_LED_on(); + } else if (STATUS_LED_GREEN == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN]) + green_LED_off(); + else + green_LED_on(); + } +} + +void __led_set(led_id_t mask, int state) +{ + if (STATUS_LED_RED == mask) { + if (STATUS_LED_ON == state) + red_LED_on(); + else + red_LED_off(); + } else if (STATUS_LED_GREEN == mask) { + if (STATUS_LED_ON == state) + green_LED_on(); + else + green_LED_off(); + } +} diff --git a/cpu/arm920t/ep93xx/lowlevel_init.S b/cpu/arm920t/ep93xx/lowlevel_init.S new file mode 100644 index 0000000..a20ec89 --- /dev/null +++ b/cpu/arm920t/ep93xx/lowlevel_init.S @@ -0,0 +1,65 @@ +/* + * Low-level initialization for EP93xx + * + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2006 Dominic Rath + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +.globl lowlevel_init +lowlevel_init: + /* backup return address */ + ldr r1, =SYSCON_SCRATCH0 + str lr, [r1] + + /* Turn on both LEDs */ + bl red_LED_on + bl green_LED_on + + /* Configure flash wait states before we switch to the PLL */ + bl flash_cfg + + /* Set up PLL */ + bl pll_cfg + + /* Turn off the Green LED and leave the Red LED on */ + bl green_LED_off + + /* Setup SDRAM */ + bl sdram_cfg + + /* Turn on Green LED, Turn off the Red LED */ + bl green_LED_on + bl red_LED_off + + /* FIXME: we use async mode for now */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0xc0000000 + mcr p15, 0, r0, c1, c0, 0 + + /* restore return address */ + ldr r1, =SYSCON_SCRATCH0 + ldr lr, [r1] + + mov pc, lr diff --git a/cpu/arm920t/ep93xx/speed.c b/cpu/arm920t/ep93xx/speed.c new file mode 100644 index 0000000..c83a3bb --- /dev/null +++ b/cpu/arm920t/ep93xx/speed.c @@ -0,0 +1,110 @@ +/* + * Cirrus Logic EP93xx PLL support. + * + * Copyright (C) 2009 Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +/* + * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. + * + * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of + * the specified bus in HZ. + */ + +/* + * return the PLL output frequency + * + * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1) + * / (X2IPD + 1) / 2^PS + */ +static ulong get_PLLCLK(uint32_t *pllreg) +{ + uint8_t i; + const uint32_t clkset = readl(pllreg); + uint64_t rate = CONFIG_SYS_CLK_FREQ; + rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; + rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; + do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ + for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) + rate >>= 1; + + return (ulong)rate; +} + +/* return FCLK frequency */ +ulong get_FCLK() +{ + const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + + const uint32_t clkset1 = readl(&syscon->clkset1); + const uint8_t fclk_div = + fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; + const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; + + return fclk_rate; +} + +/* return HCLK frequency */ +ulong get_HCLK(void) +{ + const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + + const uint32_t clkset1 = readl(&syscon->clkset1); + const uint8_t hclk_div = + hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; + const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; + + return hclk_rate; +} + +/* return PCLK frequency */ +ulong get_PCLK(void) +{ + const uint8_t pclk_divisors[] = { 1, 2, 4, 8 }; + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + + const uint32_t clkset1 = readl(&syscon->clkset1); + const uint8_t pclk_div = + pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; + const ulong pclk_rate = get_HCLK() / pclk_div; + + return pclk_rate; +} + +/* return UCLK frequency */ +ulong get_UCLK(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + ulong uclk_rate; + + const uint32_t value = readl(&syscon->pwrcnt); + if (value & SYSCON_PWRCNT_UART_BAUD) + uclk_rate = CONFIG_SYS_CLK_FREQ; + else + uclk_rate = CONFIG_SYS_CLK_FREQ / 2; + + return uclk_rate; +} diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c new file mode 100644 index 0000000..6d969d9 --- /dev/null +++ b/cpu/arm920t/ep93xx/timer.c @@ -0,0 +1,168 @@ +/* + * Cirrus Logic EP93xx timer support. + * + * Copyright (C) 2009, 2010 + * Matthias Kaehlcke + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support, + * author unknown. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +#define TIMER_CLKSEL (1 << 3) +#define TIMER_MODE (1 << 6) +#define TIMER_ENABLE (1 << 7) + +#define TIMER_FREQ 508469 +#define TIMER_LOAD_VAL (TIMER_FREQ / CONFIG_SYS_HZ) + +static ulong timestamp; +static ulong lastdec; + +static inline unsigned long clk_to_systicks(unsigned long clk_ticks) +{ + unsigned long sys_ticks = (clk_ticks * CONFIG_SYS_HZ) / TIMER_FREQ; + + return sys_ticks; +} + +static inline unsigned long usecs_to_ticks(unsigned long usecs) +{ + unsigned long ticks; + + if (usecs >= 1000) { + ticks = usecs / 1000; + ticks *= (TIMER_LOAD_VAL * CONFIG_SYS_HZ); + ticks /= 1000; + } else { + ticks = usecs * TIMER_LOAD_VAL * CONFIG_SYS_HZ; + ticks /= (1000 * 1000); + } + + return ticks; +} + +static inline unsigned long read_timer(void) +{ + struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; + + return readl(&timer->timer3.value); +} + +/* + * timer without interrupts + */ +unsigned long long get_ticks(void) +{ + const unsigned long now = read_timer(); + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + + lastdec = now; + + return timestamp; +} + +unsigned long get_timer_masked(void) +{ + return clk_to_systicks(get_ticks()); +} + +unsigned long get_timer(unsigned long base) +{ + return get_timer_masked() - base; +} + +void reset_timer_masked(void) +{ + lastdec = read_timer(); + timestamp = 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +void set_timer(unsigned long t) +{ + timestamp = t; +} + +void __udelay(unsigned long usec) +{ + const unsigned long ticks = usecs_to_ticks(usec); + const unsigned long target = clk_to_systicks(ticks) + get_timer(0); + + while (get_timer_masked() < target) + /* noop */; +} + +void udelay_masked(unsigned long usec) +{ + const unsigned long ticks = usecs_to_ticks(usec); + const unsigned long target = clk_to_systicks(ticks) + get_timer(0); + + reset_timer_masked(); + + while (get_timer_masked() < target) + /* noop */; +} + +int timer_init(void) +{ + struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; + + /* use timer 3 with 508KHz and free running */ + writel(TIMER_CLKSEL, &timer->timer3.control); + + /* auto load, manual update of Timer 3 */ + lastdec = TIMER_LOAD_VAL; + writel(TIMER_LOAD_VAL, &timer->timer3.load); + + /* Enable the timer and periodic mode */ + writel(TIMER_ENABLE | TIMER_MODE | TIMER_CLKSEL, + &timer->timer3.control); + + reset_timer_masked(); + + return 0; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +unsigned long get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/cpu/arm920t/ep93xx/u-boot.lds b/cpu/arm920t/ep93xx/u-boot.lds new file mode 100644 index 0000000..737c9d8 --- /dev/null +++ b/cpu/arm920t/ep93xx/u-boot.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */ + . = 0x1000; + LONG(0x53555243) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/include/asm-arm/arch-ep93xx/ep93xx.h b/include/asm-arm/arch-ep93xx/ep93xx.h new file mode 100644 index 0000000..6cafe54 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/ep93xx.h @@ -0,0 +1,595 @@ +/* + * Cirrus Logic EP93xx register definitions. + * + * Copyright (C) 2009 + * Matthias Kaehlcke + * + * Copyright (C) 2006 + * Dominic Rath + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is + * + * Copyright (C) 2004 Ray Lehtiniemi + * Copyright (C) 2003 Cirrus Logic, Inc + * Copyright (C) 1999 ARM Limited. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#define EP93XX_AHB_BASE 0x80000000 +#define EP93XX_APB_BASE 0x80800000 + +/* + * 0x80000000 - 0x8000FFFF: DMA + */ +#define DMA_OFFSET 0x000000 +#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET) + +#ifndef __ASSEMBLY__ +struct dma_channel { + uint32_t control; + uint32_t interrupt; + uint32_t ppalloc; + uint32_t status; + uint32_t reserved0; + uint32_t remain; + uint32_t reserved1[2]; + uint32_t maxcnt0; + uint32_t base0; + uint32_t current0; + uint32_t reserved2; + uint32_t maxcnt1; + uint32_t base1; + uint32_t current1; + uint32_t reserved3; +}; + +struct dma_regs { + struct dma_channel m2p_channel_0; + struct dma_channel m2p_channel_1; + struct dma_channel m2p_channel_2; + struct dma_channel m2p_channel_3; + struct dma_channel m2m_channel_0; + struct dma_channel m2m_channel_1; + struct dma_channel reserved0[2]; + struct dma_channel m2p_channel_5; + struct dma_channel m2p_channel_4; + struct dma_channel m2p_channel_7; + struct dma_channel m2p_channel_6; + struct dma_channel m2p_channel_9; + struct dma_channel m2p_channel_8; + uint32_t channel_arbitration; + uint32_t reserved[15]; + uint32_t global_interrupt; +}; +#endif + +/* + * 0x80010000 - 0x8001FFFF: Ethernet MAC + */ +#define MAC_OFFSET 0x010000 +#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET) + +#ifndef __ASSEMBLY__ +struct mac_queue { + uint32_t badd; + union { /* deal with half-word aligned registers */ + uint32_t blen; + union { + uint16_t filler; + uint16_t curlen; + }; + }; + uint32_t curadd; +}; + +struct mac_regs { + uint32_t rxctl; + uint32_t txctl; + uint32_t testctl; + uint32_t reserved0; + uint32_t miicmd; + uint32_t miidata; + uint32_t miists; + uint32_t reserved1; + uint32_t selfctl; + uint32_t inten; + uint32_t intstsp; + uint32_t intstsc; + uint32_t reserved2[2]; + uint32_t diagad; + uint32_t diagdata; + uint32_t gt; + uint32_t fct; + uint32_t fcf; + uint32_t afp; + union { + struct { + uint32_t indad; + uint32_t indad_upper; + }; + uint32_t hashtbl; + }; + uint32_t reserved3[2]; + uint32_t giintsts; + uint32_t giintmsk; + uint32_t giintrosts; + uint32_t giintfrc; + uint32_t txcollcnt; + uint32_t rxmissnct; + uint32_t rxruntcnt; + uint32_t reserved4; + uint32_t bmctl; + uint32_t bmsts; + uint32_t rxbca; + uint32_t reserved5; + struct mac_queue rxdq; + uint32_t rxdqenq; + struct mac_queue rxstsq; + uint32_t rxstsqenq; + struct mac_queue txdq; + uint32_t txdqenq; + struct mac_queue txstsq; + uint32_t reserved6; + uint32_t rxbufthrshld; + uint32_t txbufthrshld; + uint32_t rxststhrshld; + uint32_t txststhrshld; + uint32_t rxdthrshld; + uint32_t txdthrshld; + uint32_t maxfrmlen; + uint32_t maxhdrlen; +}; +#endif + +#define SELFCTL_RWP (1 << 7) +#define SELFCTL_GPO0 (1 << 5) +#define SELFCTL_PUWE (1 << 4) +#define SELFCTL_PDWE (1 << 3) +#define SELFCTL_MIIL (1 << 2) +#define SELFCTL_RESET (1 << 0) + +#define INTSTS_RWI (1 << 30) +#define INTSTS_RXMI (1 << 29) +#define INTSTS_RXBI (1 << 28) +#define INTSTS_RXSQI (1 << 27) +#define INTSTS_TXLEI (1 << 26) +#define INTSTS_ECIE (1 << 25) +#define INTSTS_TXUHI (1 << 24) +#define INTSTS_MOI (1 << 18) +#define INTSTS_TXCOI (1 << 17) +#define INTSTS_RXROI (1 << 16) +#define INTSTS_MIII (1 << 12) +#define INTSTS_PHYI (1 << 11) +#define INTSTS_TI (1 << 10) +#define INTSTS_AHBE (1 << 8) +#define INTSTS_OTHER (1 << 4) +#define INTSTS_TXSQ (1 << 3) +#define INTSTS_RXSQ (1 << 2) + +#define BMCTL_MT (1 << 13) +#define BMCTL_TT (1 << 12) +#define BMCTL_UNH (1 << 11) +#define BMCTL_TXCHR (1 << 10) +#define BMCTL_TXDIS (1 << 9) +#define BMCTL_TXEN (1 << 8) +#define BMCTL_EH2 (1 << 6) +#define BMCTL_EH1 (1 << 5) +#define BMCTL_EEOB (1 << 4) +#define BMCTL_RXCHR (1 << 2) +#define BMCTL_RXDIS (1 << 1) +#define BMCTL_RXEN (1 << 0) + +#define BMSTS_TXACT (1 << 7) +#define BMSTS_TP (1 << 4) +#define BMSTS_RXACT (1 << 3) +#define BMSTS_QID_MASK 0x07 +#define BMSTS_QID_RXDATA 0x00 +#define BMSTS_QID_TXDATA 0x01 +#define BMSTS_QID_RXSTS 0x02 +#define BMSTS_QID_TXSTS 0x03 +#define BMSTS_QID_RXDESC 0x04 +#define BMSTS_QID_TXDESC 0x05 + +#define AFP_MASK 0x07 +#define AFP_IAPRIMARY 0x00 +#define AFP_IASECONDARY1 0x01 +#define AFP_IASECONDARY2 0x02 +#define AFP_IASECONDARY3 0x03 +#define AFP_TX 0x06 +#define AFP_HASH 0x07 + +#define RXCTL_PAUSEA (1 << 20) +#define RXCTL_RXFCE1 (1 << 19) +#define RXCTL_RXFCE0 (1 << 18) +#define RXCTL_BCRC (1 << 17) +#define RXCTL_SRXON (1 << 16) +#define RXCTL_RCRCA (1 << 13) +#define RXCTL_RA (1 << 12) +#define RXCTL_PA (1 << 11) +#define RXCTL_BA (1 << 10) +#define RXCTL_MA (1 << 9) +#define RXCTL_IAHA (1 << 8) +#define RXCTL_IA3 (1 << 3) +#define RXCTL_IA2 (1 << 2) +#define RXCTL_IA1 (1 << 1) +#define RXCTL_IA0 (1 << 0) + +#define TXCTL_DEFDIS (1 << 7) +#define TXCTL_MBE (1 << 6) +#define TXCTL_ICRC (1 << 5) +#define TXCTL_TPD (1 << 4) +#define TXCTL_OCOLL (1 << 3) +#define TXCTL_SP (1 << 2) +#define TXCTL_PB (1 << 1) +#define TXCTL_STXON (1 << 0) + +#define MIICMD_REGAD_MASK (0x001F) +#define MIICMD_PHYAD_MASK (0x03E0) +#define MIICMD_OPCODE_MASK (0xC000) +#define MIICMD_PHYAD_8950 (0x0000) +#define MIICMD_OPCODE_READ (0x8000) +#define MIICMD_OPCODE_WRITE (0x4000) + +#define MIISTS_BUSY (1 << 0) + +/* + * 0x80020000 - 0x8002FFFF: USB OHCI + */ +#define USB_OFFSET 0x020000 +#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET) + +/* + * 0x80030000 - 0x8003FFFF: Raster engine + */ +#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315)) +#define RASTER_OFFSET 0x030000 +#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET) +#endif + +/* + * 0x80040000 - 0x8004FFFF: Graphics accelerator + */ +#if defined(CONFIG_EP9315) +#define GFX_OFFSET 0x040000 +#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET) +#endif + +/* + * 0x80050000 - 0x8005FFFF: Reserved + */ + +/* + * 0x80060000 - 0x8006FFFF: SDRAM controller + */ +#define SDRAM_OFFSET 0x060000 +#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET) + +#ifndef __ASSEMBLY__ +struct sdram_regs { + uint32_t reserved; + uint32_t glconfig; + uint32_t refrshtimr; + uint32_t bootsts; + uint32_t devcfg0; + uint32_t devcfg1; + uint32_t devcfg2; + uint32_t devcfg3; +}; +#endif + +#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2) +#define SDRAM_DEVCFG_BANKCOUNT (1 << 3) +#define SDRAM_DEVCFG_SROMLL (1 << 5) +#define SDRAM_DEVCFG_CASLAT_2 0x00010000 +#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000 + +#define GLCONFIG_INIT (1 << 0) +#define GLCONFIG_MRS (1 << 1) +#define GLCONFIG_SMEMBUSY (1 << 5) +#define GLCONFIG_LCR (1 << 6) +#define GLCONFIG_REARBEN (1 << 7) +#define GLCONFIG_CLKSHUTDOWN (1 << 30) +#define GLCONFIG_CKE (1 << 31) + +/* + * 0x80070000 - 0x8007FFFF: Reserved + */ + +/* + * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA + */ +#define SMC_OFFSET 0x080000 +#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET) + +#ifndef __ASSEMBLY__ +struct smc_regs { + uint32_t bcr0; + uint32_t bcr1; + uint32_t bcr2; + uint32_t bcr3; + uint32_t reserved0[2]; + uint32_t bcr6; + uint32_t bcr7; +#if defined(CONFIG_EP9315) + uint32_t pcattribute; + uint32_t pccommon; + uint32_t pcio; + uint32_t reserved1[5]; + uint32_t pcmciactrl; +#endif +}; +#endif + +#define SMC_BCR_IDCY_SHIFT 0 +#define SMC_BCR_WST1_SHIFT 5 +#define SMC_BCR_BLE (1 << 10) +#define SMC_BCR_WST2_SHIFT 11 +#define SMC_BCR_MW_SHIFT 28 + +/* + * 0x80090000 - 0x8009FFFF: Boot ROM + */ + +/* + * 0x800A0000 - 0x800AFFFF: IDE interface + */ + +/* + * 0x800B0000 - 0x800BFFFF: VIC1 + */ + +/* + * 0x800C0000 - 0x800CFFFF: VIC2 + */ + +/* + * 0x800D0000 - 0x800FFFFF: Reserved + */ + +/* + * 0x80800000 - 0x8080FFFF: Reserved + */ + +/* + * 0x80810000 - 0x8081FFFF: Timers + */ +#define TIMER_OFFSET 0x010000 +#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET) + +#ifndef __ASSEMBLY__ +struct timer { + uint32_t load; + uint32_t value; + uint32_t control; + uint32_t clear; +}; + +struct timer4 { + uint32_t value_low; + uint32_t value_high; +}; + +struct timer_regs { + struct timer timer1; + uint32_t reserved0[4]; + struct timer timer2; + uint32_t reserved1[12]; + struct timer4 timer4; + uint32_t reserved2[6]; + struct timer timer3; +}; +#endif + +/* + * 0x80820000 - 0x8082FFFF: I2S + */ +#define I2S_OFFSET 0x020000 +#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET) + +/* + * 0x80830000 - 0x8083FFFF: Security + */ +#define SECURITY_OFFSET 0x030000 +#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET) + +#define EXTENSIONID (SECURITY_BASE + 0x2714) + +/* + * 0x80840000 - 0x8084FFFF: GPIO + */ +#define GPIO_OFFSET 0x040000 +#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET) + +#ifndef __ASSEMBLY__ +struct gpio_int { + uint32_t inttype1; + uint32_t inttype2; + uint32_t eoi; + uint32_t inten; + uint32_t intsts; + uint32_t rawintsts; + uint32_t db; +}; + +struct gpio_regs { + uint32_t padr; + uint32_t pbdr; + uint32_t pcdr; + uint32_t pddr; + uint32_t paddr; + uint32_t pbddr; + uint32_t pcddr; + uint32_t pdddr; + uint32_t pedr; + uint32_t peddr; + uint32_t reserved0[2]; + uint32_t pfdr; + uint32_t pfddr; + uint32_t pgdr; + uint32_t pgddr; + uint32_t phdr; + uint32_t phddr; + uint32_t reserved1; + uint32_t finttype1; + uint32_t finttype2; + uint32_t reserved2; + struct gpio_int pfint; + uint32_t reserved3[10]; + struct gpio_int paint; + struct gpio_int pbint; + uint32_t eedrive; +}; +#endif + +/* + * 0x80850000 - 0x8087FFFF: Reserved + */ + +/* + * 0x80880000 - 0x8088FFFF: AAC + */ +#define AAC_OFFSET 0x080000 +#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET) + +/* + * 0x80890000 - 0x8089FFFF: Reserved + */ + +/* + * 0x808A0000 - 0x808AFFFF: SPI + */ +#define SPI_OFFSET 0x0A0000 +#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET) + +/* + * 0x808B0000 - 0x808BFFFF: IrDA + */ +#define IRDA_OFFSET 0x0B0000 +#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET) + +/* + * 0x808C0000 - 0x808CFFFF: UART1 + */ +#define UART1_OFFSET 0x0C0000 +#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET) + +/* + * 0x808D0000 - 0x808DFFFF: UART2 + */ +#define UART2_OFFSET 0x0D0000 +#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET) + +/* + * 0x808E0000 - 0x808EFFFF: UART3 + */ +#define UART3_OFFSET 0x0E0000 +#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET) + +/* + * 0x808F0000 - 0x808FFFFF: Key Matrix + */ +#define KEY_OFFSET 0x0F0000 +#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET) + +/* + * 0x80900000 - 0x8090FFFF: Touchscreen + */ +#define TOUCH_OFFSET 0x900000 +#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET) + +/* + * 0x80910000 - 0x8091FFFF: Pulse Width Modulation + */ +#define PWM_OFFSET 0x910000 +#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET) + +/* + * 0x80920000 - 0x8092FFFF: Real time clock + */ +#define RTC_OFFSET 0x920000 +#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET) + +/* + * 0x80930000 - 0x8093FFFF: Syscon + */ +#define SYSCON_OFFSET 0x930000 +#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET) + +#ifndef __ASSEMBLY__ +struct syscon_regs { + uint32_t pwrsts; + uint32_t pwrcnt; + uint32_t halt; + uint32_t stby; + uint32_t reserved0[2]; + uint32_t teoi; + uint32_t stfclr; + uint32_t clkset1; + uint32_t clkset2; + uint32_t reserved1[6]; + uint32_t scratch0; + uint32_t scratch1; + uint32_t reserved2[2]; + uint32_t apbwait; + uint32_t bustmstrarb; + uint32_t bootmodeclr; + uint32_t reserved3[9]; + uint32_t devicecfg; + uint32_t vidclkdiv; + uint32_t mirclkdiv; + uint32_t i2sclkdiv; + uint32_t keytchclkdiv; + uint32_t chipid; + uint32_t syscfg; + uint32_t reserved4[8]; + uint32_t sysswlock; +}; +#else +#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040) +#endif + +#define SYSCON_PWRCNT_UART_BAUD (1 << 29) + +#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0 +#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5 +#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11 +#define SYSCON_CLKSET_PLL_PS_SHIFT 16 +#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18 +#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20 +#define SYSCON_CLKSET1_NBYP1 (1 << 23) +#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25 + +#define SYSCON_CLKSET2_PLL2_EN (1 << 18) +#define SYSCON_CLKSET2_NBYP2 (1 << 19) +#define SYSCON_CLKSET2_USB_DIV_SHIFT 28 + +#define SYSCON_CHIPID_REV_MASK 0xF0000000 +#define SYSCON_DEVICECFG_SWRST (1 << 31) + +/* + * 0x80930000 - 0x8093FFFF: Watchdog Timer + */ +#define WATCHDOG_OFFSET 0x940000 +#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET) + +/* + * 0x80950000 - 0x9000FFFF: Reserved + */ diff --git a/include/common.h b/include/common.h index 81f2b59..86e3163 100644 --- a/include/common.h +++ b/include/common.h @@ -502,7 +502,8 @@ ulong get_PCI_freq (void); #endif #if defined(CONFIG_S3C24X0) || \ defined(CONFIG_LH7A40X) || \ - defined(CONFIG_S3C6400) + defined(CONFIG_S3C6400) || \ + defined(CONFIG_EP93XX) ulong get_FCLK (void); ulong get_HCLK (void); ulong get_PCLK (void); -- cgit v1.1 From c20a3c0bac909a0a1311eaafdec156b6a8686d46 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 1 Feb 2010 21:29:44 +0100 Subject: Add EP93xx ethernet driver Added ethernet driver for EP93xx SoCs Signed-off-by: Matthias Kaehlcke Acked-by: Ben Warren --- drivers/net/Makefile | 1 + drivers/net/ep93xx_eth.c | 653 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ep93xx_eth.h | 144 +++++++++++ include/common.h | 5 + include/netdev.h | 1 + 5 files changed, 804 insertions(+) create mode 100644 drivers/net/ep93xx_eth.c create mode 100644 drivers/net/ep93xx_eth.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 904727e..dc3107c 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_DNET) += dnet.o COBJS-$(CONFIG_E1000) += e1000.o COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o +COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c new file mode 100644 index 0000000..4e39948 --- /dev/null +++ b/drivers/net/ep93xx_eth.c @@ -0,0 +1,653 @@ +/* + * Cirrus Logic EP93xx ethernet MAC / MII driver. + * + * Copyright (C) 2010, 2009 + * Matthias Kaehlcke + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver, + * which is + * + * (C) Copyright 2002 2003 + * Adam Bezanson, Network Audio Technologies, Inc. + * + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ep93xx_eth.h" + +#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv) +#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs) + +/* ep93xx_miiphy ops forward declarations */ +static int ep93xx_miiphy_read(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short * const value); +static int ep93xx_miiphy_write(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short const value); + +#if defined(EP93XX_MAC_DEBUG) +/** + * Dump ep93xx_mac values to the terminal. + */ +static void dump_dev(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_dev()\n"); + printf(" rx_dq.base %p\n", priv->rx_dq.base); + printf(" rx_dq.current %p\n", priv->rx_dq.current); + printf(" rx_dq.end %p\n", priv->rx_dq.end); + printf(" rx_sq.base %p\n", priv->rx_sq.base); + printf(" rx_sq.current %p\n", priv->rx_sq.current); + printf(" rx_sq.end %p\n", priv->rx_sq.end); + + for (i = 0; i < NUMRXDESC; i++) + printf(" rx_buffer[%2.d] %p\n", i, NetRxPackets[i]); + + printf(" tx_dq.base %p\n", priv->tx_dq.base); + printf(" tx_dq.current %p\n", priv->tx_dq.current); + printf(" tx_dq.end %p\n", priv->tx_dq.end); + printf(" tx_sq.base %p\n", priv->tx_sq.base); + printf(" tx_sq.current %p\n", priv->tx_sq.current); + printf(" tx_sq.end %p\n", priv->tx_sq.end); +} + +/** + * Dump all RX status queue entries to the terminal. + */ +static void dump_rx_status_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_rx_status_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMRXDESC; i++) { + printf(" [ %p ] %08X %08X\n", + priv->rx_sq.base + i, + (priv->rx_sq.base + i)->word1, + (priv->rx_sq.base + i)->word2); + } +} + +/** + * Dump all RX descriptor queue entries to the terminal. + */ +static void dump_rx_descriptor_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_rx_descriptor_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMRXDESC; i++) { + printf(" [ %p ] %08X %08X\n", + priv->rx_dq.base + i, + (priv->rx_dq.base + i)->word1, + (priv->rx_dq.base + i)->word2); + } +} + +/** + * Dump all TX descriptor queue entries to the terminal. + */ +static void dump_tx_descriptor_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_tx_descriptor_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMTXDESC; i++) { + printf(" [ %p ] %08X %08X\n", + priv->tx_dq.base + i, + (priv->tx_dq.base + i)->word1, + (priv->tx_dq.base + i)->word2); + } +} + +/** + * Dump all TX status queue entries to the terminal. + */ +static void dump_tx_status_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_tx_status_queue()\n"); + printf(" descriptor address word1\n"); + for (i = 0; i < NUMTXDESC; i++) { + printf(" [ %p ] %08X\n", + priv->rx_sq.base + i, + (priv->rx_sq.base + i)->word1); + } +} +#else +#define dump_dev(x) +#define dump_rx_descriptor_queue(x) +#define dump_rx_status_queue(x) +#define dump_tx_descriptor_queue(x) +#define dump_tx_status_queue(x) +#endif /* defined(EP93XX_MAC_DEBUG) */ + +/** + * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until + * it's cleared. + */ +static void ep93xx_mac_reset(struct eth_device *dev) +{ + struct mac_regs *mac = GET_REGS(dev); + uint32_t value; + + debug("+ep93xx_mac_reset"); + + value = readl(&mac->selfctl); + value |= SELFCTL_RESET; + writel(value, &mac->selfctl); + + while (readl(&mac->selfctl) & SELFCTL_RESET) + ; /* noop */ + + debug("-ep93xx_mac_reset"); +} + +/* Eth device open */ +static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + struct mac_regs *mac = GET_REGS(dev); + uchar *mac_addr = dev->enetaddr; + int i; + + debug("+ep93xx_eth_open"); + + /* Reset the MAC */ + ep93xx_mac_reset(dev); + + /* Reset the descriptor queues' current and end address values */ + priv->tx_dq.current = priv->tx_dq.base; + priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC); + + priv->tx_sq.current = priv->tx_sq.base; + priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC); + + priv->rx_dq.current = priv->rx_dq.base; + priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC); + + priv->rx_sq.current = priv->rx_sq.base; + priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC); + + /* + * Set the transmit descriptor and status queues' base address, + * current address, and length registers. Set the maximum frame + * length and threshold. Enable the transmit descriptor processor. + */ + writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd); + writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd); + writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen); + + writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd); + writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd); + writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen); + + writel(0x00040000, &mac->txdthrshld); + writel(0x00040000, &mac->txststhrshld); + + writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen); + writel(BMCTL_TXEN, &mac->bmctl); + + /* + * Set the receive descriptor and status queues' base address, + * current address, and length registers. Enable the receive + * descriptor processor. + */ + writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd); + writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd); + writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen); + + writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd); + writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd); + writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen); + + writel(0x00040000, &mac->rxdthrshld); + + writel(BMCTL_RXEN, &mac->bmctl); + + writel(0x00040000, &mac->rxststhrshld); + + /* Wait until the receive descriptor processor is active */ + while (!(readl(&mac->bmsts) & BMSTS_RXACT)) + ; /* noop */ + + /* + * Initialize the RX descriptor queue. Clear the TX descriptor queue. + * Clear the RX and TX status queues. Enqueue the RX descriptor and + * status entries to the MAC. + */ + for (i = 0; i < NUMRXDESC; i++) { + /* set buffer address */ + (priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i]; + + /* set buffer length, clear buffer index and NSOF */ + (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN; + } + + memset(priv->tx_dq.base, 0, + (sizeof(struct tx_descriptor) * NUMTXDESC)); + memset(priv->rx_sq.base, 0, + (sizeof(struct rx_status) * NUMRXDESC)); + memset(priv->tx_sq.base, 0, + (sizeof(struct tx_status) * NUMTXDESC)); + + writel(NUMRXDESC, &mac->rxdqenq); + writel(NUMRXDESC, &mac->rxstsqenq); + + /* Set the primary MAC address */ + writel(AFP_IAPRIMARY, &mac->afp); + writel(mac_addr[0] | (mac_addr[1] << 8) | + (mac_addr[2] << 16) | (mac_addr[3] << 24), + &mac->indad); + writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper); + + /* Turn on RX and TX */ + writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON | + RXCTL_RCRCA | RXCTL_MA, &mac->rxctl); + writel(TXCTL_STXON, &mac->txctl); + + /* Dump data structures if we're debugging */ + dump_dev(dev); + dump_rx_descriptor_queue(dev); + dump_rx_status_queue(dev); + dump_tx_descriptor_queue(dev); + dump_tx_status_queue(dev); + + debug("-ep93xx_eth_open"); + + return 1; +} + +/** + * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL + * registers. + */ +static void ep93xx_eth_close(struct eth_device *dev) +{ + struct mac_regs *mac = GET_REGS(dev); + + debug("+ep93xx_eth_close"); + + writel(0x00000000, &mac->rxctl); + writel(0x00000000, &mac->txctl); + + debug("-ep93xx_eth_close"); +} + +/** + * Copy a frame of data from the MAC into the protocol layer for further + * processing. + */ +static int ep93xx_eth_rcv_packet(struct eth_device *dev) +{ + struct mac_regs *mac = GET_REGS(dev); + struct ep93xx_priv *priv = GET_PRIV(dev); + int len = -1; + + debug("+ep93xx_eth_rcv_packet"); + + if (RX_STATUS_RFP(priv->rx_sq.current)) { + if (RX_STATUS_RWE(priv->rx_sq.current)) { + /* + * We have a good frame. Extract the frame's length + * from the current rx_status_queue entry, and copy + * the frame's data into NetRxPackets[] of the + * protocol stack. We track the total number of + * bytes in the frame (nbytes_frame) which will be + * used when we pass the data off to the protocol + * layer via NetReceive(). + */ + len = RX_STATUS_FRAME_LEN(priv->rx_sq.current); + + NetReceive((uchar *)priv->rx_dq.current->word1, len); + + debug("reporting %d bytes...\n", len); + } else { + /* Do we have an erroneous packet? */ + error("packet rx error, status %08X %08X", + priv->rx_sq.current->word1, + priv->rx_sq.current->word2); + dump_rx_descriptor_queue(dev); + dump_rx_status_queue(dev); + } + + /* + * Clear the associated status queue entry, and + * increment our current pointers to the next RX + * descriptor and status queue entries (making sure + * we wrap properly). + */ + memset((void *)priv->rx_sq.current, 0, + sizeof(struct rx_status)); + + priv->rx_sq.current++; + if (priv->rx_sq.current >= priv->rx_sq.end) + priv->rx_sq.current = priv->rx_sq.base; + + priv->rx_dq.current++; + if (priv->rx_dq.current >= priv->rx_dq.end) + priv->rx_dq.current = priv->rx_dq.base; + + /* + * Finally, return the RX descriptor and status entries + * back to the MAC engine, and loop again, checking for + * more descriptors to process. + */ + writel(1, &mac->rxdqenq); + writel(1, &mac->rxstsqenq); + } else { + len = 0; + } + + debug("-ep93xx_eth_rcv_packet %d", len); + return len; +} + +/** + * Send a block of data via ethernet. + */ +static int ep93xx_eth_send_packet(struct eth_device *dev, + volatile void * const packet, int const length) +{ + struct mac_regs *mac = GET_REGS(dev); + struct ep93xx_priv *priv = GET_PRIV(dev); + int ret = -1; + + debug("+ep93xx_eth_send_packet"); + + /* Parameter check */ + BUG_ON(packet == NULL); + + /* + * Initialize the TX descriptor queue with the new packet's info. + * Clear the associated status queue entry. Enqueue the packet + * to the MAC for transmission. + */ + + /* set buffer address */ + priv->tx_dq.current->word1 = (uint32_t)packet; + + /* set buffer length and EOF bit */ + priv->tx_dq.current->word2 = length | TX_DESC_EOF; + + /* clear tx status */ + priv->tx_sq.current->word1 = 0; + + /* enqueue the TX descriptor */ + writel(1, &mac->txdqenq); + + /* wait for the frame to become processed */ + while (!TX_STATUS_TXFP(priv->tx_sq.current)) + ; /* noop */ + + if (!TX_STATUS_TXWE(priv->tx_sq.current)) { + error("packet tx error, status %08X", + priv->tx_sq.current->word1); + dump_tx_descriptor_queue(dev); + dump_tx_status_queue(dev); + + /* TODO: Add better error handling? */ + goto eth_send_out; + } + + ret = 0; + /* Fall through */ + +eth_send_out: + debug("-ep93xx_eth_send_packet %d", ret); + return ret; +} + +#if defined(CONFIG_MII) +int ep93xx_miiphy_initialize(bd_t * const bd) +{ + miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write); + return 0; +} +#endif + +/** + * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are + * allocated, if necessary, for the TX and RX descriptor and status queues, + * as well as for received packets. The EP93XX MAC hardware is initialized. + * Transmit and receive operations are enabled. + */ +int ep93xx_eth_initialize(u8 dev_num, int base_addr) +{ + int ret = -1; + struct eth_device *dev; + struct ep93xx_priv *priv; + + debug("+ep93xx_eth_initialize"); + + priv = malloc(sizeof(*priv)); + if (!priv) { + error("malloc() failed"); + goto eth_init_failed_0; + } + memset(priv, 0, sizeof(*priv)); + + priv->regs = (struct mac_regs *)base_addr; + + priv->tx_dq.base = calloc(NUMTXDESC, + sizeof(struct tx_descriptor)); + if (priv->tx_dq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_1; + } + + priv->tx_sq.base = calloc(NUMTXDESC, + sizeof(struct tx_status)); + if (priv->tx_sq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_2; + } + + priv->rx_dq.base = calloc(NUMRXDESC, + sizeof(struct rx_descriptor)); + if (priv->rx_dq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_3; + } + + priv->rx_sq.base = calloc(NUMRXDESC, + sizeof(struct rx_status)); + if (priv->rx_sq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_4; + } + + dev = malloc(sizeof *dev); + if (dev == NULL) { + error("malloc() failed"); + goto eth_init_failed_5; + } + memset(dev, 0, sizeof *dev); + + dev->iobase = base_addr; + dev->priv = priv; + dev->init = ep93xx_eth_open; + dev->halt = ep93xx_eth_close; + dev->send = ep93xx_eth_send_packet; + dev->recv = ep93xx_eth_rcv_packet; + + sprintf(dev->name, "ep93xx_eth-%hu", dev_num); + + eth_register(dev); + + /* Done! */ + ret = 1; + goto eth_init_done; + +eth_init_failed_5: + free(priv->rx_sq.base); + /* Fall through */ + +eth_init_failed_4: + free(priv->rx_dq.base); + /* Fall through */ + +eth_init_failed_3: + free(priv->tx_sq.base); + /* Fall through */ + +eth_init_failed_2: + free(priv->tx_dq.base); + /* Fall through */ + +eth_init_failed_1: + free(priv); + /* Fall through */ + +eth_init_failed_0: + /* Fall through */ + +eth_init_done: + debug("-ep93xx_eth_initialize %d", ret); + return ret; +} + +#if defined(CONFIG_MII) + +/** + * Maximum MII address we support + */ +#define MII_ADDRESS_MAX 31 + +/** + * Maximum MII register address we support + */ +#define MII_REGISTER_MAX 31 + +/** + * Read a 16-bit value from an MII register. + */ +static int ep93xx_miiphy_read(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short * const value) +{ + struct mac_regs *mac = (struct mac_regs *)MAC_BASE; + int ret = -1; + uint32_t self_ctl; + + debug("+ep93xx_miiphy_read"); + + /* Parameter checks */ + BUG_ON(dev == NULL); + BUG_ON(addr > MII_ADDRESS_MAX); + BUG_ON(reg > MII_REGISTER_MAX); + BUG_ON(value == NULL); + + /* + * Save the current SelfCTL register value. Set MAC to suppress + * preamble bits. Wait for any previous MII command to complete + * before issuing the new command. + */ + self_ctl = readl(&mac->selfctl); +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) + writel(self_ctl & ~(1 << 8), &mac->selfctl); +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ + + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + /* + * Issue the MII 'read' command. Wait for the command to complete. + * Read the MII data value. + */ + writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg, + &mac->miicmd); + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + *value = (unsigned short)readl(&mac->miidata); + + /* Restore the saved SelfCTL value and return. */ + writel(self_ctl, &mac->selfctl); + + ret = 0; + /* Fall through */ + + debug("-ep93xx_miiphy_read"); + return ret; +} + +/** + * Write a 16-bit value to an MII register. + */ +static int ep93xx_miiphy_write(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short const value) +{ + struct mac_regs *mac = (struct mac_regs *)MAC_BASE; + int ret = -1; + uint32_t self_ctl; + + debug("+ep93xx_miiphy_write"); + + /* Parameter checks */ + BUG_ON(dev == NULL); + BUG_ON(addr > MII_ADDRESS_MAX); + BUG_ON(reg > MII_REGISTER_MAX); + + /* + * Save the current SelfCTL register value. Set MAC to suppress + * preamble bits. Wait for any previous MII command to complete + * before issuing the new command. + */ + self_ctl = readl(&mac->selfctl); +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) + writel(self_ctl & ~(1 << 8), &mac->selfctl); +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ + + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + /* Issue the MII 'write' command. Wait for the command to complete. */ + writel((uint32_t)value, &mac->miidata); + writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg, + &mac->miicmd); + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + /* Restore the saved SelfCTL value and return. */ + writel(self_ctl, &mac->selfctl); + + ret = 0; + /* Fall through */ + + debug("-ep93xx_miiphy_write"); + return ret; +} +#endif /* defined(CONFIG_MII) */ diff --git a/drivers/net/ep93xx_eth.h b/drivers/net/ep93xx_eth.h new file mode 100644 index 0000000..4654b2f --- /dev/null +++ b/drivers/net/ep93xx_eth.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _EP93XX_ETH_H +#define _EP93XX_ETH_H + +#include + +/** + * #define this to dump device status and queue info during initialization and + * following errors. + */ +#undef EP93XX_MAC_DEBUG + +/** + * Number of descriptor and status entries in our RX queues. + * It must be power of 2 ! + */ +#define NUMRXDESC PKTBUFSRX + +/** + * Number of descriptor and status entries in our TX queues. + */ +#define NUMTXDESC 1 + +/** + * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT) + */ +#define TXSTARTMAX 944 + +/** + * Receive descriptor queue entry + */ +struct rx_descriptor { + uint32_t word1; + uint32_t word2; +}; + +/** + * Receive status queue entry + */ +struct rx_status { + uint32_t word1; + uint32_t word2; +}; + +#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01) +#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01) +#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF) + +/** + * Transmit descriptor queue entry + */ +struct tx_descriptor { + uint32_t word1; + uint32_t word2; +}; + +#define TX_DESC_EOF (1 << 31) + +/** + * Transmit status queue entry + */ +struct tx_status { + uint32_t word1; +}; + +#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01) +#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01) + +/** + * Transmit descriptor queue + */ +struct tx_descriptor_queue { + struct tx_descriptor *base; + struct tx_descriptor *current; + struct tx_descriptor *end; +}; + +/** + * Transmit status queue + */ +struct tx_status_queue { + struct tx_status *base; + volatile struct tx_status *current; + struct tx_status *end; +}; + +/** + * Receive descriptor queue + */ +struct rx_descriptor_queue { + struct rx_descriptor *base; + struct rx_descriptor *current; + struct rx_descriptor *end; +}; + +/** + * Receive status queue + */ +struct rx_status_queue { + struct rx_status *base; + volatile struct rx_status *current; + struct rx_status *end; +}; + +/** + * EP93xx MAC private data structure + */ +struct ep93xx_priv { + struct rx_descriptor_queue rx_dq; + struct rx_status_queue rx_sq; + void *rx_buffer[NUMRXDESC]; + + struct tx_descriptor_queue tx_dq; + struct tx_status_queue tx_sq; + + struct mac_regs *regs; +}; + +#endif diff --git a/include/common.h b/include/common.h index 86e3163..a133e34 100644 --- a/include/common.h +++ b/include/common.h @@ -123,6 +123,11 @@ typedef volatile unsigned char vu_char; #define debugX(level,fmt,args...) #endif /* DEBUG */ +#define error(fmt, args...) do { \ + printf("ERROR: " fmt "\nat %s:%d/%s()\n", \ + ##args, __FILE__, __LINE__, __func__); \ +} while (0) + #ifndef BUG #define BUG() do { \ printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ diff --git a/include/netdev.h b/include/netdev.h index a9d5ec9..1e0484f 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -49,6 +49,7 @@ int davinci_emac_initialize(void); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis); +int ep93xx_eth_initialize(u8 dev_num, int base_addr); int eth_3com_initialize (bd_t * bis); int fec_initialize (bd_t *bis); int fecmxc_initialize (bd_t *bis); -- cgit v1.1