From ba70d6a4170ebbec5513f01ceae66a200102ba9a Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Fri, 24 Mar 2006 12:23:27 +0100 Subject: delta board: DA9030 initialization and i2c support. Some minor changes to make the pxa i2c driver work with the monahans cpu. --- board/delta/delta.c | 67 +++++++++++++++++++++++ cpu/pxa/i2c.c | 19 +++++-- include/asm-arm/arch-pxa/pxa-regs.h | 6 +- include/configs/delta.h | 18 ++++-- include/da9030.h | 106 ++++++++++++++++++++++++++++++++++++ 5 files changed, 204 insertions(+), 12 deletions(-) create mode 100644 include/da9030.h diff --git a/board/delta/delta.c b/board/delta/delta.c index 3ffcc2a..6ef7e2f 100644 --- a/board/delta/delta.c +++ b/board/delta/delta.c @@ -26,9 +26,13 @@ */ #include +#include +#include +#include /* ------------------------------------------------------------------------- */ +static void init_DA9030(void); /* * Miscelaneous platform dependent initialisations @@ -54,6 +58,7 @@ int board_late_init(void) { setenv("stdout", "serial"); setenv("stderr", "serial"); + init_DA9030(); return 0; } @@ -73,3 +78,65 @@ int dram_init (void) return 0; } + +/* initialize the DA9030 Power Controller */ +static void init_DA9030() +{ + uchar addr = (uchar) DA9030_I2C_ADDR, val = 0; + + /* setup I2C GPIO's */ + GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */ + GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */ + + /* rising Edge on EXTON */ + GPIO17 = 0x8800; + udelay(5); + GPIO17 = 0xc800; + udelay(100000); /* wait for DA9030 */ + + /* reset the watchdog and go active (0xec) */ + val = (SYS_CONTROL_A_HWRES_ENABLE | + (0x6<<4) | + SYS_CONTROL_A_WDOG_ACTION | + SYS_CONTROL_A_WATCHDOG); + + i2c_reg_write(addr, SYS_CONTROL_A, val); + + i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */ + i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */ + i2c_reg_write(addr, LDO4_5, 0xcc); /* LDO2 =1,9V, LDO3=3,1V */ + i2c_reg_write(addr, LDO6_SIMCP, 0x3e); /* LDO6=3,2V, SIMCP = 5V support */ + i2c_reg_write(addr, LDO7_8, 0xc9); /* LDO7=2,7V, LDO8=3,0V */ + i2c_reg_write(addr, LDO9_12, 0xec); /* LDO9=3,0V, LDO12=3,2V */ + i2c_reg_write(addr, BUCK, 0x0c); /* Buck=1.2V */ + i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */ + i2c_reg_write(addr, LDO_10_11, 0xcc); /* LDO10=3.0V LDO11=3.0V */ + i2c_reg_write(addr, LDO_15, 0xae); /* LDO15=1.8V, dislock first 3bit */ + i2c_reg_write(addr, LDO_14_16, 0x05); /* LDO14=2.8V, LDO16=NB */ + i2c_reg_write(addr, LDO_18_19, 0x9c); /* LDO18=3.0V, LDO19=2.7V */ + i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */ + i2c_reg_write(addr, BUCK2_DVC1, 0x9a); /* Buck2=1.5V plus Update support of 520 MHz */ + i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */ + i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */ + i2c_reg_write(addr, USBPUMP, 0xc1); /* start pump, ignore HW signals */ + + val = i2c_reg_read(addr, STATUS); + if(val & STATUS_CHDET) + printf("Charger detected, turning on LED.\n"); + else { + printf("No charger detetected.\n"); + /* undervoltage? print error and power down */ + } +} + + +#if 0 +/* reset the DA9030 watchdog */ +void hw_watchdog_reset(void) +{ + uchar addr = (uchar) DA9030_I2C_ADDR, val = 0; + val = i2c_reg_read(addr, SYS_CONTROL_A); + val |= SYS_CONTROL_A_WATCHDOG; + i2c_reg_write(addr, SYS_CONTROL_A, val); +} +#endif diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c index b6155b1..722d949 100644 --- a/cpu/pxa/i2c.c +++ b/cpu/pxa/i2c.c @@ -47,7 +47,13 @@ /*#define DEBUG_I2C 1 /###* activate local debugging output */ #define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ -#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) + +#if (CFG_I2C_SPEED == 400000) +#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) +#else +#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) +#endif + #define I2C_ISR_INIT 0x7FF #ifdef DEBUG_I2C @@ -91,7 +97,11 @@ static void i2c_reset( void ) ICR |= ICR_UR; /* reset the unit */ udelay(100); ICR &= ~ICR_IUE; /* disable unit */ +#ifdef CONFIG_CPU_MONAHANS + CKENB |= (CKENB_4_I2C); /* | CKENB_1_PWM1 | CKENB_0_PWM0); */ +#else /* CONFIG_CPU_MONAHANS */ CKEN |= CKEN14_I2C; /* set the global I2C clock on */ +#endif ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */ ICR = I2C_ICR_INIT; /* set control register values */ ISR = I2C_ISR_INIT; /* set clear interrupt bits */ @@ -104,9 +114,8 @@ static void i2c_reset( void ) * i2c_isr_set_cleared: - wait until certain bits of the I2C status register * are set and cleared * - * @return: 0 in case of success, 1 means timeout (no match within 10 ms). + * @return: 1 in case of success, 0 means timeout (no match within 10 ms). */ - static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask ) { int timeout = 10000; @@ -360,9 +369,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) msg.data = 0x00; if ((ret=i2c_transfer(&msg))) return -1; - *(buffer++) = msg.data; - + *buffer = msg.data; PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); + buffer++; } diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index a92a450..ebda719 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -475,11 +475,11 @@ typedef void (*ExcpHndlr) (void) ; #define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */ #define ICR_TB 0x8 /* transfer byte bit */ #define ICR_MA 0x10 /* master abort */ -#define ICR_SCLE 0x20 /* master clock enable */ +#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */ #define ICR_IUE 0x40 /* unit enable */ #define ICR_GCD 0x80 /* general call disable */ #define ICR_ITEIE 0x100 /* enable tx interrupts */ -#define ICR_IRFIE 0x200 /* enable rx interrupts */ +#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */ #define ICR_BEIE 0x400 /* enable bus error ints */ #define ICR_SSDIE 0x800 /* slave STOP detected int enable */ #define ICR_ALDIE 0x1000 /* enable arbitration interrupt */ @@ -923,7 +923,7 @@ typedef void (*ExcpHndlr) (void) ; #define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */ /* Missing: 32 Interrupt priority registers * These are the same as beneath for PXA27x: maybe can be merged if - * GPIO Stuff is same too. + * GPIO Stuff is same too. */ #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ diff --git a/include/configs/delta.h b/include/configs/delta.h index cb002f7..eaa4c43 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -49,7 +49,6 @@ /* * Hardware drivers */ - #undef TURN_ON_ETHERNET #ifdef TURN_ON_ETHERNET # define CONFIG_DRIVER_SMC91111 1 @@ -59,6 +58,12 @@ # undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */ #endif +#define CONFIG_HARD_I2C 1 /* required for DA9030 access */ +#define CFG_I2C_SPEED 400000 /* I2C speed */ +#define CFG_I2C_SLAVE 1 /* I2C controllers address */ +#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */ +/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */ + /* * select serial console configuration */ @@ -73,8 +78,13 @@ #ifdef TURN_ON_ETHERNET # define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) #else -# define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_ENV | CFG_CMD_NAND) \ - & ~(CFG_CMD_NET | CFG_CMD_FLASH | CFG_CMD_IMLS)) +# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_ENV \ + | CFG_CMD_NAND \ + | CFG_CMD_I2C) \ + & ~(CFG_CMD_NET \ + | CFG_CMD_FLASH \ + | CFG_CMD_IMLS)) #endif @@ -121,7 +131,7 @@ #define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */ #define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ /* valid baudrates */ diff --git a/include/da9030.h b/include/da9030.h new file mode 100644 index 0000000..41108b9 --- /dev/null +++ b/include/da9030.h @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* DA9030 register definitions */ +#define CID 0x00 +#define EVENT_A 0x01 +#define EVENT_B 0x02 +#define EVENT_C 0x03 +#define STATUS 0x04 +#define IRQ_MASK_A 0x05 +#define IRQ_MASK_B 0x06 +#define IRQ_MASK_C 0x07 +#define SYS_CONTROL_A 0x08 +#define SYS_CONTROL_B 0x09 +#define FAULT_LOG 0x0A +#define LDO_10_11 0x10 +#define LDO_15 0x11 +#define LDO_14_16 0x12 +#define LDO_18_19 0x13 +#define LDO_17_SIMCP0 0x14 +#define BUCK2_DVC1 0x15 +#define BUCK2_DVC2 0x16 +#define REG_CONTROL_1_17 0x17 +#define REG_CONTROL_2_18 0x18 +#define USBPUMP 0x19 +#define SLEEP_CONTROL 0x1A +#define STARTUP_CONTROL 0x1B +#define LED1_CONTROL 0x20 +#define LED2_CONTROL 0x21 +#define LED3_CONTROL 0x22 +#define LED4_CONTROL 0x23 +#define LEDPC_CONTROL 0x24 +#define WLED_CONTROL 0x25 +#define MISC_CONTROLA 0x26 +#define MISC_CONTROLB 0x27 +#define CHARGE_CONTROL 0x28 +#define CCTR_CONTROL 0x29 +#define TCTR_CONTROL 0x2A +#define CHARGE_PULSE 0x2B + +/* ... some missing ...*/ + +#define LDO1 0x90 +#define LDO2_3 0x91 +#define LDO4_5 0x92 +#define LDO6_SIMCP 0x93 +#define LDO7_8 0x94 +#define LDO9_12 0x95 +#define BUCK 0x96 +#define REG_CONTROL_1_97 0x97 +#define REG_CONTROL_2_98 0x98 +#define REG_SLEEP_CONTROL1 0x99 +#define REG_SLEEP_CONTROL2 0x9A +#define REG_SLEEP_CONTROL3 0x9B +#define ADC_MAN_CONTROL 0xA0 +#define ADC_AUTO_CONTROL 0xA1 +#define VBATMON 0xA2 +#define VBATMONTXMON 0xA3 +#define TBATHIGHP 0xA4 +#define TBATHIGHN 0xA5 +#define TBATLOW 0xA6 +#define MAN_RES 0xB0 +#define VBAT_RES 0xB1 +#define VBATMIN_RES 0xB2 +#define VBATMINTXON_RES 0xB3 +#define ICHMAX_RES 0xB4 +#define ICHMIN_RES 0xB5 +#define ICHAVERAGE_RES 0xB6 +#define VCHMAX_RES 0xB7 +#define VCHMIN_RES 0xB8 +#define TBAT_RES 0xB9 +#define ADC_IN4_RES 0xBA + +#define STATUS_ONKEY_N 0x1 /* current ONKEY_N value */ +#define STATUS_PWREN1 (1<<1) /* PWREN1 value */ +#define STATUS_EXTON (1<<2) /* EXTON value */ +#define STATUS_CHDET (1<<3) /* Charger detection status */ +#define STATUS_TBAT (1<<4) /* Battery over/under temperature status */ +#define STATUS_VBATMON (1<<5) /* VBATMON comparison status */ +#define STATUS_VBATMONTXON (1<<6) /* VBATMONTXON comparison status */ +#define STATUS_CHIOVER (1<<7) /* Charge overcurrent */ + +#define SYS_CONTROL_A_SLEEP_N_PIN_ENABLE 0x1 +#define SYS_CONTROL_A_SHUT_DOWN (1<<1) +#define SYS_CONTROL_A_HWRES_ENABLE (1<<2) +#define SYS_CONTROL_A_WDOG_ACTION (1<<3) +#define SYS_CONTROL_A_WATCHDOG (1<<7) -- cgit v1.1