From b1d71358a9448802a08bc822b78debe9f754eae7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 10 Jun 2006 22:00:40 +0200 Subject: Minor code cleanup. --- board/BuS/EB+MCF-EV123/Makefile | 2 +- board/BuS/EB+MCF-EV123/VCxK.c | 2 +- board/BuS/EB+MCF-EV123/cfm_flash.c | 2 +- board/BuS/EB+MCF-EV123/flash.c | 4 +- cpu/mcf52x2/fec.c | 8 ++-- include/asm-m68k/immap_5282.h | 76 +++++++++++++++++++------------------- include/configs/EB+MCF-EV123.h | 10 ++--- 7 files changed, 51 insertions(+), 53 deletions(-) diff --git a/board/BuS/EB+MCF-EV123/Makefile b/board/BuS/EB+MCF-EV123/Makefile index d5dbc71..0596572 100644 --- a/board/BuS/EB+MCF-EV123/Makefile +++ b/board/BuS/EB+MCF-EV123/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o +OBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/BuS/EB+MCF-EV123/VCxK.c b/board/BuS/EB+MCF-EV123/VCxK.c index 736c101..4938817 100644 --- a/board/BuS/EB+MCF-EV123/VCxK.c +++ b/board/BuS/EB+MCF-EV123/VCxK.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005 * BuS Elektronik GmbH & Co.KG * * See file CREDITS for list of people who contributed to this diff --git a/board/BuS/EB+MCF-EV123/cfm_flash.c b/board/BuS/EB+MCF-EV123/cfm_flash.c index d5a1c30..6ecf0d1 100644 --- a/board/BuS/EB+MCF-EV123/cfm_flash.c +++ b/board/BuS/EB+MCF-EV123/cfm_flash.c @@ -22,7 +22,7 @@ * MA 02111-1307 USA */ -#include +#include #include #include "cfm_flash.h" diff --git a/board/BuS/EB+MCF-EV123/flash.c b/board/BuS/EB+MCF-EV123/flash.c index a5d621c..ba76bef 100644 --- a/board/BuS/EB+MCF-EV123/flash.c +++ b/board/BuS/EB+MCF-EV123/flash.c @@ -1,7 +1,7 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005 * BuS Elektronik GmbH & Co.KG - * + * * Based On * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c index 702563d..6db6214 100644 --- a/cpu/mcf52x2/fec.c +++ b/cpu/mcf52x2/fec.c @@ -283,7 +283,7 @@ int eth_init (bd_t * bd) rtx = (RTXBD *) CFG_ENET_BD_BASE; #else rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off - - (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t) + (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t) +0xFF) & ~0xFF) ); @@ -327,13 +327,13 @@ int eth_init (bd_t * bd) fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; #else /* Half duplex mode */ - fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */ + fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */ fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; fecp->fec_x_cntrl = 0; #endif /* Set MII speed */ - fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10; - fecp->fec_mii_speed *= 2; + fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10; + fecp->fec_mii_speed *= 2; /* Configure port B for MII. */ diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h index a95912f..6553b08 100644 --- a/include/asm-m68k/immap_5282.h +++ b/include/asm-m68k/immap_5282.h @@ -13,7 +13,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -41,47 +41,45 @@ struct sys_ctrl { /* TODO: finish these */ }; - - /* Fast ethernet controller registers */ typedef struct fec { - uint res1; /* reserved 1000*/ - uint fec_ievent; /* interrupt event register 1004*/ /* EIR */ - uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */ - uint res2; /* reserved 100c*/ - uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */ - uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */ - uint res3[3]; /* reserved 1018*/ - uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */ - uint res4[6]; /* reserved 1028*/ - uint fec_mii_data; /* MII data register 1040*/ /* MDATA */ - uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */ - /*1044*/ - uint res5[7]; /* reserved 1048*/ - uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */ - uint res6[7]; /* reserved 1068*/ - uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */ - uint res7[15]; /* reserved 1088*/ - uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */ - uint res8[7]; /* reserved 10C8*/ - uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */ - uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */ - uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */ - uint res9[10]; /* reserved 10F0*/ - uint fec_ihash_table_high; /* upper 32-bits of individual hash *//* IAUR */ - uint fec_ihash_table_low; /* lower 32-bits of individual hash *//* IALR */ - uint fec_ghash_table_high; /* upper 32-bits of group hash *//* GAUR */ - uint fec_ghash_table_low; /* lower 32-bits of group hash *//* GALR */ - uint res10[7]; /* reserved 1128*/ - uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */ - uint res11; /* reserved 1148*/ - uint fec_r_bound; /* FIFO Receive Bound Register = end of *//* FRBR */ - uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = *//* FRSR */ - uint res12[11]; /* reserved 1154*/ - uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*//* ERDSR */ - uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*//* ETDSR */ - uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */ + uint res1; /* reserved 1000*/ + uint fec_ievent; /* interrupt event register 1004*/ /* EIR */ + uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */ + uint res2; /* reserved 100c*/ + uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */ + uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */ + uint res3[3]; /* reserved 1018*/ + uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */ + uint res4[6]; /* reserved 1028*/ + uint fec_mii_data; /* MII data register 1040*/ /* MDATA */ + uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */ + /*1044*/ + uint res5[7]; /* reserved 1048*/ + uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */ + uint res6[7]; /* reserved 1068*/ + uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */ + uint res7[15]; /* reserved 1088*/ + uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */ + uint res8[7]; /* reserved 10C8*/ + uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */ + uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */ + uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */ + uint res9[10]; /* reserved 10F0*/ + uint fec_ihash_table_high; /* upper 32-bits of individual hash */ /* IAUR */ + uint fec_ihash_table_low; /* lower 32-bits of individual hash */ /* IALR */ + uint fec_ghash_table_high; /* upper 32-bits of group hash */ /* GAUR */ + uint fec_ghash_table_low; /* lower 32-bits of group hash */ /* GALR */ + uint res10[7]; /* reserved 1128*/ + uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */ + uint res11; /* reserved 1148*/ + uint fec_r_bound; /* FIFO Receive Bound Register = end of */ /* FRBR */ + uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = */ /* FRSR */ + uint res12[11]; /* reserved 1154*/ + uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*/ /* ERDSR */ + uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*/ /* ETDSR */ + uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */ } fec_t; #endif /* __IMMAP_5282__ */ diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index f49a4b7..720b335 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -30,7 +30,7 @@ #undef DEBUG #undef CFG_HALT_BEFOR_RAM_JUMP #undef ET_DEBUG - + /* * High Level Configuration Options (easy to change) */ @@ -68,7 +68,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif -//#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) +/*#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) */ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB)) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -95,12 +95,12 @@ #undef CFG_DRAM_TEST /* Clock and PLL Configuration */ -#define CFG_HZ 10000000 +#define CFG_HZ 10000000 #define CFG_CLK 58982400 /* 9,8304MHz * 6 */ /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ -#define CFG_MFD 0x01 /* PLL Multiplication Factor Devider */ +#define CFG_MFD 0x01 /* PLL Multiplication Factor Devider */ #define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */ /* @@ -143,7 +143,7 @@ /* If M5282 port is fully implemented the monitor base will be behind * the vector table. */ #if (TEXT_BASE != CFG_INT_FLASH_BASE) -#define CFG_MONITOR_BASE (TEXT_BASE + 0x400) +#define CFG_MONITOR_BASE (TEXT_BASE + 0x400) #else #define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ #endif -- cgit v1.1