From 674ef7bd02de948b6d8757f6a43a6f2fa4d88769 Mon Sep 17 00:00:00 2001 From: Liu Yu Date: Mon, 18 Jan 2010 19:03:28 +0800 Subject: Nand boot: Add nand boot support for MPC8569mds board This patch add nand boot support for MPC8569mds board. Signed-off-by: Liu Yu --- MAKEALL | 1 + Makefile | 1 + board/freescale/mpc8569mds/config.mk | 9 ++ board/freescale/mpc8569mds/tlb.c | 11 ++ include/configs/MPC8569MDS.h | 64 +++++++++++- nand_spl/board/freescale/mpc8569mds/Makefile | 133 ++++++++++++++++++++++++ nand_spl/board/freescale/mpc8569mds/nand_boot.c | 75 +++++++++++++ 7 files changed, 291 insertions(+), 3 deletions(-) create mode 100644 nand_spl/board/freescale/mpc8569mds/Makefile create mode 100644 nand_spl/board/freescale/mpc8569mds/nand_boot.c diff --git a/MAKEALL b/MAKEALL index 15e93cf..aac52bb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -404,6 +404,7 @@ LIST_85xx=" \ MPC8568MDS \ MPC8569MDS \ MPC8569MDS_ATM \ + MPC8569MDS_NAND \ MPC8572DS \ MPC8572DS_36BIT \ P2020DS \ diff --git a/Makefile b/Makefile index 69b963f..c4ef585 100644 --- a/Makefile +++ b/Makefile @@ -2490,6 +2490,7 @@ MPC8568MDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale MPC8569MDS_ATM_config \ +MPC8569MDS_NAND_config \ MPC8569MDS_config: unconfig @$(MKCONFIG) -t $(@:_config=) MPC8569MDS ppc mpc85xx mpc8569mds freescale diff --git a/board/freescale/mpc8569mds/config.mk b/board/freescale/mpc8569mds/config.mk index 962f79b..7de0f7c 100644 --- a/board/freescale/mpc8569mds/config.mk +++ b/board/freescale/mpc8569mds/config.mk @@ -23,4 +23,13 @@ # # mpc8569mds board # +ifndef NAND_SPL +ifeq ($(CONFIG_MK_NAND), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds +endif +endif + +ifndef TEXT_BASE TEXT_BASE = 0xfff80000 +endif diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c index 3b8ee05..73dcc3e 100644 --- a/board/freescale/mpc8569mds/tlb.c +++ b/board/freescale/mpc8569mds/tlb.c @@ -90,6 +90,17 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index ae2fc19..6cf807b 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -62,6 +62,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_NAND 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 +#endif + /* * Only possible on E500 Version 2 or newer cores. */ @@ -74,16 +80,29 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_END 0x00400000 /* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR +#else +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif + #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) @@ -152,8 +171,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE /*Chip select 0 - Flash*/ -#define CONFIG_SYS_BR0_PRELIM 0xfe000801 -#define CONFIG_SYS_OR0_PRELIM 0xfe000ff7 +#define CONFIG_FLASH_BR_PRELIM 0xfe000801 +#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 /*Chip select 1 - BCSR*/ #define CONFIG_SYS_BR1_PRELIM 0xf8000801 @@ -175,12 +194,33 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO /* Chip select 3 - NAND */ +#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xFC000000 +#else +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#endif + +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START \ + (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) + #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -200,8 +240,18 @@ extern unsigned long get_clock_freq(void); | OR_FCM_SCY_1 \ | OR_FCM_TRLX \ | OR_FCM_EHTR) + +#ifdef CONFIG_RAMBOOT_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#endif /* * SDRAM on the LocalBus @@ -437,10 +487,18 @@ extern unsigned long get_clock_freq(void); /* * Environment */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif +#else #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile new file mode 100644 index 0000000..7ed9d61 --- /dev/null +++ b/nand_spl/board/freescale/mpc8569mds/Makefile @@ -0,0 +1,133 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +TEXT_BASE := 0xfff00000 +PAD_TO := 0xfff01000 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o resetvec.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)fsl_law.c: + @rm -f $(obj)fsl_law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + +$(obj)nand_boot_fsl_elbc.c: + @rm -f $(obj)nand_boot_fsl_elbc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S + +$(obj)fixed_ivor.S: + @rm -f $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + +$(obj)start.S: $(obj)fixed_ivor.S + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +endif + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/mpc8569mds/nand_boot.c b/nand_spl/board/freescale/mpc8569mds/nand_boot.c new file mode 100644 index 0000000..e030656 --- /dev/null +++ b/nand_spl/board/freescale/mpc8569mds/nand_boot.c @@ -0,0 +1,75 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SYSCLK_66 66666666 + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong bootflag) +{ + uint plat_ratio, bus_clk, sys_clk; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + sys_clk = SYSCLK_66; + + plat_ratio = gur->porpllsr & 0x0000003e; + plat_ratio >>= 1; + bus_clk = plat_ratio * sys_clk; + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* copy code to DDR and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} -- cgit v1.1 From 15b86c3d6c9a5a2e917b73d758a556568430021a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 16 Jan 2010 21:50:26 -0700 Subject: env_nand.c: print error message and fail gracefully env_nand.c would crash silently if a malloc() for the environment buffers failed; make it print an error message and fail gracefully, i. e. use the default environment then. Signed-off-by: Wolfgang Denk Acked-by: John Rigby --- common/env_nand.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/common/env_nand.c b/common/env_nand.c index ca631af..a15a950 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -298,6 +298,13 @@ void env_relocate_spec (void) tmp_env1 = (env_t *) malloc(CONFIG_ENV_SIZE); tmp_env2 = (env_t *) malloc(CONFIG_ENV_SIZE); + if ((tmp_env1 == NULL) || (tmp_env2 == NULL)) { + puts("Can't allocate buffers for environment\n"); + free (tmp_env1); + free (tmp_env2); + return use_default(); + } + if (readenv(CONFIG_ENV_OFFSET, (u_char *) tmp_env1)) puts("No Valid Environment Area Found\n"); if (readenv(CONFIG_ENV_OFFSET_REDUND, (u_char *) tmp_env2)) -- cgit v1.1 From ef22b50370f7b6d8deba9e9e64d2cb13c542b647 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Mon, 25 Jan 2010 23:12:52 -0700 Subject: arm926ejs: add nand_spl boot support Add CONFIG_PRELOADER/CONFIG_NAND_SPL support for nand booting to arm926ejs/start.S This is derived from CONFIG_PRELOADER support in arm1136/start.S Signed-off-by: John Rigby CC: Scott Wood --- cpu/arm926ejs/start.S | 42 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S index 4421b6a..3b81151 100644 --- a/cpu/arm926ejs/start.S +++ b/cpu/arm926ejs/start.S @@ -53,6 +53,27 @@ .globl _start _start: b reset +#ifdef CONFIG_PRELOADER +/* No exception handlers in preloader */ + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + +_hang: + .word do_hang +/* pad to 64 byte boundary */ + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 +#else ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -76,6 +97,7 @@ _irq: _fiq: .word fiq +#endif /* CONFIG_PRELOADER */ .balignl 16,0xdeadbeef @@ -150,7 +172,6 @@ relocate: /* relocate U-Boot to RAM */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ cmp r0, r1 /* don't reloc during debug */ beq stack_setup - ldr r2, _armboot_start ldr r3, _bss_start sub r2, r3, r2 /* r2 <- size of armboot */ @@ -166,11 +187,14 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub sp, r0, #128 /* leave 32 words for abort-stack */ +#ifndef CONFIG_PRELOADER sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif +#endif /* CONFIG_PRELOADER */ sub sp, r0, #12 /* leave 3 words for abort-stack */ bic sp, r0, #7 /* 8-byte align stack for ABI compliance */ @@ -179,6 +203,7 @@ clear_bss: ldr r1, _bss_end /* stop here */ mov r2, #0x00000000 /* clear */ +#ifndef CONFIG_PRELOADER clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 @@ -186,11 +211,16 @@ clbss_l:str r2, [r0] /* clear loop... */ bl coloured_LED_init bl red_LED_on +#endif /* CONFIG_PRELOADER */ ldr pc, _start_armboot _start_armboot: +#ifdef CONFIG_NAND_SPL + .word nand_boot +#else .word start_armboot +#endif /* CONFIG_NAND_SPL */ /* @@ -231,6 +261,7 @@ cpu_init_crit: mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#ifndef CONFIG_PRELOADER /* ************************************************************************* * @@ -332,10 +363,18 @@ cpu_init_crit: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm +#endif /* CONFIG_PRELOADER */ /* * exception handlers */ +#ifdef CONFIG_PRELOADER + .align 5 +do_hang: + ldr sp, _TEXT_BASE /* switch to abort stack */ +1: + bl 1b /* hang and never return */ +#else /* !CONFIG_PRELOADER */ .align 5 undefined_instruction: get_bad_stack @@ -398,3 +437,4 @@ fiq: bl do_fiq #endif +#endif /* CONFIG_PRELOADER */ -- cgit v1.1 From f3bb63a304c4e76010a2a4e99da61f7b6ffffc77 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Tue, 26 Jan 2010 19:24:17 -0700 Subject: Add MX25 support to nand_spl fsl nfc driver MX25 has a different version of the fsl_nfc flash controller known as version 1.1. Add support to the nand_spl fsl_nfc driver Versioning differs from mainline mxc kernel driver no consensus yet on if the naming here and in Redboot or the kernel is "correct". Signed-off-by: John Rigby Signed-off-by: Wolfgang Denk CC: Scott Wood --- include/fsl_nfc.h | 86 +++++++++++++++++++++++++++++++++++++------- nand_spl/nand_boot_fsl_nfc.c | 72 +++++++++++++++++++++++++++++-------- 2 files changed, 131 insertions(+), 27 deletions(-) diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h index da5be37..279aaa5 100644 --- a/include/fsl_nfc.h +++ b/include/fsl_nfc.h @@ -1,5 +1,4 @@ /* - * * (c) 2009 Magnus Lilja * * See file CREDITS for list of people who contributed to this @@ -25,21 +24,57 @@ #define __FSL_NFC_H /* + * TODO: Use same register defs for nand_spl mxc nand driver + * and mtd mxc nand driver. + * * Register map and bit definitions for the Freescale NAND Flash - * Controller present in i.MX31 and other devices. + * Controller present in various i.MX devices. + * + * MX31 and MX27 have version 1 which has + * 4 512 byte main buffers and + * 4 16 byte spare buffers + * to support up to 2K byte pagesize nand. + * Reading or writing a 2K page requires 4 FDI/FDO cycles. + * + * MX25 has version 1.1 which has + * 8 512 byte main buffers and + * 8 64 byte spare buffers + * to support up to 4K byte pagesize nand. + * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. + * Also some of registers are moved and/or changed meaning as seen below. */ +#if defined(CONFIG_MX31) || defined(CONFIG_MX27) +#define MXC_NFC_V1 +#elif defined(CONFIG_MX25) +#define MXC_NFC_V1_1 +#else +#warning "MXC NFC version not defined" +#endif + +#if defined(MXC_NFC_V1) +#define NAND_MXC_NR_BUFS 4 +#define NAND_MXC_SPARE_BUF_SIZE 16 +#define NAND_MXC_REG_OFFSET 0xe00 +#define NAND_MXC_2K_MULTI_CYCLE 1 +#elif defined(MXC_NFC_V1_1) +#define NAND_MXC_NR_BUFS 8 +#define NAND_MXC_SPARE_BUF_SIZE 64 +#define NAND_MXC_REG_OFFSET 0x1e00 +#else +#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver" +#endif struct fsl_nfc_regs { - u32 main_area0[128]; /* @0x000 */ - u32 main_area1[128]; - u32 main_area2[128]; - u32 main_area3[128]; - u32 spare_area0[4]; - u32 spare_area1[4]; - u32 spare_area2[4]; - u32 spare_area3[4]; - u32 reserved1[64 - 16 + 64 * 5]; - u16 bufsiz; /* @ 0xe00 */ + u32 main_area[NAND_MXC_NR_BUFS][512/4]; + u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4]; + /* + * reserved size is offset of nfc registers + * minus total main and spare sizes + */ + u8 reserved1[NAND_MXC_REG_OFFSET + - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)]; +#if defined(MXC_NFC_V1) + u16 bufsiz; u16 reserved2; u16 buffer_address; u16 flash_add; @@ -54,6 +89,30 @@ struct fsl_nfc_regs { u16 nand_flash_wr_pr_st; u16 nand_flash_config1; u16 nand_flash_config2; +#elif defined(MXC_NFC_V1_1) + u16 reserved2[2]; + u16 buffer_address; + u16 flash_add; + u16 flash_cmd; + u16 configuration; + u16 ecc_status_result; + u16 ecc_status_result2; + u16 spare_area_size; + u16 nf_wr_prot; + u16 reserved3[2]; + u16 nand_flash_wr_pr_st; + u16 nand_flash_config1; + u16 nand_flash_config2; + u16 reserved4; + u16 unlock_start_blk_add0; + u16 unlock_end_blk_add0; + u16 unlock_start_blk_add1; + u16 unlock_end_blk_add1; + u16 unlock_start_blk_add2; + u16 unlock_end_blk_add2; + u16 unlock_start_blk_add3; + u16 unlock_end_blk_add3; +#endif }; /* @@ -98,6 +157,9 @@ struct fsl_nfc_regs { */ #define NFC_INT 0x8000 +#ifdef MXC_NFC_V1_1 +#define NFC_4_8N_ECC (1 << 0) +#endif #define NFC_SP_EN (1 << 2) #define NFC_ECC_EN (1 << 3) #define NFC_INT_MSK (1 << 4) diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c index a9df2a8..f4040a7 100644 --- a/nand_spl/nand_boot_fsl_nfc.c +++ b/nand_spl/nand_boot_fsl_nfc.c @@ -26,11 +26,15 @@ #include #include +#ifdef CONFIG_MX31 #include +#else +#include +#endif #include #include -static struct fsl_nfc_regs *nfc; +struct fsl_nfc_regs *nfc; static void nfc_wait_ready(void) { @@ -45,13 +49,35 @@ static void nfc_wait_ready(void) writew(tmp, &nfc->nand_flash_config2); } -static void nfc_nand_init(void) +void nfc_nand_init(void) { +#if defined(MXC_NFC_V1_1) + int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; + int config1; + + writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size); + + /* unlocking RAM Buff */ + writew(0x2, &nfc->configuration); + + /* hardware ECC checking and correct */ + config1 = readw(&nfc->nand_flash_config1) | NFC_ECC_EN | 0x800; + /* + * if spare size is larger that 16 bytes per 512 byte hunk + * then use 8 symbol correction instead of 4 + */ + if ((CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page) > 16) + config1 &= ~NFC_4_8N_ECC; + else + config1 |= NFC_4_8N_ECC; + writew(config1, &nfc->nand_flash_config1); +#elif defined(MXC_NFC_V1) /* unlocking RAM Buff */ writew(0x2, &nfc->configuration); /* hardware ECC checking and correct */ writew(NFC_ECC_EN, &nfc->nand_flash_config1); +#endif } static void nfc_nand_command(unsigned short command) @@ -65,12 +91,12 @@ static void nfc_nand_page_address(unsigned int page_address) { unsigned int page_count; - writew(0x00, &nfc->flash_cmd); + writew(0x00, &nfc->flash_add); writew(NFC_ADDR, &nfc->nand_flash_config2); nfc_wait_ready(); - /* code only for 2kb flash */ - if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) { + /* code only for large page flash */ + if (CONFIG_SYS_NAND_PAGE_SIZE > 512) { writew(0x00, &nfc->flash_add); writew(NFC_ADDR, &nfc->nand_flash_config2); nfc_wait_ready(); @@ -88,22 +114,38 @@ static void nfc_nand_page_address(unsigned int page_address) page_count = page_count >> 8; } while (page_count); } + + writew(0x00, &nfc->flash_add); + writew(NFC_ADDR, &nfc->nand_flash_config2); + nfc_wait_ready(); } static void nfc_nand_data_output(void) { + int config1 = readw(&nfc->nand_flash_config1); +#ifdef NAND_MXC_2K_MULTI_CYCLE int i; +#endif + config1 |= NFC_ECC_EN | NFC_INT_MSK; + writew(config1, &nfc->nand_flash_config1); + writew(0, &nfc->buffer_address); + writew(NFC_OUTPUT, &nfc->nand_flash_config2); + nfc_wait_ready(); +#ifdef NAND_MXC_2K_MULTI_CYCLE /* - * The NAND controller requires four output commands for - * large page devices. + * This NAND controller requires multiple input commands + * for pages larger than 512 bytes. */ - for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) { - writew(NFC_ECC_EN, &nfc->nand_flash_config1); - writew(i, &nfc->buffer_address); /* read in i:th buffer */ + for (i = 1; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) { + config1 = readw(&nfc->nand_flash_config1); + config1 |= NFC_ECC_EN | NFC_INT_MSK; + writew(config1, &nfc->nand_flash_config1); + writew(i, &nfc->buffer_address); writew(NFC_OUTPUT, &nfc->nand_flash_config2); nfc_wait_ready(); } +#endif } static int nfc_nand_check_ecc(void) @@ -121,7 +163,7 @@ static int nfc_read_page(unsigned int page_address, unsigned char *buf) nfc_nand_command(NAND_CMD_READ0); nfc_nand_page_address(page_address); - if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) + if (CONFIG_SYS_NAND_PAGE_SIZE > 512) nfc_nand_command(NAND_CMD_READSTART); nfc_nand_data_output(); /* fill the main buffer 0 */ @@ -129,7 +171,7 @@ static int nfc_read_page(unsigned int page_address, unsigned char *buf) if (nfc_nand_check_ecc()) return -1; - src = &nfc->main_area0[0]; + src = &nfc->main_area[0][0]; dst = (u32 *)buf; /* main copy loop from NAND-buffer to SDRAM memory */ @@ -154,12 +196,12 @@ static int is_badblock(int pagenumber) nfc_nand_command(NAND_CMD_READ0); nfc_nand_page_address(page); - if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) + if (CONFIG_SYS_NAND_PAGE_SIZE > 512) nfc_nand_command(NAND_CMD_READSTART); nfc_nand_data_output(); /* fill the main buffer 0 */ - src = &nfc->spare_area0[0]; + src = &nfc->spare_area[0][0]; /* * IMPORTANT NOTE: The nand flash controller uses a non- @@ -209,7 +251,7 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) { /* * Yes, new block. See if this block is good. If not, - * loop until we find i good block. + * loop until we find a good block. */ while (is_badblock(page)) { page = page + CONFIG_SYS_NAND_PAGE_COUNT; -- cgit v1.1 From b081c2e9b9329d7dadc8d13fc9a2bae5c90a1204 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Tue, 26 Jan 2010 19:24:18 -0700 Subject: Nand mxc_nand add v1.1 controller support Add support for version 1.1 of the nfc nand flash controller which is on the i.mx25 soc. Signed-off-by: John Rigby CC: Scott Wood --- drivers/mtd/nand/mxc_nand.c | 617 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 546 insertions(+), 71 deletions(-) diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index b2b612e..9633858 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -22,27 +22,65 @@ #include #include #include -#ifdef CONFIG_MX27 +#if defined(CONFIG_MX27) || defined(CONFIG_MX25) #include #endif #define DRIVER_NAME "mxc_nand" +/* + * TODO: Use same register defs here as nand_spl mxc nand driver. + */ +/* + * Register map and bit definitions for the Freescale NAND Flash Controller + * present in various i.MX devices. + * + * MX31 and MX27 have version 1 which has + * 4 512 byte main buffers and + * 4 16 byte spare buffers + * to support up to 2K byte pagesize nand. + * Reading or writing a 2K page requires 4 FDI/FDO cycles. + * + * MX25 has version 1.1 which has + * 8 512 byte main buffers and + * 8 64 byte spare buffers + * to support up to 4K byte pagesize nand. + * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. + * Also some of registers are moved and/or changed meaning as seen below. + */ +#if defined(CONFIG_MX31) || defined(CONFIG_MX27) +#define MXC_NFC_V1 +#elif defined(CONFIG_MX25) +#define MXC_NFC_V1_1 +#else +#warning "MXC NFC version not defined" +#endif + +#if defined(MXC_NFC_V1) +#define NAND_MXC_NR_BUFS 4 +#define NAND_MXC_SPARE_BUF_SIZE 16 +#define NAND_MXC_REG_OFFSET 0xe00 +#define is_mxc_nfc_11() 0 +#elif defined(MXC_NFC_V1_1) +#define NAND_MXC_NR_BUFS 8 +#define NAND_MXC_SPARE_BUF_SIZE 64 +#define NAND_MXC_REG_OFFSET 0x1e00 +#define is_mxc_nfc_11() 1 +#else +#error "define CONFIG_NAND_MXC_VXXX to use mtd mxc nand driver" +#endif struct nfc_regs { -/* NFC RAM BUFFER Main area 0 */ - uint8_t main_area0[0x200]; - uint8_t main_area1[0x200]; - uint8_t main_area2[0x200]; - uint8_t main_area3[0x200]; -/* SPARE BUFFER Spare area 0 */ - uint8_t spare_area0[0x10]; - uint8_t spare_area1[0x10]; - uint8_t spare_area2[0x10]; - uint8_t spare_area3[0x10]; - uint8_t pad[0x5c0]; -/* NFC registers */ + uint8_t main_area[NAND_MXC_NR_BUFS][0x200]; + uint8_t spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE]; + /* + * reserved size is offset of nfc registers + * minus total main and spare sizes + */ + uint8_t reserved1[NAND_MXC_REG_OFFSET + - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)]; +#if defined(MXC_NFC_V1) uint16_t nfc_buf_size; - uint16_t reserved; + uint16_t reserved2; uint16_t nfc_buf_addr; uint16_t nfc_flash_addr; uint16_t nfc_flash_cmd; @@ -56,6 +94,30 @@ struct nfc_regs { uint16_t nfc_nf_wrprst; uint16_t nfc_config1; uint16_t nfc_config2; +#elif defined(MXC_NFC_V1_1) + uint16_t reserved2[2]; + uint16_t nfc_buf_addr; + uint16_t nfc_flash_addr; + uint16_t nfc_flash_cmd; + uint16_t nfc_config; + uint16_t nfc_ecc_status_result; + uint16_t nfc_ecc_status_result2; + uint16_t nfc_spare_area_size; + uint16_t nfc_wrprot; + uint16_t reserved3[2]; + uint16_t nfc_nf_wrprst; + uint16_t nfc_config1; + uint16_t nfc_config2; + uint16_t reserved4; + uint16_t nfc_unlockstart_blkaddr; + uint16_t nfc_unlockend_blkaddr; + uint16_t nfc_unlockstart_blkaddr1; + uint16_t nfc_unlockend_blkaddr1; + uint16_t nfc_unlockstart_blkaddr2; + uint16_t nfc_unlockend_blkaddr2; + uint16_t nfc_unlockstart_blkaddr3; + uint16_t nfc_unlockend_blkaddr3; +#endif }; /* @@ -100,6 +162,11 @@ struct nfc_regs { */ #define NFC_INT 0x8000 +#ifdef MXC_NFC_V1_1 +#define NFC_4_8N_ECC (1 << 0) +#else +#define NFC_4_8N_ECC 0 +#endif #define NFC_SP_EN (1 << 2) #define NFC_ECC_EN (1 << 3) #define NFC_BIG (1 << 5) @@ -119,6 +186,7 @@ struct mxc_nand_host { int pagesize_2k; int clk_act; uint16_t col_addr; + unsigned int page_addr; }; static struct mxc_nand_host mxc_host; @@ -135,26 +203,45 @@ static struct mxc_nand_host *host = &mxc_host; #define SPARE_SINGLEBIT_ERROR 0x1 /* OOB placement block for use with hardware ecc generation */ -#ifdef CONFIG_MXC_NAND_HWECC +#if defined(MXC_NFC_V1) +#ifndef CONFIG_SYS_NAND_LARGEPAGE static struct nand_ecclayout nand_hw_eccoob = { .eccbytes = 5, .eccpos = {6, 7, 8, 9, 10}, - .oobfree = {{0, 5}, {11, 5}, } + .oobfree = { {0, 5}, {11, 5}, } }; #else -static struct nand_ecclayout nand_soft_eccoob = { - .eccbytes = 6, - .eccpos = {6, 7, 8, 9, 10, 11}, - .oobfree = {{0, 5}, {12, 4}, } +static struct nand_ecclayout nand_hw_eccoob2k = { + .eccbytes = 20, + .eccpos = { + 6, 7, 8, 9, 10, + 22, 23, 24, 25, 26, + 38, 39, 40, 41, 42, + 54, 55, 56, 57, 58, + }, + .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} }, }; #endif - -static struct nand_ecclayout nand_hw_eccoob_largepage = { - .eccbytes = 20, - .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, - 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, - .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, } +#elif defined(MXC_NFC_V1_1) +#ifndef CONFIG_SYS_NAND_LARGEPAGE +static struct nand_ecclayout nand_hw_eccoob = { + .eccbytes = 9, + .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, + .oobfree = { {2, 5} } }; +#else +static struct nand_ecclayout nand_hw_eccoob2k = { + .eccbytes = 36, + .eccpos = { + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 23, 24, 25, 26, 27, 28, 29, 30, 31, + 39, 40, 41, 42, 43, 44, 45, 46, 47, + 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} }, +}; +#endif +#endif #ifdef CONFIG_MX27 static int is_16bit_nand(void) @@ -178,6 +265,17 @@ static int is_16bit_nand(void) else return 0; } +#elif defined(CONFIG_MX25) +static int is_16bit_nand(void) +{ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL) + return 1; + else + return 0; +} #else #warning "8/16 bit NAND autodetection not supported" static int is_16bit_nand(void) @@ -258,7 +356,24 @@ static void send_addr(struct mxc_nand_host *host, uint16_t addr) static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, int spare_only) { - MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only); + if (spare_only) + MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only); + + if (is_mxc_nfc_11()) { + int i; + /* + * The controller copies the 64 bytes of spare data from + * the first 16 bytes of each of the 4 64 byte spare buffers. + * Copy the contiguous data starting in spare_area[0] to + * the four spare area buffers. + */ + for (i = 1; i < 4; i++) { + void __iomem *src = &host->regs->spare_area[0][i * 16]; + void __iomem *dst = &host->regs->spare_area[i][0]; + + mxc_nand_memcpy32(dst, src, 16); + } + } writew(buf_id, &host->regs->nfc_buf_addr); @@ -303,6 +418,22 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only); + + if (is_mxc_nfc_11()) { + int i; + + /* + * The controller copies the 64 bytes of spare data to + * the first 16 bytes of each of the 4 spare buffers. + * Make the data contiguous starting in spare_area[0]. + */ + for (i = 1; i < 4; i++) { + void __iomem *src = &host->regs->spare_area[i][0]; + void __iomem *dst = &host->regs->spare_area[0][i * 16]; + + mxc_nand_memcpy32(dst, src, 16); + } + } } /* Request the NANDFC to perform a read of the NAND device ID. */ @@ -330,7 +461,7 @@ static void send_read_id(struct mxc_nand_host *host) */ static uint16_t get_dev_status(struct mxc_nand_host *host) { - void __iomem *main_buf = host->regs->main_area1; + void __iomem *main_buf = host->regs->main_area[1]; uint32_t store; uint16_t ret, tmp; /* Issue status request to NAND device */ @@ -379,6 +510,330 @@ static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) */ } +#ifdef MXC_NFC_V1_1 +static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on) +{ + struct nand_chip *nand_chip = mtd->priv; + struct mxc_nand_host *host = nand_chip->priv; + uint16_t tmp = readw(&host->regs->nfc_config1); + + if (on) + tmp |= NFC_ECC_EN; + else + tmp &= ~NFC_ECC_EN; + writew(tmp, &host->regs->nfc_config1); +} + +static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + int page, int sndcmd) +{ + struct mxc_nand_host *host = chip->priv; + uint8_t *buf = chip->oob_poi; + int length = mtd->oobsize; + int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; + uint8_t *bufpoi = buf; + int i, toread; + + MTDDEBUG(MTD_DEBUG_LEVEL0, + "%s: Reading OOB area of page %u to oob %p\n", + __FUNCTION__, host->page_addr, buf); + + chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page); + for (i = 0; i < chip->ecc.steps; i++) { + toread = min_t(int, length, chip->ecc.prepad); + if (toread) { + chip->read_buf(mtd, bufpoi, toread); + bufpoi += toread; + length -= toread; + } + bufpoi += chip->ecc.bytes; + host->col_addr += chip->ecc.bytes; + length -= chip->ecc.bytes; + + toread = min_t(int, length, chip->ecc.postpad); + if (toread) { + chip->read_buf(mtd, bufpoi, toread); + bufpoi += toread; + length -= toread; + } + } + if (length > 0) + chip->read_buf(mtd, bufpoi, length); + + _mxc_nand_enable_hwecc(mtd, 0); + chip->cmdfunc(mtd, NAND_CMD_READOOB, + mtd->writesize + chip->ecc.prepad, page); + bufpoi = buf + chip->ecc.prepad; + length = mtd->oobsize - chip->ecc.prepad; + for (i = 0; i < chip->ecc.steps; i++) { + toread = min_t(int, length, chip->ecc.bytes); + chip->read_buf(mtd, bufpoi, toread); + bufpoi += eccpitch; + length -= eccpitch; + host->col_addr += chip->ecc.postpad + chip->ecc.prepad; + } + _mxc_nand_enable_hwecc(mtd, 1); + return 1; +} + +static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf, + int page) +{ + struct mxc_nand_host *host = chip->priv; + int eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; + uint8_t *oob = chip->oob_poi; + int steps, size; + int n; + + _mxc_nand_enable_hwecc(mtd, 0); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr); + + for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) { + host->col_addr = n * eccsize; + chip->read_buf(mtd, buf, eccsize); + buf += eccsize; + + host->col_addr = mtd->writesize + n * eccpitch; + if (chip->ecc.prepad) { + chip->read_buf(mtd, oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + chip->read_buf(mtd, oob, eccbytes); + oob += eccbytes; + + if (chip->ecc.postpad) { + chip->read_buf(mtd, oob, chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + size = mtd->oobsize - (oob - chip->oob_poi); + if (size) + chip->read_buf(mtd, oob, size); + _mxc_nand_enable_hwecc(mtd, 0); + + return 0; +} + +static int mxc_nand_read_page_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf, + int page) +{ + struct mxc_nand_host *host = chip->priv; + int n, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; + int eccsteps = chip->ecc.steps; + uint8_t *p = buf; + uint8_t *oob = chip->oob_poi; + + MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n", + host->page_addr, buf, oob); + + /* first read out the data area and the available portion of OOB */ + for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) { + int stat; + + host->col_addr = n * eccsize; + + chip->read_buf(mtd, p, eccsize); + + host->col_addr = mtd->writesize + n * eccpitch; + + if (chip->ecc.prepad) { + chip->read_buf(mtd, oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + stat = chip->ecc.correct(mtd, p, oob, NULL); + + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + oob += eccbytes; + + if (chip->ecc.postpad) { + chip->read_buf(mtd, oob, chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + /* Calculate remaining oob bytes */ + n = mtd->oobsize - (oob - chip->oob_poi); + if (n) + chip->read_buf(mtd, oob, n); + + /* Then switch ECC off and read the OOB area to get the ECC code */ + _mxc_nand_enable_hwecc(mtd, 0); + chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr); + eccsteps = chip->ecc.steps; + oob = chip->oob_poi + chip->ecc.prepad; + for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) { + host->col_addr = mtd->writesize + + n * eccpitch + + chip->ecc.prepad; + chip->read_buf(mtd, oob, eccbytes); + oob += eccbytes + chip->ecc.postpad; + } + _mxc_nand_enable_hwecc(mtd, 1); + return 0; +} + +static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, int page) +{ + struct mxc_nand_host *host = chip->priv; + int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; + int length = mtd->oobsize; + int i, len, status, steps = chip->ecc.steps; + const uint8_t *bufpoi = chip->oob_poi; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); + for (i = 0; i < steps; i++) { + len = min_t(int, length, eccpitch); + + chip->write_buf(mtd, bufpoi, len); + bufpoi += len; + length -= len; + host->col_addr += chip->ecc.prepad + chip->ecc.postpad; + } + if (length > 0) + chip->write_buf(mtd, bufpoi, length); + + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + return status & NAND_STATUS_FAIL ? -EIO : 0; +} + +static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf) +{ + struct mxc_nand_host *host = chip->priv; + int eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; + uint8_t *oob = chip->oob_poi; + int steps, size; + int n; + + for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) { + host->col_addr = n * eccsize; + chip->write_buf(mtd, buf, eccsize); + buf += eccsize; + + host->col_addr = mtd->writesize + n * eccpitch; + + if (chip->ecc.prepad) { + chip->write_buf(mtd, oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + host->col_addr += eccbytes; + oob += eccbytes; + + if (chip->ecc.postpad) { + chip->write_buf(mtd, oob, chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + size = mtd->oobsize - (oob - chip->oob_poi); + if (size) + chip->write_buf(mtd, oob, size); +} + +static void mxc_nand_write_page_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf) +{ + struct mxc_nand_host *host = chip->priv; + int i, n, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; + int eccsteps = chip->ecc.steps; + const uint8_t *p = buf; + uint8_t *oob = chip->oob_poi; + + chip->ecc.hwctl(mtd, NAND_ECC_WRITE); + + for (i = n = 0; + eccsteps; + n++, eccsteps--, i += eccbytes, p += eccsize) { + host->col_addr = n * eccsize; + + chip->write_buf(mtd, p, eccsize); + + host->col_addr = mtd->writesize + n * eccpitch; + + if (chip->ecc.prepad) { + chip->write_buf(mtd, oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + chip->write_buf(mtd, oob, eccbytes); + oob += eccbytes; + + if (chip->ecc.postpad) { + chip->write_buf(mtd, oob, chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + /* Calculate remaining oob bytes */ + i = mtd->oobsize - (oob - chip->oob_poi); + if (i) + chip->write_buf(mtd, oob, i); +} + +static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + struct nand_chip *nand_chip = mtd->priv; + struct mxc_nand_host *host = nand_chip->priv; + uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result); + int subpages = mtd->writesize / nand_chip->subpagesize; + int pg2blk_shift = nand_chip->phys_erase_shift - + nand_chip->page_shift; + + do { + if ((ecc_status & 0xf) > 4) { + static int last_bad = -1; + + if (last_bad != host->page_addr >> pg2blk_shift) { + last_bad = host->page_addr >> pg2blk_shift; + printk(KERN_DEBUG + "MXC_NAND: HWECC uncorrectable ECC error" + " in block %u page %u subpage %d\n", + last_bad, host->page_addr, + mtd->writesize / nand_chip->subpagesize + - subpages); + } + return -1; + } + ecc_status >>= 4; + subpages--; + } while (subpages > 0); + + return 0; +} +#else +#define mxc_nand_read_page_syndrome NULL +#define mxc_nand_read_page_raw_syndrome NULL +#define mxc_nand_read_oob_syndrome NULL +#define mxc_nand_write_page_syndrome NULL +#define mxc_nand_write_page_raw_syndrome NULL +#define mxc_nand_write_oob_syndrome NULL +#define mxc_nfc_11_nand_correct_data NULL + static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { @@ -400,6 +855,9 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, return 0; } +#endif + + static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) @@ -415,9 +873,9 @@ static u_char mxc_nand_read_byte(struct mtd_info *mtd) uint8_t ret = 0; uint16_t col; uint16_t __iomem *main_buf = - (uint16_t __iomem *)host->regs->main_area0; + (uint16_t __iomem *)host->regs->main_area[0]; uint16_t __iomem *spare_buf = - (uint16_t __iomem *)host->regs->spare_area0; + (uint16_t __iomem *)host->regs->spare_area[0]; union { uint16_t word; uint8_t bytes[2]; @@ -464,9 +922,10 @@ static uint16_t mxc_nand_read_word(struct mtd_info *mtd) col += mtd->writesize; if (col < mtd->writesize) { - p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1)); + p = (uint16_t __iomem *)(host->regs->main_area[0] + + (col >> 1)); } else { - p = (uint16_t __iomem *)(host->regs->spare_area0 + + p = (uint16_t __iomem *)(host->regs->spare_area[0] + ((col - mtd->writesize) >> 1)); } @@ -525,9 +984,9 @@ static void mxc_nand_write_buf(struct mtd_info *mtd, void __iomem *p; if (col < mtd->writesize) { - p = host->regs->main_area0 + (col & ~3); + p = host->regs->main_area[0] + (col & ~3); } else { - p = host->regs->spare_area0 - + p = host->regs->spare_area[0] - mtd->writesize + (col & ~3); } @@ -595,9 +1054,9 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) void __iomem *p; if (col < mtd->writesize) { - p = host->regs->main_area0 + (col & ~3); + p = host->regs->main_area[0] + (col & ~3); } else { - p = host->regs->spare_area0 - + p = host->regs->spare_area[0] - mtd->writesize + (col & ~3); } @@ -683,7 +1142,7 @@ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) * Used by the upper layer to write command to NAND Flash for * different operations to be carried out on NAND Flash */ -static void mxc_nand_command(struct mtd_info *mtd, unsigned command, +void mxc_nand_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) { struct nand_chip *nand_chip = mtd->priv; @@ -705,6 +1164,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, break; case NAND_CMD_READ0: + host->page_addr = page_addr; host->col_addr = column; host->spare_only = false; break; @@ -750,7 +1210,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, case NAND_CMD_PAGEPROG: send_prog_page(host, 0, host->spare_only); - if (host->pagesize_2k) { + if (host->pagesize_2k && !is_mxc_nfc_11()) { /* data in 4 areas datas */ send_prog_page(host, 1, host->spare_only); send_prog_page(host, 2, host->spare_only); @@ -780,30 +1240,12 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, /* Write out page address, if necessary */ if (page_addr != -1) { - /* paddr_0 - p_addr_7 */ - send_addr(host, (page_addr & 0xff)); - - if (host->pagesize_2k) { - send_addr(host, (page_addr >> 8) & 0xFF); - if (mtd->size >= 0x10000000) { - /* paddr_8 - paddr_15 */ - send_addr(host, (page_addr >> 8) & 0xff); - send_addr(host, (page_addr >> 16) & 0xff); - } else { - /* paddr_8 - paddr_15 */ - send_addr(host, (page_addr >> 8) & 0xff); - } - } else { - /* One more address cycle for higher density devices */ - if (mtd->size >= 0x4000000) { - /* paddr_8 - paddr_15 */ - send_addr(host, (page_addr >> 8) & 0xff); - send_addr(host, (page_addr >> 16) & 0xff); - } else { - /* paddr_8 - paddr_15 */ - send_addr(host, (page_addr >> 8) & 0xff); - } - } + u32 page_mask = nand_chip->pagemask; + do { + send_addr(host, page_addr & 0xFF); + page_addr >>= 8; + page_mask >>= 8; + } while (page_mask); } /* Command post-processing step */ @@ -819,9 +1261,11 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, send_cmd(host, NAND_CMD_READSTART); /* read for each AREA */ send_read_page(host, 0, host->spare_only); - send_read_page(host, 1, host->spare_only); - send_read_page(host, 2, host->spare_only); - send_read_page(host, 3, host->spare_only); + if (!is_mxc_nfc_11()) { + send_read_page(host, 1, host->spare_only); + send_read_page(host, 2, host->spare_only); + send_read_page(host, 3, host->spare_only); + } } else { send_read_page(host, 0, host->spare_only); } @@ -843,6 +1287,24 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, } } +#ifdef MXC_NFC_V1_1 +static void mxc_setup_config1(void) +{ + uint16_t tmp; + + tmp = readw(&host->regs->nfc_config1); + tmp |= NFC_ONE_CYCLE; + tmp |= NFC_4_8N_ECC; + writew(tmp, &host->regs->nfc_config1); + if (host->pagesize_2k) + writew(64/2, &host->regs->nfc_spare_area_size); + else + writew(16/2, &host->regs->nfc_spare_area_size); +} +#else +#define mxc_setup_config1() +#endif + int board_nand_init(struct nand_chip *this) { struct mtd_info *mtd; @@ -874,10 +1336,23 @@ int board_nand_init(struct nand_chip *this) this->ecc.calculate = mxc_nand_calculate_ecc; this->ecc.hwctl = mxc_nand_enable_hwecc; this->ecc.correct = mxc_nand_correct_data; - this->ecc.mode = NAND_ECC_HW; + if (is_mxc_nfc_11()) { + this->ecc.mode = NAND_ECC_HW_SYNDROME; + this->ecc.read_page = mxc_nand_read_page_syndrome; + this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome; + this->ecc.read_oob = mxc_nand_read_oob_syndrome; + this->ecc.write_page = mxc_nand_write_page_syndrome; + this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome; + this->ecc.write_oob = mxc_nand_write_oob_syndrome; + this->ecc.bytes = 9; + this->ecc.prepad = 7; + } else { + this->ecc.mode = NAND_ECC_HW; + } + + host->pagesize_2k = 0; + this->ecc.size = 512; - this->ecc.bytes = 3; - this->ecc.layout = &nand_hw_eccoob; tmp = readw(&host->regs->nfc_config1); tmp |= NFC_ECC_EN; writew(tmp, &host->regs->nfc_config1); @@ -888,7 +1363,6 @@ int board_nand_init(struct nand_chip *this) tmp &= ~NFC_ECC_EN; writew(tmp, &host->regs->nfc_config1); #endif - /* Reset NAND */ this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); @@ -911,10 +1385,11 @@ int board_nand_init(struct nand_chip *this) #ifdef CONFIG_SYS_NAND_LARGEPAGE host->pagesize_2k = 1; - this->ecc.layout = &nand_hw_eccoob_largepage; + this->ecc.layout = &nand_hw_eccoob2k; #else host->pagesize_2k = 0; + this->ecc.layout = &nand_hw_eccoob; #endif - + mxc_setup_config1(); return err; } -- cgit v1.1 From 3e446cbdf30221b9ca3a89b0f5abbfc691ce7755 Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Sat, 5 Dec 2009 13:39:31 +0100 Subject: video: add amba-clcd prime-cell This adds support for the CLCD logic cell. It accepts precompiled register values for specific configuration through a board-supplied data structure. It is used by the Nomadik nhk8815, added by a later patch in this series. Signed-off-by: Alessandro Rubini Acked-by: Andrea Gallo --- drivers/video/Makefile | 1 + drivers/video/amba.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/amba_clcd.h | 77 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 157 insertions(+) create mode 100644 drivers/video/amba.c create mode 100644 include/amba_clcd.h diff --git a/drivers/video/Makefile b/drivers/video/Makefile index bb6b5a0..a5e339a 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o COBJS-$(CONFIG_S6E63D6) += s6e63d6.o +COBJS-$(CONFIG_VIDEO_AMBA) += amba.o COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o diff --git a/drivers/video/amba.c b/drivers/video/amba.c new file mode 100644 index 0000000..ffa1c39 --- /dev/null +++ b/drivers/video/amba.c @@ -0,0 +1,79 @@ +/* + * Driver for AMBA PrimeCell CLCD + * + * Copyright (C) 2009 Alessandro Rubini + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* These variables are required by lcd.c -- although it sets them by itself */ +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; +void *lcd_base; +void *lcd_console_address; +short console_col; +short console_row; + +/* + * To use this driver you need to provide the following in board files: + * a panel_info definition + * an lcd_enable function (can't define a weak default with current code) + */ + +/* There is nothing to do with color registers, we use true color */ +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ + return; +} + +/* Low level initialization of the logic cell: depends on panel_info */ +void lcd_ctrl_init(void *lcdbase) +{ + struct clcd_config *config; + struct clcd_registers *regs; + u32 cntl; + + config = panel_info.priv; + regs = config->address; + cntl = config->cntl & ~CNTL_LCDEN; + + /* Lazily, just copy the registers over: first control with disable */ + writel(cntl, ®s->cntl); + + writel(config->tim0, ®s->tim0); + writel(config->tim1, ®s->tim1); + writel(config->tim2, ®s->tim2); + writel(config->tim3, ®s->tim3); + writel((u32)lcdbase, ®s->ubas); + /* finally, enable */ + writel(cntl | CNTL_LCDEN, ®s->cntl); +} + +/* This is trivial, and copied from atmel_lcdfb.c */ +ulong calc_fbsize(void) +{ + return ((panel_info.vl_col * panel_info.vl_row * + NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; +} diff --git a/include/amba_clcd.h b/include/amba_clcd.h new file mode 100644 index 0000000..db80517 --- /dev/null +++ b/include/amba_clcd.h @@ -0,0 +1,77 @@ +/* + * Register definitions for the AMBA CLCD logic cell. + * + * derived from David A Rusling, although rearranged as a C structure + * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel. + * + * Copyright (C) 2001 ARM Limited + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/* + * CLCD Controller Internal Register addresses + */ +struct clcd_registers { + u32 tim0; /* 0x00 */ + u32 tim1; + u32 tim2; + u32 tim3; + u32 ubas; /* 0x10 */ + u32 lbas; +#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW) + u32 ienb; + u32 cntl; +#else /* Someone rearranged these two registers on the Versatile */ + u32 cntl; + u32 ienb; +#endif + u32 stat; /* 0x20 */ + u32 intr; + u32 ucur; + u32 lcur; + u32 unused[0x74]; /* 0x030..0x1ff */ + u32 palette[0x80]; /* 0x200..0x3ff */ +}; + +/* Bit definition for TIM2 */ +#define TIM2_CLKSEL (1 << 5) +#define TIM2_IVS (1 << 11) +#define TIM2_IHS (1 << 12) +#define TIM2_IPC (1 << 13) +#define TIM2_IOE (1 << 14) +#define TIM2_BCD (1 << 26) + +/* Bit definitions for control register */ +#define CNTL_LCDEN (1 << 0) +#define CNTL_LCDBPP1 (0 << 1) +#define CNTL_LCDBPP2 (1 << 1) +#define CNTL_LCDBPP4 (2 << 1) +#define CNTL_LCDBPP8 (3 << 1) +#define CNTL_LCDBPP16 (4 << 1) +#define CNTL_LCDBPP16_565 (6 << 1) +#define CNTL_LCDBPP24 (5 << 1) +#define CNTL_LCDBW (1 << 4) +#define CNTL_LCDTFT (1 << 5) +#define CNTL_LCDMONO8 (1 << 6) +#define CNTL_LCDDUAL (1 << 7) +#define CNTL_BGR (1 << 8) +#define CNTL_BEBO (1 << 9) +#define CNTL_BEPO (1 << 10) +#define CNTL_LCDPWR (1 << 11) +#define CNTL_LCDVCOMP(x) ((x) << 12) +#define CNTL_LDMAFIFOTIME (1 << 15) +#define CNTL_WATERMARK (1 << 16) + +/* u-boot specific: information passed by the board file */ +struct clcd_config { + struct clcd_registers *address; + u32 tim0; + u32 tim1; + u32 tim2; + u32 tim3; + u32 cntl; + unsigned long pixclock; +}; -- cgit v1.1 From d841978ea616e661e48f8da4045a71d6217823bd Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Sat, 5 Dec 2009 13:39:41 +0100 Subject: include/nomadik.h: add physical address for cldc Signed-off-by: Alessandro Rubini Acked-by: Andrea Gallo --- include/nomadik.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/nomadik.h b/include/nomadik.h index d9405fd..ea65b2d 100644 --- a/include/nomadik.h +++ b/include/nomadik.h @@ -4,6 +4,7 @@ #define __NOMADIK_H__ /* Base addresses of our peripherals */ +#define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */ #define NOMADIK_SRC_BASE 0x101E0000 /* System and Reset Cnt */ #define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */ #define NOMADIK_MPMC_BASE 0x10110000 /* SDRAM Controller */ -- cgit v1.1 From a6e42ed097220a82870a32f4e60ac8863a8b05ab Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Sat, 12 Dec 2009 21:20:57 +0100 Subject: lcd: remove CONFIG_ATMEL_LCD ifdefs from lcd_setfgcolor Not all boards defining LCD_COLOR16 are able to set lcd_color_fg/lcd_color_bg correctly. The issue seems to be caused by CONFIG_ATMEL_LCD ifdefs in lcd_setfgcolor() and lcd_setbgcolor(). Actually, the color values passed to these functions are already correct, we don't need to fix them. So remove ifdefs here. Reported-by: Alessandro Rubini Signed-off-by: Anatolij Gustschin --- common/lcd.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/common/lcd.c b/common/lcd.c index 4e31618..db799db 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -456,22 +456,14 @@ ulong lcd_setmem (ulong addr) static void lcd_setfgcolor (int color) { -#ifdef CONFIG_ATMEL_LCD lcd_color_fg = color; -#else - lcd_color_fg = color & 0x0F; -#endif } /*----------------------------------------------------------------------*/ static void lcd_setbgcolor (int color) { -#ifdef CONFIG_ATMEL_LCD lcd_color_bg = color; -#else - lcd_color_bg = color & 0x0F; -#endif } /*----------------------------------------------------------------------*/ -- cgit v1.1 From 5f566f454750be4f2f83288ef382afcb9c4aa8a4 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 31 Jan 2010 21:51:43 +0100 Subject: cmd_ximg.c: fix error: 'i' undeclared Fix compile error: cmd_ximg.c: In function 'do_imgextract': cmd_ximg.c:234: error: 'i' undeclared (first use in this function) cmd_ximg.c:234: error: (Each undeclared identifier is reported only once cmd_ximg.c:234: error: for each function it appears in.) Signed-off-by: Wolfgang Denk --- common/cmd_ximg.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/common/cmd_ximg.c b/common/cmd_ximg.c index 3e5fb44..b34c4d0 100644 --- a/common/cmd_ximg.c +++ b/common/cmd_ximg.c @@ -225,20 +225,25 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) break; #if defined(CONFIG_BZIP2) case IH_COMP_BZIP2: - printf (" Uncompressing part %d ... ", part); - /* - * If we've got less than 4 MB of malloc() space, - * use slower decompression algorithm which requires - * at most 2300 KB of memory. - */ - i = BZ2_bzBuffToBuffDecompress - ((char*)ntohl(hdr->ih_load), - &unc_len, (char *)data, len, - CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0); - if (i != BZ_OK) { - printf ("BUNZIP2 ERROR %d - " - "image not loaded\n", i); - return 1; + { + int i; + + printf (" Uncompressing part %d ... ", part); + /* + * If we've got less than 4 MB of malloc() + * space, use slower decompression algorithm + * which requires at most 2300 KB of memory. + */ + i = BZ2_bzBuffToBuffDecompress( + (char*)ntohl(hdr->ih_load), + &unc_len, (char *)data, len, + CONFIG_SYS_MALLOC_LEN < (4096 * 1024), + 0); + if (i != BZ_OK) { + printf ("BUNZIP2 ERROR %d - " + "image not loaded\n", i); + return 1; + } } break; #endif /* CONFIG_BZIP2 */ -- cgit v1.1 From c4168af3ba03c17a73751b98c124bbd2e3e1f5b0 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 21 Jan 2010 05:04:59 -0500 Subject: smc91111_eeprom: fix linking error Building for a bf533-stamp ends up with this error: smc91111_eeprom.o: In function `smc91111_eeprom': examples/standalone/smc91111_eeprom.c:58: undefined reference to `memset' make[2]: *** [smc91111_eeprom] Error 1 The new eth_struct definition means gcc has to zero out the structure on the stack, and some gcc versions optimize this with an implicit call to memset. So tweak the structure style to avoid that gcc feature. Signed-off-by: Mike Frysinger Signed-off-by: Ben Warren --- examples/standalone/smc91111_eeprom.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/examples/standalone/smc91111_eeprom.c b/examples/standalone/smc91111_eeprom.c index 9145763..b91f34c 100644 --- a/examples/standalone/smc91111_eeprom.c +++ b/examples/standalone/smc91111_eeprom.c @@ -53,9 +53,8 @@ int smc91111_eeprom (int argc, char *argv[]) int c, i, j, done, line, reg, value, start, what; char input[50]; - struct eth_device dev = { - .iobase = CONFIG_SMC91111_BASE - }; + struct eth_device dev; + dev.iobase = CONFIG_SMC91111_BASE; /* Print the ABI version */ app_startup (argv); -- cgit v1.1 From 07c966066b977b24f4b08b1684eed130f463b4c6 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Thu, 21 Jan 2010 22:16:34 +0100 Subject: cs8900_initialize() cleanup cs8900_initialize(): remove unecessary calls to free() and fix memory leak Signed-off-by: Matthias Kaehlcke Signed-off-by: Ben Warren --- drivers/net/cs8900.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c index df36004..9424fb2 100644 --- a/drivers/net/cs8900.c +++ b/drivers/net/cs8900.c @@ -308,14 +308,13 @@ int cs8900_initialize(u8 dev_num, int base_addr) dev = malloc(sizeof(*dev)); if (!dev) { - free(dev); return 0; } memset(dev, 0, sizeof(*dev)); priv = malloc(sizeof(*priv)); if (!priv) { - free(priv); + free(dev); return 0; } memset(priv, 0, sizeof(*priv)); -- cgit v1.1 From 76771e595aa2640da8c7b5ea81bd9583ccdab8a1 Mon Sep 17 00:00:00 2001 From: Seunghyeon Rhee Date: Mon, 2 Nov 2009 00:00:00 -0800 Subject: NET: Fix MAC addr handling for smc911x This patch turns off MAC address mismatch warning when optional eeprom programmed with MAC address is not available. In that case, smc911x's MAC address register has its default value ff:ff:ff:ff:ff:ff and it's not a valid address. This makes eth_initialize() show the warning which has no meaningful information while environment variable ethaddr overrides the address read from the register. If there's no eeprom and the value of MAC address register is not valid after initialization, dev->enetaddr had better not be updated and maintain its initial value 00:00:00:00:00:00, which I think is what eth_initialize() expects. This is not a bug fix. Even without this patch, the driver works fine. It's just for enhancing the way of displaying messages. Signed-off-by: Seunghyeon Rhee Signed-off-by: Ben Warren --- drivers/net/smc911x.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 5d51406..cac08d0 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -257,12 +257,15 @@ int smc911x_initialize(u8 dev_num, int base_addr) addrh = smc911x_get_mac_csr(dev, ADDRH); addrl = smc911x_get_mac_csr(dev, ADDRL); - dev->enetaddr[0] = addrl; - dev->enetaddr[1] = addrl >> 8; - dev->enetaddr[2] = addrl >> 16; - dev->enetaddr[3] = addrl >> 24; - dev->enetaddr[4] = addrh; - dev->enetaddr[5] = addrh >> 8; + if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) { + /* address is obtained from optional eeprom */ + dev->enetaddr[0] = addrl; + dev->enetaddr[1] = addrl >> 8; + dev->enetaddr[2] = addrl >> 16; + dev->enetaddr[3] = addrl >> 24; + dev->enetaddr[4] = addrh; + dev->enetaddr[5] = addrh >> 8; + } dev->init = smc911x_init; dev->halt = smc911x_halt; -- cgit v1.1 From 46e91674fb4b6d06c6a4984c0b5ac7d9a16923f4 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 3 Nov 2009 17:52:07 -0600 Subject: tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode In SGMII mode the link between a processor's internal TBI PHY and an external PHY should always be 1000Mbps, full duplex. Also, the SGMII interface between an internal TBI PHY and external PHY does not support in-band auto-negotation. Previously, when configured for SGMII mode a TBI PHY would attempt to restart auto-negotation during initializtion. This auto-negotation between a TBI PHY and external PHY would fail and result in unusable ethernet operation. Forcing the TBI PHY and and external PHY to link at 1000Mbps full duplex in SGMII mode resolves this issue of auto-negotation failing. Note that 10Mbps and 100Mbps operation is still possible on the external side of the external PHY even when SGMII is operating at 1000Mbps. The SGMII interface still operates at 1000Mbps, but each byte of data is repeated 100 or 10 times for 10/100Mbps and the external PHY handles converting this data stream into proper 10/100Mbps signalling. Signed-off-by: Peter Tyser Signed-off-by: Ben Warren --- drivers/net/tsec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index d8b6619..67441d4 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -277,12 +277,13 @@ uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, uint phyid, uint regnum | TBIANA_FULL_DUPLEX \ ) +/* Force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ #define TBICR_SETTINGS ( \ TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ | TBICR_FULL_DUPLEX \ | TBICR_SPEED1_SET \ ) + /* Configure the TBI for SGMII operation */ static void tsec_configure_serdes(struct tsec_private *priv) { -- cgit v1.1 From 27165b5c328464b706601b1cd586e359a3dc2f6d Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 9 Nov 2009 13:09:44 -0600 Subject: tsec: Clean up Broadcom PHY status parsing - Remove unnecessary printing "Enet starting in /" This same information is already printed during normal ethernet operation in the form "Speed: 1000, full duplex". - Add a check for link before determining link speed and duplex If there is no link, speed/duplex don't matter. This also removes the annoying and unneeded "Auto-neg error, defaulting to 10BT/HD" message that occurs when no link is detected. - Whitespace and line > 80 characters cleanup Signed-off-by: Peter Tyser Signed-off-by: Ben Warren --- drivers/net/tsec.c | 77 ++++++++++++++++++++++++------------------------------ 1 file changed, 34 insertions(+), 43 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 67441d4..76902bc 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -488,50 +488,41 @@ uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv) */ uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) { + /* If there is no link, speed and duplex don't matter */ + if (!priv->link) + return 0; - switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ - - case 1: - printf("Enet starting in 10BT/HD\n"); - priv->duplexity = 0; - priv->speed = 10; - break; - - case 2: - printf("Enet starting in 10BT/FD\n"); - priv->duplexity = 1; - priv->speed = 10; - break; - - case 3: - printf("Enet starting in 100BT/HD\n"); - priv->duplexity = 0; - priv->speed = 100; - break; - - case 5: - printf("Enet starting in 100BT/FD\n"); - priv->duplexity = 1; - priv->speed = 100; - break; - - case 6: - printf("Enet starting in 1000BT/HD\n"); - priv->duplexity = 0; - priv->speed = 1000; - break; - - case 7: - printf("Enet starting in 1000BT/FD\n"); - priv->duplexity = 1; - priv->speed = 1000; - break; - - default: - printf("Auto-neg error, defaulting to 10BT/HD\n"); - priv->duplexity = 0; - priv->speed = 10; - break; + switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> + MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) { + case 1: + priv->duplexity = 0; + priv->speed = 10; + break; + case 2: + priv->duplexity = 1; + priv->speed = 10; + break; + case 3: + priv->duplexity = 0; + priv->speed = 100; + break; + case 5: + priv->duplexity = 1; + priv->speed = 100; + break; + case 6: + priv->duplexity = 0; + priv->speed = 1000; + break; + case 7: + priv->duplexity = 1; + priv->speed = 1000; + break; + default: + printf("Auto-neg error, defaulting to 10BT/HD\n"); + priv->duplexity = 0; + priv->speed = 10; + break; } return 0; -- cgit v1.1 From e1957ef02c0d949c27f7386e5fa509a57e033d5a Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 9 Nov 2009 13:09:45 -0600 Subject: tsec: Make functions/data static when possible This is generally good practice and saves ~150 bytes. Signed-off-by: Peter Tyser Signed-off-by: Ben Warren --- drivers/net/tsec.c | 90 ++++++++++++++++++++++++++++-------------------------- include/tsec.h | 1 - 2 files changed, 47 insertions(+), 44 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 76902bc..e4d0b9d 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -48,14 +48,15 @@ static int tsec_send(struct eth_device *dev, volatile void *packet, int length); static int tsec_recv(struct eth_device *dev); static int tsec_init(struct eth_device *dev, bd_t * bd); +static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info); static void tsec_halt(struct eth_device *dev); static void init_registers(volatile tsec_t * regs); static void startup_tsec(struct eth_device *dev); static int init_phy(struct eth_device *dev); void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); uint read_phy_reg(struct tsec_private *priv, uint regnum); -struct phy_info *get_phy_info(struct eth_device *dev); -void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); +static struct phy_info *get_phy_info(struct eth_device *dev); +static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); static void adjust_link(struct eth_device *dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ && !defined(BITBANGMII) @@ -112,7 +113,7 @@ int tsec_standard_init(bd_t *bis) /* Initialize device structure. Returns success if PHY * initialization succeeded (i.e. if it recognizes the PHY) */ -int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) +static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) { struct eth_device *dev; int i; @@ -174,7 +175,7 @@ int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) * that it returns success if the link is up, failure otherwise. * This allows u-boot to find the first active controller. */ -int tsec_init(struct eth_device *dev, bd_t * bd) +static int tsec_init(struct eth_device *dev, bd_t * bd) { uint tempval; char tmpbuf[MAC_ADDR_LEN]; @@ -243,7 +244,8 @@ static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr, * notvalid bit cleared), and the bus to cease activity (miimind * busy bit cleared), and then returns the value */ -uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, uint phyid, uint regnum) +static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, + uint phyid, uint regnum) { uint value; @@ -343,7 +345,7 @@ static int init_phy(struct eth_device *dev) * Returns which value to write to the control register. * For 10/100, the value is slightly different */ -uint mii_cr_init(uint mii_reg, struct tsec_private * priv) +static uint mii_cr_init(uint mii_reg, struct tsec_private * priv) { if (priv->flags & TSEC_GIGABIT) return MIIM_CONTROL_INIT; @@ -354,7 +356,7 @@ uint mii_cr_init(uint mii_reg, struct tsec_private * priv) /* * Wait for auto-negotiation to complete, then determine link */ -uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) +static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) { /* * Wait if the link is up, and autonegotiation is in progress @@ -408,7 +410,7 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) * * Stolen from Linux's mii.c and phy_device.c */ -uint mii_parse_link(uint mii_reg, struct tsec_private *priv) +static uint mii_parse_link(uint mii_reg, struct tsec_private *priv) { /* We're using autonegotiation */ if (mii_reg & PHY_BMSR_AUTN_ABLE) { @@ -477,7 +479,7 @@ uint mii_parse_link(uint mii_reg, struct tsec_private *priv) * link. "Ethernet@Wirespeed" reduces advertised speed until link * can be achieved. */ -uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv) +static uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv) { return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010; } @@ -486,7 +488,7 @@ uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv) * Parse the BCM54xx status register for speed and duplex information. * The linux sungem_phy has this information, but in a table format. */ -uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) +static uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) { /* If there is no link, speed and duplex don't matter */ if (!priv->link) @@ -531,7 +533,7 @@ uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) /* Parse the 88E1011's status register for speed and duplex * information */ -uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) +static uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) { uint speed; @@ -589,7 +591,7 @@ uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) /* Parse the RTL8211B's status register for speed and duplex * information */ -uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) +static uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) { uint speed; @@ -647,7 +649,7 @@ uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) /* Parse the cis8201's status register for speed and duplex * information */ -uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) +static uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) { uint speed; @@ -675,7 +677,7 @@ uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) /* Parse the vsc8244's status register for speed and duplex * information */ -uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) +static uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) { uint speed; @@ -703,7 +705,7 @@ uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) /* Parse the DM9161's status register for speed and duplex * information */ -uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) +static uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) { if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) priv->speed = 100; @@ -721,7 +723,7 @@ uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) /* * Hack to write all 4 PHYs with the LED values */ -uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) +static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) { uint phyid; volatile tsec_mdio_t *regbase = priv->phyregs; @@ -739,7 +741,7 @@ uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) return MIIM_CIS8204_SLEDCON_INIT; } -uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) +static uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) { if (priv->flags & TSEC_REDUCED) return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; @@ -747,7 +749,7 @@ uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) return MIIM_CIS8204_EPHYCON_INIT; } -uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) +static uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) { uint mii_data = read_phy_reg(priv, mii_reg); @@ -988,7 +990,7 @@ static void tsec_halt(struct eth_device *dev) phy_run_commands(priv, priv->phyinfo->shutdown); } -struct phy_info phy_info_M88E1149S = { +static struct phy_info phy_info_M88E1149S = { 0x1410ca, "Marvell 88E1149S", 4, @@ -1022,7 +1024,7 @@ struct phy_info phy_info_M88E1149S = { }; /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ -struct phy_info phy_info_BCM5461S = { +static struct phy_info phy_info_BCM5461S = { 0x02060c1, /* 5461 ID */ "Broadcom BCM5461S", 0, /* not clear to me what minor revisions we can shift away */ @@ -1049,7 +1051,7 @@ struct phy_info phy_info_BCM5461S = { }, }; -struct phy_info phy_info_BCM5464S = { +static struct phy_info phy_info_BCM5464S = { 0x02060b1, /* 5464 ID */ "Broadcom BCM5464S", 0, /* not clear to me what minor revisions we can shift away */ @@ -1076,7 +1078,7 @@ struct phy_info phy_info_BCM5464S = { }, }; -struct phy_info phy_info_BCM5482S = { +static struct phy_info phy_info_BCM5482S = { 0x0143bcb, "Broadcom BCM5482S", 4, @@ -1104,7 +1106,7 @@ struct phy_info phy_info_BCM5482S = { }, }; -struct phy_info phy_info_M88E1011S = { +static struct phy_info phy_info_M88E1011S = { 0x01410c6, "Marvell 88E1011S", 4, @@ -1137,7 +1139,7 @@ struct phy_info phy_info_M88E1011S = { }, }; -struct phy_info phy_info_M88E1111S = { +static struct phy_info phy_info_M88E1111S = { 0x01410cc, "Marvell 88E1111S", 4, @@ -1167,7 +1169,7 @@ struct phy_info phy_info_M88E1111S = { }, }; -struct phy_info phy_info_M88E1118 = { +static struct phy_info phy_info_M88E1118 = { 0x01410e1, "Marvell 88E1118", 4, @@ -1205,7 +1207,7 @@ struct phy_info phy_info_M88E1118 = { * Since to access LED register we need do switch the page, we * do LED configuring in the miim_read-like function as follows */ -uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) +static uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) { uint pg; @@ -1222,7 +1224,7 @@ uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) return 0; } -struct phy_info phy_info_M88E1121R = { +static struct phy_info phy_info_M88E1121R = { 0x01410cb, "Marvell 88E1121R", 4, @@ -1305,7 +1307,7 @@ static struct phy_info phy_info_M88E1145 = { }, }; -struct phy_info phy_info_cis8204 = { +static struct phy_info phy_info_cis8204 = { 0x3f11, "Cicada Cis8204", 6, @@ -1337,7 +1339,7 @@ struct phy_info phy_info_cis8204 = { }; /* Cicada 8201 */ -struct phy_info phy_info_cis8201 = { +static struct phy_info phy_info_cis8201 = { 0xfc41, "CIS8201", 4, @@ -1366,7 +1368,8 @@ struct phy_info phy_info_cis8201 = { {miim_end,} }, }; -struct phy_info phy_info_VSC8211 = { + +static struct phy_info phy_info_VSC8211 = { 0xfc4b, "Vitesse VSC8211", 4, @@ -1395,7 +1398,8 @@ struct phy_info phy_info_VSC8211 = { {miim_end,} }, }; -struct phy_info phy_info_VSC8244 = { + +static struct phy_info phy_info_VSC8244 = { 0x3f1b, "Vitesse VSC8244", 6, @@ -1420,7 +1424,7 @@ struct phy_info phy_info_VSC8244 = { }, }; -struct phy_info phy_info_VSC8641 = { +static struct phy_info phy_info_VSC8641 = { 0x7043, "Vitesse VSC8641", 4, @@ -1444,7 +1448,7 @@ struct phy_info phy_info_VSC8641 = { }, }; -struct phy_info phy_info_VSC8221 = { +static struct phy_info phy_info_VSC8221 = { 0xfc55, "Vitesse VSC8221", 4, @@ -1468,7 +1472,7 @@ struct phy_info phy_info_VSC8221 = { }, }; -struct phy_info phy_info_VSC8601 = { +static struct phy_info phy_info_VSC8601 = { 0x00007042, "Vitesse VSC8601", 4, @@ -1505,7 +1509,7 @@ struct phy_info phy_info_VSC8601 = { }; -struct phy_info phy_info_dm9161 = { +static struct phy_info phy_info_dm9161 = { 0x0181b88, "Davicom DM9161E", 4, @@ -1537,7 +1541,7 @@ struct phy_info phy_info_dm9161 = { }, }; /* a generic flavor. */ -struct phy_info phy_info_generic = { +static struct phy_info phy_info_generic = { 0, "Unknown/Generic PHY", 32, @@ -1558,7 +1562,7 @@ struct phy_info phy_info_generic = { }; -uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) +static uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) { unsigned int speed; if (priv->link) { @@ -1612,7 +1616,7 @@ static struct phy_info phy_info_lxt971 = { /* Parse the DP83865's link and auto-neg status register for speed and duplex * information */ -uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) +static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) { switch (mii_reg & MIIM_DP83865_SPD_MASK) { @@ -1638,7 +1642,7 @@ uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) return 0; } -struct phy_info phy_info_dp83865 = { +static struct phy_info phy_info_dp83865 = { 0x20005c7, "NatSemi DP83865", 4, @@ -1661,7 +1665,7 @@ struct phy_info phy_info_dp83865 = { }, }; -struct phy_info phy_info_rtl8211b = { +static struct phy_info phy_info_rtl8211b = { 0x001cc91, "RealTek RTL8211B", 4, @@ -1688,7 +1692,7 @@ struct phy_info phy_info_rtl8211b = { }, }; -struct phy_info *phy_info[] = { +static struct phy_info *phy_info[] = { &phy_info_cis8204, &phy_info_cis8201, &phy_info_BCM5461S, @@ -1717,7 +1721,7 @@ struct phy_info *phy_info[] = { * all of the known PHYs to see if one matches. If so, return * it, if not, return NULL */ -struct phy_info *get_phy_info(struct eth_device *dev) +static struct phy_info *get_phy_info(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; uint phy_reg, phy_ID; @@ -1753,7 +1757,7 @@ struct phy_info *get_phy_info(struct eth_device *dev) /* Execute the given series of commands on the given device's * PHY, running functions as necessary */ -void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) +static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) { int i; uint result; diff --git a/include/tsec.h b/include/tsec.h index f56723a..29e4c56 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -644,7 +644,6 @@ struct tsec_info_struct { u32 flags; }; -int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info); int tsec_standard_init(bd_t *bis); int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num); -- cgit v1.1 From c6dbdfda5393c155bb13a90d9d6be4fe75ec3498 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 9 Nov 2009 13:09:46 -0600 Subject: tsec: General cleanup - Cleanup formatting of phy_info structures - Fix lines > 80 chars - Fix some random indentation inconsistencies Signed-off-by: Peter Tyser Signed-off-by: Ben Warren --- drivers/net/tsec.c | 671 ++++++++++++++++++++++++++--------------------------- 1 file changed, 326 insertions(+), 345 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index e4d0b9d..6a44418 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -236,7 +236,8 @@ static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr, /* Provide the default behavior of writing the PHY of this ethernet device */ -#define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value) +#define write_phy_reg(priv, regnum, value) \ + tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value) /* Reads register regnum on the device's PHY through the * specified registers. It lowers and raises the read @@ -271,7 +272,8 @@ static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, } /* #define to provide old read_phy_reg functionality without duplicating code */ -#define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum) +#define read_phy_reg(priv,regnum) \ + tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum) #define TBIANA_SETTINGS ( \ TBIANA_ASYMMETRIC_PAUSE \ @@ -289,8 +291,8 @@ static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, /* Configure the TBI for SGMII operation */ static void tsec_configure_serdes(struct tsec_private *priv) { - /* Access TBI PHY registers at given TSEC register offset as opposed to the - * register offset used for external PHY accesses */ + /* Access TBI PHY registers at given TSEC register offset as opposed + * to the register offset used for external PHY accesses */ tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA, TBIANA_SETTINGS); tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, @@ -994,7 +996,7 @@ static struct phy_info phy_info_M88E1149S = { 0x1410ca, "Marvell 88E1149S", 4, - (struct phy_cmd[]){ /* config */ + (struct phy_cmd[]) { /* config */ /* Reset and configure the PHY */ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, {0x1d, 0x1f, NULL}, @@ -1008,17 +1010,16 @@ static struct phy_info phy_info_M88E1149S = { {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, {miim_end,} }, - (struct phy_cmd[]){ /* startup */ + (struct phy_cmd[]) { /* startup */ /* Status is read once to clear old link state */ {MIIM_STATUS, miim_read, NULL}, /* Auto-negotiate */ {MIIM_STATUS, miim_read, &mii_parse_sr}, /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, - &mii_parse_88E1011_psr}, + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, {miim_end,} }, - (struct phy_cmd[]){ /* shutdown */ + (struct phy_cmd[]) { /* shutdown */ {miim_end,} }, }; @@ -1110,70 +1111,68 @@ static struct phy_info phy_info_M88E1011S = { 0x01410c6, "Marvell 88E1011S", 4, - (struct phy_cmd[]){ /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {0x1d, 0x1f, NULL}, - {0x1e, 0x200c, NULL}, - {0x1d, 0x5, NULL}, - {0x1e, 0x0, NULL}, - {0x1e, 0x100, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, - &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; static struct phy_info phy_info_M88E1111S = { 0x01410cc, "Marvell 88E1111S", 4, - (struct phy_cmd[]){ /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {0x1b, 0x848f, &mii_m88e1111s_setmode}, - {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, - &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1b, 0x848f, &mii_m88e1111s_setmode}, + {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; static struct phy_info phy_info_M88E1118 = { 0x01410e1, "Marvell 88E1118", 4, - (struct phy_cmd[]){ /* config */ + (struct phy_cmd[]) { /* config */ /* Reset and configure the PHY */ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, {0x16, 0x0002, NULL}, /* Change Page Number */ @@ -1186,8 +1185,8 @@ static struct phy_info phy_info_M88E1118 = { {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ + }, + (struct phy_cmd[]) { /* startup */ {0x16, 0x0000, NULL}, /* Change Page Number */ /* Status is read once to clear old link state */ {MIIM_STATUS, miim_read, NULL}, @@ -1197,10 +1196,10 @@ static struct phy_info phy_info_M88E1118 = { {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ + }, + (struct phy_cmd[]) { /* shutdown */ {miim_end,} - }, + }, }; /* @@ -1228,30 +1227,29 @@ static struct phy_info phy_info_M88E1121R = { 0x01410cb, "Marvell 88E1121R", 4, - (struct phy_cmd[]){ /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - /* Configure leds */ - {MIIM_88E1121_PHY_LED_CTRL, miim_read, - &mii_88E1121_set_led}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - /* Disable IRQs and de-assert interrupt */ - {MIIM_88E1121_PHY_IRQ_EN, 0, NULL}, - {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - {MIIM_STATUS, miim_read, &mii_parse_sr}, - {MIIM_STATUS, miim_read, &mii_parse_link}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + /* Configure leds */ + {MIIM_88E1121_PHY_LED_CTRL, miim_read, &mii_88E1121_set_led}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + /* Disable IRQs and de-assert interrupt */ + {MIIM_88E1121_PHY_IRQ_EN, 0, NULL}, + {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_STATUS, miim_read, &mii_parse_link}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) @@ -1270,72 +1268,67 @@ static struct phy_info phy_info_M88E1145 = { 0x01410cd, "Marvell 88E1145", 4, - (struct phy_cmd[]){ /* config */ - /* Reset the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - - /* Errata E0, E1 */ - {29, 0x001b, NULL}, - {30, 0x418f, NULL}, - {29, 0x0016, NULL}, - {30, 0xa2da, NULL}, - - /* Configure the PHY */ - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, - NULL}, - {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - {MIIM_88E1111_PHY_LED_CONTROL, - MIIM_88E1111_PHY_LED_DIRECT, NULL}, - /* Read the Status */ - {MIIM_88E1011_PHY_STATUS, miim_read, - &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Reset the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + + /* Errata E0, E1 */ + {29, 0x001b, NULL}, + {30, 0x418f, NULL}, + {29, 0x0016, NULL}, + {30, 0xa2da, NULL}, + + /* Configure the PHY */ + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL}, + {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL}, + /* Read the Status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; static struct phy_info phy_info_cis8204 = { 0x3f11, "Cicada Cis8204", 6, - (struct phy_cmd[]){ /* config */ - /* Override PHY config settings */ - {MIIM_CIS8201_AUX_CONSTAT, - MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, - &mii_cis8204_fixled}, - {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, - &mii_cis8204_setmode}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_CIS8201_AUX_CONSTAT, miim_read, - &mii_parse_cis8201}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, + &mii_cis8204_fixled}, + {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, + &mii_cis8204_setmode}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; /* Cicada 8201 */ @@ -1343,30 +1336,27 @@ static struct phy_info phy_info_cis8201 = { 0xfc41, "CIS8201", 4, - (struct phy_cmd[]){ /* config */ - /* Override PHY config settings */ - {MIIM_CIS8201_AUX_CONSTAT, - MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, - /* Set up the interface mode */ - {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, - NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_CIS8201_AUX_CONSTAT, miim_read, - &mii_parse_cis8201}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Set up the interface mode */ + {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; static struct phy_info phy_info_VSC8211 = { @@ -1374,28 +1364,25 @@ static struct phy_info phy_info_VSC8211 = { "Vitesse VSC8211", 4, (struct phy_cmd[]) { /* config */ - /* Override PHY config settings */ - {MIIM_CIS8201_AUX_CONSTAT, - MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, - /* Set up the interface mode */ - {MIIM_CIS8201_EXT_CON1, - MIIM_CIS8201_EXTCON1_INIT, NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Set up the interface mode */ + {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, (struct phy_cmd[]) { /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_CIS8201_AUX_CONSTAT, miim_read, - &mii_parse_cis8201}, - {miim_end,} - }, + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, + {miim_end,} + }, (struct phy_cmd[]) { /* shutdown */ - {miim_end,} + {miim_end,} }, }; @@ -1403,143 +1390,138 @@ static struct phy_info phy_info_VSC8244 = { 0x3f1b, "Vitesse VSC8244", 6, - (struct phy_cmd[]){ /* config */ - /* Override PHY config settings */ - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_VSC8244_AUX_CONSTAT, miim_read, - &mii_parse_vsc8244}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; static struct phy_info phy_info_VSC8641 = { 0x7043, "Vitesse VSC8641", 4, - (struct phy_cmd[]){ /* config */ - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_VSC8244_AUX_CONSTAT, miim_read, - &mii_parse_vsc8244}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; static struct phy_info phy_info_VSC8221 = { 0xfc55, "Vitesse VSC8221", 4, - (struct phy_cmd[]){ /* config */ - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_VSC8244_AUX_CONSTAT, miim_read, - &mii_parse_vsc8244}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; static struct phy_info phy_info_VSC8601 = { - 0x00007042, - "Vitesse VSC8601", - 4, - (struct phy_cmd[]){ /* config */ - /* Override PHY config settings */ - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + 0x00007042, + "Vitesse VSC8601", + 4, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, #ifdef CONFIG_SYS_VSC8601_SKEWFIX - {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, + {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX) - {MIIM_EXT_PAGE_ACCESS,1,NULL}, -#define VSC8101_SKEW (CONFIG_SYS_VSC8601_SKEW_TX<<14)|(CONFIG_SYS_VSC8601_SKEW_RX<<12) - {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, - {MIIM_EXT_PAGE_ACCESS,0,NULL}, + {MIIM_EXT_PAGE_ACCESS,1,NULL}, +#define VSC8101_SKEW \ + (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12) + {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, + {MIIM_EXT_PAGE_ACCESS,0,NULL}, #endif #endif - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_VSC8244_AUX_CONSTAT, miim_read, - &mii_parse_vsc8244}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; - static struct phy_info phy_info_dm9161 = { 0x0181b88, "Davicom DM9161E", 4, - (struct phy_cmd[]){ /* config */ - {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, - /* Do not bypass the scrambler/descrambler */ - {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, - /* Clear 10BTCSR to default */ - {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, - NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CR_INIT, NULL}, - /* Restart Auto Negotiation */ - {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_DM9161_SCSR, miim_read, - &mii_parse_dm9161_scsr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, + /* Do not bypass the scrambler/descrambler */ + {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, + /* Clear 10BTCSR to default */ + {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CR_INIT, NULL}, + /* Restart Auto Negotiation */ + {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; + /* a generic flavor. */ static struct phy_info phy_info_generic = { 0, @@ -1561,7 +1543,6 @@ static struct phy_info phy_info_generic = { } }; - static uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) { unsigned int speed; @@ -1597,20 +1578,20 @@ static struct phy_info phy_info_lxt971 = { 0x0001378e, "LXT971", 4, - (struct phy_cmd[]){ /* config */ - {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ - {miim_end,} - }, - (struct phy_cmd[]){ /* startup - enable interrupts */ - /* { 0x12, 0x00f2, NULL }, */ - {MIIM_STATUS, miim_read, NULL}, - {MIIM_STATUS, miim_read, &mii_parse_sr}, - {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown - disable interrupts */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ + {miim_end,} + }, + (struct phy_cmd[]) { /* startup - enable interrupts */ + /* { 0x12, 0x00f2, NULL }, */ + {MIIM_STATUS, miim_read, NULL}, + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown - disable interrupts */ + {miim_end,} + }, }; /* Parse the DP83865's link and auto-neg status register for speed and duplex @@ -1646,30 +1627,29 @@ static struct phy_info phy_info_dp83865 = { 0x20005c7, "NatSemi DP83865", 4, - (struct phy_cmd[]){ /* config */ - {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the link and auto-neg status */ - {MIIM_DP83865_LANR, miim_read, - &mii_parse_dp83865_lanr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]) { /* config */ + {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the link and auto-neg status */ + {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, }; static struct phy_info phy_info_rtl8211b = { 0x001cc91, "RealTek RTL8211B", 4, - (struct phy_cmd[]){ /* config */ + (struct phy_cmd[]) { /* config */ /* Reset and configure the PHY */ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, @@ -1678,7 +1658,7 @@ static struct phy_info phy_info_rtl8211b = { {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, {miim_end,} }, - (struct phy_cmd[]){ /* startup */ + (struct phy_cmd[]) { /* startup */ /* Status is read once to clear old link state */ {MIIM_STATUS, miim_read, NULL}, /* Auto-negotiate */ @@ -1687,7 +1667,7 @@ static struct phy_info phy_info_rtl8211b = { {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, {miim_end,} }, - (struct phy_cmd[]){ /* shutdown */ + (struct phy_cmd[]) { /* shutdown */ {miim_end,} }, }; @@ -1746,7 +1726,8 @@ static struct phy_info *get_phy_info(struct eth_device *dev) } if (theInfo == &phy_info_generic) { - printf("%s: No support for PHY id %x; assuming generic\n", dev->name, phy_ID); + printf("%s: No support for PHY id %x; assuming generic\n", + dev->name, phy_ID); } else { debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); } @@ -1859,10 +1840,10 @@ static int tsec_miiphy_write(char *devname, unsigned char addr, static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) { - struct tsec_private *priv = privlist[1]; - volatile tsec_t *regs = priv->regs; - volatile u32 *reg_array, value; - u8 result, whichbit, whichreg; + struct tsec_private *priv = privlist[1]; + volatile tsec_t *regs = priv->regs; + volatile u32 *reg_array, value; + u8 result, whichbit, whichreg; result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ -- cgit v1.1 From 8abb8dcc8d6f2a9e31551a6fa41de97bd1f15350 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 9 Nov 2009 13:09:47 -0600 Subject: tsec: Add support for using the BCM5482 PHY in fiber mode The BCM5482 PHY supports both copper and fiber as an ethernet medium. By enabling its copper/fiber mode auto-detection feature it can dynamically determine if it should be configured for copper or fiber. Signed-off-by: Peter Tyser Signed-off-by: Ben Warren --- drivers/net/tsec.c | 110 +++++++++++++++++++++++++++++++++++++++++++++++++++-- include/tsec.h | 13 +++++++ 2 files changed, 119 insertions(+), 4 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 6a44418..7600e40 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -530,8 +530,105 @@ static uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) } return 0; +} +/* + * Find out if PHY is in copper or serdes mode by looking at Expansion Reg + * 0x42 - "Operating Mode Status Register" + */ +static int BCM8482_is_serdes(struct tsec_private *priv) +{ + u16 val; + int serdes = 0; + + write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_ER | 0x42); + val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA); + + switch (val & 0x1f) { + case 0x0d: /* RGMII-to-100Base-FX */ + case 0x0e: /* RGMII-to-SGMII */ + case 0x0f: /* RGMII-to-SerDes */ + case 0x12: /* SGMII-to-SerDes */ + case 0x13: /* SGMII-to-100Base-FX */ + case 0x16: /* SerDes-to-Serdes */ + serdes = 1; + break; + case 0x6: /* RGMII-to-Copper */ + case 0x14: /* SGMII-to-Copper */ + case 0x17: /* SerDes-to-Copper */ + break; + default: + printf("ERROR, invalid PHY mode (0x%x\n)", val); + break; + } + + return serdes; } + +/* + * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating + * Mode Status Register" + */ +uint mii_parse_BCM5482_serdes_sr(struct tsec_private *priv) +{ + u16 val; + int i = 0; + + /* Wait 1s for link - Clause 37 autonegotiation happens very fast */ + while (1) { + write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, + MIIM_BCM54XX_EXP_SEL_ER | 0x42); + val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA); + + if (val & 0x8000) + break; + + if (i++ > 1000) { + priv->link = 0; + return 1; + } + + udelay(1000); /* 1 ms */ + } + + priv->link = 1; + switch ((val >> 13) & 0x3) { + case (0x00): + priv->speed = 10; + break; + case (0x01): + priv->speed = 100; + break; + case (0x02): + priv->speed = 1000; + break; + } + + priv->duplexity = (val & 0x1000) == 0x1000; + + return 0; +} + +/* + * Figure out if BCM5482 is in serdes or copper mode and determine link + * configuration accordingly + */ +static uint mii_parse_BCM5482_sr(uint mii_reg, struct tsec_private *priv) +{ + if (BCM8482_is_serdes(priv)) { + mii_parse_BCM5482_serdes_sr(priv); + } else { + /* Wait for auto-negotiation to complete or fail */ + mii_parse_sr(mii_reg, priv); + + /* Parse BCM54xx copper aux status register */ + mii_reg = read_phy_reg(priv, MIIM_BCM54xx_AUXSTATUS); + mii_parse_BCM54xx_sr(mii_reg, priv); + } + + return 0; +} + /* Parse the 88E1011's status register for speed and duplex * information */ @@ -1091,15 +1188,20 @@ static struct phy_info phy_info_BCM5482S = { /* Read Misc Control register and or in Ethernet@Wirespeed */ {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed}, {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + /* Initial config/enable of secondary SerDes interface */ + {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf), NULL}, + /* Write intial value to secondary SerDes Contol */ + {MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_SSD | 0, NULL}, + {MIIM_BCM54XX_EXP_DATA, MIIM_CONTROL_RESTART, NULL}, + /* Enable copper/fiber auto-detect */ + {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)}, {miim_end,} }, (struct phy_cmd[]) { /* startup */ /* Status is read once to clear old link state */ {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, + /* Determine copper/fiber, auto-negotiate, and read the result */ + {MIIM_STATUS, miim_read, &mii_parse_BCM5482_sr}, {miim_end,} }, (struct phy_cmd[]) { /* shutdown */ diff --git a/include/tsec.h b/include/tsec.h index 29e4c56..b2e37d4 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -153,6 +153,19 @@ #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 +#define MIIM_BCM54XX_SHD 0x1c /* 0x1c shadow registers */ +#define MIIM_BCM54XX_SHD_WRITE 0x8000 +#define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) +#define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) +#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \ + (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \ + MIIM_BCM54XX_SHD_DATA(data)) + +#define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ +#define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ +#define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ +#define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ + /* Cicada Auxiliary Control/Status Register */ #define MIIM_CIS8201_AUX_CONSTAT 0x1c #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 -- cgit v1.1 From 5f6b1442218fcb6a3ef0d2be05d84119cebfe0ae Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 9 Nov 2009 13:09:48 -0600 Subject: tsec: Add TSEC_FIBER flag The TSEC_FIBER flag should be set when a PHY is operating with an external fiber interface. Currently it is only used to notify a user that the PHY is operating in fiber mode. A short description was also added to the other TSEC flag defines so that it is clear how they differ from one another. Signed-off-by: Peter Tyser Signed-off-by: Ben Warren --- drivers/net/tsec.c | 6 ++++-- include/tsec.h | 6 +++--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 7600e40..fd49eff 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -617,6 +617,7 @@ static uint mii_parse_BCM5482_sr(uint mii_reg, struct tsec_private *priv) { if (BCM8482_is_serdes(priv)) { mii_parse_BCM5482_serdes_sr(priv); + priv->flags |= TSEC_FIBER; } else { /* Wait for auto-negotiation to complete or fail */ mii_parse_sr(mii_reg, priv); @@ -940,8 +941,9 @@ static void adjust_link(struct eth_device *dev) break; } - printf("Speed: %d, %s duplex\n", priv->speed, - (priv->duplexity) ? "full" : "half"); + printf("Speed: %d, %s duplex%s\n", priv->speed, + (priv->duplexity) ? "full" : "half", + (priv->flags & TSEC_FIBER) ? ", fiber mode" : ""); } else { printf("%s: No link.\n", dev->name); diff --git a/include/tsec.h b/include/tsec.h index b2e37d4..1e90365 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -584,9 +584,9 @@ typedef struct tsec /* This flag currently only has * meaning if we're using the eTSEC */ -#define TSEC_REDUCED (1 << 1) - -#define TSEC_SGMII (1 << 2) +#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */ +#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */ +#define TSEC_FIBER (1 << 3) /* PHY uses fiber, eg 1000 Base-X */ struct tsec_private { volatile tsec_t *regs; -- cgit v1.1 From 0f751d6ef3e6fb1d28ac272c39c34831d629a59e Mon Sep 17 00:00:00 2001 From: Semih Hazar Date: Thu, 17 Dec 2009 15:07:15 +0200 Subject: macb: Fix mii_phy_read and mii_phy_write functions Enabling CONFIG_CMD_MII in AVR32 boards was not possible due to compile errors. This patch fixes miiphy_read and miiphy_write functions and registers them properly. Signed-off-by: Semih Hazar Signed-off-by: Ben Warren --- drivers/net/macb.c | 110 ++++++++++++++++------------------------------------- 1 file changed, 33 insertions(+), 77 deletions(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index c184353..dcb8850 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include @@ -164,6 +165,36 @@ static u16 macb_mdio_read(struct macb_device *macb, u8 reg) return MACB_BFEXT(DATA, frame); } +#if defined(CONFIG_CMD_MII) + +int macb_miiphy_read(char *devname, u8 phy_adr, u8 reg, u16 *value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct macb_device *macb = to_macb(dev); + + if ( macb->phy_addr != phy_adr ) + return -1; + + *value = macb_mdio_read(macb, reg); + + return 0; +} + +int macb_miiphy_write(char *devname, u8 phy_adr, u8 reg, u16 value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct macb_device *macb = to_macb(dev); + + if ( macb->phy_addr != phy_adr ) + return -1; + + macb_mdio_write(macb, reg, value); + + return 0; +} +#endif + + #if defined(CONFIG_CMD_NET) static int macb_send(struct eth_device *netdev, volatile void *packet, @@ -542,84 +573,9 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) eth_register(netdev); - return 0; -} - -#endif - #if defined(CONFIG_CMD_MII) - -int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value) -{ - unsigned long netctl; - unsigned long netstat; - unsigned long frame; - int iflag; - - iflag = disable_interrupts(); - netctl = macb_readl(&macb, EMACB_NCR); - netctl |= MACB_BIT(MPE); - macb_writel(&macb, EMACB_NCR, netctl); - if (iflag) - enable_interrupts(); - - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 2) - | MACB_BF(PHYA, addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2)); - macb_writel(&macb, EMACB_MAN, frame); - - do { - netstat = macb_readl(&macb, EMACB_NSR); - } while (!(netstat & MACB_BIT(IDLE))); - - frame = macb_readl(&macb, EMACB_MAN); - *value = MACB_BFEXT(DATA, frame); - - iflag = disable_interrupts(); - netctl = macb_readl(&macb, EMACB_NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(&macb, EMACB_NCR, netctl); - if (iflag) - enable_interrupts(); - - return 0; -} - -int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) -{ - unsigned long netctl; - unsigned long netstat; - unsigned long frame; - int iflag; - - iflag = disable_interrupts(); - netctl = macb_readl(&macb, EMACB_NCR); - netctl |= MACB_BIT(MPE); - macb_writel(&macb, EMACB_NCR, netctl); - if (iflag) - enable_interrupts(); - - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 1) - | MACB_BF(PHYA, addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2) - | MACB_BF(DATA, value)); - macb_writel(&macb, EMACB_MAN, frame); - - do { - netstat = macb_readl(&macb, EMACB_NSR); - } while (!(netstat & MACB_BIT(IDLE))); - - iflag = disable_interrupts(); - netctl = macb_readl(&macb, EMACB_NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(&macb, EMACB_NCR, netctl); - if (iflag) - enable_interrupts(); - + miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write); +#endif return 0; } -- cgit v1.1 From d7e354374c8eb0a5d8b8226b881c5ee276c77a60 Mon Sep 17 00:00:00 2001 From: Nick Thompson Date: Fri, 18 Dec 2009 13:33:07 +0000 Subject: TI: DaVinci: Updating EMAC driver for DM365, DM646x and DA8XX The EMAC IP on DM365, DM646x and DA830 is slightly different from that on DM644x. This change updates the DaVinci EMAC driver so that EMAC becomes operational on SOCs with EMAC v2. Signed-off-by: Nick Thompson Signed-off-by: Ben Warren --- drivers/net/davinci_emac.c | 266 ++++++++++++++++++++----------- include/asm-arm/arch-davinci/emac_defs.h | 59 ++++++- 2 files changed, 226 insertions(+), 99 deletions(-) diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index fa8cee4..02bbb8c 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -42,10 +42,17 @@ #include #include #include +#include unsigned int emac_dbg = 0; #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) +#ifdef DAVINCI_EMAC_GIG_ENABLE +#define emac_gigabit_enable() davinci_eth_gigabit_enable() +#else +#define emac_gigabit_enable() /* no gigabit to enable */ +#endif + static void davinci_eth_mdio_enable(void); static int gen_init_phy(int phy_addr); @@ -99,12 +106,14 @@ static void davinci_eth_mdio_enable(void) clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; - adap_mdio->CONTROL = (clkdiv & 0xff) | - MDIO_CONTROL_ENABLE | - MDIO_CONTROL_FAULT | - MDIO_CONTROL_FAULT_ENABLE; + writel((clkdiv & 0xff) | + MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT | + MDIO_CONTROL_FAULT_ENABLE, + &adap_mdio->CONTROL); - while (adap_mdio->CONTROL & MDIO_CONTROL_IDLE) {;} + while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) + ; } /* @@ -119,7 +128,8 @@ static int davinci_eth_phy_detect(void) active_phy_addr = 0xff; - if ((phy_act_state = adap_mdio->ALIVE) == 0) + phy_act_state = readl(&adap_mdio->ALIVE) & EMAC_MDIO_PHY_MASK; + if (phy_act_state == 0) return(0); /* No active PHYs */ debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); @@ -144,15 +154,18 @@ int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) { int tmp; - while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) + ; - adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | - MDIO_USERACCESS0_WRITE_READ | - ((reg_num & 0x1f) << 21) | - ((phy_addr & 0x1f) << 16); + writel(MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_READ | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16), + &adap_mdio->USERACCESS0); /* Wait for command to complete */ - while ((tmp = adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) {;} + while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) + ; if (tmp & MDIO_USERACCESS0_ACK) { *data = tmp & 0xffff; @@ -167,16 +180,19 @@ int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) { - while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) + ; - adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | - MDIO_USERACCESS0_WRITE_WRITE | - ((reg_num & 0x1f) << 21) | - ((phy_addr & 0x1f) << 16) | - (data & 0xffff); + writel(MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_WRITE | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16) | + (data & 0xffff), + &adap_mdio->USERACCESS0); /* Wait for command to complete */ - while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) + ; return(1); } @@ -245,9 +261,24 @@ static int davinci_mii_phy_write(char *devname, unsigned char addr, unsigned cha { return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); } - #endif +static void __attribute__((unused)) davinci_eth_gigabit_enable(void) +{ + u_int16_t data; + + if (davinci_eth_phy_read(EMAC_MDIO_PHY_NUM, 0, &data)) { + if (data & (1 << 6)) { /* speed selection MSB */ + /* + * Check if link detected is giga-bit + * If Gigabit mode detected, enable gigbit in MAC + */ + writel(EMAC_MACCONTROL_GIGFORCE | + EMAC_MACCONTROL_GIGABIT_ENABLE, + &adap_emac->MACCONTROL); + } + } +} /* Eth device open */ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) @@ -255,64 +286,73 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) dv_reg_p addr; u_int32_t clkdiv, cnt; volatile emac_desc *rx_desc; + unsigned long mac_hi; + unsigned long mac_lo; debug_emac("+ emac_open\n"); /* Reset EMAC module and disable interrupts in wrapper */ - adap_emac->SOFTRESET = 1; - while (adap_emac->SOFTRESET != 0) {;} - adap_ewrap->EWCTL = 0; + writel(1, &adap_emac->SOFTRESET); + while (readl(&adap_emac->SOFTRESET) != 0) + ; +#if defined(DAVINCI_EMAC_VERSION2) + writel(1, &adap_ewrap->softrst); + while (readl(&adap_ewrap->softrst) != 0) + ; +#else + writel(0, &adap_ewrap->EWCTL); for (cnt = 0; cnt < 5; cnt++) { - clkdiv = adap_ewrap->EWCTL; + clkdiv = readl(&adap_ewrap->EWCTL); } +#endif rx_desc = emac_rx_desc; - adap_emac->TXCONTROL = 0x01; - adap_emac->RXCONTROL = 0x01; + writel(1, &adap_emac->TXCONTROL); + writel(1, &adap_emac->RXCONTROL); /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */ /* Using channel 0 only - other channels are disabled */ - adap_emac->MACINDEX = 0; - adap_emac->MACADDRHI = - (davinci_eth_mac_addr[3] << 24) | - (davinci_eth_mac_addr[2] << 16) | - (davinci_eth_mac_addr[1] << 8) | - (davinci_eth_mac_addr[0]); - adap_emac->MACADDRLO = - (davinci_eth_mac_addr[5] << 8) | - (davinci_eth_mac_addr[4]); - - adap_emac->MACHASH1 = 0; - adap_emac->MACHASH2 = 0; + writel(0, &adap_emac->MACINDEX); + mac_hi = (davinci_eth_mac_addr[3] << 24) | + (davinci_eth_mac_addr[2] << 16) | + (davinci_eth_mac_addr[1] << 8) | + (davinci_eth_mac_addr[0]); + mac_lo = (davinci_eth_mac_addr[5] << 8) | + (davinci_eth_mac_addr[4]); + + writel(mac_hi, &adap_emac->MACADDRHI); +#if defined(DAVINCI_EMAC_VERSION2) + writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, + &adap_emac->MACADDRLO); +#else + writel(mac_lo, &adap_emac->MACADDRLO); +#endif + + writel(0, &adap_emac->MACHASH1); + writel(0, &adap_emac->MACHASH2); /* Set source MAC address - REQUIRED */ - adap_emac->MACSRCADDRHI = - (davinci_eth_mac_addr[3] << 24) | - (davinci_eth_mac_addr[2] << 16) | - (davinci_eth_mac_addr[1] << 8) | - (davinci_eth_mac_addr[0]); - adap_emac->MACSRCADDRLO = - (davinci_eth_mac_addr[4] << 8) | - (davinci_eth_mac_addr[5]); + writel(mac_hi, &adap_emac->MACSRCADDRHI); + writel(mac_lo, &adap_emac->MACSRCADDRLO); /* Set DMA 8 TX / 8 RX Head pointers to 0 */ addr = &adap_emac->TX0HDP; for(cnt = 0; cnt < 16; cnt++) - *addr++ = 0; + writel(0, addr++); addr = &adap_emac->RX0HDP; for(cnt = 0; cnt < 16; cnt++) - *addr++ = 0; + writel(0, addr++); /* Clear Statistics (do this before setting MacControl register) */ addr = &adap_emac->RXGOODFRAMES; for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) - *addr++ = 0; + writel(0, addr++); /* No multicast addressing */ - adap_emac->MACHASH1 = 0; - adap_emac->MACHASH2 = 0; + writel(0, &adap_emac->MACHASH1); + writel(0, &adap_emac->MACHASH2); /* Create RX queue and set receive process in place */ emac_rx_active_head = emac_rx_desc; @@ -324,34 +364,52 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) rx_desc++; } - /* Set the last descriptor's "next" parameter to 0 to end the RX desc list */ + /* Finalize the rx desc list */ rx_desc--; rx_desc->next = 0; emac_rx_active_tail = rx_desc; emac_rx_queue_active = 1; /* Enable TX/RX */ - adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE; - adap_emac->RXBUFFEROFFSET = 0; + writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); + writel(0, &adap_emac->RXBUFFEROFFSET); - /* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */ - adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN; + /* + * No fancy configs - Use this for promiscous debug + * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE + */ + writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); /* Enable ch 0 only */ - adap_emac->RXUNICASTSET = 0x01; + writel(1, &adap_emac->RXUNICASTSET); /* Enable MII interface and Full duplex mode */ - adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE); +#ifdef CONFIG_SOC_DA8XX + writel((EMAC_MACCONTROL_MIIEN_ENABLE | + EMAC_MACCONTROL_FULLDUPLEX_ENABLE | + EMAC_MACCONTROL_RMIISPEED_100), + &adap_emac->MACCONTROL); +#else + writel((EMAC_MACCONTROL_MIIEN_ENABLE | + EMAC_MACCONTROL_FULLDUPLEX_ENABLE), + &adap_emac->MACCONTROL); +#endif /* Init MDIO & get link state */ clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; - adap_mdio->CONTROL = ((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT); + writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, + &adap_mdio->CONTROL); + + /* We need to wait for MDIO to start */ + udelay(1000); if (!phy.get_link_speed(active_phy_addr)) return(0); + emac_gigabit_enable(); + /* Start receive process */ - adap_emac->RX0HDP = (u_int32_t)emac_rx_desc; + writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP); debug_emac("- emac_open\n"); @@ -368,34 +426,42 @@ static void davinci_eth_ch_teardown(int ch) if (ch == EMAC_CH_TX) { /* Init TX channel teardown */ - adap_emac->TXTEARDOWN = 1; - for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->TX0CP) { - /* Wait here for Tx teardown completion interrupt to occur - * Note: A task delay can be called here to pend rather than - * occupying CPU cycles - anyway it has been found that teardown - * takes very few cpu cycles and does not affect functionality */ - dly--; - udelay(1); - if (dly == 0) + writel(1, &adap_emac->TXTEARDOWN); + do { + /* + * Wait here for Tx teardown completion interrupt to + * occur. Note: A task delay can be called here to pend + * rather than occupying CPU cycles - anyway it has + * been found that teardown takes very few cpu cycles + * and does not affect functionality + */ + dly--; + udelay(1); + if (dly == 0) break; - } - adap_emac->TX0CP = cnt; - adap_emac->TX0HDP = 0; + cnt = readl(&adap_emac->TX0CP); + } while (cnt != 0xfffffffc); + writel(cnt, &adap_emac->TX0CP); + writel(0, &adap_emac->TX0HDP); } else { /* Init RX channel teardown */ - adap_emac->RXTEARDOWN = 1; - for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->RX0CP) { - /* Wait here for Rx teardown completion interrupt to occur - * Note: A task delay can be called here to pend rather than - * occupying CPU cycles - anyway it has been found that teardown - * takes very few cpu cycles and does not affect functionality */ - dly--; - udelay(1); - if (dly == 0) + writel(1, &adap_emac->RXTEARDOWN); + do { + /* + * Wait here for Rx teardown completion interrupt to + * occur. Note: A task delay can be called here to pend + * rather than occupying CPU cycles - anyway it has + * been found that teardown takes very few cpu cycles + * and does not affect functionality + */ + dly--; + udelay(1); + if (dly == 0) break; - } - adap_emac->RX0CP = cnt; - adap_emac->RX0HDP = 0; + cnt = readl(&adap_emac->RX0CP); + } while (cnt != 0xfffffffc); + writel(cnt, &adap_emac->RX0CP); + writel(0, &adap_emac->RX0HDP); } debug_emac("- emac_ch_teardown\n"); @@ -410,8 +476,12 @@ static void davinci_eth_close(struct eth_device *dev) davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ /* Reset EMAC module and disable interrupts in wrapper */ - adap_emac->SOFTRESET = 1; - adap_ewrap->EWCTL = 0; + writel(1, &adap_emac->SOFTRESET); +#if defined(DAVINCI_EMAC_VERSION2) + writel(1, &adap_ewrap->softrst); +#else + writel(0, &adap_ewrap->EWCTL); +#endif debug_emac("- emac_close\n"); } @@ -435,6 +505,8 @@ static int davinci_eth_send_packet (struct eth_device *dev, return (ret_status); } + emac_gigabit_enable(); + /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { length = EMAC_MIN_ETHERNET_PKT_SIZE; @@ -449,7 +521,7 @@ static int davinci_eth_send_packet (struct eth_device *dev, EMAC_CPPI_OWNERSHIP_BIT | EMAC_CPPI_EOP_BIT); /* Send the packet */ - adap_emac->TX0HDP = (unsigned int) emac_tx_desc; + writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP); /* Wait for packet to complete or link down */ while (1) { @@ -457,7 +529,10 @@ static int davinci_eth_send_packet (struct eth_device *dev, davinci_eth_ch_teardown (EMAC_CH_TX); return (ret_status); } - if (adap_emac->TXINTSTATRAW & 0x01) { + + emac_gigabit_enable(); + + if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { ret_status = length; break; } @@ -490,15 +565,15 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) } /* Ack received packet descriptor */ - adap_emac->RX0CP = (unsigned int) rx_curr_desc; + writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP); curr_desc = rx_curr_desc; emac_rx_active_head = (volatile emac_desc *) rx_curr_desc->next; if (status & EMAC_CPPI_EOQ_BIT) { if (emac_rx_active_head) { - adap_emac->RX0HDP = - (unsigned int) emac_rx_active_head; + writel((unsigned long)emac_rx_active_head, + &adap_emac->RX0HDP); } else { emac_rx_queue_active = 0; printf ("INFO:emac_rcv_packet: RX Queue not active\n"); @@ -515,8 +590,8 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) emac_rx_active_head = curr_desc; emac_rx_active_tail = curr_desc; if (emac_rx_queue_active != 0) { - adap_emac->RX0HDP = - (unsigned int) emac_rx_active_head; + writel((unsigned long)emac_rx_active_head, + &adap_emac->RX0HDP); printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); emac_rx_queue_active = 1; } @@ -526,7 +601,8 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) tail_desc->next = (unsigned int) curr_desc; status = tail_desc->pkt_flag_len; if (status & EMAC_CPPI_EOQ_BIT) { - adap_emac->RX0HDP = (unsigned int) curr_desc; + writel((unsigned long)curr_desc, + &adap_emac->RX0HDP); status &= ~EMAC_CPPI_EOQ_BIT; tail_desc->pkt_flag_len = status; } @@ -566,7 +642,7 @@ int davinci_emac_initialize(void) davinci_eth_mdio_enable(); for (i = 0; i < 256; i++) { - if (adap_mdio->ALIVE) + if (readl(&adap_mdio->ALIVE)) break; udelay(10); } diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/include/asm-arm/arch-davinci/emac_defs.h index 96bc80e..e313263 100644 --- a/include/asm-arm/arch-davinci/emac_defs.h +++ b/include/asm-arm/arch-davinci/emac_defs.h @@ -43,6 +43,13 @@ #define EMAC_WRAPPER_BASE_ADDR (0x01d0a000) #define EMAC_WRAPPER_RAM_ADDR (0x01d08000) #define EMAC_MDIO_BASE_ADDR (0x01d0b000) +#define DAVINCI_EMAC_VERSION2 +#elif defined(CONFIG_SOC_DA8XX) +#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE +#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE +#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE +#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE +#define DAVINCI_EMAC_VERSION2 #else #define EMAC_BASE_ADDR (0x01c80000) #define EMAC_WRAPPER_BASE_ADDR (0x01c81000) @@ -51,6 +58,11 @@ #endif #ifdef CONFIG_SOC_DM646X +#define DAVINCI_EMAC_VERSION2 +#define DAVINCI_EMAC_GIG_ENABLE +#endif + +#ifdef CONFIG_SOC_DM646X /* MDIO module input frequency */ #define EMAC_MDIO_BUS_FREQ 76500000 /* MDIO clock output frequency */ @@ -60,6 +72,11 @@ #define EMAC_MDIO_BUS_FREQ 121500000 /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */ +#elif defined(CONFIG_SOC_DA8XX) +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID) +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ #else /* MDIO module input frequency */ #define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ @@ -128,6 +145,10 @@ typedef volatile struct _emac_desc #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) #define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) #define EMAC_MACCONTROL_GIGFORCE (1 << 17) +#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) + +#define EMAC_MAC_ADDR_MATCH (1 << 19) +#define EMAC_MAC_ADDR_IS_VALID (1 << 20) #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) #define EMAC_RXMBPENABLE_RXBROADEN (0x2000) @@ -283,10 +304,40 @@ typedef struct { /* EMAC Wrapper Registers Structure */ typedef struct { -#if defined(CONFIG_SOC_DM646X) || defined(CONFIG_SOC_DM365) - dv_reg IDVER; - dv_reg SOFTRST; - dv_reg EMCTRL; +#ifdef DAVINCI_EMAC_VERSION2 + dv_reg idver; + dv_reg softrst; + dv_reg emctrl; + dv_reg c0rxthreshen; + dv_reg c0rxen; + dv_reg c0txen; + dv_reg c0miscen; + dv_reg c1rxthreshen; + dv_reg c1rxen; + dv_reg c1txen; + dv_reg c1miscen; + dv_reg c2rxthreshen; + dv_reg c2rxen; + dv_reg c2txen; + dv_reg c2miscen; + dv_reg c0rxthreshstat; + dv_reg c0rxstat; + dv_reg c0txstat; + dv_reg c0miscstat; + dv_reg c1rxthreshstat; + dv_reg c1rxstat; + dv_reg c1txstat; + dv_reg c1miscstat; + dv_reg c2rxthreshstat; + dv_reg c2rxstat; + dv_reg c2txstat; + dv_reg c2miscstat; + dv_reg c0rximax; + dv_reg c0tximax; + dv_reg c1rximax; + dv_reg c1tximax; + dv_reg c2rximax; + dv_reg c2tximax; #else u_int8_t RSVD0[4100]; dv_reg EWCTL; -- cgit v1.1 From 582c55a0274f38e6e7e35b95e7ab81d3e912f700 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 20 Jan 2010 09:04:28 +0100 Subject: 83xx, uec: split enet_interface in two variables There's no sensible reason to unite speed and interface type into one variable. So split this variable enet_interface into two vars: enet_interface_type, which hold the interface type and speed. Also: add the possibility for switching between 10 and 100 MBit interfaces on the fly, when running in FAST_ETH mode. Signed-off-by: Heiko Schocher Signed-off-by: Ben Warren --- board/freescale/mpc8360emds/mpc8360emds.c | 3 +- drivers/qe/uec.c | 122 +++++++++++++++++------------- drivers/qe/uec.h | 34 ++++----- drivers/qe/uec_phy.c | 84 ++++++++++---------- include/configs/MPC8323ERDB.h | 6 +- include/configs/MPC832XEMDS.h | 6 +- include/configs/MPC8360EMDS.h | 6 +- include/configs/MPC8360ERDK.h | 6 +- include/configs/MPC8568MDS.h | 6 +- include/configs/MPC8569MDS.h | 30 +++++--- include/configs/kmeter1.h | 3 +- 11 files changed, 175 insertions(+), 131 deletions(-) diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index d4ba043..4f55732 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -159,7 +159,8 @@ int board_eth_init(bd_t *bd) int i; for (i = 0; i < ARRAY_SIZE(uec_info); i++) - uec_info[i].enet_interface = ENET_1000_RGMII_RXID; + uec_info[i].enet_interface_type = RGMII_RXID; + uec_info[i].speed = 1000; } return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info)); } diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index db95ada..27dc500 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -323,9 +323,10 @@ static int uec_set_mac_duplex(uec_private_t *uec, int duplex) return 0; } -static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode) +static int uec_set_mac_if_mode(uec_private_t *uec, + enet_interface_type_e if_mode, int speed) { - enet_interface_e enet_if_mode; + enet_interface_type_e enet_if_mode; uec_info_t *uec_info; uec_t *uec_regs; u32 upsmr; @@ -346,52 +347,68 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode) upsmr = in_be32(&uec->uccf->uf_regs->upsmr); upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM); - switch (enet_if_mode) { - case ENET_100_MII: - case ENET_10_MII: + switch (speed) { + case 10: maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; + switch (enet_if_mode) { + case MII: + break; + case RGMII: + upsmr |= (UPSMR_RPM | UPSMR_R10M); + break; + case RMII: + upsmr |= (UPSMR_R10M | UPSMR_RMM); + break; + default: + return -EINVAL; + break; + } break; - case ENET_1000_GMII: - maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; - break; - case ENET_1000_TBI: - maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; - upsmr |= UPSMR_TBIM; - break; - case ENET_1000_RTBI: - maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; - upsmr |= (UPSMR_RPM | UPSMR_TBIM); - break; - case ENET_1000_RGMII_RXID: - case ENET_1000_RGMII_ID: - case ENET_1000_RGMII: - maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; - upsmr |= UPSMR_RPM; - break; - case ENET_100_RGMII: - maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; - upsmr |= UPSMR_RPM; - break; - case ENET_10_RGMII: - maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; - upsmr |= (UPSMR_RPM | UPSMR_R10M); - break; - case ENET_100_RMII: - maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; - upsmr |= UPSMR_RMM; - break; - case ENET_10_RMII: + case 100: maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; - upsmr |= (UPSMR_R10M | UPSMR_RMM); + switch (enet_if_mode) { + case MII: + break; + case RGMII: + upsmr |= UPSMR_RPM; + break; + case RMII: + upsmr |= UPSMR_RMM; + break; + default: + return -EINVAL; + break; + } break; - case ENET_1000_SGMII: + case 1000: maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; - upsmr |= UPSMR_SGMM; + switch (enet_if_mode) { + case GMII: + break; + case TBI: + upsmr |= UPSMR_TBIM; + break; + case RTBI: + upsmr |= (UPSMR_RPM | UPSMR_TBIM); + break; + case RGMII_RXID: + case RGMII_ID: + case RGMII: + upsmr |= UPSMR_RPM; + break; + case SGMII: + upsmr |= UPSMR_SGMM; + break; + default: + return -EINVAL; + break; + } break; default: return -EINVAL; break; } + out_be32(&uec_regs->maccfg2, maccfg2); out_be32(&uec->uccf->uf_regs->upsmr, upsmr); @@ -504,7 +521,7 @@ static void adjust_link(struct eth_device *dev) struct uec_mii_info *mii_info = uec->mii_info; extern void change_phy_interface_mode(struct eth_device *dev, - enet_interface_e mode); + enet_interface_type_e mode, int speed); uec_regs = uec->uec_regs; if (mii_info->link) { @@ -522,25 +539,19 @@ static void adjust_link(struct eth_device *dev) } if (mii_info->speed != uec->oldspeed) { + enet_interface_type_e mode = \ + uec->uec_info->enet_interface_type; if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { switch (mii_info->speed) { case 1000: break; case 100: printf ("switching to rgmii 100\n"); - /* change phy to rgmii 100 */ - change_phy_interface_mode(dev, - ENET_100_RGMII); - /* change the MAC interface mode */ - uec_set_mac_if_mode(uec,ENET_100_RGMII); + mode = RGMII; break; case 10: printf ("switching to rgmii 10\n"); - /* change phy to rgmii 10 */ - change_phy_interface_mode(dev, - ENET_10_RGMII); - /* change the MAC interface mode */ - uec_set_mac_if_mode(uec,ENET_10_RGMII); + mode = RGMII; break; default: printf("%s: Ack,Speed(%d)is illegal\n", @@ -549,6 +560,11 @@ static void adjust_link(struct eth_device *dev) } } + /* change phy */ + change_phy_interface_mode(dev, mode, mii_info->speed); + /* change the MAC interface mode */ + uec_set_mac_if_mode(uec, mode, mii_info->speed); + printf("%s: Speed %dBT\n", dev->name, mii_info->speed); uec->oldspeed = mii_info->speed; } @@ -980,7 +996,6 @@ static int uec_startup(uec_private_t *uec) int num_threads_tx; int num_threads_rx; u32 utbipar; - enet_interface_e enet_interface; u32 length; u32 align; qe_bd_t *bd; @@ -1060,7 +1075,7 @@ static int uec_startup(uec_private_t *uec) out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE); /* Setup MAC interface mode */ - uec_set_mac_if_mode(uec, uec_info->enet_interface); + uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed); /* Setup MII management base */ #ifndef CONFIG_eTSEC_MDIO_BUS @@ -1075,7 +1090,6 @@ static int uec_startup(uec_private_t *uec) /* Setup UTBIPAR */ utbipar = in_be32(&uec_regs->utbipar); utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK; - enet_interface = uec->uec_info->enet_interface; /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC. * This frees up the remaining SMI addresses for use. @@ -1084,7 +1098,8 @@ static int uec_startup(uec_private_t *uec) out_be32(&uec_regs->utbipar, utbipar); /* Configure the TBI for SGMII operation */ - if (uec->uec_info->enet_interface == ENET_1000_SGMII) { + if ((uec->uec_info->enet_interface_type == SGMII) && + (uec->uec_info->speed == 1000)) { uec_write_phy_reg(uec->dev, uec_regs->utbipar, ENET_TBI_MII_ANA, TBIANA_SETTINGS); @@ -1215,6 +1230,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd) if (err || i <= 0) printf("warning: %s: timeout on PHY link\n", dev->name); + adjust_link(dev); uec->the_first_run = 1; } diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index febfbce..2a9e2dc 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -662,22 +662,18 @@ typedef enum uec_num_of_threads { /* UEC ethernet interface type */ -typedef enum enet_interface { - ENET_10_MII, - ENET_10_RMII, - ENET_10_RGMII, - ENET_100_MII, - ENET_100_RMII, - ENET_100_RGMII, - ENET_1000_GMII, - ENET_1000_RGMII, - ENET_1000_RGMII_ID, - ENET_1000_RGMII_RXID, - ENET_1000_RGMII_TXID, - ENET_1000_TBI, - ENET_1000_RTBI, - ENET_1000_SGMII -} enet_interface_e; +typedef enum enet_interface_type { + MII, + RMII, + RGMII, + GMII, + RGMII_ID, + RGMII_RXID, + RGMII_TXID, + TBI, + RTBI, + SGMII +} enet_interface_type_e; /* UEC initialization info struct */ @@ -696,7 +692,8 @@ typedef enum enet_interface { .tx_bd_ring_len = 16, \ .rx_bd_ring_len = 16, \ .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ - .enet_interface = CONFIG_SYS_UEC##num##_INTERFACE_MODE, \ + .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \ + .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \ } typedef struct uec_info { @@ -708,7 +705,8 @@ typedef struct uec_info { u16 rx_bd_ring_len; u16 tx_bd_ring_len; u8 phy_address; - enet_interface_e enet_interface; + enet_interface_type_e enet_interface_type; + int speed; } uec_info_t; /* UEC driver initialized info diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 9715183..c4214d9 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -401,7 +401,8 @@ static int bcm_init(struct uec_mii_info *mii_info) gbit_config_aneg(mii_info); - if (uec->uec_info->enet_interface == ENET_1000_RGMII_RXID) { + if ((uec->uec_info->enet_interface_type == RGMII_RXID) && + (uec->uec_info->speed == 1000)) { u16 val; int cnt = 50; @@ -429,20 +430,22 @@ static int marvell_init(struct uec_mii_info *mii_info) { struct eth_device *edev = mii_info->dev; uec_private_t *uec = edev->priv; - enum enet_interface iface = uec->uec_info->enet_interface; + enum enet_interface_type iface = uec->uec_info->enet_interface_type; + int speed = uec->uec_info->speed; - if (iface == ENET_1000_RGMII_ID || - iface == ENET_1000_RGMII_RXID || - iface == ENET_1000_RGMII_TXID) { + if ((speed == 1000) && + (iface == RGMII_ID || + iface == RGMII_RXID || + iface == RGMII_TXID)) { int temp; temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR); - if (iface == ENET_1000_RGMII_ID) { + if (iface == RGMII_ID) { temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY; - } else if (iface == ENET_1000_RGMII_RXID) { + } else if (iface == RGMII_RXID) { temp &= ~MII_M1111_TX_DELAY; temp |= MII_M1111_RX_DELAY; - } else if (iface == ENET_1000_RGMII_TXID) { + } else if (iface == RGMII_TXID) { temp &= ~MII_M1111_RX_DELAY; temp |= MII_M1111_TX_DELAY; } @@ -795,7 +798,9 @@ struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info) } void marvell_phy_interface_mode (struct eth_device *dev, - enet_interface_e mode) + enet_interface_type_e type, + int speed + ) { uec_private_t *uec = (uec_private_t *) dev->priv; struct uec_mii_info *mii_info; @@ -807,33 +812,35 @@ void marvell_phy_interface_mode (struct eth_device *dev, } mii_info = uec->mii_info; - if (mode == ENET_100_RGMII) { - phy_write (mii_info, 0x00, 0x9140); - phy_write (mii_info, 0x1d, 0x001f); - phy_write (mii_info, 0x1e, 0x200c); - phy_write (mii_info, 0x1d, 0x0005); - phy_write (mii_info, 0x1e, 0x0000); - phy_write (mii_info, 0x1e, 0x0100); - phy_write (mii_info, 0x09, 0x0e00); - phy_write (mii_info, 0x04, 0x01e1); - phy_write (mii_info, 0x00, 0x9140); - phy_write (mii_info, 0x00, 0x1000); - udelay (100000); - phy_write (mii_info, 0x00, 0x2900); - phy_write (mii_info, 0x14, 0x0cd2); - phy_write (mii_info, 0x00, 0xa100); - phy_write (mii_info, 0x09, 0x0000); - phy_write (mii_info, 0x1b, 0x800b); - phy_write (mii_info, 0x04, 0x05e1); - phy_write (mii_info, 0x00, 0xa100); - phy_write (mii_info, 0x00, 0x2100); - udelay (1000000); - } else if (mode == ENET_10_RGMII) { - phy_write (mii_info, 0x14, 0x8e40); - phy_write (mii_info, 0x1b, 0x800b); - phy_write (mii_info, 0x14, 0x0c82); - phy_write (mii_info, 0x00, 0x8100); - udelay (1000000); + if (type == RGMII) { + if (speed == 100) { + phy_write (mii_info, 0x00, 0x9140); + phy_write (mii_info, 0x1d, 0x001f); + phy_write (mii_info, 0x1e, 0x200c); + phy_write (mii_info, 0x1d, 0x0005); + phy_write (mii_info, 0x1e, 0x0000); + phy_write (mii_info, 0x1e, 0x0100); + phy_write (mii_info, 0x09, 0x0e00); + phy_write (mii_info, 0x04, 0x01e1); + phy_write (mii_info, 0x00, 0x9140); + phy_write (mii_info, 0x00, 0x1000); + udelay (100000); + phy_write (mii_info, 0x00, 0x2900); + phy_write (mii_info, 0x14, 0x0cd2); + phy_write (mii_info, 0x00, 0xa100); + phy_write (mii_info, 0x09, 0x0000); + phy_write (mii_info, 0x1b, 0x800b); + phy_write (mii_info, 0x04, 0x05e1); + phy_write (mii_info, 0x00, 0xa100); + phy_write (mii_info, 0x00, 0x2100); + udelay (1000000); + } else if (speed == 10) { + phy_write (mii_info, 0x14, 0x8e40); + phy_write (mii_info, 0x1b, 0x800b); + phy_write (mii_info, 0x14, 0x0c82); + phy_write (mii_info, 0x00, 0x8100); + udelay (1000000); + } } /* handle 88e1111 rev.B2 erratum 5.6 */ @@ -844,9 +851,10 @@ void marvell_phy_interface_mode (struct eth_device *dev, /* now the B2 will correctly report autoneg completion status */ } -void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode) +void change_phy_interface_mode (struct eth_device *dev, + enet_interface_type_e type, int speed) { #ifdef CONFIG_PHY_MODE_NEED_CHANGE - marvell_phy_interface_mode (dev, mode); + marvell_phy_interface_mode (dev, type, speed); #endif } diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 356586c..8e6f7ce 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -347,7 +347,8 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 4 -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_MII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif #define CONFIG_UEC_ETH2 /* ETH4 */ @@ -358,7 +359,8 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_MII +#define CONFIG_SYS_UEC2_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 #endif /* diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f17f9c7..1adac64 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -362,7 +362,8 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 3 -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_MII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif #define CONFIG_UEC_ETH2 /* ETH4 */ @@ -373,7 +374,8 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 4 -#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_MII +#define CONFIG_SYS_UEC2_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 #endif /* diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 8520155..6fa7287 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -400,7 +400,8 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #endif #define CONFIG_UEC_ETH2 /* GETH2 */ @@ -411,7 +412,8 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #endif /* diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 1d1f94f..c6f1409 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -318,7 +318,8 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 2 -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_RXID +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #endif #define CONFIG_UEC_ETH2 /* GETH2 */ @@ -329,7 +330,8 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 4 -#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_RXID +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #endif /* diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 128a7e1..6973538 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -333,7 +333,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 7 -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #endif #define CONFIG_UEC_ETH2 /* GETH2 */ @@ -344,7 +345,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #endif #endif /* CONFIG_QE */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index ae2fc19..4f4bcbe 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -326,12 +326,14 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 7 -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH1 */ @@ -345,12 +347,14 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ -#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII +#define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH2 */ @@ -364,12 +368,14 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC3_PHY_ADDR 2 -#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID +#define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ -#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII +#define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH3 */ @@ -383,12 +389,14 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC4_PHY_ADDR 3 -#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID +#define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ -#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII +#define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH4 */ @@ -401,7 +409,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC6_PHY_ADDR 4 -#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII +#define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII +#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 #endif /* CONFIG_UEC_ETH6 */ #undef CONFIG_UEC_ETH8 /* GETH8 */ @@ -413,7 +422,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC8_PHY_ADDR 6 -#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII +#define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII +#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 #endif /* CONFIG_UEC_ETH8 */ #endif /* CONFIG_QE */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 0327b97..d27b75b 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -295,7 +295,8 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif /* -- cgit v1.1 From 594d57d0ccce649d6ccd881b8d9c5ea8d0c307ef Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Sun, 31 Jan 2010 17:39:49 +0100 Subject: Add EP93xx ethernet driver Added ethernet driver for EP93xx SoCs Signed-off-by: Matthias Kaehlcke Signed-off-by: Ben Warren --- drivers/net/Makefile | 1 + drivers/net/ep93xx_eth.c | 653 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ep93xx_eth.h | 144 +++++++++++ include/common.h | 5 + include/netdev.h | 1 + 5 files changed, 804 insertions(+) create mode 100644 drivers/net/ep93xx_eth.c create mode 100644 drivers/net/ep93xx_eth.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 904727e..dc3107c 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_DNET) += dnet.o COBJS-$(CONFIG_E1000) += e1000.o COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o +COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c new file mode 100644 index 0000000..4e39948 --- /dev/null +++ b/drivers/net/ep93xx_eth.c @@ -0,0 +1,653 @@ +/* + * Cirrus Logic EP93xx ethernet MAC / MII driver. + * + * Copyright (C) 2010, 2009 + * Matthias Kaehlcke + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver, + * which is + * + * (C) Copyright 2002 2003 + * Adam Bezanson, Network Audio Technologies, Inc. + * + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ep93xx_eth.h" + +#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv) +#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs) + +/* ep93xx_miiphy ops forward declarations */ +static int ep93xx_miiphy_read(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short * const value); +static int ep93xx_miiphy_write(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short const value); + +#if defined(EP93XX_MAC_DEBUG) +/** + * Dump ep93xx_mac values to the terminal. + */ +static void dump_dev(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_dev()\n"); + printf(" rx_dq.base %p\n", priv->rx_dq.base); + printf(" rx_dq.current %p\n", priv->rx_dq.current); + printf(" rx_dq.end %p\n", priv->rx_dq.end); + printf(" rx_sq.base %p\n", priv->rx_sq.base); + printf(" rx_sq.current %p\n", priv->rx_sq.current); + printf(" rx_sq.end %p\n", priv->rx_sq.end); + + for (i = 0; i < NUMRXDESC; i++) + printf(" rx_buffer[%2.d] %p\n", i, NetRxPackets[i]); + + printf(" tx_dq.base %p\n", priv->tx_dq.base); + printf(" tx_dq.current %p\n", priv->tx_dq.current); + printf(" tx_dq.end %p\n", priv->tx_dq.end); + printf(" tx_sq.base %p\n", priv->tx_sq.base); + printf(" tx_sq.current %p\n", priv->tx_sq.current); + printf(" tx_sq.end %p\n", priv->tx_sq.end); +} + +/** + * Dump all RX status queue entries to the terminal. + */ +static void dump_rx_status_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_rx_status_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMRXDESC; i++) { + printf(" [ %p ] %08X %08X\n", + priv->rx_sq.base + i, + (priv->rx_sq.base + i)->word1, + (priv->rx_sq.base + i)->word2); + } +} + +/** + * Dump all RX descriptor queue entries to the terminal. + */ +static void dump_rx_descriptor_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_rx_descriptor_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMRXDESC; i++) { + printf(" [ %p ] %08X %08X\n", + priv->rx_dq.base + i, + (priv->rx_dq.base + i)->word1, + (priv->rx_dq.base + i)->word2); + } +} + +/** + * Dump all TX descriptor queue entries to the terminal. + */ +static void dump_tx_descriptor_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_tx_descriptor_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMTXDESC; i++) { + printf(" [ %p ] %08X %08X\n", + priv->tx_dq.base + i, + (priv->tx_dq.base + i)->word1, + (priv->tx_dq.base + i)->word2); + } +} + +/** + * Dump all TX status queue entries to the terminal. + */ +static void dump_tx_status_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_tx_status_queue()\n"); + printf(" descriptor address word1\n"); + for (i = 0; i < NUMTXDESC; i++) { + printf(" [ %p ] %08X\n", + priv->rx_sq.base + i, + (priv->rx_sq.base + i)->word1); + } +} +#else +#define dump_dev(x) +#define dump_rx_descriptor_queue(x) +#define dump_rx_status_queue(x) +#define dump_tx_descriptor_queue(x) +#define dump_tx_status_queue(x) +#endif /* defined(EP93XX_MAC_DEBUG) */ + +/** + * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until + * it's cleared. + */ +static void ep93xx_mac_reset(struct eth_device *dev) +{ + struct mac_regs *mac = GET_REGS(dev); + uint32_t value; + + debug("+ep93xx_mac_reset"); + + value = readl(&mac->selfctl); + value |= SELFCTL_RESET; + writel(value, &mac->selfctl); + + while (readl(&mac->selfctl) & SELFCTL_RESET) + ; /* noop */ + + debug("-ep93xx_mac_reset"); +} + +/* Eth device open */ +static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + struct mac_regs *mac = GET_REGS(dev); + uchar *mac_addr = dev->enetaddr; + int i; + + debug("+ep93xx_eth_open"); + + /* Reset the MAC */ + ep93xx_mac_reset(dev); + + /* Reset the descriptor queues' current and end address values */ + priv->tx_dq.current = priv->tx_dq.base; + priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC); + + priv->tx_sq.current = priv->tx_sq.base; + priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC); + + priv->rx_dq.current = priv->rx_dq.base; + priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC); + + priv->rx_sq.current = priv->rx_sq.base; + priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC); + + /* + * Set the transmit descriptor and status queues' base address, + * current address, and length registers. Set the maximum frame + * length and threshold. Enable the transmit descriptor processor. + */ + writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd); + writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd); + writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen); + + writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd); + writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd); + writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen); + + writel(0x00040000, &mac->txdthrshld); + writel(0x00040000, &mac->txststhrshld); + + writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen); + writel(BMCTL_TXEN, &mac->bmctl); + + /* + * Set the receive descriptor and status queues' base address, + * current address, and length registers. Enable the receive + * descriptor processor. + */ + writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd); + writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd); + writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen); + + writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd); + writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd); + writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen); + + writel(0x00040000, &mac->rxdthrshld); + + writel(BMCTL_RXEN, &mac->bmctl); + + writel(0x00040000, &mac->rxststhrshld); + + /* Wait until the receive descriptor processor is active */ + while (!(readl(&mac->bmsts) & BMSTS_RXACT)) + ; /* noop */ + + /* + * Initialize the RX descriptor queue. Clear the TX descriptor queue. + * Clear the RX and TX status queues. Enqueue the RX descriptor and + * status entries to the MAC. + */ + for (i = 0; i < NUMRXDESC; i++) { + /* set buffer address */ + (priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i]; + + /* set buffer length, clear buffer index and NSOF */ + (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN; + } + + memset(priv->tx_dq.base, 0, + (sizeof(struct tx_descriptor) * NUMTXDESC)); + memset(priv->rx_sq.base, 0, + (sizeof(struct rx_status) * NUMRXDESC)); + memset(priv->tx_sq.base, 0, + (sizeof(struct tx_status) * NUMTXDESC)); + + writel(NUMRXDESC, &mac->rxdqenq); + writel(NUMRXDESC, &mac->rxstsqenq); + + /* Set the primary MAC address */ + writel(AFP_IAPRIMARY, &mac->afp); + writel(mac_addr[0] | (mac_addr[1] << 8) | + (mac_addr[2] << 16) | (mac_addr[3] << 24), + &mac->indad); + writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper); + + /* Turn on RX and TX */ + writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON | + RXCTL_RCRCA | RXCTL_MA, &mac->rxctl); + writel(TXCTL_STXON, &mac->txctl); + + /* Dump data structures if we're debugging */ + dump_dev(dev); + dump_rx_descriptor_queue(dev); + dump_rx_status_queue(dev); + dump_tx_descriptor_queue(dev); + dump_tx_status_queue(dev); + + debug("-ep93xx_eth_open"); + + return 1; +} + +/** + * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL + * registers. + */ +static void ep93xx_eth_close(struct eth_device *dev) +{ + struct mac_regs *mac = GET_REGS(dev); + + debug("+ep93xx_eth_close"); + + writel(0x00000000, &mac->rxctl); + writel(0x00000000, &mac->txctl); + + debug("-ep93xx_eth_close"); +} + +/** + * Copy a frame of data from the MAC into the protocol layer for further + * processing. + */ +static int ep93xx_eth_rcv_packet(struct eth_device *dev) +{ + struct mac_regs *mac = GET_REGS(dev); + struct ep93xx_priv *priv = GET_PRIV(dev); + int len = -1; + + debug("+ep93xx_eth_rcv_packet"); + + if (RX_STATUS_RFP(priv->rx_sq.current)) { + if (RX_STATUS_RWE(priv->rx_sq.current)) { + /* + * We have a good frame. Extract the frame's length + * from the current rx_status_queue entry, and copy + * the frame's data into NetRxPackets[] of the + * protocol stack. We track the total number of + * bytes in the frame (nbytes_frame) which will be + * used when we pass the data off to the protocol + * layer via NetReceive(). + */ + len = RX_STATUS_FRAME_LEN(priv->rx_sq.current); + + NetReceive((uchar *)priv->rx_dq.current->word1, len); + + debug("reporting %d bytes...\n", len); + } else { + /* Do we have an erroneous packet? */ + error("packet rx error, status %08X %08X", + priv->rx_sq.current->word1, + priv->rx_sq.current->word2); + dump_rx_descriptor_queue(dev); + dump_rx_status_queue(dev); + } + + /* + * Clear the associated status queue entry, and + * increment our current pointers to the next RX + * descriptor and status queue entries (making sure + * we wrap properly). + */ + memset((void *)priv->rx_sq.current, 0, + sizeof(struct rx_status)); + + priv->rx_sq.current++; + if (priv->rx_sq.current >= priv->rx_sq.end) + priv->rx_sq.current = priv->rx_sq.base; + + priv->rx_dq.current++; + if (priv->rx_dq.current >= priv->rx_dq.end) + priv->rx_dq.current = priv->rx_dq.base; + + /* + * Finally, return the RX descriptor and status entries + * back to the MAC engine, and loop again, checking for + * more descriptors to process. + */ + writel(1, &mac->rxdqenq); + writel(1, &mac->rxstsqenq); + } else { + len = 0; + } + + debug("-ep93xx_eth_rcv_packet %d", len); + return len; +} + +/** + * Send a block of data via ethernet. + */ +static int ep93xx_eth_send_packet(struct eth_device *dev, + volatile void * const packet, int const length) +{ + struct mac_regs *mac = GET_REGS(dev); + struct ep93xx_priv *priv = GET_PRIV(dev); + int ret = -1; + + debug("+ep93xx_eth_send_packet"); + + /* Parameter check */ + BUG_ON(packet == NULL); + + /* + * Initialize the TX descriptor queue with the new packet's info. + * Clear the associated status queue entry. Enqueue the packet + * to the MAC for transmission. + */ + + /* set buffer address */ + priv->tx_dq.current->word1 = (uint32_t)packet; + + /* set buffer length and EOF bit */ + priv->tx_dq.current->word2 = length | TX_DESC_EOF; + + /* clear tx status */ + priv->tx_sq.current->word1 = 0; + + /* enqueue the TX descriptor */ + writel(1, &mac->txdqenq); + + /* wait for the frame to become processed */ + while (!TX_STATUS_TXFP(priv->tx_sq.current)) + ; /* noop */ + + if (!TX_STATUS_TXWE(priv->tx_sq.current)) { + error("packet tx error, status %08X", + priv->tx_sq.current->word1); + dump_tx_descriptor_queue(dev); + dump_tx_status_queue(dev); + + /* TODO: Add better error handling? */ + goto eth_send_out; + } + + ret = 0; + /* Fall through */ + +eth_send_out: + debug("-ep93xx_eth_send_packet %d", ret); + return ret; +} + +#if defined(CONFIG_MII) +int ep93xx_miiphy_initialize(bd_t * const bd) +{ + miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write); + return 0; +} +#endif + +/** + * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are + * allocated, if necessary, for the TX and RX descriptor and status queues, + * as well as for received packets. The EP93XX MAC hardware is initialized. + * Transmit and receive operations are enabled. + */ +int ep93xx_eth_initialize(u8 dev_num, int base_addr) +{ + int ret = -1; + struct eth_device *dev; + struct ep93xx_priv *priv; + + debug("+ep93xx_eth_initialize"); + + priv = malloc(sizeof(*priv)); + if (!priv) { + error("malloc() failed"); + goto eth_init_failed_0; + } + memset(priv, 0, sizeof(*priv)); + + priv->regs = (struct mac_regs *)base_addr; + + priv->tx_dq.base = calloc(NUMTXDESC, + sizeof(struct tx_descriptor)); + if (priv->tx_dq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_1; + } + + priv->tx_sq.base = calloc(NUMTXDESC, + sizeof(struct tx_status)); + if (priv->tx_sq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_2; + } + + priv->rx_dq.base = calloc(NUMRXDESC, + sizeof(struct rx_descriptor)); + if (priv->rx_dq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_3; + } + + priv->rx_sq.base = calloc(NUMRXDESC, + sizeof(struct rx_status)); + if (priv->rx_sq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_4; + } + + dev = malloc(sizeof *dev); + if (dev == NULL) { + error("malloc() failed"); + goto eth_init_failed_5; + } + memset(dev, 0, sizeof *dev); + + dev->iobase = base_addr; + dev->priv = priv; + dev->init = ep93xx_eth_open; + dev->halt = ep93xx_eth_close; + dev->send = ep93xx_eth_send_packet; + dev->recv = ep93xx_eth_rcv_packet; + + sprintf(dev->name, "ep93xx_eth-%hu", dev_num); + + eth_register(dev); + + /* Done! */ + ret = 1; + goto eth_init_done; + +eth_init_failed_5: + free(priv->rx_sq.base); + /* Fall through */ + +eth_init_failed_4: + free(priv->rx_dq.base); + /* Fall through */ + +eth_init_failed_3: + free(priv->tx_sq.base); + /* Fall through */ + +eth_init_failed_2: + free(priv->tx_dq.base); + /* Fall through */ + +eth_init_failed_1: + free(priv); + /* Fall through */ + +eth_init_failed_0: + /* Fall through */ + +eth_init_done: + debug("-ep93xx_eth_initialize %d", ret); + return ret; +} + +#if defined(CONFIG_MII) + +/** + * Maximum MII address we support + */ +#define MII_ADDRESS_MAX 31 + +/** + * Maximum MII register address we support + */ +#define MII_REGISTER_MAX 31 + +/** + * Read a 16-bit value from an MII register. + */ +static int ep93xx_miiphy_read(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short * const value) +{ + struct mac_regs *mac = (struct mac_regs *)MAC_BASE; + int ret = -1; + uint32_t self_ctl; + + debug("+ep93xx_miiphy_read"); + + /* Parameter checks */ + BUG_ON(dev == NULL); + BUG_ON(addr > MII_ADDRESS_MAX); + BUG_ON(reg > MII_REGISTER_MAX); + BUG_ON(value == NULL); + + /* + * Save the current SelfCTL register value. Set MAC to suppress + * preamble bits. Wait for any previous MII command to complete + * before issuing the new command. + */ + self_ctl = readl(&mac->selfctl); +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) + writel(self_ctl & ~(1 << 8), &mac->selfctl); +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ + + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + /* + * Issue the MII 'read' command. Wait for the command to complete. + * Read the MII data value. + */ + writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg, + &mac->miicmd); + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + *value = (unsigned short)readl(&mac->miidata); + + /* Restore the saved SelfCTL value and return. */ + writel(self_ctl, &mac->selfctl); + + ret = 0; + /* Fall through */ + + debug("-ep93xx_miiphy_read"); + return ret; +} + +/** + * Write a 16-bit value to an MII register. + */ +static int ep93xx_miiphy_write(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short const value) +{ + struct mac_regs *mac = (struct mac_regs *)MAC_BASE; + int ret = -1; + uint32_t self_ctl; + + debug("+ep93xx_miiphy_write"); + + /* Parameter checks */ + BUG_ON(dev == NULL); + BUG_ON(addr > MII_ADDRESS_MAX); + BUG_ON(reg > MII_REGISTER_MAX); + + /* + * Save the current SelfCTL register value. Set MAC to suppress + * preamble bits. Wait for any previous MII command to complete + * before issuing the new command. + */ + self_ctl = readl(&mac->selfctl); +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) + writel(self_ctl & ~(1 << 8), &mac->selfctl); +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ + + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + /* Issue the MII 'write' command. Wait for the command to complete. */ + writel((uint32_t)value, &mac->miidata); + writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg, + &mac->miicmd); + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + /* Restore the saved SelfCTL value and return. */ + writel(self_ctl, &mac->selfctl); + + ret = 0; + /* Fall through */ + + debug("-ep93xx_miiphy_write"); + return ret; +} +#endif /* defined(CONFIG_MII) */ diff --git a/drivers/net/ep93xx_eth.h b/drivers/net/ep93xx_eth.h new file mode 100644 index 0000000..4654b2f --- /dev/null +++ b/drivers/net/ep93xx_eth.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _EP93XX_ETH_H +#define _EP93XX_ETH_H + +#include + +/** + * #define this to dump device status and queue info during initialization and + * following errors. + */ +#undef EP93XX_MAC_DEBUG + +/** + * Number of descriptor and status entries in our RX queues. + * It must be power of 2 ! + */ +#define NUMRXDESC PKTBUFSRX + +/** + * Number of descriptor and status entries in our TX queues. + */ +#define NUMTXDESC 1 + +/** + * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT) + */ +#define TXSTARTMAX 944 + +/** + * Receive descriptor queue entry + */ +struct rx_descriptor { + uint32_t word1; + uint32_t word2; +}; + +/** + * Receive status queue entry + */ +struct rx_status { + uint32_t word1; + uint32_t word2; +}; + +#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01) +#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01) +#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF) + +/** + * Transmit descriptor queue entry + */ +struct tx_descriptor { + uint32_t word1; + uint32_t word2; +}; + +#define TX_DESC_EOF (1 << 31) + +/** + * Transmit status queue entry + */ +struct tx_status { + uint32_t word1; +}; + +#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01) +#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01) + +/** + * Transmit descriptor queue + */ +struct tx_descriptor_queue { + struct tx_descriptor *base; + struct tx_descriptor *current; + struct tx_descriptor *end; +}; + +/** + * Transmit status queue + */ +struct tx_status_queue { + struct tx_status *base; + volatile struct tx_status *current; + struct tx_status *end; +}; + +/** + * Receive descriptor queue + */ +struct rx_descriptor_queue { + struct rx_descriptor *base; + struct rx_descriptor *current; + struct rx_descriptor *end; +}; + +/** + * Receive status queue + */ +struct rx_status_queue { + struct rx_status *base; + volatile struct rx_status *current; + struct rx_status *end; +}; + +/** + * EP93xx MAC private data structure + */ +struct ep93xx_priv { + struct rx_descriptor_queue rx_dq; + struct rx_status_queue rx_sq; + void *rx_buffer[NUMRXDESC]; + + struct tx_descriptor_queue tx_dq; + struct tx_status_queue tx_sq; + + struct mac_regs *regs; +}; + +#endif diff --git a/include/common.h b/include/common.h index 81f2b59..0ae5abc 100644 --- a/include/common.h +++ b/include/common.h @@ -123,6 +123,11 @@ typedef volatile unsigned char vu_char; #define debugX(level,fmt,args...) #endif /* DEBUG */ +#define error(fmt, args...) do { \ + printf("ERROR: " fmt "\nat %s:%d/%s()\n", \ + ##args, __FILE__, __LINE__, __func__); \ +} while (0) + #ifndef BUG #define BUG() do { \ printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ diff --git a/include/netdev.h b/include/netdev.h index a9d5ec9..1e0484f 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -49,6 +49,7 @@ int davinci_emac_initialize(void); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis); +int ep93xx_eth_initialize(u8 dev_num, int base_addr); int eth_3com_initialize (bd_t * bis); int fec_initialize (bd_t *bis); int fecmxc_initialize (bd_t *bis); -- cgit v1.1 From c041e9d212162f6c85cd3b6a40ad6ba9d9292451 Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Sat, 23 Jan 2010 12:03:45 +0100 Subject: new at91_emac network driver (NET_MULTI api) * add's at91_emac (AT91RM9200) network driver (NET_MULTI api) * enable driver with CONFIG_DRIVER_AT91EMAC * generic PHY initialization * modify AT91RM9200 boards to use NET_MULTI driver * the drivers has been tested with LXT971 Phy and DM9161 Phy at MII and RMII interface Signed-off-by: Jens Scharsig Signed-off-by: Ben Warren --- README | 10 + board/atmel/at91rm9200dk/at91rm9200dk.c | 15 + board/atmel/at91rm9200ek/at91rm9200ek.c | 14 + board/cmc_pu2/cmc_pu2.c | 13 + board/csb637/csb637.c | 13 + board/eukrea/cpuat91/cpuat91.c | 14 + board/kb9202/kb9202.c | 13 + board/m501sk/m501sk.c | 14 + board/mp2usb/mp2usb.c | 13 + cpu/arm920t/at91rm9200/bcm5221.c | 4 +- cpu/arm920t/at91rm9200/dm9161.c | 3 +- drivers/net/Makefile | 1 + drivers/net/at91_emac.c | 498 ++++++++++++++++++++++++++++++++ include/asm-arm/arch-at91/at91_emac.h | 145 ++++++++++ include/configs/at91rm9200dk.h | 9 +- include/configs/at91rm9200ek.h | 8 +- include/configs/cmc_pu2.h | 8 +- include/configs/cpuat91.h | 8 +- include/configs/csb637.h | 8 +- include/configs/kb9202.h | 8 +- include/configs/m501sk.h | 9 +- include/configs/mp2usb.h | 8 +- include/netdev.h | 1 + 23 files changed, 825 insertions(+), 12 deletions(-) create mode 100644 drivers/net/at91_emac.c create mode 100644 include/asm-arm/arch-at91/at91_emac.h diff --git a/README b/README index 263bb05..1158e24 100644 --- a/README +++ b/README @@ -822,6 +822,16 @@ The following options need to be configured: - NETWORK Support (other): + CONFIG_DRIVER_AT91EMAC + Support for AT91RM9200 EMAC. + + CONFIG_RMII + Define this to use reduced MII inteface + + CONFIG_DRIVER_AT91EMAC_QUIET + If this defined, the driver is quiet. + The driver doen't show link status messages. + CONFIG_DRIVER_LAN91C96 Support for SMSC's LAN91C96 chips. diff --git a/board/atmel/at91rm9200dk/at91rm9200dk.c b/board/atmel/at91rm9200dk/at91rm9200dk.c index c761dd7..49b5fe3 100644 --- a/board/atmel/at91rm9200dk/at91rm9200dk.c +++ b/board/atmel/at91rm9200dk/at91rm9200dk.c @@ -23,9 +23,15 @@ */ #include +#include +#include #include +#include + +#if defined(CONFIG_DRIVER_ETHER) #include #include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -95,6 +101,15 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) #endif #endif /* CONFIG_DRIVER_ETHER */ +#ifdef CONFIG_DRIVER_AT91EMAC +int board_eth_init(bd_t *bis) +{ + int rc = 0; + rc = at91emac_register(bis, 0); + return rc; +} +#endif + /* * Disk On Chip (NAND) Millenium initialization. * The NAND lives in the CS2* space diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c index ea684e9..570a09a 100644 --- a/board/atmel/at91rm9200ek/at91rm9200ek.c +++ b/board/atmel/at91rm9200ek/at91rm9200ek.c @@ -23,9 +23,14 @@ */ #include +#include +#include #include +#include +#if defined(CONFIG_DRIVER_ETHER) #include #include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -84,3 +89,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) p_phyops->AutoNegotiate = dm9161_AutoNegotiate; } #endif + +#ifdef CONFIG_DRIVER_AT91EMAC +int board_eth_init(bd_t *bis) +{ + int rc = 0; + rc = at91emac_register(bis, 0); + return rc; +} +#endif diff --git a/board/cmc_pu2/cmc_pu2.c b/board/cmc_pu2/cmc_pu2.c index 3ad756d..0ac851c 100644 --- a/board/cmc_pu2/cmc_pu2.c +++ b/board/cmc_pu2/cmc_pu2.c @@ -30,8 +30,12 @@ #include #include #include +#include +#include +#if defined(CONFIG_DRIVER_ETHER) #include #include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -177,3 +181,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) #endif #endif /* CONFIG_DRIVER_ETHER */ + +#ifdef CONFIG_DRIVER_AT91EMAC +int board_eth_init(bd_t *bis) +{ + int rc = 0; + rc = at91emac_register(bis, 0); + return rc; +} +#endif diff --git a/board/csb637/csb637.c b/board/csb637/csb637.c index fbc3c87..d7fdcc4 100644 --- a/board/csb637/csb637.c +++ b/board/csb637/csb637.c @@ -23,8 +23,12 @@ #include #include +#include +#include +#if defined(CONFIG_DRIVER_ETHER) #include #include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -79,3 +83,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) #endif #endif /* CONFIG_DRIVER_ETHER */ + +#ifdef CONFIG_DRIVER_AT91EMAC +int board_eth_init(bd_t *bis) +{ + int rc = 0; + rc = at91emac_register(bis, 0); + return rc; +} +#endif diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c index 1a700b6..0017962 100644 --- a/board/eukrea/cpuat91/cpuat91.c +++ b/board/eukrea/cpuat91/cpuat91.c @@ -26,9 +26,14 @@ */ #include +#include #include +#include + +#if defined(CONFIG_DRIVER_ETHER) #include #include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -79,3 +84,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) #endif /* CONFIG_CMD_NET */ #endif /* CONFIG_DRIVER_ETHER */ +#ifdef CONFIG_DRIVER_AT91EMAC + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + rc = at91emac_register(bis, 0); + return rc; +} +#endif diff --git a/board/kb9202/kb9202.c b/board/kb9202/kb9202.c index 59ed8ff..3164cc5 100644 --- a/board/kb9202/kb9202.c +++ b/board/kb9202/kb9202.c @@ -28,8 +28,12 @@ #include #include +#include +#include +#if defined(CONFIG_DRIVER_ETHER) #include #include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -92,3 +96,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) #endif #endif /* CONFIG_DRIVER_ETHER */ + +#ifdef CONFIG_DRIVER_AT91EMAC +int board_eth_init(bd_t *bis) +{ + int rc = 0; + rc = at91emac_register(bis, 0); + return rc; +} +#endif diff --git a/board/m501sk/m501sk.c b/board/m501sk/m501sk.c index 1e6a605..c995768 100644 --- a/board/m501sk/m501sk.c +++ b/board/m501sk/m501sk.c @@ -24,8 +24,13 @@ */ #include +#include +#include +#if defined(CONFIG_DRIVER_ETHER) #include #include +#endif + #include "m501sk.h" #include "net.h" @@ -186,4 +191,13 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) } #endif /* CONFIG_CMD_NET */ #endif /* CONFIG_DRIVER_ETHER */ + +#ifdef CONFIG_DRIVER_AT91EMAC +int board_eth_init(bd_t *bis) +{ + int rc = 0; + rc = at91emac_register(bis, 0); + return rc; +} +#endif #endif /* CONFIG_M501SK */ diff --git a/board/mp2usb/mp2usb.c b/board/mp2usb/mp2usb.c index dcda699..e5eba6b 100644 --- a/board/mp2usb/mp2usb.c +++ b/board/mp2usb/mp2usb.c @@ -27,8 +27,12 @@ #include #include +#include +#include +#if defined(CONFIG_DRIVER_ETHER) #include #include +#endif #include DECLARE_GLOBAL_DATA_PTR; @@ -83,3 +87,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) #endif #endif /* CONFIG_DRIVER_ETHER */ + +#ifdef CONFIG_DRIVER_AT91EMAC +int board_eth_init(bd_t *bis) +{ + int rc = 0; + rc = at91emac_register(bis, 0); + return rc; +} +#endif diff --git a/cpu/arm920t/at91rm9200/bcm5221.c b/cpu/arm920t/at91rm9200/bcm5221.c index b52c615..8de3cba 100644 --- a/cpu/arm920t/at91rm9200/bcm5221.c +++ b/cpu/arm920t/at91rm9200/bcm5221.c @@ -28,10 +28,10 @@ #include #include -#include - #ifdef CONFIG_DRIVER_ETHER +#include + #if defined(CONFIG_CMD_NET) /* diff --git a/cpu/arm920t/at91rm9200/dm9161.c b/cpu/arm920t/at91rm9200/dm9161.c index 1beb6e8..6d4384f 100644 --- a/cpu/arm920t/at91rm9200/dm9161.c +++ b/cpu/arm920t/at91rm9200/dm9161.c @@ -23,9 +23,8 @@ #include #include -#include - #ifdef CONFIG_DRIVER_ETHER +#include #if defined(CONFIG_CMD_NET) diff --git a/drivers/net/Makefile b/drivers/net/Makefile index dc3107c..1ec0ba1 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libnet.a COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o +COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c new file mode 100644 index 0000000..2399569 --- /dev/null +++ b/drivers/net/at91_emac.c @@ -0,0 +1,498 @@ +/* + * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG + * Jens Scharsig (esw@bus-elektronik.de) + * + * (C) Copyright 2003 + * Author : Hamid Ikdoumi (Atmel) + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#ifndef CONFIG_AT91_LEGACY +#include +#include +#include +#include +#else +/* remove next 5 lines, if all RM9200 boards convert to at91 arch */ +#include +#include +#include +#include +#include +#endif +#include +#include +#include +#include +#include + +#undef MII_DEBUG +#undef ET_DEBUG + +#if (CONFIG_SYS_RX_ETH_BUFFER > 1024) +#error AT91 EMAC supports max 1024 RX buffers. \ + Please decrease the CONFIG_SYS_RX_ETH_BUFFER value +#endif + +/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ +#if (AT91C_MASTER_CLOCK > 80000000) + #define HCLK_DIV AT91_EMAC_CFG_MCLK_64 +#elif (AT91C_MASTER_CLOCK > 40000000) + #define HCLK_DIV AT91_EMAC_CFG_MCLK_32 +#elif (AT91C_MASTER_CLOCK > 20000000) + #define HCLK_DIV AT91_EMAC_CFG_MCLK_16 +#else + #define HCLK_DIV AT91_EMAC_CFG_MCLK_8 +#endif + +#ifdef ET_DEBUG +#define DEBUG_AT91EMAC(...) printf(__VA_ARGS__); +#else +#define DEBUG_AT91EMAC(...) +#endif + +#ifdef MII_DEBUG +#define DEBUG_AT91PHY(...) printf(__VA_ARGS__); +#else +#define DEBUG_AT91PHY(...) +#endif + +#ifndef CONFIG_DRIVER_AT91EMAC_QUIET +#define VERBOSEP(...) printf(__VA_ARGS__); +#else +#define VERBOSEP(...) +#endif + +#define RBF_ADDR 0xfffffffc +#define RBF_OWNER (1<<0) +#define RBF_WRAP (1<<1) +#define RBF_BROADCAST (1<<31) +#define RBF_MULTICAST (1<<30) +#define RBF_UNICAST (1<<29) +#define RBF_EXTERNAL (1<<28) +#define RBF_UNKOWN (1<<27) +#define RBF_SIZE 0x07ff +#define RBF_LOCAL4 (1<<26) +#define RBF_LOCAL3 (1<<25) +#define RBF_LOCAL2 (1<<24) +#define RBF_LOCAL1 (1<<23) + +#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER +#define RBF_FRAMELEN 0x600 + +typedef struct { + unsigned long addr, size; +} rbf_t; + +typedef struct { + rbf_t rbfdt[RBF_FRAMEMAX]; + unsigned long rbindex; +} emac_device; + +void at91emac_EnableMDIO(at91_emac_t *at91mac) +{ + /* Mac CTRL reg set for MDIO enable */ + writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); +} + +void at91emac_DisableMDIO(at91_emac_t *at91mac) +{ + /* Mac CTRL reg set for MDIO disable */ + writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); +} + +int at91emac_read(at91_emac_t *at91mac, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + at91emac_EnableMDIO(at91mac); + + writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R | + AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | + AT91_EMAC_MAN_PHYA(addr), + &at91mac->man); + udelay(10000); + *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK; + + at91emac_DisableMDIO(at91mac); + + DEBUG_AT91PHY("AT91PHY read %x REG(%d)=%x\n", at91mac, reg, *value) + + return 0; +} + +int at91emac_write(at91_emac_t *at91mac, unsigned char addr, + unsigned char reg, unsigned short value) +{ + DEBUG_AT91PHY("AT91PHY write %x REG(%d)=%x\n", at91mac, reg, &value) + + at91emac_EnableMDIO(at91mac); + + writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W | + AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | + AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK), + &at91mac->man); + udelay(10000); + + at91emac_DisableMDIO(at91mac); + return 0; +} + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + +at91_emac_t *get_emacbase_by_name(char *devname) +{ + struct eth_device *netdev; + + netdev = eth_get_dev_by_name(devname); + return (at91_emac_t *) netdev->iobase; +} + +int at91emac_mii_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + at91_emac_t *emac; + + emac = get_emacbase_by_name(devname); + at91emac_read(emac , addr, reg, value); + return 0; +} + + +int at91emac_mii_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + at91_emac_t *emac; + + emac = get_emacbase_by_name(devname); + at91emac_write(emac, addr, reg, value); + return 0; +} + +#endif + +static int at91emac_phy_reset(struct eth_device *netdev) +{ + int i; + u16 status, adv; + at91_emac_t *emac; + + emac = (at91_emac_t *) netdev->iobase; + + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + at91emac_write(emac, 0, MII_ADVERTISE, adv); + VERBOSEP("%s: Starting autonegotiation...\n", netdev->name); + at91emac_write(emac, 0, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); + + for (i = 0; i < 100000 / 100; i++) { + at91emac_read(emac, 0, MII_BMSR, &status); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } + + if (status & BMSR_ANEGCOMPLETE) { + VERBOSEP("%s: Autonegotiation complete\n", netdev->name); + } else { + printf("%s: Autonegotiation timed out (status=0x%04x)\n", + netdev->name, status); + return 1; + } + return 0; +} + +static int at91emac_phy_init(struct eth_device *netdev) +{ + u16 phy_id, status, adv, lpa; + int media, speed, duplex; + int i; + at91_emac_t *emac; + + emac = (at91_emac_t *) netdev->iobase; + + /* Check if the PHY is up to snuff... */ + at91emac_read(emac, 0, MII_PHYSID1, &phy_id); + if (phy_id == 0xffff) { + printf("%s: No PHY present\n", netdev->name); + return 1; + } + + at91emac_read(emac, 0, MII_BMSR, &status); + + if (!(status & BMSR_LSTATUS)) { + /* Try to re-negotiate if we don't have link already. */ + if (at91emac_phy_reset(netdev)) + return 2; + + for (i = 0; i < 100000 / 100; i++) { + at91emac_read(emac, 0, MII_BMSR, &status); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } + if (!(status & BMSR_LSTATUS)) { + VERBOSEP("%s: link down\n", netdev->name); + return 3; + } else { + at91emac_read(emac, 0, MII_ADVERTISE, &adv); + at91emac_read(emac, 0, MII_LPA, &lpa); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + VERBOSEP("%s: link up, %sMbps %s-duplex\n", + netdev->name, + speed ? "100" : "10", + duplex ? "full" : "half"); + } + return 0; +} + +int at91emac_UpdateLinkSpeed(at91_emac_t *emac) +{ + unsigned short stat1; + + at91emac_read(emac, 0, MII_BMSR, &stat1); + + if (!(stat1 & BMSR_LSTATUS)) /* link status up? */ + return 1; + + if (stat1 & BMSR_100FULL) { + /*set Emac for 100BaseTX and Full Duplex */ + writel(readl(&emac->cfg) | + AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD, + &emac->cfg); + return 0; + } + + if (stat1 & BMSR_10FULL) { + /*set MII for 10BaseT and Full Duplex */ + writel((readl(&emac->cfg) & + ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) + ) | AT91_EMAC_CFG_FD, + &emac->cfg); + return 0; + } + + if (stat1 & BMSR_100HALF) { + /*set MII for 100BaseTX and Half Duplex */ + writel((readl(&emac->cfg) & + ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) + ) | AT91_EMAC_CFG_SPD, + &emac->cfg); + return 0; + } + + if (stat1 & BMSR_10HALF) { + /*set MII for 10BaseT and Half Duplex */ + writel((readl(&emac->cfg) & + ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)), + &emac->cfg); + return 0; + } + return 1; +} + +static int at91emac_init(struct eth_device *netdev, bd_t *bd) +{ + int i; + u32 value; + emac_device *dev; + at91_emac_t *emac; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + emac = (at91_emac_t *) netdev->iobase; + dev = (emac_device *) netdev->priv; + + /* PIO Disable Register */ + value = AT91_PMX_AA_EMDIO | AT91_PMX_AA_EMDC | + AT91_PMX_AA_ERXER | AT91_PMX_AA_ERX1 | + AT91_PMX_AA_ERX0 | AT91_PMX_AA_ECRS | + AT91_PMX_AA_ETX1 | AT91_PMX_AA_ETX0 | + AT91_PMX_AA_ETXEN | AT91_PMX_AA_EREFCK; + + writel(value, &pio->pioa.pdr); + writel(value, &pio->pioa.asr); + +#ifdef CONFIG_RMII + value = AT91_PMX_BA_ERXCK; +#else + value = AT91_PMX_BA_ERXCK | AT91_PMX_BA_ECOL | + AT91_PMX_BA_ERXDV | AT91_PMX_BA_ERX3 | + AT91_PMX_BA_ERX2 | AT91_PMX_BA_ETXER | + AT91_PMX_BA_ETX3 | AT91_PMX_BA_ETX2; +#endif + writel(value, &pio->piob.pdr); + writel(value, &pio->piob.bsr); + + writel(1 << AT91_ID_EMAC, &pmc->pcer); + writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); + + DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", + cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), + cpu_to_le32(*((u32 *)netdev->enetaddr))); + writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l); + writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h); + DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", + readl(&emac->sa2h), readl(&emac->sa2l)); + + /* Init Ethernet buffers */ + for (i = 0; i < RBF_FRAMEMAX; i++) { + dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i]; + dev->rbfdt[i].size = 0; + } + dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; + dev->rbindex = 0; + writel((u32) &(dev->rbfdt[0]), &emac->rbqp); + + writel(readl(&emac->rsr) & + ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA), + &emac->rsr); + + value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC | + HCLK_DIV; +#ifdef CONFIG_RMII + value |= AT91C_EMAC_RMII; +#endif + writel(value, &emac->cfg); + + writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE, + &emac->ctl); + + if (!at91emac_phy_init(netdev)) { + at91emac_UpdateLinkSpeed(emac); + return 0; + } + return 1; +} + +static void at91emac_halt(struct eth_device *netdev) +{ + at91_emac_t *emac; + + emac = (at91_emac_t *) netdev->iobase; + writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE), + &emac->ctl); + DEBUG_AT91EMAC("halt MAC\n"); +} + +static int at91emac_send(struct eth_device *netdev, volatile void *packet, + int length) +{ + at91_emac_t *emac; + + emac = (at91_emac_t *) netdev->iobase; + + while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ)) + ; + writel((u32) packet, &emac->tar); + writel(AT91_EMAC_TCR_LEN(length), &emac->tcr); + while (AT91_EMAC_TCR_LEN(readl(&emac->tcr))) + ; + DEBUG_AT91EMAC("Send %d \n", length); + writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr); + return 0; +} + +static int at91emac_recv(struct eth_device *netdev) +{ + emac_device *dev; + at91_emac_t *emac; + rbf_t *rbfp; + int size; + + emac = (at91_emac_t *) netdev->iobase; + dev = (emac_device *) netdev->priv; + + rbfp = &dev->rbfdt[dev->rbindex]; + while (rbfp->addr & RBF_OWNER) { + size = rbfp->size & RBF_SIZE; + NetReceive(NetRxPackets[dev->rbindex], size); + + DEBUG_AT91EMAC("Recv[%d]: %d bytes @ %x \n", + dev->rbindex, size, rbfp->addr); + + rbfp->addr &= ~RBF_OWNER; + rbfp->size = 0; + if (dev->rbindex < (RBF_FRAMEMAX-1)) + dev->rbindex++; + else + dev->rbindex = 0; + + rbfp = &(dev->rbfdt[dev->rbindex]); + if (!(rbfp->addr & RBF_OWNER)) + writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC, + &emac->rsr); + } + + if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) { + /* EMAC silicon bug 41.3.1 workaround 1 */ + writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl); + writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl); + dev->rbindex = 0; + printf("%s: reset receiver (EMAC dead lock bug)\n", + netdev->name); + } + return 0; +} + +int at91emac_register(bd_t *bis, unsigned long iobase) +{ + emac_device *emac; + emac_device *emacfix; + struct eth_device *dev; + + if (iobase == 0) + iobase = AT91_EMAC_BASE; + emac = malloc(sizeof(*emac)+512); + if (emac == NULL) + return 1; + dev = malloc(sizeof(*dev)); + if (dev == NULL) { + free(emac); + return 1; + } + /* alignment as per Errata (64 bytes) is insufficient! */ + emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00); + memset(emacfix, 0, sizeof(emac_device)); + + memset(dev, 0, sizeof(*dev)); +#ifndef CONFIG_RMII + sprintf(dev->name, "AT91 EMAC"); +#else + sprintf(dev->name, "AT91 EMAC RMII"); +#endif + dev->iobase = iobase; + dev->priv = emacfix; + dev->init = at91emac_init; + dev->halt = at91emac_halt; + dev->send = at91emac_send; + dev->recv = at91emac_recv; + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write); +#endif + return 1; +} diff --git a/include/asm-arm/arch-at91/at91_emac.h b/include/asm-arm/arch-at91/at91_emac.h new file mode 100644 index 0000000..4b96f04 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_emac.h @@ -0,0 +1,145 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) + * + * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC)) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef AT91_H +#define AT91_H + +typedef struct at91_emac { + u32 ctl; + u32 cfg; + u32 sr; + u32 tar; + u32 tcr; + u32 tsr; + u32 rbqp; + u32 reserved0; + u32 rsr; + u32 isr; + u32 ier; + u32 idr; + u32 imr; + u32 man; + u32 reserved1[2]; + u32 fra; + u32 scol; + u32 mocl; + u32 ok; + u32 seqe; + u32 ale; + u32 dte; + u32 lcol; + u32 ecol; + u32 cse; + u32 tue; + u32 cde; + u32 elr; + u32 rjb; + u32 usf; + u32 sqee; + u32 drfc; + u32 reserved2[3]; + u32 hsh; + u32 hsl; + u32 sh1l; + u32 sa1h; + u32 sa2l; + u32 sa2h; + u32 sa3l; + u32 sa3h; + u32 sa4l; + u32 sa4h; +} at91_emac_t; + +#define AT91_EMAC_CTL_LB 0x0001 +#define AT91_EMAC_CTL_LBL 0x0002 +#define AT91_EMAC_CTL_RE 0x0004 +#define AT91_EMAC_CTL_TE 0x0008 +#define AT91_EMAC_CTL_MPE 0x0010 +#define AT91_EMAC_CTL_CSR 0x0020 +#define AT91_EMAC_CTL_ISR 0x0040 +#define AT91_EMAC_CTL_WES 0x0080 +#define AT91_EMAC_CTL_BP 0x1000 + +#define AT91_EMAC_CFG_SPD 0x0001 +#define AT91_EMAC_CFG_FD 0x0002 +#define AT91_EMAC_CFG_BR 0x0004 +#define AT91_EMAC_CFG_CAF 0x0010 +#define AT91_EMAC_CFG_NBC 0x0020 +#define AT91_EMAC_CFG_MTI 0x0040 +#define AT91_EMAC_CFG_UNI 0x0080 +#define AT91_EMAC_CFG_BIG 0x0100 +#define AT91_EMAC_CFG_EAE 0x0200 +#define AT91_EMAC_CFG_CLK_MASK 0xFFFFF3FF +#define AT91_EMAC_CFG_MCLK_8 0x0000 +#define AT91_EMAC_CFG_MCLK_16 0x0400 +#define AT91_EMAC_CFG_MCLK_32 0x0800 +#define AT91_EMAC_CFG_MCLK_64 0x0C00 +#define AT91_EMAC_CFG_RTY 0x1000 +#define AT91_EMAC_CFG_RMII 0x2000 + +#define AT91_EMAC_SR_LINK 0x0001 +#define AT91_EMAC_SR_MDIO 0x0002 +#define AT91_EMAC_SR_IDLE 0x0004 + +#define AT91_EMAC_TCR_LEN(x) (x & 0x7FF) +#define AT91_EMAC_TCR_NCRC 0x8000 + +#define AT91_EMAC_TSR_OVR 0x0001 +#define AT91_EMAC_TSR_COL 0x0002 +#define AT91_EMAC_TSR_RLE 0x0004 +#define AT91_EMAC_TSR_TXIDLE 0x0008 +#define AT91_EMAC_TSR_BNQ 0x0010 +#define AT91_EMAC_TSR_COMP 0x0020 +#define AT91_EMAC_TSR_UND 0x0040 + +#define AT91_EMAC_RSR_BNA 0x0001 +#define AT91_EMAC_RSR_REC 0x0002 +#define AT91_EMAC_RSR_OVR 0x0004 + +/* ISR, IER, IDR, IMR use the same bits */ +#define AT91_EMAC_IxR_DONE 0x0001 +#define AT91_EMAC_IxR_RCOM 0x0002 +#define AT91_EMAC_IxR_RBNA 0x0004 +#define AT91_EMAC_IxR_TOVR 0x0008 +#define AT91_EMAC_IxR_TUND 0x0010 +#define AT91_EMAC_IxR_RTRY 0x0020 +#define AT91_EMAC_IxR_TBRE 0x0040 +#define AT91_EMAC_IxR_TCOM 0x0080 +#define AT91_EMAC_IxR_TIDLE 0x0100 +#define AT91_EMAC_IxR_LINK 0x0200 +#define AT91_EMAC_IxR_ROVR 0x0400 +#define AT91_EMAC_IxR_HRESP 0x0800 + +#define AT91_EMAC_MAN_DATA_MASK 0xFFFF +#define AT91_EMAC_MAN_CODE_802_3 0x00020000 +#define AT91_EMAC_MAN_REGA(reg) ((reg & 0x1F) << 18) +#define AT91_EMAC_MAN_PHYA(phy) ((phy & 0x1F) << 23) +#define AT91_EMAC_MAN_RW_R 0x20000000 +#define AT91_EMAC_MAN_RW_W 0x10000000 +#define AT91_EMAC_MAN_HIGH 0x40000000 +#define AT91_EMAC_MAN_LOW 0x80000000 + +#endif diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 590c69a..5de70cb 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -122,7 +122,14 @@ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 -#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_MULTI 1 +#ifdef CONFIG_NET_MULTI +#define CONFIG_DRIVER_AT91EMAC 1 +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#else +#define CONFIG_DRIVER_ETHER 1 +#endif + #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91C_USE_RMII diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index b4f075e..4750855 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -145,7 +145,13 @@ /* * Network Driver Setting */ -#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_MULTI 1 +#ifdef CONFIG_NET_MULTI +#define CONFIG_DRIVER_AT91EMAC 1 +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#else +#define CONFIG_DRIVER_ETHER 1 +#endif #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91C_USE_RMII diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index be478b2..00d0cec 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -152,7 +152,13 @@ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 -#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_MULTI 1 +#ifdef CONFIG_NET_MULTI +#define CONFIG_DRIVER_AT91EMAC 1 +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#else +#define CONFIG_DRIVER_ETHER 1 +#endif #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91C_USE_RMII diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index 8746f70..e872fe9 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -128,7 +128,13 @@ #define CONFIG_SYS_MEMTEST_END \ (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024) -#define CONFIG_DRIVER_ETHER 1 +#define CONFIG_NET_MULTI 1 +#ifdef CONFIG_NET_MULTI +#define CONFIG_DRIVER_AT91EMAC 1 +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#else +#define CONFIG_DRIVER_ETHER 1 +#endif #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91C_USE_RMII 1 #define CONFIG_PHY_ADDRESS (1 << 5) diff --git a/include/configs/csb637.h b/include/configs/csb637.h index f4fd808..689e7f0 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -126,7 +126,13 @@ #define CONFIG_SYS_ALT_MEMTEST 1 #define CONFIG_SYS_MEMTEST_SCRATCH CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 4 -#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_MULTI 1 +#ifdef CONFIG_NET_MULTI +#define CONFIG_DRIVER_AT91EMAC 1 +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#else +#define CONFIG_DRIVER_ETHER 1 +#endif #define CONFIG_NET_RETRY_COUNT 20 #undef CONFIG_AT91C_USE_RMII diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 7dd81e6..3fe88fe 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -115,7 +115,13 @@ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024) -#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_MULTI 1 +#ifdef CONFIG_NET_MULTI +#define CONFIG_DRIVER_AT91EMAC 1 +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#else +#define CONFIG_DRIVER_ETHER 1 +#endif #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_SYS_FLASH_BASE 0x10000000 diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h index 5c06642..a28fd27 100644 --- a/include/configs/m501sk.h +++ b/include/configs/m501sk.h @@ -34,6 +34,7 @@ #define AT91C_MASTER_CLOCK 59904000 #define AT91_SLOW_CLOCK 32768 /* slow clock */ +#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ @@ -166,7 +167,13 @@ /* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */ #define CONFIG_SYS_MEMTEST_END 0x00100000 -#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_MULTI 1 +#ifdef CONFIG_NET_MULTI +#define CONFIG_DRIVER_AT91EMAC 1 +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#else +#define CONFIG_DRIVER_ETHER 1 +#endif #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91C_USE_RMII diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index 0c2ee60..31eb1b6 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -181,7 +181,13 @@ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 -#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_MULTI 1 +#ifdef CONFIG_NET_MULTI +#define CONFIG_DRIVER_AT91EMAC 1 +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#else +#define CONFIG_DRIVER_ETHER 1 +#endif #define CONFIG_NET_RETRY_COUNT 20 #undef CONFIG_AT91C_USE_RMII diff --git a/include/netdev.h b/include/netdev.h index 1e0484f..1dd80f0 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -42,6 +42,7 @@ int cpu_eth_init(bd_t *bis); /* Driver initialization prototypes */ int au1x00_enet_initialize(bd_t*); +int at91emac_register(bd_t *bis, unsigned long iobase); int bfin_EMAC_initialize(bd_t *bis); int cs8900_initialize(u8 dev_num, int base_addr); int dc21x4x_initialize(bd_t *bis); -- cgit v1.1 From f3dec798d9ebf7f17c11ec7671b979ce3d251955 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Thu, 28 Jan 2010 12:27:14 +0100 Subject: CFI: fix eraseregions numblocks eraseregions numblocks was sometimes one less than actual, possibly producing erase regions with zero blocks. As MTD code touches eraseregions only if numeraseregions is greater that zero, allocate eraseregions only for non uniform erase size flash. Signed-off-by: Ladislav Michl Signed-off-by: Stefan Roese --- drivers/mtd/cfi_mtd.c | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c index 34748dd..6a0cab3 100644 --- a/drivers/mtd/cfi_mtd.c +++ b/drivers/mtd/cfi_mtd.c @@ -161,8 +161,8 @@ static int cfi_mtd_set_erasesize(struct mtd_info *mtd, flash_info_t *fi) int sect; int regions = 0; int numblocks = 0; - ulong offset = 0; - ulong base_addr = fi->start[0]; + ulong offset; + ulong base_addr; /* * First detect the number of eraseregions so that we can allocate @@ -174,29 +174,35 @@ static int cfi_mtd_set_erasesize(struct mtd_info *mtd, flash_info_t *fi) sect_size_old = flash_sector_size(fi, sect); } + switch (regions) { + case 0: + return 1; + case 1: /* flash has uniform erase size */ + mtd->numeraseregions = 0; + mtd->erasesize = sect_size_old; + return 0; + } + + mtd->numeraseregions = regions; mtd->eraseregions = malloc(sizeof(struct mtd_erase_region_info) * regions); /* * Now detect the largest sector and fill the eraseregions */ - sect_size_old = 0; regions = 0; + base_addr = offset = fi->start[0]; + sect_size_old = flash_sector_size(fi, 0); for (sect = 0; sect < fi->sector_count; sect++) { - if ((sect_size_old != flash_sector_size(fi, sect)) && - (sect_size_old != 0)) { + if (sect_size_old != flash_sector_size(fi, sect)) { mtd->eraseregions[regions].offset = offset - base_addr; mtd->eraseregions[regions].erasesize = sect_size_old; mtd->eraseregions[regions].numblocks = numblocks; - /* Now start counting the next eraseregions */ numblocks = 0; regions++; - } else { - numblocks++; - } - - if (sect_size_old != flash_sector_size(fi, sect)) offset = fi->start[sect]; + } + numblocks++; /* * Select the largest sector size as erasesize (e.g. for UBI) @@ -212,12 +218,7 @@ static int cfi_mtd_set_erasesize(struct mtd_info *mtd, flash_info_t *fi) */ mtd->eraseregions[regions].offset = offset - base_addr; mtd->eraseregions[regions].erasesize = sect_size_old; - mtd->eraseregions[regions].numblocks = numblocks + 1; - - if (regions) - mtd->numeraseregions = regions + 1; - else - mtd->numeraseregions = 0; + mtd->eraseregions[regions].numblocks = numblocks; mtd->erasesize = sect_size; -- cgit v1.1 From 6f6c26e430ffae87b6b3d74ba7cbf9439703feea Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 26 Jan 2010 13:33:29 +0100 Subject: ppc4xx: Fix compilation error on ML2 board Recently this compilation error occurs: Configuring for ML2 board... traps.c: In function 'MachineCheckException': traps.c:159: error: 'debugger_exception_handler' undeclared (first use in this function) traps.c:159: error: (Each undeclared identifier is reported only once traps.c:159: error: for each function it appears in.) This patch now fixes it by including kgdb.h Signed-off-by: Stefan Roese --- cpu/ppc4xx/traps.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index cb35faf..42e4221 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -34,6 +34,7 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; -- cgit v1.1 From 59c1db6dab52b981e6ea25a203d0a919ede61ed2 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 1 Feb 2010 13:53:47 +0100 Subject: ppc4xx: Fix building of PMC440 board Remove some unused features and default environment variable to shrink the PMC440 u-boot. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- include/configs/PMC440.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 6310cfc..89799af 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -287,12 +287,8 @@ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \ "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \ - "nand_boot=run nandargs addip addtty addmisc;bootm ${kernel_addr}\0" \ "nand_boot_fdt=run nandargs addip addtty addmisc;" \ "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmisc;" \ - "bootm\0" \ "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \ "tftp ${fdt_addr_r} ${fdt_file};" \ "run nfsargs addip addtty addmisc;" \ @@ -353,7 +349,6 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_DTT -#define CONFIG_CMD_DIAG #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT @@ -366,7 +361,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_USB #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SDRAM /* POST support */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ -- cgit v1.1 From 976c21ad8e136df0ec361aca0c4bc287c5637c01 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 1 Feb 2010 13:53:59 +0100 Subject: ppc4xx: Fix building for PLU405 boards The init_coupler() function from board/esd/plu405/plu405.c got lost somehow! This patch readds it. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/plu405/plu405.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index e385a78..0f7fa69 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -46,6 +46,34 @@ const unsigned char fpgadata[] = */ #include "../common/fpga.c" +/* + * generate a short spike on the CAN tx line + * to bring the couplers in sync + */ +void init_coupler(u32 addr) +{ + struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr; + + /* reset */ + out_8(&ctrl->cr, CR_RR); + + /* dominant */ + out_8(&ctrl->btr0, 0x00); /* btr setup is required */ + out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */ + out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 | + OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1); + out_8(&ctrl->cr, 0x00); + + /* delay */ + in_8(&ctrl->cr); + in_8(&ctrl->cr); + in_8(&ctrl->cr); + in_8(&ctrl->cr); + + /* reset */ + out_8(&ctrl->cr, CR_RR); +} + int board_early_init_f(void) { /* -- cgit v1.1 From 4710cee1b5292fe077a67cc23193cc43060fbe3d Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 1 Feb 2010 13:54:09 +0100 Subject: ppc4xx: Remove unused feature from AR405 board This patch fixes building for AR405 boards by remove an unused feature. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- include/configs/AR405.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/AR405.h b/include/configs/AR405.h index 73e34bd..52ead43 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -93,6 +93,7 @@ #define CONFIG_CMD_IRQ #define CONFIG_CMD_ELF #define CONFIG_CMD_MII +#undef CONFIG_CMD_NFS #define CONFIG_CMD_PING #define CONFIG_CMD_BSP -- cgit v1.1 From 13d8bfe26c0dd2c08b76c5f077e800a718859bbc Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 31 Jan 2010 21:58:48 +0100 Subject: mpc5xxx/cpu_init.c: fix warning: unused variable 'gpt0' Signed-off-by: Wolfgang Denk Acked-by: Detlev Zundel --- cpu/mpc5xxx/cpu_init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c index b151464..2aa6e1c 100644 --- a/cpu/mpc5xxx/cpu_init.c +++ b/cpu/mpc5xxx/cpu_init.c @@ -46,9 +46,12 @@ void cpu_init_f (void) (struct mpc5xxx_gpio *) MPC5XXX_GPIO; volatile struct mpc5xxx_xlb *xlb = (struct mpc5xxx_xlb *) MPC5XXX_XLBARB; +#if defined(CONFIG_WATCHDOG) volatile struct mpc5xxx_gpt *gpt0 = (struct mpc5xxx_gpt *) MPC5XXX_GPT; +#endif /* CONFIG_WATCHDOG */ unsigned long addecr = (1 << 25); /* Boot_CS */ + #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100) addecr |= (1 << 22); /* SDRAM enable */ #endif -- cgit v1.1 From 9461a939cabd606d7f0e9b8490b40841af104ff5 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 31 Jan 2010 22:03:15 +0100 Subject: mpc5xxx/cpu_init.c: fix warning: unused variable 'cdm' Signed-off-by: Wolfgang Denk Acked-by: Detlev Zundel --- cpu/mpc5xxx/cpu_init.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c index 2aa6e1c..560c9b3 100644 --- a/cpu/mpc5xxx/cpu_init.c +++ b/cpu/mpc5xxx/cpu_init.c @@ -40,12 +40,14 @@ void cpu_init_f (void) (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *) MPC5XXX_LPB; - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *) MPC5XXX_CDM; volatile struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO; volatile struct mpc5xxx_xlb *xlb = (struct mpc5xxx_xlb *) MPC5XXX_XLBARB; +#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) + volatile struct mpc5xxx_cdm *cdm = + (struct mpc5xxx_cdm *) MPC5XXX_CDM; +#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ #if defined(CONFIG_WATCHDOG) volatile struct mpc5xxx_gpt *gpt0 = (struct mpc5xxx_gpt *) MPC5XXX_GPT; @@ -187,11 +189,11 @@ void cpu_init_f (void) # if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) /* Motorola reports IPB should better run at 133 MHz. */ -#if defined(CONFIG_MGT5100) +# if defined(CONFIG_MGT5100) setbits_be32(&mm->addecr, 1); -#elif defined(CONFIG_MPC5200) +# elif defined(CONFIG_MPC5200) setbits_be32(&mm->ipbi_ws_ctrl, 1); -#endif +# endif /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ addecr = in_be32(&cdm->cfg); addecr &= ~0x103; -- cgit v1.1 From d0750bc9e5932baf4c90eda2456106f21a26bdc1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 1 Feb 2010 11:36:29 +0100 Subject: EXBITGEN: drop support for unmaintained board The EXBITGEN board has not been maintained for a long time; it has build problems, but no hardware is available any more for testing. Drop support for this board. Signed-off-by: Wolfgang Denk Acked-by: Stefan Roese --- MAINTAINERS | 2 - MAKEALL | 1 - Makefile | 3 - board/exbitgen/Makefile | 52 --- board/exbitgen/config.mk | 33 -- board/exbitgen/exbitgen.c | 126 ------ board/exbitgen/exbitgen.h | 52 --- board/exbitgen/flash.c | 597 -------------------------- board/exbitgen/init.S | 1011 --------------------------------------------- 9 files changed, 1877 deletions(-) delete mode 100644 board/exbitgen/Makefile delete mode 100644 board/exbitgen/config.mk delete mode 100644 board/exbitgen/exbitgen.c delete mode 100644 board/exbitgen/exbitgen.h delete mode 100644 board/exbitgen/flash.c delete mode 100644 board/exbitgen/init.S diff --git a/MAINTAINERS b/MAINTAINERS index e8ba4bc..fe63a9f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -134,8 +134,6 @@ Wolfgang Denk PCIPPC2 MPC750 PCIPPC6 MPC750 - EXBITGEN PPC405GP - Jon Diekema sbc8260 MPC8260 diff --git a/MAKEALL b/MAKEALL index 15e93cf..7047e46 100755 --- a/MAKEALL +++ b/MAKEALL @@ -213,7 +213,6 @@ LIST_4xx=" \ DU440 \ ebony \ ERIC \ - EXBITGEN \ fx12mm \ G2000 \ gdppc440etx \ diff --git a/Makefile b/Makefile index 69b963f..62fa1df 100644 --- a/Makefile +++ b/Makefile @@ -1336,9 +1336,6 @@ ebony_config: unconfig ERIC_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx eric -EXBITGEN_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx exbitgen - fx12mm_flash_config: unconfig @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic @mkdir -p $(obj)include $(obj)board/avnet/fx12mm diff --git a/board/exbitgen/Makefile b/board/exbitgen/Makefile deleted file mode 100644 index 4f752a8..0000000 --- a/board/exbitgen/Makefile +++ /dev/null @@ -1,52 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o flash.o - -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/exbitgen/config.mk b/board/exbitgen/config.mk deleted file mode 100644 index 42ea0c6..0000000 --- a/board/exbitgen/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# ExbitGen board -# - -LDFLAGS += $(LINKER_UNDEFS) - -TEXT_BASE := 0xFFF80000 -#TEXT_BASE := 0x00100000 - -PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS) diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c deleted file mode 100644 index 50d9748..0000000 --- a/board/exbitgen/exbitgen.c +++ /dev/null @@ -1,126 +0,0 @@ -#include -#include -#include -#include "exbitgen.h" - -void sdram_init(void); - -/* ************************************************************************ */ -int board_early_init_f (void) -/* ------------------------------------------------------------------------ -- - * Purpose : - * Remarks : - * Restrictions: - * See also : - * Example : - * ************************************************************************ */ -{ - unsigned long i; - - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the Walnut board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive - | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive - | IRQ 27 (EXT IRQ 2) Not Used - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for Walnut board: - | An interrupt taken for the FPGA (IRQ 25) indicates that either - | the Mouse, Keyboard, IRDA, or External Expansion caused the - | interrupt. The FPGA must be read to determine which device - | caused the interrupt. The default setting of the FPGA clears - | - +-------------------------------------------------------------------------*/ - - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF90); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* Perform reset of PHY connected to PPC via register in CPLD */ - out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */ - for (i = 0; i < 10000000; i++) { - ; - } - out8 (PHY_CTRL_ADDR, 0x2f); /* deactivate nRESET */ - - return 0; -} - - -/* ************************************************************************ */ -int checkboard (void) -/* ------------------------------------------------------------------------ -- - * Purpose : - * Remarks : - * Restrictions: - * See also : - * Example : - * ************************************************************************ */ -{ - printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR)); - return (0); -} - -/* ************************************************************************ */ -phys_size_t initdram (int board_type) -/* ------------------------------------------------------------------------ -- - * Purpose : Determines size of mounted DRAM. - * Remarks : Size is determined by reading SDRAM configuration registers as - * set up by sdram_init. - * Restrictions: - * See also : - * Example : - * ************************************************************************ */ -{ - ulong tot_size; - ulong bank_size; - ulong tmp; - - /* - * ToDo: Move the asm init routine sdram_init() to this C file, - * or even better use some common ppc4xx code available - * in cpu/ppc4xx - */ - sdram_init(); - - tot_size = 0; - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - return tot_size; -} diff --git a/board/exbitgen/exbitgen.h b/board/exbitgen/exbitgen.h deleted file mode 100644 index dceaf6d..0000000 --- a/board/exbitgen/exbitgen.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define GPIO_CPU_LED GPIO_3 - - -#define CPLD_BASE 0x10000000 /* t.b.m. */ -#define DEBUG_LEDS_ADDR CPLD_BASE + 0x01 -#define HW_ID_ADDR CPLD_BASE + 0x02 -#define DIP_SWITCH_ADDR CPLD_BASE + 0x04 -#define PHY_CTRL_ADDR CPLD_BASE + 0x05 -#define SPI_OUT_ADDR CPLD_BASE + 0x07 -#define SPI_IN_ADDR CPLD_BASE + 0x08 -#define MDIO_OUT_ADDR CPLD_BASE + 0x09 -#define MDIO_IN_ADDR CPLD_BASE + 0x0A -#define MISC_OUT_ADDR CPLD_BASE + 0x0B - -/* Addresses used on I2C bus */ -#define LM75_CHIP_ADDR 0x9C -#define LM75_CPU_ADDR 0x9E -#define SDRAM_SPD_ADDR 0xA0 - -#define SDRAM_SPD_WRITE_ADDRESS (SDRAM_SPD_ADDR) -#define SDRAM_SPD_READ_ADDRESS (SDRAM_SPD_ADDR+1) - -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef TRUE -#define TRUE 1 -#endif diff --git a/board/exbitgen/flash.c b/board/exbitgen/flash.c deleted file mode 100644 index cd45cb6..0000000 --- a/board/exbitgen/flash.c +++ /dev/null @@ -1,597 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include -#include -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -#ifdef MEIGSBOARD_ONBOARD_FLASH /* onboard = 2MB */ -# ifdef CONFIG_EXBITGEN -# define FLASH_WORD_SIZE unsigned long -# endif -#else /* Meigsboard socket flash = 512KB */ -# ifdef CONFIG_EXBITGEN -# define FLASH_WORD_SIZE unsigned char -# endif -#endif - -#ifdef CONFIG_EXBITGEN -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char -#endif - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long bank_size; - unsigned long tot_size; - unsigned long bank_addr; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = 0; - } - - tot_size = 0; - - /* Detect Boot Flash */ - bank_addr = CONFIG_SYS_FLASH0_BASE; - bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[0]); - if (bank_size > 0) { - (void)flash_protect(FLAG_PROTECT_CLEAR, - bank_addr, - bank_addr + bank_size - 1, - &flash_info[0]); - } - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Boot Flash Bank\n"); - } - flash_info[0].size = bank_size; - tot_size += bank_size; - - /* Detect Application Flash */ - bank_addr = CONFIG_SYS_FLASH1_BASE; - for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[i]); - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - break; - } - if (bank_size > 0) { - (void)flash_protect(FLAG_PROTECT_CLEAR, - bank_addr, - bank_addr + bank_size - 1, - &flash_info[i]); - } - flash_info[i].size = bank_size; - tot_size += bank_size; - bank_addr += bank_size; - } - if (flash_info[1].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Application Flash Bank\n"); - } - - /* Protect monitor and environment sectors */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#if 0xfffffffc >= CONFIG_SYS_FLASH0_BASE -#if 0xfffffffc <= CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_FLASH0_SIZE - 1 - flash_protect(FLAG_PROTECT_SET, - 0xfffffffc, 0xffffffff, - &flash_info[0]); -#endif -#endif -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return tot_size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDLV033C: printf ("AM29LV033C (32 Mbit, uniform sector size)\n"); - break; - case FLASH_AMDLV065D: printf ("AM29LV065D (64 Mbit, uniform sector size)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV065D: - info->flash_id += FLASH_AMDLV065D; - info->sector_count = 128; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - case (FLASH_WORD_SIZE)SST_ID_xF040: - info->flash_id += FLASH_SST040; - info->sector_count = 128; - info->size = 0x00080000; - break; /* => 512KB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040) || - (info->flash_id == FLASH_AMDLV033C) || - (info->flash_id == FLASH_AMDLV065D)) { - ulong sectsize = info->size / info->sector_count; - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sectsize); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* switch to the read mode */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while ((addr2[0] & 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now=get_timer(start)) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; - } - } - - printf (" done\n"); - - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile ulong *)dest) & data) != data) { - printf("dest = %08lx, *dest = %08lx, data = %08lx\n", - dest, *(volatile ulong *)dest, data); - return 2; - } - - for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & 0x00800080) != (data2[i] & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - addr2[0] = (FLASH_WORD_SIZE)0x00F000F0; - return (1); - } - } - } - - addr2[0] = (FLASH_WORD_SIZE)0x00F000F0; - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S deleted file mode 100644 index 721aaac..0000000 --- a/board/exbitgen/init.S +++ /dev/null @@ -1,1011 +0,0 @@ -/*----------------------------------------------------------------------+ - * This source code is dual-licensed. You may use it under the terms of - * the GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *----------------------------------------------------------------------- - */ - -#include -#include -#include "config.h" - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ -#define FPGA_BRDC 0xF0300004 - -#include -#include - -#include -#include - -#include "exbitgen.h" - -/* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */ -/* c-code declarations and consequently can't be included here). */ -/* (Possibly to be solved somehow else). */ -/*--------------------------------------------------------------------- */ -#define I2C_REGISTERS_BASE_ADDRESS 0xEF600500 -#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF) -#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF) -#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR) -#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR) -#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL) -#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL) -#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS) -#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS) -#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR) -#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR) -#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV) -#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK) -#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT) -#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS) -#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL) - -/* MDCNTL Register Bit definition */ -#define IIC_MDCNTL_HSCL 0x01 -#define IIC_MDCNTL_EUBS 0x02 -#define IIC_MDCNTL_FMDB 0x40 -#define IIC_MDCNTL_FSDB 0x80 - -/* CNTL Register Bit definition */ -#define IIC_CNTL_PT 0x01 -#define IIC_CNTL_READ 0x02 -#define IIC_CNTL_CHT 0x04 - -/* STS Register Bit definition */ -#define IIC_STS_PT 0X01 -#define IIC_STS_ERR 0X04 -#define IIC_STS_MDBS 0X20 - -/* EXTSTS Register Bit definition */ -#define IIC_EXTSTS_XFRA 0X01 -#define IIC_EXTSTS_ICT 0X02 -#define IIC_EXTSTS_LA 0X04 - -/* LED codes used for inditing progress and errors during read of DIMM SPD. */ -/*--------------------------------------------------------------------- */ -#define LED_SDRAM_CODE_1 0xef -#define LED_SDRAM_CODE_2 0xee -#define LED_SDRAM_CODE_3 0xed -#define LED_SDRAM_CODE_4 0xec -#define LED_SDRAM_CODE_5 0xeb -#define LED_SDRAM_CODE_6 0xea -#define LED_SDRAM_CODE_7 0xe9 -#define LED_SDRAM_CODE_8 0xe8 -#define LED_SDRAM_CODE_9 0xe7 -#define LED_SDRAM_CODE_10 0xe6 -#define LED_SDRAM_CODE_11 0xe5 -#define LED_SDRAM_CODE_12 0xe4 -#define LED_SDRAM_CODE_13 0xe3 -#define LED_SDRAM_CODE_14 0xe2 -#define LED_SDRAM_CODE_15 0xe1 -#define LED_SDRAM_CODE_16 0xe0 - - -#define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100 - -#define FLASH_8bit_AP 0x9B015480 -#define FLASH_8bit_CR 0xFFF18000 /* 1MB(min), 8bit, R/W */ - -#define FLASH_32bit_AP 0x9B015480 -#define FLASH_32bit_CR 0xFFE3C000 /* 2MB, 32bit, R/W */ - - -#define WDCR_EBC(reg,val) addi r4,0,reg;\ - mtdcr EBC0_CFGADDR,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr EBC0_CFGDATA,r4 - -/*--------------------------------------------------------------------- - * Function: ext_bus_cntlr_init - * Description: Initializes the External Bus Controller for the external - * peripherals. IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * Bank 0 - Boot flash - * Bank 1-4 - application flash - * Bank 5 - CPLD - * Bank 6 - not used - * Bank 7 - Heathrow chip - *--------------------------------------------------------------------- - */ - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ - - mflr r31 /* save link register */ - - /*----------------------------------------------------------- - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - *----------------------------------------------------------- - */ - - addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /*--------------------------------------------------------------- - * Memory Bank 0 (Boot Flash) initialization - *--------------------------------------------------------------- - */ - WDCR_EBC(PB1AP, FLASH_32bit_AP) - WDCR_EBC(PB0CR, 0xffe38000) -/*pnc WDCR_EBC(PB0CR, FLASH_32bit_CR) */ - - /*--------------------------------------------------------------- - * Memory Bank 5 (CPLD) initialization - *--------------------------------------------------------------- - */ - WDCR_EBC(PB5AP, 0x01010040) -/*jsa recommendation: WDCR_EBC(PB5AP, 0x00010040) */ - WDCR_EBC(PB5CR, 0x10038000) - - /*--------------------------------------------------------------- */ - /* Memory Bank 6 (not used) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(PB6CR, 0x00000000) - - /* Read HW ID to determine whether old H2 board or new generic CPU board */ - addis r3, 0, HW_ID_ADDR@h - ori r3, r3, HW_ID_ADDR@l - lbz r3,0x0000(r3) - cmpi 0, r3, 1 /* if (HW_ID==1) */ - beq setup_h2evalboard /* then jump */ - cmpi 0, r3, 2 /* if (HW_ID==2) */ - beq setup_genieboard /* then jump */ - cmpi 0, r3, 3 /* if (HW_ID==3) */ - beq setup_genieboard /* then jump */ - -setup_genieboard: - /*--------------------------------------------------------------- */ - /* Memory Bank 1 (Application Flash) initialization for generic CPU board */ - /*--------------------------------------------------------------- */ -/* WDCR_EBC(PB1AP, 0x7b015480) /###* T.B.M. */ -/* WDCR_EBC(PB1AP, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(PB1AP, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */ - -/* WDCR_EBC(PB1CR, 0x20098000) /###* 16 MB */ - WDCR_EBC(PB1CR, 0x200B8000) /* 32 MB */ - - /*--------------------------------------------------------------- */ - /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */ - /*--------------------------------------------------------------- */ - WDCR_EBC(PB4AP, 0x01010000) /* */ - WDCR_EBC(PB4CR, 0x1021c000) /* */ - - /*--------------------------------------------------------------- */ - /* Memory Bank 7 (Heathrow chip on Reference board) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(PB7AP, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */ - WDCR_EBC(PB7CR, 0X4001A000) - - bl setup_continue - - -setup_h2evalboard: - /*--------------------------------------------------------------- */ - /* Memory Bank 1 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(PB1AP, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(PB1AP, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(PB1CR, 0x20058000) - - /*--------------------------------------------------------------- */ - /* Memory Bank 2 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(PB2AP, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(PB2AP, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(PB2CR, 0x20458000) - - /*--------------------------------------------------------------- */ - /* Memory Bank 3 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(PB3AP, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(PB3AP, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(PB3CR, 0x20858000) - - /*--------------------------------------------------------------- */ - /* Memory Bank 4 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(PB4AP, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(PB4AP, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(PB4CR, 0x20C58000) - - /*--------------------------------------------------------------- */ - /* Memory Bank 7 (Heathrow chip) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(PB7AP, 0x02000280) /* No Ready, 4 wait states */ - WDCR_EBC(PB7CR, 0X4001A000) - -setup_continue: - - - mtlr r31 /* restore lr */ - nop /* pass2 DCR errata #8 */ - blr - -/*--------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: Configures SDRAM memory banks. */ -/*--------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE - blr -#else - mflr r31 - - /* output SDRAM code on LEDs */ - addi r4, 0, LED_SDRAM_CODE_1 - addis r5, 0, 0x1000 - ori r5, r5, 0x0001 - stb r4,0(r5) - eieio - - /* Read contents of spd */ - /*--------------------- */ - bl read_spd - - /*----------------------------------------------------------- */ - /* */ - /* */ - /* Update SDRAM timing register */ - /* */ - /* */ - /*----------------------------------------------------------- */ - - /* Read PLL feedback divider and calculate clock period of local bus in */ - /* granularity of 10 ps. Save clock period in r30 */ - /*-------------------------------------------------------------- */ - mfdcr r4, CPC0_PLLMR - addi r9, 0, 25 - srw r4, r4, r9 - andi. r4, r4, 0x07 - addis r5, 0, TIMEBASE_10PS@h - ori r5, r5, TIMEBASE_10PS@l - divwu r30, r5, r4 - - /* Determine CASL */ - /*--------------- */ - bl find_casl /* Returns CASL in r3 */ - - /* Calc trp_clocks = (trp * 100 + (clk - 1)) / clk */ - /* (trp read from byte 27 in granularity of 1 ns) */ - /*------------------------------------------------ */ - mulli r16, r16, 100 - add r16, r16, r30 - addi r6, 0, 1 - subf r16, r6, r16 - divwu r16, r16, r30 - - /* Calc trcd_clocks = (trcd * 100 + (clk - 1) ) / clk */ - /* (trcd read from byte 29 in granularity of 1 ns) */ - /*--------------------------------------------------- */ - mulli r17, r17, 100 - add r17, r17, r30 - addi r6, 0, 1 - subf r17, r6, r17 - divwu r17, r17, r30 - - /* Calc tras_clocks = (tras * 100 + (clk - 1) ) / clk */ - /* (tras read from byte 30 in granularity of 1 ns) */ - /*--------------------------------------------------- */ - mulli r18, r18, 100 - add r18, r18, r30 - addi r6, 0, 1 - subf r18, r6, r18 - divwu r18, r18, r30 - - /* Calc trc_clocks = trp_clocks + tras_clocks */ - /*------------------------------------------- */ - add r18, r18, r16 - - /* CASL value */ - /*----------- */ - addi r9, 0, 23 - slw r4, r3, r9 - - /* PTA = trp_clocks - 1 */ - /*--------------------- */ - addi r6, 0, 1 - subf r5, r6, r16 - addi r9, 0, 18 - slw r5, r5, r9 - or r4, r4, r5 - - /* CTP = trc_clocks - trp_clocks - trcd_clocks - 1 */ - /*------------------------------------------------ */ - addi r5, r18, 0 - subf r5, r16, r5 - subf r5, r17, r5 - addi r6, 0, 1 - subf r5, r6, r5 - addi r9, 0, 16 - slw r5, r5, r9 - or r4, r4, r5 - - /* LDF = 1 */ - /*-------- */ - ori r4, r4, 0x4000 - - /* RFTA = trc_clocks - 4 */ - /*---------------------- */ - addi r6, 0, 4 - subf r5, r6, r18 - addi r9, 0, 2 - slw r5, r5, r9 - or r4, r4, r5 - - /* RCD = trcd_clocks - 1 */ - /*---------------------- */ - addi r6, 0, 1 - subf r5, r6, r17 - or r4, r4, r5 - - /*----------------------------------------------------------- */ - /* Set SDTR1 */ - /*----------------------------------------------------------- */ - addi r5,0,SDRAM0_TR - mtdcr SDRAM0_CFGADDR,r5 - mtdcr SDRAM0_CFGDATA,r4 - - /*----------------------------------------------------------- */ - /* */ - /* */ - /* Update memory bank 0-3 configuration registers */ - /* */ - /* */ - /*----------------------------------------------------------- */ - - /* Build contents of configuration register for bank 0 into r6 */ - /*------------------------------------------------------------ */ - bl find_mode /* returns addressing mode in r3 */ - addi r29, r3, 0 /* save mode temporarily in r29 */ - bl find_size_code /* returns size code in r3 */ - addi r9, 0, 17 /* bit offset of size code in configuration register */ - slw r3, r3, r9 /* */ - addi r9, 0, 13 /* bit offset of addressing mode in configuration register */ - slw r29, r29, r9 /* */ - or r3, r29, r3 /* merge size code and addressing mode */ - ori r6, r3, CONFIG_SYS_SDRAM_BASE + 1 /* insert base address and enable bank */ - - /* Calculate banksize r15 = (density << 22) / 2 */ - /*--------------------------------------------- */ - addi r9, 0, 21 - slw r15, r15, r9 - - /* Set SDRAM bank 0 register and adjust r6 for next bank */ - /*------------------------------------------------------ */ - addi r7,0,SDRAM0_B0CR - mtdcr SDRAM0_CFGADDR,r7 - mtdcr SDRAM0_CFGDATA,r6 - - add r6, r6, r15 /* add bank size to base address for next bank */ - - /* If two rows/banks then set SDRAM bank 1 register and adjust r6 for next bank */ - /*---------------------------------------------------------------------------- */ - cmpi 0, r12, 2 - bne b1skip - - addi r7,0,SDRAM0_B1CR - mtdcr SDRAM0_CFGADDR,r7 - mtdcr SDRAM0_CFGDATA,r6 - - add r6, r6, r15 /* add bank size to base address for next bank */ - - /* Set SDRAM bank 2 register and adjust r6 for next bank */ - /*------------------------------------------------------ */ -b1skip: addi r7,0,SDRAM0_B2CR - mtdcr SDRAM0_CFGADDR,r7 - mtdcr SDRAM0_CFGDATA,r6 - - add r6, r6, r15 /* add bank size to base address for next bank */ - - /* If two rows/banks then set SDRAM bank 3 register */ - /*------------------------------------------------ */ - cmpi 0, r12, 2 - bne b3skip - - addi r7,0,SDRAM0_B3CR - mtdcr SDRAM0_CFGADDR,r7 - mtdcr SDRAM0_CFGDATA,r6 -b3skip: - - /*----------------------------------------------------------- */ - /* Set RTR */ - /*----------------------------------------------------------- */ - cmpi 0, r30, 1600 - bge rtr_1 - addis r7, 0, 0x05F0 /* RTR value for 100Mhz */ - bl rtr_2 -rtr_1: addis r7, 0, 0x03F8 -rtr_2: addi r4,0,SDRAM0_RTR - mtdcr SDRAM0_CFGADDR,r4 - mtdcr SDRAM0_CFGDATA,r7 - - /*----------------------------------------------------------- */ - /* Delay to ensure 200usec have elapsed since reset. Assume worst */ - /* case that the core is running 200Mhz: */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*----------------------------------------------------------- */ - addis r3,0,0x0000 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp2: - bdnz ..spinlp2 /* spin loop */ - - /*----------------------------------------------------------- */ - /* Set memory controller options reg, MCOPT1. */ - /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ - /* read/prefetch. */ - /*----------------------------------------------------------- */ - addi r4,0,SDRAM0_CFG - mtdcr SDRAM0_CFGADDR,r4 - addis r4,0,0x80C0 /* set DC_EN=1 */ - ori r4,r4,0x0000 - mtdcr SDRAM0_CFGDATA,r4 - - - /*----------------------------------------------------------- */ - /* Delay to ensure 10msec have elapsed since reset. This is */ - /* required for the MPC952 to stabalize. Assume worst */ - /* case that the core is running 200Mhz: */ - /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */ - /* This delay should occur before accessing SDRAM. */ - /*----------------------------------------------------------- */ - addis r3,0,0x001E - ori r3,r3,0x8480 /* ensure 10msec have passed since reset */ - mtctr r3 -..spinlp3: - bdnz ..spinlp3 /* spin loop */ - - /* output SDRAM code on LEDs */ - addi r4, 0, LED_SDRAM_CODE_16 - addis r5, 0, 0x1000 - ori r5, r5, 0x0001 - stb r4,0(r5) - eieio - - mtlr r31 /* restore lr */ - blr - -/*--------------------------------------------------------------------- */ -/* Function: read_spd */ -/* Description: Reads contents of SPD and saves parameters to be used for */ -/* configuration in dedicated registers (see code below). */ -/*--------------------------------------------------------------------- */ - -#define WRITE_I2C(reg,val) \ - addi r3,0,val;\ - addis r4, 0, 0xef60;\ - ori r4, r4, 0x0500 + reg;\ - stb r3, 0(r4);\ - eieio - -#define READ_I2C(reg) \ - addis r3, 0, 0xef60;\ - ori r3, r3, 0x0500 + reg;\ - lbz r3, 0x0000(r3);\ - eieio - -read_spd: - - mflr r5 - - /* Initialize i2c */ - /*--------------- */ - WRITE_I2C(IICLMADR, 0x00) /* clear lo master address */ - WRITE_I2C(IICHMADR, 0x00) /* clear hi master address */ - WRITE_I2C(IICLSADR, 0x00) /* clear lo slave address */ - WRITE_I2C(IICHSADR, 0x00) /* clear hi slave address */ - WRITE_I2C(IICSTS, 0x08) /* update status register */ - WRITE_I2C(IICEXTSTS, 0x8f) - WRITE_I2C(IIC0_CLKDIV, 0x05) - WRITE_I2C(IICINTRMSK, 0x00) /* no interrupts */ - WRITE_I2C(IICXFRCNT, 0x00) /* clear transfer count */ - WRITE_I2C(IICXTCNTLSS, 0xf0) /* clear extended control & stat */ - WRITE_I2C(IICMDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB) /* mode control */ - READ_I2C(IICMDCNTL) - ori r3, r3, IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL - WRITE_I2C(IICMDCNTL, r3) /* mode control */ - WRITE_I2C(IICCNTL, 0x00) /* clear control reg */ - - /* Wait until initialization completed */ - /*------------------------------------ */ - bl wait_i2c_transfer_done - - WRITE_I2C(IICHMADR, 0x00) /* 7-bit addressing */ - WRITE_I2C(IICLMADR, SDRAM_SPD_WRITE_ADDRESS) - - /* Write 0 into buffer(start address) */ - /*----------------------------------- */ - WRITE_I2C(IICMDBUF, 0x00); - - /* Wait a little */ - /*-------------- */ - addis r3,0,0x0000 - ori r3,r3,0xA000 - mtctr r3 -in02: bdnz in02 - - /* Issue write command */ - /*-------------------- */ - WRITE_I2C(IICCNTL, IIC_CNTL_PT) - bl wait_i2c_transfer_done - - /* Read 128 bytes */ - /*--------------- */ - addi r7, 0, 0 /* byte counter in r7 */ - addi r8, 0, 0 /* checksum in r8 */ -rdlp: - /* issue read command */ - /*------------------- */ - cmpi 0, r7, 127 - blt rd01 - WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT) - bl rd02 -rd01: WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT) -rd02: bl wait_i2c_transfer_done - - /* Fetch byte from buffer */ - /*----------------------- */ - READ_I2C(IICMDBUF) - - /* Retrieve parameters that are going to be used during configuration. */ - /* Save them in dedicated registers. */ - /*------------------------------------------------------------ */ - cmpi 0, r7, 3 /* Save byte 3 in r10 */ - bne rd10 - addi r10, r3, 0 -rd10: cmpi 0, r7, 4 /* Save byte 4 in r11 */ - bne rd11 - addi r11, r3, 0 -rd11: cmpi 0, r7, 5 /* Save byte 5 in r12 */ - bne rd12 - addi r12, r3, 0 -rd12: cmpi 0, r7, 17 /* Save byte 17 in r13 */ - bne rd13 - addi r13, r3, 0 -rd13: cmpi 0, r7, 18 /* Save byte 18 in r14 */ - bne rd14 - addi r14, r3, 0 -rd14: cmpi 0, r7, 31 /* Save byte 31 in r15 */ - bne rd15 - addi r15, r3, 0 -rd15: cmpi 0, r7, 27 /* Save byte 27 in r16 */ - bne rd16 - addi r16, r3, 0 -rd16: cmpi 0, r7, 29 /* Save byte 29 in r17 */ - bne rd17 - addi r17, r3, 0 -rd17: cmpi 0, r7, 30 /* Save byte 30 in r18 */ - bne rd18 - addi r18, r3, 0 -rd18: cmpi 0, r7, 9 /* Save byte 9 in r19 */ - bne rd19 - addi r19, r3, 0 -rd19: cmpi 0, r7, 23 /* Save byte 23 in r20 */ - bne rd20 - addi r20, r3, 0 -rd20: cmpi 0, r7, 25 /* Save byte 25 in r21 */ - bne rd21 - addi r21, r3, 0 -rd21: - - /* Calculate checksum of the first 63 bytes */ - /*----------------------------------------- */ - cmpi 0, r7, 63 - bgt rd31 - beq rd30 - add r8, r8, r3 - bl rd31 - - /* Verify checksum at byte 63 */ - /*--------------------------- */ -rd30: andi. r8, r8, 0xff /* use only 8 bits */ - cmp 0, r8, r3 - beq rd31 - addi r4, 0, LED_SDRAM_CODE_8 - addis r5, 0, 0x1000 - ori r5, r5, 0x0001 - stb r4,0(r5) - eieio -rderr: bl rderr - -rd31: - - /* Increment byte counter and check whether all bytes have been read. */ - /*------------------------------------------------------------------- */ - addi r7, r7, 1 - cmpi 0, r7, 127 - bgt rd05 - bl rdlp -rd05: - mtlr r5 /* restore lr */ - blr - -wait_i2c_transfer_done: - mflr r6 -wt01: READ_I2C(IICSTS) - andi. r4, r3, IIC_STS_PT - cmpi 0, r4, IIC_STS_PT - beq wt01 - mtlr r6 /* restore lr */ - blr - -/*--------------------------------------------------------------------- */ -/* Function: find_mode */ -/* Description: Determines addressing mode to be used dependent on */ -/* number of rows (r10 = byte 3 from SPD), number of columns (r11 = */ -/* byte 4 from SPD) and number of banks (r13 = byte 17 from SPD). */ -/* mode is returned in r3. */ -/* (It would be nicer having a table, pnc). */ -/*--------------------------------------------------------------------- */ -find_mode: - - mflr r5 - - cmpi 0, r10, 11 - bne fm01 - cmpi 0, r11, 9 - bne fm01 - cmpi 0, r13, 2 - bne fm01 - addi r3, 0, 1 - bl fmfound - -fm01: cmpi 0, r10, 11 - bne fm02 - cmpi 0, r11, 10 - bne fm02 - cmpi 0, r13, 2 - bne fm02 - addi r3, 0, 1 - bl fmfound - -fm02: cmpi 0, r10, 12 - bne fm03 - cmpi 0, r11, 9 - bne fm03 - cmpi 0, r13, 4 - bne fm03 - addi r3, 0, 2 - bl fmfound - -fm03: cmpi 0, r10, 12 - bne fm04 - cmpi 0, r11, 10 - bne fm04 - cmpi 0, r13, 4 - bne fm04 - addi r3, 0, 2 - bl fmfound - -fm04: cmpi 0, r10, 13 - bne fm05 - cmpi 0, r11, 9 - bne fm05 - cmpi 0, r13, 4 - bne fm05 - addi r3, 0, 3 - bl fmfound - -fm05: cmpi 0, r10, 13 - bne fm06 - cmpi 0, r11, 10 - bne fm06 - cmpi 0, r13, 4 - bne fm06 - addi r3, 0, 3 - bl fmfound - -fm06: cmpi 0, r10, 13 - bne fm07 - cmpi 0, r11, 11 - bne fm07 - cmpi 0, r13, 4 - bne fm07 - addi r3, 0, 3 - bl fmfound - -fm07: cmpi 0, r10, 12 - bne fm08 - cmpi 0, r11, 8 - bne fm08 - cmpi 0, r13, 2 - bne fm08 - addi r3, 0, 4 - bl fmfound - -fm08: cmpi 0, r10, 12 - bne fm09 - cmpi 0, r11, 8 - bne fm09 - cmpi 0, r13, 4 - bne fm09 - addi r3, 0, 4 - bl fmfound - -fm09: cmpi 0, r10, 11 - bne fm10 - cmpi 0, r11, 8 - bne fm10 - cmpi 0, r13, 2 - bne fm10 - addi r3, 0, 5 - bl fmfound - -fm10: cmpi 0, r10, 11 - bne fm11 - cmpi 0, r11, 8 - bne fm11 - cmpi 0, r13, 4 - bne fm11 - addi r3, 0, 5 - bl fmfound - -fm11: cmpi 0, r10, 13 - bne fm12 - cmpi 0, r11, 8 - bne fm12 - cmpi 0, r13, 2 - bne fm12 - addi r3, 0, 6 - bl fmfound - -fm12: cmpi 0, r10, 13 - bne fm13 - cmpi 0, r11, 8 - bne fm13 - cmpi 0, r13, 4 - bne fm13 - addi r3, 0, 6 - bl fmfound - -fm13: cmpi 0, r10, 13 - bne fm14 - cmpi 0, r11, 9 - bne fm14 - cmpi 0, r13, 2 - bne fm14 - addi r3, 0, 7 - bl fmfound - -fm14: cmpi 0, r10, 13 - bne fm15 - cmpi 0, r11, 10 - bne fm15 - cmpi 0, r13, 2 - bne fm15 - addi r3, 0, 7 - bl fmfound - -fm15: - /* not found, error code to be issued on LEDs */ - addi r7, 0, LED_SDRAM_CODE_2 - addis r6, 0, 0x1000 - ori r6, r6, 0x0001 - stb r7,0(r6) - eieio -fmerr: bl fmerr - -fmfound:addi r6, 0, 1 - subf r3, r6, r3 - - mtlr r5 /* restore lr */ - blr - -/*--------------------------------------------------------------------- */ -/* Function: find_size_code */ -/* Description: Determines size code to be used in configuring SDRAM controller */ -/* dependent on density (r15 = byte 31 from SPD) */ -/*--------------------------------------------------------------------- */ -find_size_code: - - mflr r5 - - addi r3, r15, 0 /* density */ - addi r7, 0, 0 -fs01: andi. r6, r3, 0x01 - cmpi 0, r6, 1 - beq fs04 - - addi r7, r7, 1 - cmpi 0, r7, 7 - bge fs02 - addi r9, 0, 1 - srw r3, r3, r9 - bl fs01 - - /* not found, error code to be issued on LEDs */ -fs02: addi r4, 0, LED_SDRAM_CODE_3 - addis r8, 0, 0x1000 - ori r8, r8, 0x0001 - stb r4,0(r8) - eieio -fs03: bl fs03 - -fs04: addi r3, r7, 0 - cmpi 0, r3, 0 - beq fs05 - addi r6, 0, 1 - subf r3, r6, r3 -fs05: - mtlr r5 /* restore lr */ - blr - -/*--------------------------------------------------------------------- */ -/* Function: find_casl */ -/* Description: Determines CAS latency */ -/*--------------------------------------------------------------------- */ -find_casl: - - mflr r5 - - andi. r14, r14, 0x7f /* r14 holds supported CAS latencies */ - addi r3, 0, 0xff /* preset determined CASL */ - addi r4, 0, 6 /* Start at bit 6 of supported CAS latencies */ - addi r2, 0, 0 /* Start finding highest CAS latency */ - -fc01: srw r6, r14, r4 /* */ - andi. r6, r6, 0x01 /* */ - cmpi 0, r6, 1 /* Check bit for current latency */ - bne fc06 /* If not supported, go to next */ - - cmpi 0, r2, 2 /* Check if third-highest latency */ - bge fc04 /* If so, go calculate with another format */ - - cmpi 0, r2, 0 /* Check if highest latency */ - bgt fc02 /* */ - addi r7, r19, 0 /* SDRAM cycle time for highest CAS latenty */ - - bl fc03 -fc02: - addi r7, r20, 0 /* SDRAM cycle time for next-highest CAS latenty */ -fc03: - addi r8, r7, 0 - addi r9, 0, 4 - srw r7, r7, r9 - andi. r7, r7, 0x0f - mulli r7, r7, 100 - andi. r8, r8, 0x0f - mulli r8, r8, 10 - add r7, r7, r8 - cmp 0, r7, r30 - bgt fc05 - addi r3, r2, 0 - bl fc05 -fc04: - addi r7, r21, 0 /* SDRAM cycle time for third-highest CAS latenty */ - addi r8, r7, 0 - addi r9, 0, 2 - srw r7, r7, r9 - andi. r7, r7, 0x3f - mulli r7, r7, 100 - andi. r8, r8, 0x03 - mulli r8, r8, 25 - add r7, r7, r8 - - cmp 0, r7, r30 - bgt fc05 - addi r3, r2, 0 - -fc05: addi r2, r2, 1 /* next latency */ - cmpi 0, r2, 3 - bge fc07 -fc06: addi r6, 0, 1 - subf r4, r6, r4 - cmpi 0, r4, 0 - bne fc01 - -fc07: - - mtlr r5 /* restore lr */ - blr -#endif - - -/* Peripheral Bank 1 Access Parameters */ -/* 0 BME = 1 ; burstmode enabled */ -/* " 1:8" TWT=00110110 ;Transfer wait (details below) */ -/* 1:5 FWT=00110 ; first wait = 6 cycles */ -/* 6:8 BWT=110 ; burst wait = 6 cycles */ -/* 9:11 000 ; reserved */ -/* 12:13 CSN=00 ; chip select on timing = 0 */ -/* 14:15 OEN=01 ; output enable */ -/* 16:17 WBN=01 ; write byte enable on timing 1 cycle */ -/* 18:19 WBF=01 ; write byte enable off timing 1 cycle */ -/* 20:22 TH=010 ; transfer hold = 2 cycles */ -/* 23 RE=0 ; ready enable = disabled */ -/* 24 SOR=1 ; sample on ready = same PerClk */ -/* 25 BEM=0 ; byte enable mode = only for write cycles */ -/* 26 PEN=0 ; parity enable = disable */ -/* 27:31 00000 ;reserved */ -/* */ -/* 1 + 00110 + 110 + 000 + 00 + 01 + 01 + 01 + 010 + 0 + 1 + 0 + 0 + 00000 = 0x9b015480 */ -/* */ -/* */ -/* Code for BDI probe: */ -/* */ -/* WDCR 18 0x00000011 ;Select PB1AP */ -/* WDCR 19 0x1b015480 ;PB1AP: Flash */ -/* */ -/* Peripheral Bank 0 Access Parameters */ -/* 0:11 BAS=0x200 ; base address select = 0x200 * 0x100000 (1MB) = */ -/* 12:14 BS=100 ; bank size = 16MB (100) / 32MB (101) */ -/* 15:16 BU=11 ; bank usage = read/write */ -/* 17:18 BW=00 ; bus width = 8-bit */ -/* 19:31 ; reserved */ -/* */ -/* 0x200 + 100 + 11 + 00 + 0 0000 0000 0000 = 0x20098000 */ -/* WDCR 18 0x00000001 ;Select PB1CR */ -/* WDCR 19 0x20098000 ;PB1CR: 1MB at 0x00100000, r/w, 8bit */ - -/* For CPLD */ -/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */ -/* WDCR_EBC(PB5AP, 0x01010040) */ -/*jsa recommendation: WDCR_EBC(PB5AP, 0x00010040) */ -/* WDCR_EBC(PB5CR, 0X10018000) */ -/* Access parms */ -/* 100 3 8 0 0 0 */ -/* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */ -/* Address : 0x10000000 */ -/* Size: 2 MB */ -/* Usage: read/write */ -/* Width: 32 bit */ - -/* For Genie onboard fpga 32 bit interface */ -/* 0 1 0 1 0 0 0 0 */ -/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 0 + 0 + 00000 */ -/* 0x01010000 */ -/* Access parms */ -/* 102 1 c 0 0 0 */ -/* 0x102 + 000 + 11 + 10 + 0 0000 0000 0000 = 0x1021c000 */ -/* Address : 0x10200000 */ -/* Size: 2 MB */ -/* Usage: read/write */ -/* Width: 32 bit */ - -/* Walnut fpga PB7AP */ -/* 0 1 8 1 5 2 8 0 */ -/* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */ -/* Walnut fpga PB7CR */ -/* 0xF0318000 */ -/* */ -- cgit v1.1 From ec2aadb40855cecb088b68c062e3534d6ce39128 Mon Sep 17 00:00:00 2001 From: Cliff Cai Date: Tue, 19 Jan 2010 00:10:42 -0500 Subject: usb: musb: fix Blackfin DMA register padding The conversion from offsets to C structs lost a little padding in the DMA register map. Accessing endpoints other than ep0 with DMA would fail as the addresses wouldn't be adjusted correctly. Signed-off-by: Cliff Cai Signed-off-by: Mike Frysinger --- drivers/usb/musb/blackfin_usb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/musb/blackfin_usb.h b/drivers/usb/musb/blackfin_usb.h index ab26ca2..de994bf 100644 --- a/drivers/usb/musb/blackfin_usb.h +++ b/drivers/usb/musb/blackfin_usb.h @@ -82,7 +82,7 @@ struct bfin_musb_dma_regs { ureg(addr_high); ureg(count_low); ureg(count_high); - ureg(pad); + u32 reserved0[2]; }; #undef ureg -- cgit v1.1 From 6e20e64f5c6deb5b48e40a0cba4877f9170545e0 Mon Sep 17 00:00:00 2001 From: Prathap Srinivas Date: Mon, 11 Jan 2010 15:36:46 +0530 Subject: musb: Add host support for DM365 EVM Add support for musb host on DM365 EVM. Signed-off-by: Prathap Srinivas --- drivers/usb/musb/davinci.c | 21 +++++++++++++++++++-- drivers/usb/musb/davinci.h | 1 + include/configs/davinci_dm365evm.h | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c index a7648fc..8fbadc9 100644 --- a/drivers/usb/musb/davinci.c +++ b/drivers/usb/musb/davinci.c @@ -24,6 +24,7 @@ #include #include #include "davinci.h" +#include /* MUSB platform configuration */ struct musb_config musb_cfg = { @@ -41,10 +42,25 @@ struct davinci_usb_regs *dregs; static u8 phy_on(void) { u32 timeout; - +#ifdef DAVINCI_DM365EVM + u32 val; +#endif /* Wait until the USB phy is turned on */ +#ifdef DAVINCI_DM365EVM + writel(USBPHY_PHY24MHZ | USBPHY_SESNDEN | + USBPHY_VBDTCTEN, USBPHY_CTL_PADDR); +#else writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN, USBPHY_CTL_PADDR); +#endif timeout = musb_cfg.timeout; + +#ifdef DAVINCI_DM365EVM + /* Set the ownership of GIO33 to USB */ + val = readl(PINMUX4); + val &= ~(PINMUX4_USBDRVBUS_BITCLEAR); + val |= PINMUX4_USBDRVBUS_BITSET; + writel(val, PINMUX4); +#endif while (timeout--) if (readl(USBPHY_CTL_PADDR) & USBPHY_PHYCLKGD) return 1; @@ -70,8 +86,9 @@ int musb_platform_init(void) u32 revision; /* enable USB VBUS */ +#ifndef DAVINCI_DM365EVM enable_vbus(); - +#endif /* start the on-chip USB phy and its pll */ if (!phy_on()) return -1; diff --git a/drivers/usb/musb/davinci.h b/drivers/usb/musb/davinci.h index f6751bf..e0829d6 100644 --- a/drivers/usb/musb/davinci.h +++ b/drivers/usb/musb/davinci.h @@ -63,6 +63,7 @@ struct davinci_usb_regs { /* Integrated highspeed/otg PHY */ #define USBPHY_CTL_PADDR (DAVINCI_SYSTEM_MODULE_BASE + 0x34) +#define USBPHY_PHY24MHZ (1 << 13) #define USBPHY_PHYCLKGD (1 << 8) #define USBPHY_SESNDEN (1 << 7) /* v(sess_end) comparator */ #define USBPHY_VBDTCTEN (1 << 6) /* v(bus) comparator */ diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index c6e1d10..6f99ae0 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -85,6 +85,44 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 2 +#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000 +#define PINMUX4_USBDRVBUS_BITSET 0x2000 + +/* USB Configuration */ +#define CONFIG_USB_DAVINCI +#define CONFIG_MUSB_HCD + +#ifdef CONFIG_USB_DAVINCI +#define CONFIG_CMD_USB /* include support for usb */ +#define CONFIG_CMD_STORAGE /* include support for usb */ +#define CONFIG_CMD_FAT /* include support for FAT/storage*/ +#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/ +#endif + +#ifdef CONFIG_MUSB_HCD /* include support for usb host */ +#define CONFIG_CMD_USB /* include support for usb cmd */ +#define CONFIG_USB_STORAGE /* MSC class support */ +#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */ +#define CONFIG_CMD_FAT /* inclue support for FAT/storage */ +#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */ + +#ifdef CONFIG_USB_KEYBOARD /* HID class support */ +#define CONFIG_SYS_USB_EVENT_POLL + +#define CONFIG_PREBOOT "usb start" +#endif /* CONFIG_USB_KEYBOARD */ +#endif /* CONFIG_MUSB_HCD */ + +#ifdef CONFIG_MUSB_UDC +#define CONFIG_USB_DEVICE 1 +#define CONFIG_USB_TTY 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#define CONFIG_USBD_VENDORID 0x0451 +#define CONFIG_USBD_PRODUCTID 0x5678 +#define CONFIG_USBD_MANUFACTURER "Texas Instruments" +#define CONFIG_USBD_PRODUCT_NAME "DM365VM" +#endif /* CONFIG_MUSB_UDC */ + /* U-Boot command configuration */ #include -- cgit v1.1 From 84d36b30181acfb72f22d1105c15574b30ea2fa1 Mon Sep 17 00:00:00 2001 From: Remy Bohmer Date: Mon, 1 Feb 2010 19:40:47 +0100 Subject: USB: usb_control_msg wait for driver ISR to set status. This patch changes usb_control_msg back to the state prior to commit 48867208444cb2a82e2af9c3249e90b7ed4a1751. The USB driver ISR routine may update the status. Signed-off-by: Daniel Hellstrom --- common/usb.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/common/usb.c b/common/usb.c index eef4b34..10e23de 100644 --- a/common/usb.c +++ b/common/usb.c @@ -197,16 +197,21 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, if (timeout == 0) return (int)size; - if (dev->status != 0) { - /* - * Let's wait a while for the timeout to elapse. - * It has no real use, but it keeps the interface happy. - */ - wait_ms(timeout); - return -1; + /* + * Wait for status to update until timeout expires, USB driver + * interrupt handler may set the status when the USB operation has + * been completed. + */ + while (timeout--) { + if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC)) + break; + wait_ms(1); } + if (dev->status) + return -1; return dev->act_len; + } /*------------------------------------------------------------------- -- cgit v1.1 From a1b322a98319de568b3bc38029ef7e123643c1e8 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Mon, 1 Feb 2010 23:34:25 +0100 Subject: ns16550: kick watchdog while waiting for a character ns16550 busyloops waiting for incoming byte causing watchdog to reboot while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc loop fixes it. Signed-off-by: Ladislav Michl --- drivers/serial/ns16550.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 2fcc8c3..b3bf10b 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -6,6 +6,7 @@ #include #include +#include #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ @@ -70,6 +71,7 @@ char NS16550_getc (NS16550_t com_port) extern void usbtty_poll(void); usbtty_poll(); #endif + WATCHDOG_RESET(); } return (com_port->rbr); } -- cgit v1.1 From e66b19ce6dbe6f91b18ba47273cbe89eb5a80e78 Mon Sep 17 00:00:00 2001 From: Siddarth Gore Date: Tue, 19 Jan 2010 11:09:07 +0530 Subject: NET: kirkwood-egiga smi access fix Although the datasheet mentions seperate smi registers for each port, using Port 1 smi register to access ethernet phys does not work. Hence only Port 0 smi register should be used to access all devices connected to the smi bus. This behavior is consistant with the mv643xx driver in the linux kernel. Signed-off-by: Siddarth Gore Acked-by: Prafulla Wadaskar Signed-off-by: Ben Warren --- drivers/net/kirkwood_egiga.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index 07a86cd..2ad7fea 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -39,6 +39,7 @@ #include "kirkwood_egiga.h" #define KIRKWOOD_PHY_ADR_REQUEST 0xee +#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi) /* * smi_reg_read - miiphy_read callback function. @@ -76,7 +77,7 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) /* wait till the SMI is not busy */ do { /* read smi register */ - smi_reg = KWGBEREG_RD(regs->smi); + smi_reg = KWGBEREG_RD(KWGBE_SMI_REG); if (timeout-- == 0) { printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); return -EFAULT; @@ -89,14 +90,14 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) | KWGBE_PHY_SMI_OPCODE_READ; /* write the smi register */ - KWGBEREG_WR(regs->smi, smi_reg); + KWGBEREG_WR(KWGBE_SMI_REG, smi_reg); /*wait till read value is ready */ timeout = KWGBE_PHY_SMI_TIMEOUT; do { /* read smi register */ - smi_reg = KWGBEREG_RD(regs->smi); + smi_reg = KWGBEREG_RD(KWGBE_SMI_REG); if (timeout-- == 0) { printf("Err..(%s) SMI read ready timeout\n", __FUNCTION__); @@ -107,7 +108,7 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) /* Wait for the data to update in the SMI register */ for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ; - *data = (u16) (KWGBEREG_RD(regs->smi) & KWGBE_PHY_SMI_DATA_MASK); + *data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK); debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr, reg_ofs, *data); @@ -150,7 +151,7 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data) timeout = KWGBE_PHY_SMI_TIMEOUT; do { /* read smi register */ - smi_reg = KWGBEREG_RD(regs->smi); + smi_reg = KWGBEREG_RD(KWGBE_SMI_REG); if (timeout-- == 0) { printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); return -ETIME; @@ -164,7 +165,7 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data) smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ; /* write the smi register */ - KWGBEREG_WR(regs->smi, smi_reg); + KWGBEREG_WR(KWGBE_SMI_REG, smi_reg); return 0; } -- cgit v1.1 From 4294b2485bf0e8d68c893190a96bb0e7856b12c4 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 1 Feb 2010 14:51:30 +0100 Subject: fec_mxc: add support for MX51 processor The patch add support for the Freescale mx51 processor to the FEC ethernet driver. Signed-off-by: Stefano Babic Signed-off-by: Ben Warren --- drivers/net/fec_mxc.c | 73 ++++++++++++++++++++++----------------------------- 1 file changed, 32 insertions(+), 41 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 19116f2..446076f 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -108,6 +108,17 @@ static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr, return 0; } +static void fec_mii_setspeed(struct fec_priv *fec) +{ + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + */ + writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, + &fec->eth->mii_speed); + debug("fec_init: mii_speed %#lx\n", + fec->eth->mii_speed); +} static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr, uint16_t data) { @@ -236,7 +247,7 @@ static int fec_rbd_init(struct fec_priv *fec, int count, int size) fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); p = (uint32_t)fec->rdb_ptr; if (!p) { - puts("fec_imx27: not enough malloc memory!\n"); + puts("fec_mxc: not enough malloc memory\n"); return -ENOMEM; } memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT); @@ -299,6 +310,13 @@ static void fec_rbd_clean(int last, struct fec_bd *pRbd) static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) { +/* + * The MX27 can store the mac address in internal eeprom + * This mechanism is not supported now by MX51 + */ +#ifdef CONFIG_MX51 + return -1; +#else struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; int i; @@ -306,10 +324,12 @@ static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]); return is_valid_ether_addr(mac); +#endif } -static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac) +static int fec_set_hwaddr(struct eth_device *dev) { + uchar *mac = dev->enetaddr; struct fec_priv *fec = (struct fec_priv *)dev->priv; writel(0, &fec->eth->iaddr1); @@ -373,7 +393,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd) sizeof(struct fec_bd) + DB_ALIGNMENT); base = (uint32_t)fec->base_ptr; if (!base) { - puts("fec_imx27: not enough malloc memory!\n"); + puts("fec_mxc: not enough malloc memory\n"); return -ENOMEM; } memset((void *)base, 0, (2 + FEC_RBD_NUM) * @@ -411,14 +431,8 @@ static int fec_init(struct eth_device *dev, bd_t* bd) * Frame length=1518; MII mode; */ writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */ - /* - * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock - * and do not drop the Preamble. - */ - writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1, - &fec->eth->mii_speed); - debug("fec_init: mii_speed %#lx\n", - (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1); + + fec_mii_setspeed(fec); } /* * Set Opcode/Pause Duration Register @@ -460,6 +474,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd) miiphy_restart_aneg(dev); fec_open(dev); + fec_set_hwaddr(dev); return 0; } @@ -522,7 +537,7 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length) * Check for valid length of data. */ if ((length > 1500) || (length <= 0)) { - printf("Payload (%d) to large!\n", length); + printf("Payload (%d) too large\n", length); return -1; } @@ -651,22 +666,14 @@ static int fec_recv(struct eth_device *dev) static int fec_probe(bd_t *bd) { - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; struct eth_device *edev; struct fec_priv *fec = &gfec; - unsigned char ethaddr_str[20]; unsigned char ethaddr[6]; - char *tmp = getenv("ethaddr"); - char *end; - - /* enable FEC clock */ - writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1); - writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0); /* create and fill edev struct */ edev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (!edev) { - puts("fec_imx27: not enough malloc memory!\n"); + puts("fec_mxc: not enough malloc memory\n"); return -ENOMEM; } edev->priv = fec; @@ -702,14 +709,7 @@ static int fec_probe(bd_t *bd) * Frame length=1518; MII mode; */ writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */ - /* - * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock - * and do not drop the Preamble. - */ - writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1, - &fec->eth->mii_speed); - debug("fec_init: mii_speed %#lx\n", - (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1); + fec_mii_setspeed(fec); sprintf(edev->name, "FEC_MXC"); @@ -717,20 +717,11 @@ static int fec_probe(bd_t *bd) eth_register(edev); - if ((NULL != tmp) && (12 <= strlen(tmp))) { - int i; - /* convert MAC from string to int */ - for (i = 0; i < 6; i++) { - ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end + 1 : end; - } - } else if (fec_get_hwaddr(edev, ethaddr) == 0) { + if (fec_get_hwaddr(edev, ethaddr) == 0) { printf("got MAC address from EEPROM: %pM\n", ethaddr); - setenv("ethaddr", (char *)ethaddr_str); + memcpy(edev->enetaddr, ethaddr, 6); + fec_set_hwaddr(edev); } - memcpy(edev->enetaddr, ethaddr, 6); - fec_set_hwaddr(edev, ethaddr); return 0; } -- cgit v1.1 From ab5a0dcb9c8f19e351fc33c5db91469bfb1d9438 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 2 Feb 2010 13:43:48 +0100 Subject: net: Use 0.5 sec timeout in miiphy_reset() instead of counting loop This patch fixes a problem I've notived on a buggy PPC4xx system. This system has problems with the PHY MDIO communication and seemed to be stuck/crashed in miiphy_reset(). But degugging revealed, that the CPU didn't crash, but "only" hung in this counting loop for about 2 minutes. This patch now uses a real timeout of 0.5 seconds (as mentioned in the comment in miiphy_reset). Signed-off-by: Stefan Roese Signed-off-by: Ben Warren --- common/miiphyutil.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 196ef4a..856fbc7 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -293,7 +293,7 @@ int miiphy_info (char *devname, unsigned char addr, unsigned int *oui, int miiphy_reset (char *devname, unsigned char addr) { unsigned short reg; - int loop_cnt; + int timeout = 500; if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) { debug ("PHY status read failed\n"); @@ -311,13 +311,13 @@ int miiphy_reset (char *devname, unsigned char addr) * auto-clearing). This should happen within 0.5 seconds per the * IEEE spec. */ - loop_cnt = 0; reg = 0x8000; - while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) { - if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) { - debug ("PHY status read failed\n"); - return (-1); + while (((reg & 0x8000) != 0) && timeout--) { + if (miiphy_read(devname, addr, PHY_BMCR, ®) != 0) { + debug("PHY status read failed\n"); + return -1; } + udelay(1000); } if ((reg & 0x8000) == 0) { return (0); -- cgit v1.1 From e39bf1e2a9e437174687de687c127ec980a93eeb Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 8 Feb 2010 15:30:16 -0500 Subject: kgdb: cpu/mpc* cpu/74xx: include kgdb.h when needed Commit cbb0cab1d929839d broke some platforms which used kgdb code but didn't actually include kgdb.h. So include kgdb.h in all the relevant traps code. Signed-off-by: Mike Frysinger --- cpu/74xx_7xx/traps.c | 1 + cpu/mpc512x/traps.c | 1 + cpu/mpc5xx/traps.c | 1 + cpu/mpc5xxx/traps.c | 1 + cpu/mpc8220/traps.c | 1 + cpu/mpc8260/traps.c | 1 + cpu/mpc83xx/traps.c | 1 + cpu/mpc85xx/traps.c | 1 + cpu/mpc86xx/traps.c | 1 + cpu/mpc8xx/traps.c | 1 + 10 files changed, 10 insertions(+) diff --git a/cpu/74xx_7xx/traps.c b/cpu/74xx_7xx/traps.c index 24e28e2..1d5dd01 100644 --- a/cpu/74xx_7xx/traps.c +++ b/cpu/74xx_7xx/traps.c @@ -34,6 +34,7 @@ #include #include +#include #include #ifdef CONFIG_AMIGAONEG3SE diff --git a/cpu/mpc512x/traps.c b/cpu/mpc512x/traps.c index 8000fab..786f4a5 100644 --- a/cpu/mpc512x/traps.c +++ b/cpu/mpc512x/traps.c @@ -28,6 +28,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/cpu/mpc5xx/traps.c b/cpu/mpc5xx/traps.c index cc8e091..6882c21 100644 --- a/cpu/mpc5xx/traps.c +++ b/cpu/mpc5xx/traps.c @@ -34,6 +34,7 @@ #include #include +#include #include #if defined(CONFIG_CMD_BEDBUG) diff --git a/cpu/mpc5xxx/traps.c b/cpu/mpc5xxx/traps.c index 2a09153..934a2f2 100644 --- a/cpu/mpc5xxx/traps.c +++ b/cpu/mpc5xxx/traps.c @@ -35,6 +35,7 @@ #include #include +#include #include /* Returns 0 if exception not found and fixup otherwise. */ diff --git a/cpu/mpc8220/traps.c b/cpu/mpc8220/traps.c index f98d40f..4565780 100644 --- a/cpu/mpc8220/traps.c +++ b/cpu/mpc8220/traps.c @@ -35,6 +35,7 @@ #include #include +#include #include /* Returns 0 if exception not found and fixup otherwise. */ diff --git a/cpu/mpc8260/traps.c b/cpu/mpc8260/traps.c index f9f4dea..d216f71 100644 --- a/cpu/mpc8260/traps.c +++ b/cpu/mpc8260/traps.c @@ -34,6 +34,7 @@ #include #include +#include #include #include diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c index 3b09a62..9d71b8b 100644 --- a/cpu/mpc83xx/traps.c +++ b/cpu/mpc83xx/traps.c @@ -27,6 +27,7 @@ #include #include +#include #include #include diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 241ebd5..10108d8 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -38,6 +38,7 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index ad005c3..406403e 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -32,6 +32,7 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/cpu/mpc8xx/traps.c b/cpu/mpc8xx/traps.c index f357c8d..6efe8e0 100644 --- a/cpu/mpc8xx/traps.c +++ b/cpu/mpc8xx/traps.c @@ -34,6 +34,7 @@ #include #include +#include #include #if defined(CONFIG_CMD_BEDBUG) -- cgit v1.1 From 44d80256229d05862622f4dd886466fd70fe04ae Mon Sep 17 00:00:00 2001 From: Daniel Gorsulowski Date: Mon, 25 Jan 2010 10:50:41 +0100 Subject: at91: Add esd gmbh OTC570 board support This patch adds support for esd gmbh OTC570 board. The OTC570 is based on an Atmel AT91SAM9263 SoC. Signed-off-by: Daniel Gorsulowski --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/esd/otc570/Makefile | 55 +++++++ board/esd/otc570/config.mk | 1 + board/esd/otc570/otc570.c | 365 +++++++++++++++++++++++++++++++++++++++++++ board/esd/otc570/partition.c | 37 +++++ include/configs/otc570.h | 246 +++++++++++++++++++++++++++++ tools/Makefile | 3 + tools/logos/esd.bmp | Bin 0 -> 35078 bytes 10 files changed, 712 insertions(+) create mode 100644 board/esd/otc570/Makefile create mode 100644 board/esd/otc570/config.mk create mode 100644 board/esd/otc570/otc570.c create mode 100644 board/esd/otc570/partition.c create mode 100644 include/configs/otc570.h create mode 100644 tools/logos/esd.bmp diff --git a/MAINTAINERS b/MAINTAINERS index fe63a9f..5ad055e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -572,6 +572,7 @@ Peter Figuli Daniel Gorsulowski meesc ARM926EJS (AT91SAM9263 SoC) + otc570 ARM926EJS (AT91SAM9263 SoC) Sedji Gaouaou at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC) diff --git a/MAKEALL b/MAKEALL index 684db67..f461cd5 100755 --- a/MAKEALL +++ b/MAKEALL @@ -659,6 +659,7 @@ LIST_at91=" \ meesc \ mp2usb \ m501sk \ + otc570 \ pm9261 \ pm9263 \ SBC35_A9G20 \ diff --git a/Makefile b/Makefile index e4431f7..c4402c2 100644 --- a/Makefile +++ b/Makefile @@ -2870,6 +2870,9 @@ at91sam9g45ekes_config : unconfig fi; @$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91 +otc570_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs otc570 esd at91 + pm9263_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91 diff --git a/board/esd/otc570/Makefile b/board/esd/otc570/Makefile new file mode 100644 index 0000000..755c5ee --- /dev/null +++ b/board/esd/otc570/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/esd/otc570/config.mk b/board/esd/otc570/config.mk new file mode 100644 index 0000000..ff2cfd1 --- /dev/null +++ b/board/esd/otc570/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c new file mode 100644 index 0000000..056df37 --- /dev/null +++ b/board/esd/otc570/otc570.c @@ -0,0 +1,365 @@ +/* + * (C) Copyright 2010 + * Daniel Gorsulowski + * esd electronic system design gmbh + * + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_LCD_INFO +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ + +static int hw_rev = -1; /* hardware revision */ + +int get_hw_rev(void) +{ + if (hw_rev >= 0) + return hw_rev; + + hw_rev = at91_get_gpio_value(AT91_PIN_PB19); + hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1; + hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2; + hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3; + + if (hw_rev == 15) + hw_rev = 0; + + return hw_rev; +} + +#ifdef CONFIG_CMD_NAND +static void otc570_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBI0CSA); + at91_sys_write(AT91_MATRIX_EBI0CSA, + csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_DBW_8 | + AT91_SMC_TDF_(2)); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif /* CONFIG_CMD_NAND */ + +#ifdef CONFIG_MACB +static void otc570_macb_hw_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + at91_macb_hw_init(); +} +#endif + +/* + * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT + * controller debugging + * The ET1100 is located at physical address 0x70000000 + * Its process memory is located at physical address 0x70001000 + */ +static void otc570_ethercat_hw_init(void) +{ + /* Configure SMC EBI1_CS0 for EtherCAT */ + at91_sys_write(AT91_SMC1_SETUP(0), + AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC1_PULSE(0), + AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) | + AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(9)); + at91_sys_write(AT91_SMC1_CYCLE(0), + AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(6)); + /* + * Configure behavior at external wait signal, byte-select mode, 16 bit + * data bus width, none data float wait states and TDF optimization + */ + at91_sys_write(AT91_SMC1_MODE(0), + AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY | + AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) | + AT91_SMC_TDFMODE); + + /* Configure RDY/BSY */ + at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */ +} + +#ifdef CONFIG_LCD +/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */ +vidinfo_t panel_info = { + .vl_col = 640, + .vl_row = 480, + .vl_clk = 25175000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + + .vl_bpix = 3, /* Bits per pixel, 0 = 1bit, 3 = 8bit */ + .vl_tft = 1, /* 0 = passive, 1 = TFT */ + .vl_vsync_len = 1, /* Length of vertical sync in NOL */ + .vl_upper_margin = 35, /* Idle lines at the frame start */ + .vl_lower_margin = 5, /* Idle lines at the end of the frame */ + .vl_hsync_len = 5, /* Width of the LCDHSYNC pulse */ + .vl_left_margin = 112, /* Idle cycles at the line beginning */ + .vl_right_margin = 1, /* Idle cycles at the end of the line */ + + .mmio = AT91SAM9263_LCDC_BASE, +}; + +void lcd_enable(void) +{ + at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ +} + +static void otc570_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ + at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ + at91_set_gpio_output(AT91_PIN_PA30, 1); /* PCI */ + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC); + + gd->fb_base = CONFIG_OTC570_LCD_BASE; +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; + + lcd_printf("\n%s\n", U_BOOT_VERSION); + lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME, + strmhz(temp, get_cpu_clk_rate())); + lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, + nand_size >> 20 ); + lcd_printf(" Board : esd ARM9 HMI Panel - OTC570\n"); + lcd_printf(" Hardware-revision: 1.%d\n", get_hw_rev()); + lcd_printf(" Mach-type : %lu\n", gd->bd->bi_arch_number); +} +#endif /* CONFIG_LCD_INFO */ +#endif /* CONFIG_LCD */ + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27)); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); +#endif + return rc; +} + +int checkboard(void) +{ + char str[32]; + + puts("Board: esd ARM9 HMI Panel - OTC570"); + if (getenv_r("serial#", str, sizeof(str)) > 0) { + puts(", serial# "); + puts(str); + } + printf("\nHardware-revision: 1.%d\n", get_hw_rev()); + printf("Mach-type: %lu\n", gd->bd->bi_arch_number); + return 0; +} + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *str; + + char *serial = getenv("serial#"); + if (serial) { + str = strchr(serial, '_'); + if (str && (strlen(str) >= 4)) { + serialnr->high = (*(str + 1) << 8) | *(str + 2); + serialnr->low = simple_strtoul(str + 3, NULL, 16); + } + } else { + serialnr->high = 0; + serialnr->low = 0; + } +} +#endif + +#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void) +{ + return hw_rev | 0x100; +} +#endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + char str[64]; + + at91_set_gpio_output(AT91_PIN_PA29, 1); + at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0); + /* Set USART_MODE = 1 (RS485) */ + at91_sys_write((0xFFF8C004 - AT91_BASE_SYS), 1); + + printf("USART0: "); + + if (getenv_r("usart0", str, sizeof(str)) == -1) { + printf("No entry - assuming 1-wire\n"); + /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */ + at91_set_gpio_output(AT91_PIN_PA29, 0); + } else { + if (strcmp(str, "1-wire") == 0) { + printf("%s\n", str); + at91_set_gpio_output(AT91_PIN_PA29, 0); + } else if (strcmp(str, "rs485") == 0) { + printf("%s\n", str); + at91_set_gpio_output(AT91_PIN_PA29, 1); + } else { + printf("Wrong entry - assuming 1-wire "); + printf("(valid values are '1-wire' or 'rs485')\n"); + at91_set_gpio_output(AT91_PIN_PA29, 0); + } + } + printf("Display memory address: 0x%08lX\n", gd->fb_base); + + return 0; +} +#endif /* CONFIG_MISC_INIT_R */ + +int board_init(void) +{ + /* Peripheral Clock Enable Register */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | + 1 << AT91SAM9263_ID_PIOB | + 1 << AT91SAM9263_ID_PIOCDE | + 1 << AT91SAM9263_ID_TWI | + 1 << AT91SAM9263_ID_SPI0 | + 1 << AT91SAM9263_ID_LCDC | + 1 << AT91SAM9263_ID_UHP); + + /* arch number of OTC570-Board */ + gd->bd->bi_arch_number = MACH_TYPE_OTC570; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + otc570_nand_hw_init(); +#endif + otc570_ethercat_hw_init(); +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_MACB + otc570_macb_hw_init(); +#endif +#ifdef CONFIG_AT91_CAN + at91_can_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif +#ifdef CONFIG_LCD + otc570_lcd_hw_init(); +#endif + return 0; +} diff --git a/board/esd/otc570/partition.c b/board/esd/otc570/partition.c new file mode 100644 index 0000000..df0e1db --- /dev/null +++ b/board/esd/otc570/partition.c @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2008 + * Ulf Samuelsson + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include +#include +#include + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/* define the area offsets */ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, +}; diff --git a/include/configs/otc570.h b/include/configs/otc570.h new file mode 100644 index 0000000..bedaf13 --- /dev/null +++ b/include/configs/otc570.h @@ -0,0 +1,246 @@ +/* + * (C) Copyright 2010 + * Daniel Gorsulowski + * esd electronic system design gmbh + * + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the esd OTC570 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Common stuff */ +#define CONFIG_OTC570 1 /* Board is esd OTC570 */ +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq */ +#define CONFIG_DISPLAY_BOARDINFO 1 +#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_SERIAL_TAG 1 +#define CONFIG_REVISION_TAG 1 +#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */ + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +#define CONFIG_ARCH_CPU_INIT + +/* + * Hardware drivers + */ + +/* Console output */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 + +#undef CONFIG_SPLASH_SCREEN + +#ifndef CONFIG_SPLASH_SCREEN +#define CONFIG_LCD_LOGO 1 +#define CONFIG_LCD_INFO 1 +#undef CONFIG_LCD_INFO_BELOW_LOGO +#endif /* CONFIG_SPLASH_SCREEN */ + +#undef LCD_TEST_PATTERN +#define CONFIG_SYS_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#define CONFIG_OTC570_LCD_BASE 0x23E00000 /* LCD is in SDRAM */ +#define CONFIG_CMD_BMP 1 + +/* RTC and I2C stuff */ +#define CONFIG_RTC_DS1338 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#undef CONFIG_HARD_I2C +#define CONFIG_SOFT_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x7F + +#ifdef CONFIG_SOFT_I2C +#define CONFIG_I2C_CMD_TREE 1 +#define CONFIG_I2C_MULTI_BUS 1 +/* Enable peripheral clock and configure data and clock pins for pio */ +#define I2C_INIT { \ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB | \ + 1 << AT91SAM9263_ID_PIOCDE); \ + at91_set_gpio_output(AT91_PIN_PB4, 0); \ + at91_set_gpio_output(AT91_PIN_PB5, 0); \ +} +/* Configure data pin as output */ +#define I2C_ACTIVE at91_set_gpio_output(AT91_PIN_PB4, 0) +/* Configure data pin as input */ +#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PB4, 0) +/* Read data pin */ +#define I2C_READ at91_get_gpio_value(AT91_PIN_PB4) +/* Set data pin */ +#define I2C_SDA(bit) at91_set_gpio_value(AT91_PIN_PB4, bit) +/* Set clock pin */ +#define I2C_SCL(bit) at91_set_gpio_value(AT91_PIN_PB5, bit) +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_I2C 1 +#define CONFIG_CMD_DATE 1 + +/* LED */ +#define CONFIG_AT91_LED 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 + +/* DataFlash */ +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NOR flash is not populated, disable it */ +#define CONFIG_SYS_NO_FLASH 1 + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#undef CONFIG_RESET_PHY_R + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_CMD_FAT 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +#define CONFIG_SYS_USE_DATAFLASH 1 +#undef CONFIG_SYS_USE_NANDFLASH + +/* CAN */ +#define CONFIG_AT91_CAN 1 + +/* hw-controller addresses */ +#define CONFIG_ET1100_BASE 0x70000000 + +/* bootstrap + u-boot + env in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ + 0x8400) +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x4200 + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ + 128*1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/tools/Makefile b/tools/Makefile index 266306e..743505f 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -112,6 +112,9 @@ endif ifeq ($(VENDOR),atmel) LOGO_BMP= logos/atmel.bmp endif +ifeq ($(VENDOR),esd) +LOGO_BMP= logos/esd.bmp +endif ifeq ($(VENDOR),ronetix) LOGO_BMP= logos/ronetix.bmp endif diff --git a/tools/logos/esd.bmp b/tools/logos/esd.bmp new file mode 100644 index 0000000..a6b4030 Binary files /dev/null and b/tools/logos/esd.bmp differ -- cgit v1.1 From 8ed5885693b39c5c2cca5574dd98d6ad8a982702 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Wed, 27 Jan 2010 11:10:40 -0500 Subject: TI DaVinci: Driver for the davinci SPI controller This adds a driver for the SPI controller found on davinci based SoCs from Texas Instruments. Signed-off-by: Sekhar Nori Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Sandeep Paulraj --- drivers/spi/Makefile | 1 + drivers/spi/davinci_spi.c | 223 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/davinci_spi.h | 101 +++++++++++++++++++++ 3 files changed, 325 insertions(+) create mode 100644 drivers/spi/davinci_spi.c create mode 100644 drivers/spi/davinci_spi.h diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 824d8e7..f112ed0 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o COBJS-$(CONFIG_CF_SPI) += cf_spi.o +COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c new file mode 100644 index 0000000..ebc7f80 --- /dev/null +++ b/drivers/spi/davinci_spi.c @@ -0,0 +1,223 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Driver for SPI controller on DaVinci. Based on atmel_spi.c + * by Atmel Corporation + * + * Copyright (C) 2007 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include "davinci_spi.h" + +void spi_init() +{ + /* do nothing */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct davinci_spi_slave *ds; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ds = malloc(sizeof(*ds)); + if (!ds) + return NULL; + + ds->slave.bus = bus; + ds->slave.cs = cs; + ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE; + ds->freq = max_hz; + + return &ds->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + + free(ds); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + unsigned int scalar, data1_reg_val = 0; + + /* Enable the SPI hardware */ + writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); + udelay(1000); + writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0); + + /* Set master mode, powered up and not activated */ + writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); + + /* CS, CLK, SIMO and SOMI are functional pins */ + writel((SPIPC0_EN0FUN_MASK | SPIPC0_CLKFUN_MASK | + SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); + + /* setup format */ + scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; + + /* + * Use following format: + * character length = 8, + * clock signal delayed by half clk cycle, + * clock low in idle state - Mode 0, + * MSB shifted out first + */ + writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) | + (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0); + + /* hold cs active at end of transfer until explicitly de-asserted */ + data1_reg_val = (1 << SPIDAT1_CSHOLD_SHIFT) | + (slave->cs << SPIDAT1_CSNR_SHIFT); + writel(data1_reg_val, &ds->regs->dat1); + + /* + * Including a minor delay. No science here. Should be good even with + * no delay + */ + writel((50 << SPI_C2TDELAY_SHIFT) | + (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay); + + /* default chip select register */ + writel(SPIDEF_CSDEF0_MASK, &ds->regs->def); + + /* no interrupts */ + writel(0, &ds->regs->int0); + writel(0, &ds->regs->lvl); + + /* enable SPI */ + writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + + /* Disable the SPI hardware */ + writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + unsigned int len, data1_reg_val = readl(&ds->regs->dat1); + int ret, i; + const u8 *txp = dout; /* dout can be NULL for read operation */ + u8 *rxp = din; /* din can be NULL for write operation */ + + ret = 0; + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + /* + * It's not clear how non-8-bit-aligned transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface - here we terminate on receiving such a + * transfer request. + */ + if (bitlen % 8) { + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + /* do an empty read to clear the current contents */ + readl(&ds->regs->buf); + + /* keep writing and reading 1 byte until done */ + for (i = 0; i < len; i++) { + /* wait till TXFULL is asserted */ + while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK); + + /* write the data */ + data1_reg_val &= ~0xFFFF; + if (txp) { + data1_reg_val |= *txp; + txp++; + } + + /* + * Write to DAT1 is required to keep the serial transfer going. + * We just terminate when we reach the end. + */ + if ((i == (len - 1)) && (flags & SPI_XFER_END)) { + /* clear CS hold */ + writel(data1_reg_val & + ~(1 << SPIDAT1_CSHOLD_SHIFT), &ds->regs->dat1); + } else { + /* enable CS hold */ + data1_reg_val |= ((1 << SPIDAT1_CSHOLD_SHIFT) | + (slave->cs << SPIDAT1_CSNR_SHIFT)); + writel(data1_reg_val, &ds->regs->dat1); + } + + /* read the data - wait for data availability */ + while (readl(&ds->regs->buf) & SPIBUF_RXEMPTY_MASK); + + if (rxp) { + *rxp = readl(&ds->regs->buf) & 0xFF; + rxp++; + } else { + /* simply drop the read character */ + readl(&ds->regs->buf); + } + } + return 0; + +out: + if (flags & SPI_XFER_END) { + writel(data1_reg_val & + ~(1 << SPIDAT1_CSHOLD_SHIFT), &ds->regs->dat1); + } + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* do nothing */ +} + diff --git a/drivers/spi/davinci_spi.h b/drivers/spi/davinci_spi.h new file mode 100644 index 0000000..8d36a42 --- /dev/null +++ b/drivers/spi/davinci_spi.h @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Register definitions for the DaVinci SPI Controller + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DAVINCI_SPI_H_ +#define _DAVINCI_SPI_H_ + +struct davinci_spi_regs { + dv_reg gcr0; /* 0x00 */ + dv_reg gcr1; /* 0x04 */ + dv_reg int0; /* 0x08 */ + dv_reg lvl; /* 0x0c */ + dv_reg flg; /* 0x10 */ + dv_reg pc0; /* 0x14 */ + dv_reg pc1; /* 0x18 */ + dv_reg pc2; /* 0x1c */ + dv_reg pc3; /* 0x20 */ + dv_reg pc4; /* 0x24 */ + dv_reg pc5; /* 0x28 */ + dv_reg rsvd[3]; + dv_reg dat0; /* 0x38 */ + dv_reg dat1; /* 0x3c */ + dv_reg buf; /* 0x40 */ + dv_reg emu; /* 0x44 */ + dv_reg delay; /* 0x48 */ + dv_reg def; /* 0x4c */ + dv_reg fmt0; /* 0x50 */ + dv_reg fmt1; /* 0x54 */ + dv_reg fmt2; /* 0x58 */ + dv_reg fmt3; /* 0x5c */ + dv_reg intvec0; /* 0x60 */ + dv_reg intvec1; /* 0x64 */ +}; + +#define BIT(x) (1 << (x)) + +/* SPIGCR0 */ +#define SPIGCR0_SPIENA_MASK 0x1 +#define SPIGCR0_SPIRST_MASK 0x0 + +/* SPIGCR0 */ +#define SPIGCR1_CLKMOD_MASK BIT(1) +#define SPIGCR1_MASTER_MASK BIT(0) +#define SPIGCR1_SPIENA_MASK BIT(24) + +/* SPIPC0 */ +#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */ +#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */ +#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ +#define SPIPC0_EN0FUN_MASK BIT(0) + +/* SPIFMT0 */ +#define SPIFMT_SHIFTDIR_SHIFT 20 +#define SPIFMT_POLARITY_SHIFT 17 +#define SPIFMT_PHASE_SHIFT 16 +#define SPIFMT_PRESCALE_SHIFT 8 + +/* SPIDAT1 */ +#define SPIDAT1_CSHOLD_SHIFT 28 +#define SPIDAT1_CSNR_SHIFT 16 + +/* SPIDELAY */ +#define SPI_C2TDELAY_SHIFT 24 +#define SPI_T2CDELAY_SHIFT 16 + +/* SPIBUF */ +#define SPIBUF_RXEMPTY_MASK BIT(31) +#define SPIBUF_TXFULL_MASK BIT(29) + +/* SPIDEF */ +#define SPIDEF_CSDEF0_MASK BIT(0) + +struct davinci_spi_slave { + struct spi_slave slave; + struct davinci_spi_regs *regs; + unsigned int freq; +}; + +static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) +{ + return container_of(slave, struct davinci_spi_slave, slave); +} + +#endif /* _DAVINCI_SPI_H_ */ -- cgit v1.1 From 63a47dfd07536e399665ca7504bac512bf21491e Mon Sep 17 00:00:00 2001 From: Nick Thompson Date: Wed, 27 Jan 2010 11:11:28 -0500 Subject: da830evm: Use table driven pin mux configuration Tidyup the pin muxer configuration using the Davinci table driven pinmux configuration function and data tables. Signed-off-by: Nick Thompson Signed-off-by: Sandeep Paulraj --- board/davinci/da830evm/da830evm.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da830evm/da830evm.c index 7cf6013..12df1f8 100644 --- a/board/davinci/da830evm/da830evm.c +++ b/board/davinci/da830evm/da830evm.c @@ -42,34 +42,43 @@ DECLARE_GLOBAL_DATA_PTR; #define pinmux &davinci_syscfg_regs->pinmux -#ifdef CONFIG_SPI_FLASH /* SPI0 pin muxer settings */ -const struct pinmux_config spi0_pins[] = { +static const struct pinmux_config spi0_pins[] = { { pinmux[7], 1, 3 }, { pinmux[7], 1, 4 }, { pinmux[7], 1, 5 }, { pinmux[7], 1, 6 }, { pinmux[7], 1, 7 } }; -#endif /* UART pin muxer settings */ -const struct pinmux_config uart_pins[] = { +static const struct pinmux_config uart_pins[] = { { pinmux[8], 2, 7 }, { pinmux[9], 2, 0 } }; /* I2C pin muxer settings */ -const struct pinmux_config i2c_pins[] = { +static const struct pinmux_config i2c_pins[] = { { pinmux[9], 2, 3 }, { pinmux[9], 2, 4 } }; /* USB0_DRVVBUS pin muxer settings */ -const struct pinmux_config usb_pins[] = { +static const struct pinmux_config usb_pins[] = { { pinmux[9], 1, 1 } }; +static const struct pinmux_resource pinmuxes[] = { +#ifdef CONFIG_SPI_FLASH + PINMUX_ITEM(spi0_pins), +#endif + PINMUX_ITEM(uart_pins), + PINMUX_ITEM(i2c_pins), +#ifdef CONFIG_USB_DA8XX + PINMUX_ITEM(usb_pins), +#endif +}; + int board_init(void) { #ifndef CONFIG_USE_IRQ @@ -112,18 +121,8 @@ int board_init(void) DAVINCI_SYSCFG_SUSPSRC_UART2), &davinci_syscfg_regs->suspsrc); -#ifdef CONFIG_SPI_FLASH - if (davinci_configure_pin_mux(spi0_pins, ARRAY_SIZE(spi0_pins)) != 0) - return 1; -#endif - - if (davinci_configure_pin_mux(uart_pins, ARRAY_SIZE(uart_pins)) != 0) - return 1; - - if (davinci_configure_pin_mux(i2c_pins, ARRAY_SIZE(i2c_pins)) != 0) - return 1; - - if (davinci_configure_pin_mux(usb_pins, ARRAY_SIZE(usb_pins)) != 0) + /* configure pinmux settings */ + if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) return 1; /* enable the console UART */ -- cgit v1.1 From 093d6018cf0a8dae614c2924c0013d97e2a48662 Mon Sep 17 00:00:00 2001 From: Scott Ellis Date: Wed, 27 Jan 2010 11:11:46 -0500 Subject: Overo GPMC registers Use appropriate GPMC timings for the LAN9221 controller on the Gumstix Overo expansion boards not the values in arch-omap3/mem.h which are for a different ethernet controller. Signed-off-by: Scott Ellis Signed-off-by: Sandeep Paulraj --- board/overo/overo.c | 14 +++++++------- board/overo/overo.h | 9 +++++++++ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/board/overo/overo.c b/board/overo/overo.c index f363281..e85be7d 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -100,13 +100,13 @@ static void setup_net_chip(void) struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; /* Configure GPMC registers */ - writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); - writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); - writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); - writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); - writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); - writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); - writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); + writel(NET_LAN9221_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); + writel(NET_LAN9221_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); + writel(NET_LAN9221_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); + writel(NET_LAN9221_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); + writel(NET_LAN9221_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); + writel(NET_LAN9221_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); + writel(NET_LAN9221_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); diff --git a/board/overo/overo.h b/board/overo/overo.h index 4c7ac27..1873523 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -33,6 +33,15 @@ const omap3_sysinfo sysinfo = { #endif }; +/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */ +#define NET_LAN9221_GPMC_CONFIG1 0x00001000 +#define NET_LAN9221_GPMC_CONFIG2 0x00080701 +#define NET_LAN9221_GPMC_CONFIG3 0x00020201 +#define NET_LAN9221_GPMC_CONFIG4 0x08030703 +#define NET_LAN9221_GPMC_CONFIG5 0x00060908 +#define NET_LAN9221_GPMC_CONFIG6 0x87030000 +#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c + /* * IEN - Input Enable * IDIS - Input Disable -- cgit v1.1 From 632e1d9014848ec8d983a629c2e35b4423816336 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Wed, 27 Jan 2010 11:11:55 -0500 Subject: OMAP3 Move declaration of gpmc_cfg. Every omap3 board config file declared the global variable gpmc_cfg. This changes moves the declaration to a better location in the arch dependent header file cpu.h. Signed-off-by: Tom Rix Signed-off-by: Sandeep Paulraj --- include/asm-arm/arch-omap3/cpu.h | 4 ++++ include/configs/devkit8000.h | 1 - include/configs/omap3_beagle.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/omap3_overo.h | 1 - include/configs/omap3_pandora.h | 1 - include/configs/omap3_sdp3430.h | 1 - include/configs/omap3_zoom1.h | 1 - include/configs/omap3_zoom2.h | 1 - 9 files changed, 4 insertions(+), 8 deletions(-) diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index e51c4f3..aa8de32 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -136,6 +136,10 @@ struct gpmc { u32 ecc8_result; /* 0x21C */ u32 ecc9_result; /* 0x220 */ }; + +/* Used for board specific gpmc initialization */ +extern struct gpmc *gpmc_cfg; + #else /* __ASSEMBLY__ */ #define GPMC_CONFIG1 0x00 #define GPMC_CONFIG2 0x04 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index e81da67..7d1332f 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -297,7 +297,6 @@ #define CONFIG_ENV_OFFSET boot_flash_off #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index a8abb0e..08d79ac 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -326,7 +326,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1 #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index a8d4105..0d99f7d 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -330,7 +330,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1 #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index c72fb9d..a43500b 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -295,7 +295,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1 #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index f22fab5..945c053 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -287,7 +287,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1 #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 4d01933..b4919db 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -361,7 +361,6 @@ /*--------------------------------------------------------------------------*/ #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index cdf95c0..ae7ebf9 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -311,7 +311,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1 #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 7a8beb8..c88c732 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -270,7 +270,6 @@ #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) #ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; -- cgit v1.1 From 3843e7dc934d8ef7c592f5a2106885efe32eac7f Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Wed, 27 Jan 2010 11:12:08 -0500 Subject: NetStar: Disable CONFIG_CMD_JFFS2 This patch removes "CONFIG_CMD_JFFS" from the board config Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- include/configs/netstar.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/netstar.h b/include/configs/netstar.h index 20b423b..884dc09 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -149,7 +149,6 @@ #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_LOADB #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NAND @@ -158,8 +157,6 @@ #define CONFIG_CMD_RUN -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ - /* * BOOTP options */ -- cgit v1.1 From 89e94d81eda9af2e1c35e97125b0c049335c70fc Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Wed, 27 Jan 2010 11:12:23 -0500 Subject: NetStar: make crcit utility more readable This patch makes the crcit utility more readable Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- board/netstar/crcit.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c index e0cea9b..0eef41a 100644 --- a/board/netstar/crcit.c +++ b/board/netstar/crcit.c @@ -56,13 +56,14 @@ static int do_crc(char *path, unsigned version) fprintf(stderr, "File too large\n"); return EXIT_FAILURE; } - size = (size + 3) & ~3; /* round up to 4 bytes */ - data[0] = size + 4; /* add size of version field */ + size = (size + 3) & ~3; /* round up to 4 bytes */ + size += 4; /* add size of version field */ + data[0] = size; data[1] = version; - data[2 + (size >> 2)] = crc32(0, (unsigned char *)(data + 1), data[0]); + data[size/4 + 1] = crc32(0, (unsigned char *)(data + 1), size); close(fd); - if (write(STDOUT_FILENO, data, size + 3*4) == -1) { + if (write(STDOUT_FILENO, data, size + 4 /*size*/ + 4 /*crc*/) == -1) { perror("Error writing file"); return EXIT_FAILURE; } -- cgit v1.1 From d798e27b14543762f9f5d0561a3430c7f9e2153b Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Wed, 27 Jan 2010 11:12:28 -0500 Subject: NetStar: Remove debug junk leaked into eeprom utility This patch removes debug junk leaked into eeprom utility. Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- board/netstar/eeprom.c | 8 +-- board/netstar/eeprom_start.S | 166 +------------------------------------------ 2 files changed, 2 insertions(+), 172 deletions(-) diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c index 1366457..adb01b9 100644 --- a/board/netstar/eeprom.c +++ b/board/netstar/eeprom.c @@ -22,8 +22,6 @@ * Some code shamelessly stolen back from Robin Getz. */ -#define DEBUG - #include #include #include @@ -142,8 +140,6 @@ static int parse_element(char *s, unsigned char *buf, int len) return cnt; } -extern int crcek(void); - int eeprom(int argc, char *argv[]) { int i, len, ret; @@ -161,8 +157,6 @@ int eeprom(int argc, char *argv[]) return 1; } - return crcek(); - if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) { printf("SMSC91111 not found.\n"); return 2; @@ -176,7 +170,7 @@ int eeprom(int argc, char *argv[]) /* Print help message */ if (argv[1][1] == 'h') { - printf("VoiceBlue EEPROM writer\n"); + printf("NetStar EEPROM writer\n"); printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); printf("Usage:\n\t [] [<...>]\n"); return 0; diff --git a/board/netstar/eeprom_start.S b/board/netstar/eeprom_start.S index 1306485..3609382 100644 --- a/board/netstar/eeprom_start.S +++ b/board/netstar/eeprom_start.S @@ -8,170 +8,6 @@ */ .globl _start -_start: b eeprom - -#include "crcek.h" - -/** - * do_crc32 - calculate CRC32 of given buffer - * r0 - crc - * r1 - pointer to buffer - * r2 - buffer len - */ - .macro do_crc32 - ldr r5, FFFFFFFF - eor r0, r0, r5 - adr r3, CRC32_TABLE -1: - ldrb r4, [r1], #1 - eor r4, r4, r0 - and r4, r4, #0xff - ldr r4, [r3, r4, lsl#2] - eor r0, r4, r0, lsr#8 - subs r2, r2, #0x1 - bne 1b - eor r0, r0, r5 - .endm - - .macro crcuj, offset, size - ldr r1, \offset - ldr r2, [r1] - cmp r2, #0 @ no data, no problem - beq 2f - mov r7, #1 - tst r2, #3 @ unaligned size - bne 2f - mov r7, #2 - ldr r0, \size - cmp r2, r0 @ bogus size - bhi 2f - mov r7, #3 - add r1, r1, #4 - mov r0, #0 - do_crc32 - ldr r1, [r1] -2: - cmp r0, r1 - .endm - - .macro wait, reg - mov \reg, #0x1000 -3: - subs \reg, \reg, #0x1 - bne 3b - - .endm -.text -.globl crcek -crcek: - mov r6, #0 -@ crcuj _LOADER1_OFFSET, _LOADER_SIZE -@ bne crc1_bad -@ orr r6, r6, #1 -crc1_bad: - crcuj _LOADER2_OFFSET, _LOADER_SIZE - bne crc2_bad - orr r6, r6, #2 -crc2_bad: -@ mov r0, r6 - mov pc, lr - ldr r3, _LOADER1_OFFSET - ldr r4, _LOADER2_OFFSET - tst r6, #3 - beq one_is_bad @ one of them (or both) has bad crc - ldr r1, [r3, #4] - ldr r2, [r4, #4] - cmp r1, r2 @ boot 2nd loader if versions differ - beq boot_1st - b boot_2nd -one_is_bad: - tst r6, #1 - bne boot_1st - tst r6, #2 - bne boot_2nd -@ We are doomed, so let user know. - ldr r0, GPIO_BASE @ configure GPIO pins - ldr r1, GPIO_DIRECTION - strh r1, [r0, #0x08] -blink_loop: - mov r1, #0x08 - strh r1, [r0, #0x04] - wait r3 - mov r1, #0x10 - strh r1, [r0, #0x04] - wait r3 - b blink_loop -boot_1st: - add pc, r3, #8 -boot_2nd: - add pc, r4, #8 - -_LOADER_SIZE: - .word LOADER_SIZE - 8 @ minus size and crc32 -_LOADER1_OFFSET: - .word LOADER1_OFFSET -_LOADER2_OFFSET: - .word LOADER2_OFFSET - -FFFFFFFF: - .word 0xffffffff -CRC32_TABLE: - .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 - .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 - .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 - .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de - .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 - .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 - .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 - .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b - .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 - .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a - .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 - .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 - .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 - .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f - .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e - .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 - .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed - .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 - .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 - .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 - .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a - .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 - .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 - .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f - .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 - .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 - .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 - .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 - .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 - .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb - .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a - .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 - .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 - .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c - .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef - .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 - .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe - .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 - .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c - .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 - .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b - .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 - .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 - .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c - .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 - .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 - .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 - .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 - .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 - .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 - .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b - .word 0x2d02ef8d - -GPIO_BASE: - .word 0xfffce000 -GPIO_DIRECTION: - .word 0x0000ffe7 +_start: b eeprom .end -- cgit v1.1 From cf3c142ee4be0f077f8b84593f1b24b35d14039e Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 1 Feb 2010 21:29:48 +0100 Subject: Add support for EDB93xx boards Added support for the following EDB93xx boards: EDB9301 EDB9302 EDB9302A EDB9307 EDB9307A EDB93012 EDB9315 EDB9315A Signed-off-by: Matthias Kaehlcke --- MAINTAINERS | 10 ++ MAKEALL | 8 ++ Makefile | 10 ++ board/edb93xx/Makefile | 50 ++++++++ board/edb93xx/config.mk | 33 ++++++ board/edb93xx/early_udelay.h | 34 ++++++ board/edb93xx/edb93xx.c | 104 +++++++++++++++++ board/edb93xx/flash_cfg.c | 38 ++++++ board/edb93xx/pll_cfg.c | 58 ++++++++++ board/edb93xx/pll_cfg.h | 72 ++++++++++++ board/edb93xx/sdram_cfg.c | 123 ++++++++++++++++++++ board/edb93xx/sdram_cfg.h | 144 +++++++++++++++++++++++ include/configs/edb93xx.h | 270 +++++++++++++++++++++++++++++++++++++++++++ 13 files changed, 954 insertions(+) create mode 100644 board/edb93xx/Makefile create mode 100644 board/edb93xx/config.mk create mode 100644 board/edb93xx/early_udelay.h create mode 100644 board/edb93xx/edb93xx.c create mode 100644 board/edb93xx/flash_cfg.c create mode 100644 board/edb93xx/pll_cfg.c create mode 100644 board/edb93xx/pll_cfg.h create mode 100644 board/edb93xx/sdram_cfg.c create mode 100644 board/edb93xx/sdram_cfg.h create mode 100644 include/configs/edb93xx.h diff --git a/MAINTAINERS b/MAINTAINERS index 5ad055e..05bb396 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -597,6 +597,16 @@ Gary Jennejohn smdk2400 ARM920T trab ARM920T +Matthias Kaehlcke + edb9301 ARM920T (EP9301) + edb9302 ARM920T (EP9302) + edb9302a ARM920T (EP9302) + edb9307 ARM920T (EP9307) + edb9307a ARM920T (EP9307) + edb9312 ARM920T (EP9312) + edb9315 ARM920T (EP9315) + edb9315a ARM920T (EP9315) + Konstantin Kletschke scb9328 ARM920T diff --git a/MAKEALL b/MAKEALL index f461cd5..dec9212 100755 --- a/MAKEALL +++ b/MAKEALL @@ -555,6 +555,14 @@ LIST_ARM9=" \ cp946es \ cp966 \ da830evm \ + edb9301 \ + edb9302 \ + edb9302a \ + edb9307 \ + edb9307a \ + edb9312 \ + edb9315 \ + edb9315a \ imx27lite \ lpd7a400 \ mv88f6281gtw_ge \ diff --git a/Makefile b/Makefile index c4402c2..8ce248d 100644 --- a/Makefile +++ b/Makefile @@ -2413,6 +2413,16 @@ caddy2_config \ vme8349_config: unconfig @$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd +edb9301_config \ +edb9302_config \ +edb9302a_config \ +edb9307_config \ +edb9307a_config \ +edb9312_config \ +edb9315_config \ +edb9315a_config: unconfig + @$(MKCONFIG) -t $(@:_config=) edb93xx arm arm920t edb93xx NULL ep93xx + ######################################################################### ## MPC85xx Systems ######################################################################### diff --git a/board/edb93xx/Makefile b/board/edb93xx/Makefile new file mode 100644 index 0000000..e2e2636 --- /dev/null +++ b/board/edb93xx/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/edb93xx/config.mk b/board/edb93xx/config.mk new file mode 100644 index 0000000..b2fc6fa --- /dev/null +++ b/board/edb93xx/config.mk @@ -0,0 +1,33 @@ +LDSCRIPT := $(SRCTREE)/cpu/arm920t/ep93xx/u-boot.lds + +ifdef CONFIG_EDB9301 +TEXT_BASE = 0x05700000 +endif + +ifdef CONFIG_EDB9302 +TEXT_BASE = 0x05700000 +endif + +ifdef CONFIG_EDB9302A +TEXT_BASE = 0xc5700000 +endif + +ifdef CONFIG_EDB9307 +TEXT_BASE = 0x01f00000 +endif + +ifdef CONFIG_EDB9307A +TEXT_BASE = 0xc1f00000 +endif + +ifdef CONFIG_EDB9312 +TEXT_BASE = 0x01f00000 +endif + +ifdef CONFIG_EDB9315 +TEXT_BASE = 0x01f00000 +endif + +ifdef CONFIG_EDB9315A +TEXT_BASE = 0xc1f00000 +endif diff --git a/board/edb93xx/early_udelay.h b/board/edb93xx/early_udelay.h new file mode 100644 index 0000000..3b26b3f --- /dev/null +++ b/board/edb93xx/early_udelay.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* delay execution before timers are initialized */ +static inline void early_udelay(uint32_t usecs) +{ + /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */ + register uint32_t loops = (usecs * 1000) / 20; + + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} diff --git a/board/edb93xx/edb93xx.c b/board/edb93xx/edb93xx.c new file mode 100644 index 0000000..4df2246 --- /dev/null +++ b/board/edb93xx/edb93xx.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke + * + * (C) Copyright 2002 2003 + * Network Audio Technologies, Inc. + * Adam Bezanson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MAX_BANK_SIZE 0x04000000 /* 64 MB */ + +static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = { + PHYS_SDRAM_1, +#ifdef PHYS_SDRAM_2 + PHYS_SDRAM_2, +#endif +#ifdef PHYS_SDRAM_3 + PHYS_SDRAM_3, +#endif +#ifdef PHYS_SDRAM_4 + PHYS_SDRAM_4 +#endif +}; + +int board_init(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + + icache_enable(); + +#ifdef USE_920T_MMU + dcache_enable(); +#endif + + /* + * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of + * 14.7456/2 MHz + */ + uint32_t value = readl(&syscon->pwrcnt); + value |= SYSCON_PWRCNT_UART_BAUD; + writel(value, &syscon->pwrcnt); + + /* Machine number, as defined in linux/arch/arm/tools/mach-types */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* We have a console */ + gd->have_console = 1; + + return 0; +} + +int board_eth_init(bd_t *bd) +{ + return ep93xx_eth_initialize(0, MAC_BASE); +} + +int dram_init(void) +{ + unsigned int *src, *dst; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + const ulong bank_size = get_ram_size((long *)bank_addr[i], + MAX_BANK_SIZE); + if (bank_size) { + gd->bd->bi_dram[i].start = bank_addr[i]; + gd->bd->bi_dram[i].size = bank_size; + } + } + + /* copy exception vectors */ + src = (unsigned int *)_armboot_start; + dst = (unsigned int *)PHYS_SDRAM_1; + memcpy(dst, src, 16 * sizeof(unsigned int)); + + return 0; +} diff --git a/board/edb93xx/flash_cfg.c b/board/edb93xx/flash_cfg.c new file mode 100644 index 0000000..a4c2048 --- /dev/null +++ b/board/edb93xx/flash_cfg.c @@ -0,0 +1,38 @@ +/* + * Flash setup for Cirrus edb93xx boards + * + * Copyright (C) 2009 Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \ + SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \ + 1 << SMC_BCR_MW_SHIFT) + +void flash_cfg(void) +{ + struct smc_regs *smc = (struct smc_regs *)SMC_BASE; + + writel(SMC_BCR6_VALUE, &smc->bcr6); +} diff --git a/board/edb93xx/pll_cfg.c b/board/edb93xx/pll_cfg.c new file mode 100644 index 0000000..a687af0 --- /dev/null +++ b/board/edb93xx/pll_cfg.c @@ -0,0 +1,58 @@ +/* + * PLL setup for Cirrus edb93xx boards + * + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2006 Dominic Rath + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "pll_cfg.h" +#include "early_udelay.h" + +void pll_cfg(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + + /* setup PLL1 */ + writel(CLKSET1_VAL, &syscon->clkset1); + + /* + * flush the pipeline + * writing to CLKSET1 causes the EP93xx to enter standby for between + * 8 ms to 16 ms, until PLL1 stabilizes + */ + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + + /* setup PLL2 */ + writel(CLKSET2_VAL, &syscon->clkset2); + + /* + * the user's guide recommends to wait at least 1 ms for PLL2 to + * stabilize + */ + early_udelay(1000); +} diff --git a/board/edb93xx/pll_cfg.h b/board/edb93xx/pll_cfg.h new file mode 100644 index 0000000..0b6f469 --- /dev/null +++ b/board/edb93xx/pll_cfg.h @@ -0,0 +1,72 @@ +/* + * PLL register values for Cirrus edb93xx boards + * + * Copyright (C) 2009 Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ + defined(CONFIG_EDB9302A) +/* + * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2 + * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000, + * pll1_x2: 331776000.000000, pll1_out: 331776000.000000 + */ +#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ + 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ + 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ + 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \ + 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ + SYSCON_CLKSET1_NBYP1 | \ + 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) +#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \ + defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \ + defined(CONFIG_EDB9315A) +/* + * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2 + * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000, + * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000 + */ +#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ + 30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ + 20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ + 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \ + 2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ + SYSCON_CLKSET1_NBYP1 | \ + 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) +#else +#error "Undefined board" +#endif + +/* + * usb_div: 4, nbyp2: 1, pll2_en: 1 + * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000, + * pll2_x2: 384000000.000000, pll2_out: 192000000.000000 + */ +#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ + 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ + 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ + 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \ + SYSCON_CLKSET2_PLL2_EN | \ + SYSCON_CLKSET2_NBYP2 | \ + 3 << SYSCON_CLKSET2_USB_DIV_SHIFT) diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c new file mode 100644 index 0000000..6155f0e --- /dev/null +++ b/board/edb93xx/sdram_cfg.c @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2006 Dominic Rath + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "sdram_cfg.h" +#include "early_udelay.h" + +#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \ + (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL)) + +#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \ + (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) + +static void force_precharge(void); +static void setup_refresh_timer(void); +static void program_mode_registers(void); + +void sdram_cfg(void) +{ + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; + + writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG); + + /* Issue continous NOP commands */ + writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); + + early_udelay(200); + + force_precharge(); + + setup_refresh_timer(); + + program_mode_registers(); + + /* Select normal operation mode */ + writel(GLCONFIG_CKE, &sdram->glconfig); +} + +static void force_precharge(void) +{ + /* + * Errata most EP93xx revisions say that PRECHARGE ALL isn't always + * issued. + * + * Do a read from each bank to make sure they're precharged + */ + + PRECHARGE_BANK(0); + PRECHARGE_BANK(1); + PRECHARGE_BANK(2); + PRECHARGE_BANK(3); +} + +static void setup_refresh_timer(void) +{ + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; + + /* Load refresh timer with 10 to issue refresh every 10 cycles */ + writel(0x0a, &sdram->refrshtimr); + + /* + * Wait at least 80 clock cycles to provide 8 refresh cycles + * to all SDRAMs + */ + early_udelay(1); + + /* + * Program refresh timer with normal value + * We need 8192 refresh cycles every 64ms + * at 15ns (HCLK >= 66MHz) per cycle: + * 64ms / 8192 = 7.8125us + * 7.8125us / 15ns = 520 (0x208) + */ + /* + * TODO: redboot uses 0x1e0 for the slowest possible device + * but i don't understand how this value is calculated + */ + writel(0x208, &sdram->refrshtimr); +} + +static void program_mode_registers(void) +{ + /* + * The mode registers are programmed by performing a read from each + * SDRAM bank. The value of the address that is read defines the value + * that is written into the mode register + */ + + PROGRAM_MODE_REG(0); + +#if (CONFIG_NR_DRAM_BANKS >= 2) + PROGRAM_MODE_REG(1); +#endif + +#if (CONFIG_NR_DRAM_BANKS >= 3) + PROGRAM_MODE_REG(2); +#endif + +#if (CONFIG_NR_DRAM_BANKS == 4) + PROGRAM_MODE_REG(3); +#endif +} diff --git a/board/edb93xx/sdram_cfg.h b/board/edb93xx/sdram_cfg.h new file mode 100644 index 0000000..757b63c --- /dev/null +++ b/board/edb93xx/sdram_cfg.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2006 Dominic Rath + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define SDRAM_BASE_ADDR PHYS_SDRAM_1 + +#ifdef CONFIG_EDB93XX_SDCS0 +#define SDRAM_DEVCFG_REG devcfg0 +#elif defined(CONFIG_EDB93XX_SDCS3) +#define SDRAM_DEVCFG_REG devcfg3 +#else +#error "SDRAM bank configuration" +#endif + +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ + defined(CONFIG_EDB9302A) +/* + * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM + * + * CLK cycle time min: + * @ CAS latency = 3: 7.5ns + * @ CAS latency = 2: 10ns + * We're running at 66MHz (15ns cycle time) external bus speed (HCLK), + * so it's safe to use CAS latency = 2 + * + * RAS-to-CAS delay min: + * 20ns + * At 15ns cycle time, we use RAS-to-CAS delay = 2 + * + * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear + * as four blocks of 8MB size, instead of eight blocks of 4MB size: + * + * EDB9301/EDB9302: + * + * 0x00000000 - 0x007fffff + * 0x01000000 - 0x017fffff + * 0x04000000 - 0x047fffff + * 0x05000000 - 0x057fffff + * + * + * EDB9302a: + * + * 0xc0000000 - 0xc07fffff + * 0xc1000000 - 0xc17fffff + * 0xc4000000 - 0xc47fffff + * 0xc5000000 - 0xc57fffff + * + * BANKCOUNT = 1: This is a device with four banks + */ + +#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ + SDRAM_DEVCFG_SROMLL | \ + SDRAM_DEVCFG_CASLAT_2 | \ + SDRAM_DEVCFG_RASTOCAS_2 | \ + SDRAM_DEVCFG_EXTBUSWIDTH) + +/* + * 16 bit ext. bus + * + * A[22:09] is output as SYA[13:0] + * CAS latency: 2 + * Burst type: sequential + * Burst length: 8 (required for 16 bit ext. bus) + * SYA[13:0] = 0x0023 + */ +#define SDRAM_MODE_REG_VAL 0x4600 + +#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */ +#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */ +#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */ +#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */ + +#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \ + defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \ + defined(CONFIG_EDB9315A) +/* + * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM + * + * CLK cycle time min: + * @ CAS latency = 3: 7.5ns + * @ CAS latency = 2: 10ns + * We're running at 100MHz (10ns cycle time) external bus speed (HCLK), + * so it's safe to use CAS latency = 2 + * + * RAS-to-CAS delay min: + * 20ns + * At 10ns cycle time, we use RAS-to-CAS delay = 2 + * + * EDB9307, EDB9312, EDB9315: + * + * 0x00000000 - 0x01ffffff + * 0x04000000 - 0x05ffffff + * + * + * EDB9307a, EDB9315a: + * + * 0xc0000000 - 0xc1ffffff + * 0xc4000000 - 0xc5ffffff + */ + +#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ + SDRAM_DEVCFG_SROMLL | \ + SDRAM_DEVCFG_CASLAT_2 | \ + SDRAM_DEVCFG_RASTOCAS_2) + +/* + * 32 bit ext. bus + * + * A[23:10] is output as SYA[13:0] + * CAS latency: 2 + * Burst type: sequential + * Burst length: 4 + * SYA[13:0] = 0x0022 + */ +#define SDRAM_MODE_REG_VAL 0x8800 + +#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */ +#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */ +#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */ +#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */ +#endif diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h new file mode 100644 index 0000000..4b00391 --- /dev/null +++ b/include/configs/edb93xx.h @@ -0,0 +1,270 @@ +/* + * U-boot - Configuration file for Cirrus Logic EDB93xx boards + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_MK_edb9301 +#define CONFIG_EDB9301 +#elif defined(CONFIG_MK_edb9302) +#define CONFIG_EDB9302 +#elif defined(CONFIG_MK_edb9302a) +#define CONFIG_EDB9302A +#elif defined(CONFIG_MK_edb9307) +#define CONFIG_EDB9307 +#elif defined(CONFIG_MK_edb9307a) +#define CONFIG_EDB9307A +#elif defined(CONFIG_MK_edb9312) +#define CONFIG_EDB9312 +#elif defined(CONFIG_MK_edb9315) +#define CONFIG_EDB9315 +#elif defined(CONFIG_MK_edb9315a) +#define CONFIG_EDB9315A +#else +#error "no board defined" +#endif + +/* Initial environment and monitor configuration options. */ +#define CONFIG_BOOTDELAY 2 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp" +#define CONFIG_BOOTFILE "edb93xx.img" + +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#ifdef CONFIG_EDB9301 +#define CONFIG_EP9301 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301 +#define CONFIG_SYS_PROMPT "EDB9301> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9302) +#define CONFIG_EP9302 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302 +#define CONFIG_SYS_PROMPT "EDB9302> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9302A) +#define CONFIG_EP9302 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A +#define CONFIG_SYS_PROMPT "EDB9302A> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9307) +#define CONFIG_EP9307 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307 +#define CONFIG_SYS_PROMPT "EDB9307> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9307A) +#define CONFIG_EP9307 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A +#define CONFIG_SYS_PROMPT "EDB9307A> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9312) +#define CONFIG_EP9312 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312 +#define CONFIG_SYS_PROMPT "EDB9312> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9315) +#define CONFIG_EP9315 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315 +#define CONFIG_SYS_PROMPT "EDB9315> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9315A) +#define CONFIG_EP9315 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A +#define CONFIG_SYS_PROMPT "EDB9315A> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#else +#error "no board defined" +#endif + +/* High-level configuration options */ +#define CONFIG_ARM920T 1 /* This is an ARM920T core... */ +#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */ + +#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ +#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */ +#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ + +/* Monitor configuration */ +#include +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#undef CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 + +#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +/* Print buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +/* Boot argument buffer size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ + +/* Serial port hardware configuration */ +#define CONFIG_PL010_SERIAL +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_SERIAL0 0x808C0000 +#define CONFIG_SYS_SERIAL1 0x808D0000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} + +/* Status LED */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 +#define STATUS_LED_GREEN 0 +#define STATUS_LED_RED 1 +/* Green */ +#define STATUS_LED_BIT STATUS_LED_GREEN +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +/* Red */ +#define STATUS_LED_BIT1 STATUS_LED_RED +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* Optional value */ +#define STATUS_LED_BOOT STATUS_LED_BIT + +/* Network hardware configuration */ +#define CONFIG_DRIVER_EP93XX_MAC +#define CONFIG_MII_SUPPRESS_PREAMBLE +#define CONFIG_MII +#define CONFIG_PHY_ADDR 1 +#define CONFIG_NET_MULTI +#undef CONFIG_NETCONSOLE + +/* SDRAM configuration */ +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) +/* + * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + */ +#define CONFIG_NR_DRAM_BANKS 4 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_SIZE_1 0x00800000 +#define PHYS_SDRAM_2 0x01000000 +#define PHYS_SDRAM_SIZE_2 0x00800000 +#define PHYS_SDRAM_3 0x04000000 +#define PHYS_SDRAM_SIZE_3 0x00800000 +#define PHYS_SDRAM_4 0x05000000 +#define PHYS_SDRAM_SIZE_4 0x00800000 +#define CONFIG_EDB93XX_SDCS3 +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x007fffff + +#elif defined(CONFIG_EDB9302A) +/* + * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + */ +#define CONFIG_NR_DRAM_BANKS 4 +#define PHYS_SDRAM_1 0xc0000000 +#define PHYS_SDRAM_SIZE_1 0x00800000 +#define PHYS_SDRAM_2 0xc1000000 +#define PHYS_SDRAM_SIZE_2 0x00800000 +#define PHYS_SDRAM_3 0xc4000000 +#define PHYS_SDRAM_SIZE_3 0x00800000 +#define PHYS_SDRAM_4 0xc5000000 +#define PHYS_SDRAM_SIZE_4 0x00800000 +#define CONFIG_EDB93XX_SDCS0 +#define CONFIG_SYS_MEMTEST_START 0xc0100000 +#define CONFIG_SYS_MEMTEST_END 0xc07fffff + +#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \ + defined(CONFIG_EDB9315) +/* + * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of + * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of + * 64 MB of SDRAM. + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_SIZE_1 0x02000000 +#define PHYS_SDRAM_2 0x04000000 +#define PHYS_SDRAM_SIZE_2 0x02000000 +#define CONFIG_EDB93XX_SDCS3 +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x01e00000 + +#elif defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A) +/* + * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung + * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM. + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 0xc0000000 +#define PHYS_SDRAM_SIZE_1 0x02000000 +#define PHYS_SDRAM_2 0xc4000000 +#define PHYS_SDRAM_SIZE_2 0x02000000 +#define CONFIG_EDB93XX_SDCS0 +#define CONFIG_SYS_MEMTEST_START 0xc0100000 +#define CONFIG_SYS_MEMTEST_END 0xc1e00000 +#endif + +/* Default load address */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x01000000) + +/* Must match kernel config */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) + +/* Run-time memory allocatons */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_STACKSIZE (128 * 1024) + +#if defined(CONFIG_USE_IRQ) +#define CONFIG_STACKSIZE_IRQ (4 * 1024) +#define CONFIG_STACKSIZE_FIQ (4 * 1024) +#endif + +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) + +/* ----------------------------------------------------------------------------- + * FLASH and environment organization + * + * The EDB9301 and EDB9302(a) have 1 bank of flash memory at 0x60000000 + * consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus, + * for a total of 16 MB of CFI-compatible flash. + * + * The EDB9307(a), EDB9312, and EDB9315(a) have 1 bank of flash memory at + * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit + * data bus, for a total of 32 MB of CFI-compatible flash. + * + * EDB9301/02(a) EDB9307(a)/12/15(a) + * 0x60000000 - 0x0003FFFF u-boot u-boot + * 0x60040000 - 0x0005FFFF environment #1 environment #1 + * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued) + * 0x60080000 - 0x0009FFFF unused environment #2 + * 0x600A0000 - 0x000BFFFF unused environment #2 (continued) + * 0x600C0000 - 0x00FFFFFF unused unused + * 0x61000000 - 0x01FFFFFF not present unused + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +#define PHYS_FLASH_1 0x60000000 +#define CONFIG_SYS_FLASH_BASE (PHYS_FLASH_1) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR 0x60040000 + +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) + +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#endif /* !defined (__CONFIG_H) */ -- cgit v1.1 From fcfb632bd1e9de645b015cf73a78183c299743d8 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 1 Feb 2010 21:29:39 +0100 Subject: ARM: Add support for EP93xx SoCs Add support for the Cirrus EP93xx platform Signed-off-by: Matthias Kaehlcke Acked-by: Tom --- cpu/arm920t/ep93xx/Makefile | 56 ++++ cpu/arm920t/ep93xx/cpu.c | 51 +++ cpu/arm920t/ep93xx/led.c | 101 ++++++ cpu/arm920t/ep93xx/lowlevel_init.S | 65 ++++ cpu/arm920t/ep93xx/speed.c | 110 +++++++ cpu/arm920t/ep93xx/timer.c | 168 ++++++++++ cpu/arm920t/ep93xx/u-boot.lds | 59 ++++ include/asm-arm/arch-ep93xx/ep93xx.h | 595 +++++++++++++++++++++++++++++++++++ include/common.h | 3 +- 9 files changed, 1207 insertions(+), 1 deletion(-) create mode 100644 cpu/arm920t/ep93xx/Makefile create mode 100644 cpu/arm920t/ep93xx/cpu.c create mode 100644 cpu/arm920t/ep93xx/led.c create mode 100644 cpu/arm920t/ep93xx/lowlevel_init.S create mode 100644 cpu/arm920t/ep93xx/speed.c create mode 100644 cpu/arm920t/ep93xx/timer.c create mode 100644 cpu/arm920t/ep93xx/u-boot.lds create mode 100644 include/asm-arm/arch-ep93xx/ep93xx.h diff --git a/cpu/arm920t/ep93xx/Makefile b/cpu/arm920t/ep93xx/Makefile new file mode 100644 index 0000000..30e12af --- /dev/null +++ b/cpu/arm920t/ep93xx/Makefile @@ -0,0 +1,56 @@ +# +# Cirrus Logic EP93xx CPU-specific Makefile +# +# Copyright (C) 2009 Matthias Kaehlcke +# +# Copyright (C) 2004, 2005 +# Cory T. Tusar, Videon Central, Inc., +# +# Copyright (C) 2006 +# Dominic Rath +# +# Based on an original Makefile, which is +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 675 Mass Ave, Cambridge, MA 02139, USA. +# +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = cpu.o led.o speed.o timer.o +SOBJS = lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/cpu/arm920t/ep93xx/cpu.c b/cpu/arm920t/ep93xx/cpu.c new file mode 100644 index 0000000..1abb9c6 --- /dev/null +++ b/cpu/arm920t/ep93xx/cpu.c @@ -0,0 +1,51 @@ +/* + * Cirrus Logic EP93xx CPU-specific support. + * + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */ +extern void reset_cpu(ulong addr) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + uint32_t value; + + /* Unlock DeviceCfg and set SWRST */ + writel(0xAA, &syscon->sysswlock); + value = readl(&syscon->devicecfg); + value |= SYSCON_DEVICECFG_SWRST; + writel(value, &syscon->devicecfg); + + /* Unlock DeviceCfg and clear SWRST */ + writel(0xAA, &syscon->sysswlock); + value = readl(&syscon->devicecfg); + value &= ~SYSCON_DEVICECFG_SWRST; + writel(value, &syscon->devicecfg); + + /* Dying... */ + while (1) + ; /* noop */ +} diff --git a/cpu/arm920t/ep93xx/led.c b/cpu/arm920t/ep93xx/led.c new file mode 100644 index 0000000..7e2c897 --- /dev/null +++ b/cpu/arm920t/ep93xx/led.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2010, 2009 Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; +static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN, + 1 << STATUS_LED_RED}; + +inline void switch_LED_on(uint8_t led) +{ + register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; + + writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr); + saved_state[led] = STATUS_LED_ON; +} + +inline void switch_LED_off(uint8_t led) +{ + register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; + + writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr); + saved_state[led] = STATUS_LED_OFF; +} + +void red_LED_on(void) +{ + switch_LED_on(STATUS_LED_RED); +} + +void red_LED_off(void) +{ + switch_LED_off(STATUS_LED_RED); +} + +void green_LED_on(void) +{ + switch_LED_on(STATUS_LED_GREEN); +} + +void green_LED_off(void) +{ + switch_LED_off(STATUS_LED_GREEN); +} + +void __led_init(led_id_t mask, int state) +{ + __led_set(mask, state); +} + +void __led_toggle(led_id_t mask) +{ + if (STATUS_LED_RED == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_RED]) + red_LED_off(); + else + red_LED_on(); + } else if (STATUS_LED_GREEN == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN]) + green_LED_off(); + else + green_LED_on(); + } +} + +void __led_set(led_id_t mask, int state) +{ + if (STATUS_LED_RED == mask) { + if (STATUS_LED_ON == state) + red_LED_on(); + else + red_LED_off(); + } else if (STATUS_LED_GREEN == mask) { + if (STATUS_LED_ON == state) + green_LED_on(); + else + green_LED_off(); + } +} diff --git a/cpu/arm920t/ep93xx/lowlevel_init.S b/cpu/arm920t/ep93xx/lowlevel_init.S new file mode 100644 index 0000000..a20ec89 --- /dev/null +++ b/cpu/arm920t/ep93xx/lowlevel_init.S @@ -0,0 +1,65 @@ +/* + * Low-level initialization for EP93xx + * + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2006 Dominic Rath + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +.globl lowlevel_init +lowlevel_init: + /* backup return address */ + ldr r1, =SYSCON_SCRATCH0 + str lr, [r1] + + /* Turn on both LEDs */ + bl red_LED_on + bl green_LED_on + + /* Configure flash wait states before we switch to the PLL */ + bl flash_cfg + + /* Set up PLL */ + bl pll_cfg + + /* Turn off the Green LED and leave the Red LED on */ + bl green_LED_off + + /* Setup SDRAM */ + bl sdram_cfg + + /* Turn on Green LED, Turn off the Red LED */ + bl green_LED_on + bl red_LED_off + + /* FIXME: we use async mode for now */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0xc0000000 + mcr p15, 0, r0, c1, c0, 0 + + /* restore return address */ + ldr r1, =SYSCON_SCRATCH0 + ldr lr, [r1] + + mov pc, lr diff --git a/cpu/arm920t/ep93xx/speed.c b/cpu/arm920t/ep93xx/speed.c new file mode 100644 index 0000000..c83a3bb --- /dev/null +++ b/cpu/arm920t/ep93xx/speed.c @@ -0,0 +1,110 @@ +/* + * Cirrus Logic EP93xx PLL support. + * + * Copyright (C) 2009 Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +/* + * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. + * + * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of + * the specified bus in HZ. + */ + +/* + * return the PLL output frequency + * + * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1) + * / (X2IPD + 1) / 2^PS + */ +static ulong get_PLLCLK(uint32_t *pllreg) +{ + uint8_t i; + const uint32_t clkset = readl(pllreg); + uint64_t rate = CONFIG_SYS_CLK_FREQ; + rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; + rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; + do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ + for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) + rate >>= 1; + + return (ulong)rate; +} + +/* return FCLK frequency */ +ulong get_FCLK() +{ + const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + + const uint32_t clkset1 = readl(&syscon->clkset1); + const uint8_t fclk_div = + fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; + const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; + + return fclk_rate; +} + +/* return HCLK frequency */ +ulong get_HCLK(void) +{ + const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + + const uint32_t clkset1 = readl(&syscon->clkset1); + const uint8_t hclk_div = + hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; + const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; + + return hclk_rate; +} + +/* return PCLK frequency */ +ulong get_PCLK(void) +{ + const uint8_t pclk_divisors[] = { 1, 2, 4, 8 }; + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + + const uint32_t clkset1 = readl(&syscon->clkset1); + const uint8_t pclk_div = + pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; + const ulong pclk_rate = get_HCLK() / pclk_div; + + return pclk_rate; +} + +/* return UCLK frequency */ +ulong get_UCLK(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + ulong uclk_rate; + + const uint32_t value = readl(&syscon->pwrcnt); + if (value & SYSCON_PWRCNT_UART_BAUD) + uclk_rate = CONFIG_SYS_CLK_FREQ; + else + uclk_rate = CONFIG_SYS_CLK_FREQ / 2; + + return uclk_rate; +} diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c new file mode 100644 index 0000000..6d969d9 --- /dev/null +++ b/cpu/arm920t/ep93xx/timer.c @@ -0,0 +1,168 @@ +/* + * Cirrus Logic EP93xx timer support. + * + * Copyright (C) 2009, 2010 + * Matthias Kaehlcke + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support, + * author unknown. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +#define TIMER_CLKSEL (1 << 3) +#define TIMER_MODE (1 << 6) +#define TIMER_ENABLE (1 << 7) + +#define TIMER_FREQ 508469 +#define TIMER_LOAD_VAL (TIMER_FREQ / CONFIG_SYS_HZ) + +static ulong timestamp; +static ulong lastdec; + +static inline unsigned long clk_to_systicks(unsigned long clk_ticks) +{ + unsigned long sys_ticks = (clk_ticks * CONFIG_SYS_HZ) / TIMER_FREQ; + + return sys_ticks; +} + +static inline unsigned long usecs_to_ticks(unsigned long usecs) +{ + unsigned long ticks; + + if (usecs >= 1000) { + ticks = usecs / 1000; + ticks *= (TIMER_LOAD_VAL * CONFIG_SYS_HZ); + ticks /= 1000; + } else { + ticks = usecs * TIMER_LOAD_VAL * CONFIG_SYS_HZ; + ticks /= (1000 * 1000); + } + + return ticks; +} + +static inline unsigned long read_timer(void) +{ + struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; + + return readl(&timer->timer3.value); +} + +/* + * timer without interrupts + */ +unsigned long long get_ticks(void) +{ + const unsigned long now = read_timer(); + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + + lastdec = now; + + return timestamp; +} + +unsigned long get_timer_masked(void) +{ + return clk_to_systicks(get_ticks()); +} + +unsigned long get_timer(unsigned long base) +{ + return get_timer_masked() - base; +} + +void reset_timer_masked(void) +{ + lastdec = read_timer(); + timestamp = 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +void set_timer(unsigned long t) +{ + timestamp = t; +} + +void __udelay(unsigned long usec) +{ + const unsigned long ticks = usecs_to_ticks(usec); + const unsigned long target = clk_to_systicks(ticks) + get_timer(0); + + while (get_timer_masked() < target) + /* noop */; +} + +void udelay_masked(unsigned long usec) +{ + const unsigned long ticks = usecs_to_ticks(usec); + const unsigned long target = clk_to_systicks(ticks) + get_timer(0); + + reset_timer_masked(); + + while (get_timer_masked() < target) + /* noop */; +} + +int timer_init(void) +{ + struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; + + /* use timer 3 with 508KHz and free running */ + writel(TIMER_CLKSEL, &timer->timer3.control); + + /* auto load, manual update of Timer 3 */ + lastdec = TIMER_LOAD_VAL; + writel(TIMER_LOAD_VAL, &timer->timer3.load); + + /* Enable the timer and periodic mode */ + writel(TIMER_ENABLE | TIMER_MODE | TIMER_CLKSEL, + &timer->timer3.control); + + reset_timer_masked(); + + return 0; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +unsigned long get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/cpu/arm920t/ep93xx/u-boot.lds b/cpu/arm920t/ep93xx/u-boot.lds new file mode 100644 index 0000000..737c9d8 --- /dev/null +++ b/cpu/arm920t/ep93xx/u-boot.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */ + . = 0x1000; + LONG(0x53555243) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/include/asm-arm/arch-ep93xx/ep93xx.h b/include/asm-arm/arch-ep93xx/ep93xx.h new file mode 100644 index 0000000..6cafe54 --- /dev/null +++ b/include/asm-arm/arch-ep93xx/ep93xx.h @@ -0,0 +1,595 @@ +/* + * Cirrus Logic EP93xx register definitions. + * + * Copyright (C) 2009 + * Matthias Kaehlcke + * + * Copyright (C) 2006 + * Dominic Rath + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is + * + * Copyright (C) 2004 Ray Lehtiniemi + * Copyright (C) 2003 Cirrus Logic, Inc + * Copyright (C) 1999 ARM Limited. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#define EP93XX_AHB_BASE 0x80000000 +#define EP93XX_APB_BASE 0x80800000 + +/* + * 0x80000000 - 0x8000FFFF: DMA + */ +#define DMA_OFFSET 0x000000 +#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET) + +#ifndef __ASSEMBLY__ +struct dma_channel { + uint32_t control; + uint32_t interrupt; + uint32_t ppalloc; + uint32_t status; + uint32_t reserved0; + uint32_t remain; + uint32_t reserved1[2]; + uint32_t maxcnt0; + uint32_t base0; + uint32_t current0; + uint32_t reserved2; + uint32_t maxcnt1; + uint32_t base1; + uint32_t current1; + uint32_t reserved3; +}; + +struct dma_regs { + struct dma_channel m2p_channel_0; + struct dma_channel m2p_channel_1; + struct dma_channel m2p_channel_2; + struct dma_channel m2p_channel_3; + struct dma_channel m2m_channel_0; + struct dma_channel m2m_channel_1; + struct dma_channel reserved0[2]; + struct dma_channel m2p_channel_5; + struct dma_channel m2p_channel_4; + struct dma_channel m2p_channel_7; + struct dma_channel m2p_channel_6; + struct dma_channel m2p_channel_9; + struct dma_channel m2p_channel_8; + uint32_t channel_arbitration; + uint32_t reserved[15]; + uint32_t global_interrupt; +}; +#endif + +/* + * 0x80010000 - 0x8001FFFF: Ethernet MAC + */ +#define MAC_OFFSET 0x010000 +#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET) + +#ifndef __ASSEMBLY__ +struct mac_queue { + uint32_t badd; + union { /* deal with half-word aligned registers */ + uint32_t blen; + union { + uint16_t filler; + uint16_t curlen; + }; + }; + uint32_t curadd; +}; + +struct mac_regs { + uint32_t rxctl; + uint32_t txctl; + uint32_t testctl; + uint32_t reserved0; + uint32_t miicmd; + uint32_t miidata; + uint32_t miists; + uint32_t reserved1; + uint32_t selfctl; + uint32_t inten; + uint32_t intstsp; + uint32_t intstsc; + uint32_t reserved2[2]; + uint32_t diagad; + uint32_t diagdata; + uint32_t gt; + uint32_t fct; + uint32_t fcf; + uint32_t afp; + union { + struct { + uint32_t indad; + uint32_t indad_upper; + }; + uint32_t hashtbl; + }; + uint32_t reserved3[2]; + uint32_t giintsts; + uint32_t giintmsk; + uint32_t giintrosts; + uint32_t giintfrc; + uint32_t txcollcnt; + uint32_t rxmissnct; + uint32_t rxruntcnt; + uint32_t reserved4; + uint32_t bmctl; + uint32_t bmsts; + uint32_t rxbca; + uint32_t reserved5; + struct mac_queue rxdq; + uint32_t rxdqenq; + struct mac_queue rxstsq; + uint32_t rxstsqenq; + struct mac_queue txdq; + uint32_t txdqenq; + struct mac_queue txstsq; + uint32_t reserved6; + uint32_t rxbufthrshld; + uint32_t txbufthrshld; + uint32_t rxststhrshld; + uint32_t txststhrshld; + uint32_t rxdthrshld; + uint32_t txdthrshld; + uint32_t maxfrmlen; + uint32_t maxhdrlen; +}; +#endif + +#define SELFCTL_RWP (1 << 7) +#define SELFCTL_GPO0 (1 << 5) +#define SELFCTL_PUWE (1 << 4) +#define SELFCTL_PDWE (1 << 3) +#define SELFCTL_MIIL (1 << 2) +#define SELFCTL_RESET (1 << 0) + +#define INTSTS_RWI (1 << 30) +#define INTSTS_RXMI (1 << 29) +#define INTSTS_RXBI (1 << 28) +#define INTSTS_RXSQI (1 << 27) +#define INTSTS_TXLEI (1 << 26) +#define INTSTS_ECIE (1 << 25) +#define INTSTS_TXUHI (1 << 24) +#define INTSTS_MOI (1 << 18) +#define INTSTS_TXCOI (1 << 17) +#define INTSTS_RXROI (1 << 16) +#define INTSTS_MIII (1 << 12) +#define INTSTS_PHYI (1 << 11) +#define INTSTS_TI (1 << 10) +#define INTSTS_AHBE (1 << 8) +#define INTSTS_OTHER (1 << 4) +#define INTSTS_TXSQ (1 << 3) +#define INTSTS_RXSQ (1 << 2) + +#define BMCTL_MT (1 << 13) +#define BMCTL_TT (1 << 12) +#define BMCTL_UNH (1 << 11) +#define BMCTL_TXCHR (1 << 10) +#define BMCTL_TXDIS (1 << 9) +#define BMCTL_TXEN (1 << 8) +#define BMCTL_EH2 (1 << 6) +#define BMCTL_EH1 (1 << 5) +#define BMCTL_EEOB (1 << 4) +#define BMCTL_RXCHR (1 << 2) +#define BMCTL_RXDIS (1 << 1) +#define BMCTL_RXEN (1 << 0) + +#define BMSTS_TXACT (1 << 7) +#define BMSTS_TP (1 << 4) +#define BMSTS_RXACT (1 << 3) +#define BMSTS_QID_MASK 0x07 +#define BMSTS_QID_RXDATA 0x00 +#define BMSTS_QID_TXDATA 0x01 +#define BMSTS_QID_RXSTS 0x02 +#define BMSTS_QID_TXSTS 0x03 +#define BMSTS_QID_RXDESC 0x04 +#define BMSTS_QID_TXDESC 0x05 + +#define AFP_MASK 0x07 +#define AFP_IAPRIMARY 0x00 +#define AFP_IASECONDARY1 0x01 +#define AFP_IASECONDARY2 0x02 +#define AFP_IASECONDARY3 0x03 +#define AFP_TX 0x06 +#define AFP_HASH 0x07 + +#define RXCTL_PAUSEA (1 << 20) +#define RXCTL_RXFCE1 (1 << 19) +#define RXCTL_RXFCE0 (1 << 18) +#define RXCTL_BCRC (1 << 17) +#define RXCTL_SRXON (1 << 16) +#define RXCTL_RCRCA (1 << 13) +#define RXCTL_RA (1 << 12) +#define RXCTL_PA (1 << 11) +#define RXCTL_BA (1 << 10) +#define RXCTL_MA (1 << 9) +#define RXCTL_IAHA (1 << 8) +#define RXCTL_IA3 (1 << 3) +#define RXCTL_IA2 (1 << 2) +#define RXCTL_IA1 (1 << 1) +#define RXCTL_IA0 (1 << 0) + +#define TXCTL_DEFDIS (1 << 7) +#define TXCTL_MBE (1 << 6) +#define TXCTL_ICRC (1 << 5) +#define TXCTL_TPD (1 << 4) +#define TXCTL_OCOLL (1 << 3) +#define TXCTL_SP (1 << 2) +#define TXCTL_PB (1 << 1) +#define TXCTL_STXON (1 << 0) + +#define MIICMD_REGAD_MASK (0x001F) +#define MIICMD_PHYAD_MASK (0x03E0) +#define MIICMD_OPCODE_MASK (0xC000) +#define MIICMD_PHYAD_8950 (0x0000) +#define MIICMD_OPCODE_READ (0x8000) +#define MIICMD_OPCODE_WRITE (0x4000) + +#define MIISTS_BUSY (1 << 0) + +/* + * 0x80020000 - 0x8002FFFF: USB OHCI + */ +#define USB_OFFSET 0x020000 +#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET) + +/* + * 0x80030000 - 0x8003FFFF: Raster engine + */ +#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315)) +#define RASTER_OFFSET 0x030000 +#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET) +#endif + +/* + * 0x80040000 - 0x8004FFFF: Graphics accelerator + */ +#if defined(CONFIG_EP9315) +#define GFX_OFFSET 0x040000 +#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET) +#endif + +/* + * 0x80050000 - 0x8005FFFF: Reserved + */ + +/* + * 0x80060000 - 0x8006FFFF: SDRAM controller + */ +#define SDRAM_OFFSET 0x060000 +#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET) + +#ifndef __ASSEMBLY__ +struct sdram_regs { + uint32_t reserved; + uint32_t glconfig; + uint32_t refrshtimr; + uint32_t bootsts; + uint32_t devcfg0; + uint32_t devcfg1; + uint32_t devcfg2; + uint32_t devcfg3; +}; +#endif + +#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2) +#define SDRAM_DEVCFG_BANKCOUNT (1 << 3) +#define SDRAM_DEVCFG_SROMLL (1 << 5) +#define SDRAM_DEVCFG_CASLAT_2 0x00010000 +#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000 + +#define GLCONFIG_INIT (1 << 0) +#define GLCONFIG_MRS (1 << 1) +#define GLCONFIG_SMEMBUSY (1 << 5) +#define GLCONFIG_LCR (1 << 6) +#define GLCONFIG_REARBEN (1 << 7) +#define GLCONFIG_CLKSHUTDOWN (1 << 30) +#define GLCONFIG_CKE (1 << 31) + +/* + * 0x80070000 - 0x8007FFFF: Reserved + */ + +/* + * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA + */ +#define SMC_OFFSET 0x080000 +#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET) + +#ifndef __ASSEMBLY__ +struct smc_regs { + uint32_t bcr0; + uint32_t bcr1; + uint32_t bcr2; + uint32_t bcr3; + uint32_t reserved0[2]; + uint32_t bcr6; + uint32_t bcr7; +#if defined(CONFIG_EP9315) + uint32_t pcattribute; + uint32_t pccommon; + uint32_t pcio; + uint32_t reserved1[5]; + uint32_t pcmciactrl; +#endif +}; +#endif + +#define SMC_BCR_IDCY_SHIFT 0 +#define SMC_BCR_WST1_SHIFT 5 +#define SMC_BCR_BLE (1 << 10) +#define SMC_BCR_WST2_SHIFT 11 +#define SMC_BCR_MW_SHIFT 28 + +/* + * 0x80090000 - 0x8009FFFF: Boot ROM + */ + +/* + * 0x800A0000 - 0x800AFFFF: IDE interface + */ + +/* + * 0x800B0000 - 0x800BFFFF: VIC1 + */ + +/* + * 0x800C0000 - 0x800CFFFF: VIC2 + */ + +/* + * 0x800D0000 - 0x800FFFFF: Reserved + */ + +/* + * 0x80800000 - 0x8080FFFF: Reserved + */ + +/* + * 0x80810000 - 0x8081FFFF: Timers + */ +#define TIMER_OFFSET 0x010000 +#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET) + +#ifndef __ASSEMBLY__ +struct timer { + uint32_t load; + uint32_t value; + uint32_t control; + uint32_t clear; +}; + +struct timer4 { + uint32_t value_low; + uint32_t value_high; +}; + +struct timer_regs { + struct timer timer1; + uint32_t reserved0[4]; + struct timer timer2; + uint32_t reserved1[12]; + struct timer4 timer4; + uint32_t reserved2[6]; + struct timer timer3; +}; +#endif + +/* + * 0x80820000 - 0x8082FFFF: I2S + */ +#define I2S_OFFSET 0x020000 +#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET) + +/* + * 0x80830000 - 0x8083FFFF: Security + */ +#define SECURITY_OFFSET 0x030000 +#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET) + +#define EXTENSIONID (SECURITY_BASE + 0x2714) + +/* + * 0x80840000 - 0x8084FFFF: GPIO + */ +#define GPIO_OFFSET 0x040000 +#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET) + +#ifndef __ASSEMBLY__ +struct gpio_int { + uint32_t inttype1; + uint32_t inttype2; + uint32_t eoi; + uint32_t inten; + uint32_t intsts; + uint32_t rawintsts; + uint32_t db; +}; + +struct gpio_regs { + uint32_t padr; + uint32_t pbdr; + uint32_t pcdr; + uint32_t pddr; + uint32_t paddr; + uint32_t pbddr; + uint32_t pcddr; + uint32_t pdddr; + uint32_t pedr; + uint32_t peddr; + uint32_t reserved0[2]; + uint32_t pfdr; + uint32_t pfddr; + uint32_t pgdr; + uint32_t pgddr; + uint32_t phdr; + uint32_t phddr; + uint32_t reserved1; + uint32_t finttype1; + uint32_t finttype2; + uint32_t reserved2; + struct gpio_int pfint; + uint32_t reserved3[10]; + struct gpio_int paint; + struct gpio_int pbint; + uint32_t eedrive; +}; +#endif + +/* + * 0x80850000 - 0x8087FFFF: Reserved + */ + +/* + * 0x80880000 - 0x8088FFFF: AAC + */ +#define AAC_OFFSET 0x080000 +#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET) + +/* + * 0x80890000 - 0x8089FFFF: Reserved + */ + +/* + * 0x808A0000 - 0x808AFFFF: SPI + */ +#define SPI_OFFSET 0x0A0000 +#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET) + +/* + * 0x808B0000 - 0x808BFFFF: IrDA + */ +#define IRDA_OFFSET 0x0B0000 +#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET) + +/* + * 0x808C0000 - 0x808CFFFF: UART1 + */ +#define UART1_OFFSET 0x0C0000 +#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET) + +/* + * 0x808D0000 - 0x808DFFFF: UART2 + */ +#define UART2_OFFSET 0x0D0000 +#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET) + +/* + * 0x808E0000 - 0x808EFFFF: UART3 + */ +#define UART3_OFFSET 0x0E0000 +#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET) + +/* + * 0x808F0000 - 0x808FFFFF: Key Matrix + */ +#define KEY_OFFSET 0x0F0000 +#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET) + +/* + * 0x80900000 - 0x8090FFFF: Touchscreen + */ +#define TOUCH_OFFSET 0x900000 +#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET) + +/* + * 0x80910000 - 0x8091FFFF: Pulse Width Modulation + */ +#define PWM_OFFSET 0x910000 +#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET) + +/* + * 0x80920000 - 0x8092FFFF: Real time clock + */ +#define RTC_OFFSET 0x920000 +#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET) + +/* + * 0x80930000 - 0x8093FFFF: Syscon + */ +#define SYSCON_OFFSET 0x930000 +#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET) + +#ifndef __ASSEMBLY__ +struct syscon_regs { + uint32_t pwrsts; + uint32_t pwrcnt; + uint32_t halt; + uint32_t stby; + uint32_t reserved0[2]; + uint32_t teoi; + uint32_t stfclr; + uint32_t clkset1; + uint32_t clkset2; + uint32_t reserved1[6]; + uint32_t scratch0; + uint32_t scratch1; + uint32_t reserved2[2]; + uint32_t apbwait; + uint32_t bustmstrarb; + uint32_t bootmodeclr; + uint32_t reserved3[9]; + uint32_t devicecfg; + uint32_t vidclkdiv; + uint32_t mirclkdiv; + uint32_t i2sclkdiv; + uint32_t keytchclkdiv; + uint32_t chipid; + uint32_t syscfg; + uint32_t reserved4[8]; + uint32_t sysswlock; +}; +#else +#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040) +#endif + +#define SYSCON_PWRCNT_UART_BAUD (1 << 29) + +#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0 +#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5 +#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11 +#define SYSCON_CLKSET_PLL_PS_SHIFT 16 +#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18 +#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20 +#define SYSCON_CLKSET1_NBYP1 (1 << 23) +#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25 + +#define SYSCON_CLKSET2_PLL2_EN (1 << 18) +#define SYSCON_CLKSET2_NBYP2 (1 << 19) +#define SYSCON_CLKSET2_USB_DIV_SHIFT 28 + +#define SYSCON_CHIPID_REV_MASK 0xF0000000 +#define SYSCON_DEVICECFG_SWRST (1 << 31) + +/* + * 0x80930000 - 0x8093FFFF: Watchdog Timer + */ +#define WATCHDOG_OFFSET 0x940000 +#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET) + +/* + * 0x80950000 - 0x9000FFFF: Reserved + */ diff --git a/include/common.h b/include/common.h index 0ae5abc..a133e34 100644 --- a/include/common.h +++ b/include/common.h @@ -507,7 +507,8 @@ ulong get_PCI_freq (void); #endif #if defined(CONFIG_S3C24X0) || \ defined(CONFIG_LH7A40X) || \ - defined(CONFIG_S3C6400) + defined(CONFIG_S3C6400) || \ + defined(CONFIG_EP93XX) ulong get_FCLK (void); ulong get_HCLK (void); ulong get_PCLK (void); -- cgit v1.1 From c50a0f503967d435150bbb9f2f816ce33afdf231 Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Sat, 6 Feb 2010 20:53:43 +0100 Subject: EP93xx: fix syscon_regs definition The structure was missing a reserved entry (not listed in the manual, actually), so the last registers had a wrong offset. This prevented all swlocked registers to be modified as swlock is last in the structure. Signed-off-by: Alessandro Rubini --- include/asm-arm/arch-ep93xx/ep93xx.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/asm-arm/arch-ep93xx/ep93xx.h b/include/asm-arm/arch-ep93xx/ep93xx.h index 6cafe54..806557a 100644 --- a/include/asm-arm/arch-ep93xx/ep93xx.h +++ b/include/asm-arm/arch-ep93xx/ep93xx.h @@ -558,8 +558,9 @@ struct syscon_regs { uint32_t i2sclkdiv; uint32_t keytchclkdiv; uint32_t chipid; + uint32_t reserved4; uint32_t syscfg; - uint32_t reserved4[8]; + uint32_t reserved5[8]; uint32_t sysswlock; }; #else -- cgit v1.1 From 822bd70db49773b4d57eaa484dca83386a6b3479 Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Sat, 6 Feb 2010 20:53:54 +0100 Subject: edb93xx: change calculation un early_udelay.h Previous code compiled with gcc-4.2.2 makes a call to __aeabi_uidiv to divide by 20. As a side effect it was not inline any more, and so sdram_cfg used the stack as well, but this is early code that has no stack yet. The patch explicitly removes the division, so no stack is used. The calculation of the counter calls a division by 20 Signed-off-by: Alessandro Rubini --- board/edb93xx/early_udelay.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/edb93xx/early_udelay.h b/board/edb93xx/early_udelay.h index 3b26b3f..185283d 100644 --- a/board/edb93xx/early_udelay.h +++ b/board/edb93xx/early_udelay.h @@ -26,7 +26,7 @@ static inline void early_udelay(uint32_t usecs) { /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */ - register uint32_t loops = (usecs * 1000) / 20; + register uint32_t loops = usecs * (1000 / 20); __asm__ volatile ("1:\n" "subs %0, %1, #1\n" -- cgit v1.1 From 39a9142203e610bf2b1a216085e374277fd28f9f Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Sat, 6 Feb 2010 20:54:05 +0100 Subject: edb93xx: enable the uart in devicecfg register printf goes to uart1, but it will block forever waiting for busy to go off unless the uart is enabled first. Signed-off-by: Alessandro Rubini --- board/edb93xx/edb93xx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/edb93xx/edb93xx.c b/board/edb93xx/edb93xx.c index 4df2246..dde30ff 100644 --- a/board/edb93xx/edb93xx.c +++ b/board/edb93xx/edb93xx.c @@ -64,6 +64,12 @@ int board_init(void) value |= SYSCON_PWRCNT_UART_BAUD; writel(value, &syscon->pwrcnt); + /* Enable the uart in devicecfg */ + value = readl(&syscon->devicecfg); + value |= 1<<18 /* U1EN */; + writel(0xAA, &syscon->sysswlock); + writel(value, &syscon->devicecfg); + /* Machine number, as defined in linux/arch/arm/tools/mach-types */ gd->bd->bi_arch_number = CONFIG_MACH_TYPE; -- cgit v1.1 From eff536befd3efab538bba10bad07ecff63c9f470 Mon Sep 17 00:00:00 2001 From: Magnus Lilja Date: Tue, 9 Feb 2010 22:05:39 +0100 Subject: SPI: Fix 32 bit transfers in mxc_spi.c Commit f9b6a1575d9f1ca192e4cb60e547aa66f08baa3f, "i.MX31: fix SPI driver for shorter than 32 bit" broke 32 bit transfers. This patch makes single 32 bit transfer work again. Transfer lengths that are known not to work will abort and print an error message. Tested on i.MX31 Litekit and i.MX31 PDK using 32 bit transfers to the MC13783/ATLAS chip (using the 'date' command). Signed-off-by: Magnus Lilja --- drivers/spi/mxc_spi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index fad9840..3a45200 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -131,6 +131,13 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, return 1; } + /* This driver is currently partly broken, alert the user */ + if (bitlen > 16 && (bitlen % 32)) { + printf("Error: SPI transfer with bitlen=%d is broken.\n", + bitlen); + return 1; + } + for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout; i < n_blks; i++, in_l++, out_l++, bitlen -= 32) { @@ -142,6 +149,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, *(u8 *)din = data; else if (bitlen < 17) *(u16 *)din = data; + else + *in_l = data; } } -- cgit v1.1 From b74064a0e2984a166e3575852f3697ef5595a97b Mon Sep 17 00:00:00 2001 From: Sanjeev Premi Date: Mon, 8 Feb 2010 11:33:25 -0500 Subject: OMAP3: Avoid re-write to PRM_CLKSRC_CTRL In function get_osc_clk_speed(), do not change/ update the divider for SYS_CLK as it can has cascading effect on the other derived clocks. Sudden change in divider value can lead to inconsistent behavior in the system - often leading to crashes. The problem was found when working with OMAP3EVM using DM3730 processor card. The patch has been tested with OMAP3530 on OMAP3EVM as well Signed-off-by: Sanjeev Premi Signed-off-by: Hiremath Vaibhav Signed-off-by: Sandeep Paulraj --- cpu/arm_cortexa8/omap3/clock.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c index 174c453..6330c9e 100644 --- a/cpu/arm_cortexa8/omap3/clock.c +++ b/cpu/arm_cortexa8/omap3/clock.c @@ -40,7 +40,7 @@ *****************************************************************************/ u32 get_osc_clk_speed(void) { - u32 start, cstart, cend, cdiff, val; + u32 start, cstart, cend, cdiff, cdiv, val; struct prcm *prcm_base = (struct prcm *)PRCM_BASE; struct prm *prm_base = (struct prm *)PRM_BASE; struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; @@ -48,9 +48,15 @@ u32 get_osc_clk_speed(void) val = readl(&prm_base->clksrc_ctrl); - /* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1; - writel(val, &prm_base->clksrc_ctrl); + if (val & SYSCLKDIV_2) + cdiv = 2; + else if (val & SYSCLKDIV_1) + cdiv = 1; + else + /* + * Should never reach here! (Assume divider as 1) + */ + cdiv = 1; /* enable timer2 */ val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1; @@ -61,6 +67,7 @@ u32 get_osc_clk_speed(void) /* Enable I and F Clocks for GPT1 */ val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC; writel(val, &prcm_base->iclken_wkup); + val = readl(&prcm_base->fclken_wkup) | EN_GPT1; writel(val, &prcm_base->fclken_wkup); @@ -83,6 +90,11 @@ u32 get_osc_clk_speed(void) cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ cdiff = cend - cstart; /* get elapsed ticks */ + if (cdiv == 2) + { + cdiff *= 2; + } + /* based on number of ticks assign speed */ if (cdiff > 19000) return S38_4M; -- cgit v1.1 From 6228e6389e5ef472d5f43cc5ec4f309323305638 Mon Sep 17 00:00:00 2001 From: Nick Thompson Date: Mon, 8 Feb 2010 11:34:58 -0500 Subject: Davinci: Add EMIF-A macros for setting chip select parameters The patch adds EMIF-A macros for setting chip select parameters Signed-off-by: Nick Thompson Signed-off-by: Sandeep Paulraj --- include/asm-arm/arch-davinci/emif_defs.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h index 8fd4e01..aa57703 100644 --- a/include/asm-arm/arch-davinci/emif_defs.h +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -24,7 +24,7 @@ #include -typedef struct { +typedef struct davinci_emif_regs { dv_reg ERCSR; dv_reg AWCCR; dv_reg SDBCR; @@ -66,6 +66,9 @@ typedef struct { typedef emif_registers *emifregs; +#define davinci_emif_regs \ + ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) + #define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) @@ -73,4 +76,17 @@ typedef emif_registers *emifregs; #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) +/* Chip Select setup */ +#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) +#define DAVINCI_ABCR_EXT_WAIT (1 << 30) +#define DAVINCI_ABCR_WSETUP(n) (n << 26) +#define DAVINCI_ABCR_WSTROBE(n) (n << 20) +#define DAVINCI_ABCR_WHOLD(n) (n << 17) +#define DAVINCI_ABCR_RSETUP(n) (n << 13) +#define DAVINCI_ABCR_RSTROBE(n) (n << 7) +#define DAVINCI_ABCR_RHOLD(n) (n << 4) +#define DAVINCI_ABCR_TA(n) (n << 2) +#define DAVINCI_ABCR_ASIZE_16BIT 1 +#define DAVINCI_ABCR_ASIZE_8BIT 0 + #endif -- cgit v1.1 From 3a4e43921d2599453ea87c623099e5f347c9e54a Mon Sep 17 00:00:00 2001 From: Nick Thompson Date: Mon, 8 Feb 2010 11:36:16 -0500 Subject: DA830 EVM: Enable NAND support on Spectrum Digital EVM The EVM UI extender card has a NAND device. This change will enable saveenv to work with NAND and Linux to be booted using: mtdparts default nboot kernel bootm Signed-off-by: Nick Thompson Signed-off-by: Sandeep Paulraj --- board/davinci/da830evm/da830evm.c | 37 +++++++++++++++++++++++++++++++++++++ include/configs/da830evm.h | 21 ++++++++++++++++----- 2 files changed, 53 insertions(+), 5 deletions(-) diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da830evm/da830evm.c index 12df1f8..aac5c5c 100644 --- a/board/davinci/da830evm/da830evm.c +++ b/board/davinci/da830evm/da830evm.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include "../common/misc.h" @@ -51,6 +52,23 @@ static const struct pinmux_config spi0_pins[] = { { pinmux[7], 1, 7 } }; +/* EMIF-A bus pins for 8-bit NAND support on CS3 */ +static const struct pinmux_config emifa_nand_pins[] = { + { pinmux[13], 1, 6 }, + { pinmux[13], 1, 7 }, + { pinmux[14], 1, 0 }, + { pinmux[14], 1, 1 }, + { pinmux[14], 1, 2 }, + { pinmux[14], 1, 3 }, + { pinmux[14], 1, 4 }, + { pinmux[14], 1, 5 }, + { pinmux[15], 1, 7 }, + { pinmux[16], 1, 0 }, + { pinmux[18], 1, 1 }, + { pinmux[18], 1, 4 }, + { pinmux[18], 1, 5 }, +}; + /* UART pin muxer settings */ static const struct pinmux_config uart_pins[] = { { pinmux[8], 2, 7 }, @@ -77,6 +95,9 @@ static const struct pinmux_resource pinmuxes[] = { #ifdef CONFIG_USB_DA8XX PINMUX_ITEM(usb_pins), #endif +#ifdef CONFIG_USE_NAND + PINMUX_ITEM(emifa_nand_pins), +#endif }; int board_init(void) @@ -96,6 +117,22 @@ int board_init(void) writel(0xffffffff, &davinci_aintc_regs->ecr3); #endif +#ifdef CONFIG_NAND_DAVINCI + /* EMIFA 100MHz clock select */ + writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2, + &davinci_syscfg_regs->cfgchip3); + /* NAND CS setup */ + writel((DAVINCI_ABCR_WSETUP(0) | + DAVINCI_ABCR_WSTROBE(2) | + DAVINCI_ABCR_WHOLD(0) | + DAVINCI_ABCR_RSETUP(0) | + DAVINCI_ABCR_RSTROBE(2) | + DAVINCI_ABCR_RHOLD(0) | + DAVINCI_ABCR_TA(2) | + DAVINCI_ABCR_ASIZE_8BIT), + &davinci_emif_regs->AB2CR); +#endif + /* arch number of the board */ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM; diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 432cd57..65747fb 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -103,14 +103,15 @@ #define CONFIG_NAND_DAVINCI #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ -#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_ENV_OFFSET (512 << 10) +#define CONFIG_ENV_SIZE (512 << 10) #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define CONFIG_SYS_CLE_MASK 0x10 #define CONFIG_SYS_ALE_MASK 0x8 -#define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_MAX_CHIPS 1 #define DEF_BOOTM "" @@ -216,8 +217,7 @@ #define CONFIG_CMD_NAND #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_UBI -#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE #endif #ifdef CONFIG_USE_SPIFLASH @@ -268,4 +268,15 @@ #endif /* CONFIG_MUSB_UDC */ #endif /* CONFIG_USB_DA8XX */ + +#ifdef CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nand0=davinci_nand.1" +#define PART_BOOT "512k(bootloader)ro," +#define PART_PARAMS "512k(params)ro," +#define PART_KERNEL "4m(kernel)," +#define PART_REST "-(filesystem)" +#define MTDPARTS_DEFAULT \ + "mtdparts=davinci_nand.1:" PART_BOOT PART_PARAMS PART_KERNEL PART_REST +#endif + #endif /* __CONFIG_H */ -- cgit v1.1 From 425de62d40f84524b90e776b141b060cd438a9fe Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Wed, 3 Feb 2010 22:45:42 +0100 Subject: add new CONFIG_AT91_LEGACY * add's the new temporary CONFIG_AT91_LEGACY to all board configs This will need for backward compatiblity, while change the SoC access to c structures. If CONFIG_AT91_LEGACY is defined, the deprecated SoC is used. Signed-off-by: Jens Scharsig --- doc/README.at91-soc | 41 ++++++++++++++++++++++++++++++++++++++ include/configs/afeb9260.h | 2 ++ include/configs/at91cap9adk.h | 2 ++ include/configs/at91rm9200dk.h | 2 ++ include/configs/at91rm9200ek.h | 2 ++ include/configs/at91sam9260ek.h | 2 ++ include/configs/at91sam9261ek.h | 2 ++ include/configs/at91sam9263ek.h | 2 ++ include/configs/at91sam9m10g45ek.h | 2 ++ include/configs/at91sam9rlek.h | 2 ++ include/configs/cmc_pu2.h | 2 ++ include/configs/cpu9260.h | 2 ++ include/configs/cpuat91.h | 2 ++ include/configs/csb637.h | 2 ++ include/configs/kb9202.h | 2 ++ include/configs/m501sk.h | 2 ++ include/configs/meesc.h | 2 ++ include/configs/mp2usb.h | 2 ++ include/configs/pm9261.h | 2 ++ include/configs/pm9263.h | 2 ++ include/configs/sbc35_a9g20.h | 2 ++ include/configs/tny_a9260.h | 2 ++ 22 files changed, 83 insertions(+) create mode 100644 doc/README.at91-soc diff --git a/doc/README.at91-soc b/doc/README.at91-soc new file mode 100644 index 0000000..bed035c --- /dev/null +++ b/doc/README.at91-soc @@ -0,0 +1,41 @@ + New C structure AT91 SoC access +================================= + +The goal +-------- + +Currently the at91 arch uses hundreds of address defines and special +at91_xxxx_write/read functions to access the SOC. +The u-boot project perferred method is to access memory mapped hw +regisister via a c structure. + +e.g. old + + *AT91C_PIOA_IDR = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + *AT91C_PIOC_PUDR = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + *AT91C_PIOC_PER = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + *AT91C_PIOC_OER = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + *AT91C_PIOC_PIO = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + + at91_sys_write(AT91_RSTC_CR, + AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); + +e.g new + pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + writel(pin, &pio->pioa.idr); + writel(pin, &pio->pioa.pudr); + writel(pin, &pio->pioa.per); + writel(pin, &pio->pioa.oer); + writel(pin, &pio->pioa.sodr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | + AT91_RSTC_CR_PERRST, &rstc->cr); + +The method for updating +------------------------ + +1. add's the temporary CONFIG_AT91_LEGACY to all at91 board configs +2. Display a compile time warning, if the board has not been converted +3. add new structures for SoC access +4. Convert arch, driver and boards file to new SoC +5. remove legacy code, if all boards and drives are ready diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 58b8c8c..3b69de8 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -26,6 +26,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index 322718f..4c2782a 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 5de70cb..d39e8f2 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -25,6 +25,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 4750855..145c3c3 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -26,6 +26,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ /* * from 18.432 MHz crystal diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 0509011..a620d57 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index fbf7389..832b1cd 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 571351c..1d82a15 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 06184e7..50b118f 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 6fad75d..8db296a 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index 00d0cec..ffe83f0 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -25,6 +25,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h index 4ef8566..e967e7c 100644 --- a/include/configs/cpu9260.h +++ b/include/configs/cpu9260.h @@ -31,6 +31,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + #define CONFIG_DISPLAY_CPUINFO 1 #define AT91_MAIN_CLOCK 18432000 diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index e872fe9..b4fda76 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -26,6 +26,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + #ifdef CONFIG_CPUAT91_RAM #define CONFIG_SKIP_LOWLEVEL_INIT 1 #define CONFIG_SKIP_RELOCATE_UBOOT 1 diff --git a/include/configs/csb637.h b/include/configs/csb637.h index 689e7f0..efa2780 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -26,6 +26,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */ #define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */ diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 3fe88fe..41ec1d5 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -29,6 +29,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 180000000 /* from 10 MHz crystal */ #define AT91C_MASTER_CLOCK 60000000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h index a28fd27..26c2bcb 100644 --- a/include/configs/m501sk.h +++ b/include/configs/m501sk.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ /* from 18.432 MHz crystal (18432000 / 4 * 39) */ #define AT91C_MAIN_CLOCK 179712000 diff --git a/include/configs/meesc.h b/include/configs/meesc.h index c3255fa..e5bf5d0 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -31,6 +31,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* Common stuff */ #define CONFIG_SYS_HZ 1000 /* decrementer freq */ #define CONFIG_MEESC 1 /* Board is esd MEESC */ diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index 31eb1b6..3138b49 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */ #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 399d15f..26a2fad 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_CPU_NAME "AT91SAM9261" diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 0af1280..e55098c 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index f4b3477..7bdc729 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -26,6 +26,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + #if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM) #define CONFIG_SBC35_A9G20 #endif diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h index 4ad081b..21475f8 100644 --- a/include/configs/tny_a9260.h +++ b/include/configs/tny_a9260.h @@ -30,6 +30,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + #if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9260_EEPROM) #define CONFIG_TNY_A9260 #elif defined(CONFIG_TNY_A9G20_NANDFLASH) || defined(CONFIG_TNY_A9G20_EEPROM) -- cgit v1.1 From 5d8e359c38d3ab80015e47d0cab792efe75cacf9 Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Wed, 3 Feb 2010 22:46:01 +0100 Subject: add c structures for SoC access * add's c structures for SoC access to pheriperials head files Signed-off-by: Jens Scharsig --- include/asm-arm/arch-at91/at91_matrix.h | 116 ++++++++++++++++++++++++++++ include/asm-arm/arch-at91/at91_pdc.h | 39 ++++++++++ include/asm-arm/arch-at91/at91_pio.h | 97 +++++++++++++++++++++++ include/asm-arm/arch-at91/at91_pit.h | 15 ++++ include/asm-arm/arch-at91/at91_pmc.h | 91 ++++++++++++++++++++++ include/asm-arm/arch-at91/at91_rstc.h | 30 ++++++- include/asm-arm/arch-at91/at91_spi.h | 21 +++++ include/asm-arm/arch-at91/at91_wdt.h | 29 +++++++ include/asm-arm/arch-at91/at91cap9.h | 8 ++ include/asm-arm/arch-at91/at91sam9260.h | 14 ++++ include/asm-arm/arch-at91/at91sam9261.h | 12 ++- include/asm-arm/arch-at91/at91sam9263.h | 20 +++++ include/asm-arm/arch-at91/at91sam9_sdramc.h | 13 ++++ include/asm-arm/arch-at91/at91sam9_smc.h | 63 +++++++++++++++ include/asm-arm/arch-at91/at91sam9g45.h | 13 ++++ include/asm-arm/arch-at91/at91sam9rl.h | 12 ++- include/asm-arm/arch-at91/gpio.h | 3 + include/asm-arm/arch-at91/io.h | 3 + 18 files changed, 596 insertions(+), 3 deletions(-) create mode 100644 include/asm-arm/arch-at91/at91_matrix.h create mode 100644 include/asm-arm/arch-at91/at91_pdc.h diff --git a/include/asm-arm/arch-at91/at91_matrix.h b/include/asm-arm/arch-at91/at91_matrix.h new file mode 100644 index 0000000..9b3c110 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_matrix.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef AT91_MATRIX_H +#define AT91_MATRIX_H + +#ifdef __ASSEMBLY__ + +#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) +#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x11C) +#elif defined(CONFIG_AT91SAM9261) +#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x30) +#elif defined(CONFIG_AT91SAM9263) +#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x120) +#elif defined(CONFIG_AT91SAM9G45) +#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x128) +#else +#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU +#endif + +#define AT91_ASM_MATRIX_MCFG AT91_MATRIX_BASE + +#else +#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) +#define AT91_MATRIX_MASTERS 6 +#define AT91_MATRIX_SLAVES 5 +#elif defined(CONFIG_AT91SAM9261) +#define AT91_MATRIX_MASTERS 1 +#define AT91_MATRIX_SLAVES 5 +#elif defined(CONFIG_AT91SAM9263) +#define AT91_MATRIX_MASTERS 9 +#define AT91_MATRIX_SLAVES 7 +#elif defined(CONFIG_AT91SAM9G45) +#define AT91_MATRIX_MASTERS 11 +#define AT91_MATRIX_SLAVES 8 +#else +#error CPU not supported. Please update at91_matrix.h +#endif + +typedef struct at91_priority { + u32 a; + u32 b; +} at91_priority_t; + +typedef struct at91_matrix { + u32 mcfg[AT91_MATRIX_MASTERS]; +#if defined(CONFIG_AT91SAM9261) + u32 scfg[AT91_MATRIX_SLAVES]; + u32 res61_1[3]; + u32 tcr; + u32 res61_2[2]; + u32 csa; + u32 pucr; + u32 res61_3[114]; +#else + u32 reserve1[16 - AT91_MATRIX_MASTERS]; + u32 scfg[AT91_MATRIX_SLAVES]; + u32 reserve2[16 - AT91_MATRIX_SLAVES]; + at91_priority_t pr[AT91_MATRIX_SLAVES]; + u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)]; + u32 mrcr; /* 0x100 Master Remap Control */ + u32 reserve4[3]; +#if defined(CONFIG_AT91SAM9G45) + u32 ccr[52] /* 0x110 - 0x1E0 Chip Configuration */ + u32 womr; /* 0x1E4 Write Protect Mode */ + u32 wpsr; /* 0x1E8 Write Protect Status */ + u32 resg45_1[10]; +#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) + u32 res60_1[3]; + u32 csa; + u32 res60_2[56]; +#elif defined(CONFIG_AT91SAM9263) + u32 res63_1; + u32 tcmr; + u32 res63_2[2]; + u32 csa[2]; + u32 res63_3[54]; +#else + u32 reserve5[60]; +#endif +#endif +} at91_matrix_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_MATRIX_CSA_DBPUC 0x00000100 +#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000 +#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000 + +#define AT91_MATRIX_CSA_EBI_CS1A 0x00000002 +#define AT91_MATRIX_CSA_EBI_CS3A 0x00000008 +#define AT91_MATRIX_CSA_EBI_CS4A 0x00000010 +#define AT91_MATRIX_CSA_EBI_CS5A 0x00000020 + +#define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008 + +#endif diff --git a/include/asm-arm/arch-at91/at91_pdc.h b/include/asm-arm/arch-at91/at91_pdc.h new file mode 100644 index 0000000..42f87ca --- /dev/null +++ b/include/asm-arm/arch-at91/at91_pdc.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef AT91_PDC_H +#define AT91_PDC_H + +typedef struct at91_pdc { + u32 rpr; /* 0x100 Receive Pointer Register */ + u32 rcr; /* 0x104 Receive Counter Register */ + u32 tpr; /* 0x108 Transmit Pointer Register */ + u32 tcr; /* 0x10C Transmit Counter Register */ + u32 pnpr; /* 0x110 Receive Next Pointer Register */ + u32 pncr; /* 0x114 Receive Next Counter Register */ + u32 tnpr; /* 0x118 Transmit Next Pointer Register */ + u32 tncr; /* 0x11C Transmit Next Counter Register */ + u32 ptcr; /* 0x120 Transfer Control Register */ + u32 ptsr; /* 0x124 Transfer Status Register */ +} at91_pdc_t; + +#endif diff --git a/include/asm-arm/arch-at91/at91_pio.h b/include/asm-arm/arch-at91/at91_pio.h index f6ce1f9..92c3717 100644 --- a/include/asm-arm/arch-at91/at91_pio.h +++ b/include/asm-arm/arch-at91/at91_pio.h @@ -3,6 +3,7 @@ * * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) SAN People + * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) * * Parallel I/O Controller (PIO) - System peripherals registers. * Based on AT91RM9200 datasheet revision E. @@ -16,6 +17,101 @@ #ifndef AT91_PIO_H #define AT91_PIO_H + +#define AT91_ASM_PIO_RANGE 0x200 +#define AT91_ASM_PIOC_PDR \ + (AT91_PIO_BASE + AT91_PIO_PORTC*AT91_ASM_PIO_RANGE + 0x04) +#define AT91_ASM_PIOC_PUDR \ + (AT91_PIO_BASE + AT91_PIO_PORTC*AT91_ASM_PIO_RANGE + 0x60) + +#define AT91_ASM_PIOD_PDR \ + (AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x04) +#define AT91_ASM_PIOD_PUDR \ + (AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x60) +#define AT91_ASM_PIOD_ASR \ + (AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x70) + +#ifndef __ASSEMBLY__ + +typedef struct at91_port { + u32 per; /* 0x00 PIO Enable Register */ + u32 pdr; /* 0x04 PIO Disable Register */ + u32 psr; /* 0x08 PIO Status Register */ + u32 reserved0; + u32 oer; /* 0x10 Output Enable Register */ + u32 odr; /* 0x14 Output Disable Registerr */ + u32 osr; /* 0x18 Output Status Register */ + u32 reserved1; + u32 ifer; /* 0x20 Input Filter Enable Register */ + u32 ifdr; /* 0x24 Input Filter Disable Register */ + u32 ifsr; /* 0x28 Input Filter Status Register */ + u32 reserved2; + u32 sodr; /* 0x30 Set Output Data Register */ + u32 codr; /* 0x34 Clear Output Data Register */ + u32 odsr; /* 0x38 Output Data Status Register */ + u32 pdsr; /* 0x3C Pin Data Status Register */ + u32 ier; /* 0x40 Interrupt Enable Register */ + u32 idr; /* 0x44 Interrupt Disable Register */ + u32 imr; /* 0x48 Interrupt Mask Register */ + u32 isr; /* 0x4C Interrupt Status Register */ + u32 mder; /* 0x50 Multi-driver Enable Register */ + u32 mddr; /* 0x54 Multi-driver Disable Register */ + u32 mdsr; /* 0x58 Multi-driver Status Register */ + u32 reserved3; + u32 pudr; /* 0x60 Pull-up Disable Register */ + u32 puer; /* 0x64 Pull-up Enable Register */ + u32 pusr; /* 0x68 Pad Pull-up Status Register */ + u32 reserved4; + u32 asr; /* 0x70 Select A Register */ + u32 bsr; /* 0x74 Select B Register */ + u32 absr; /* 0x78 AB Select Status Register */ + u32 reserved5[9]; /* */ + u32 ower; /* 0xA0 Output Write Enable Register */ + u32 owdr; /* 0xA4 Output Write Disable Register */ + u32 owsr; /* OxA8 utput Write Status Register */ + u32 reserved6[85]; +} at91_port_t; + +#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ + defined(CONFIG_AT91SAM9G10) || defined(CONFIG_AT91SAM9G20) +#define AT91_PIO_PORTS 3 +#elif defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \ + defined(CONFIG_AT91SAM9M10G45) +#define AT91_PIO_PORTS 5 +#elif defined(CONFIG_AT91RM9200) || defined(CONFIG_AT91CAP9) || \ + defined(CONFIG_AT91SAM9RL) +#define AT91_PIO_PORTS 4 +#else +#error "Unsupported cpu. Please update at91_pio.h" +#endif + +typedef union at91_pio { + struct { + at91_port_t pioa; + at91_port_t piob; + at91_port_t pioc; + #if (AT91_PIO_PORTS > 3) + at91_port_t piod; + #endif + #if (AT91_PIO_PORTS > 4) + at91_port_t pioe; + #endif + } ; + at91_port_t port[AT91_PIO_PORTS]; +} at91_pio_t; + +#endif + +#define AT91_PIN_TO_MASK(x) (1< + +typedef struct at91_pmc { + u32 scer; /* 0x00 System Clock Enable Register */ + u32 scdr; /* 0x04 System Clock Disable Register */ + u32 scsr; /* 0x08 System Clock Status Register */ + u32 reserved0; + u32 pcer; /* 0x10 Peripheral Clock Enable Register */ + u32 pcdr; /* 0x14 Peripheral Clock Disable Register */ + u32 pcsr; /* 0x18 Peripheral Clock Status Register */ + u32 reserved1; + u32 mor; /* 0x20 Main Oscilator Register */ + u32 mcfr; /* 0x24 Main Clock Frequency Register */ + u32 pllar; /* 0x28 PLL A Register */ + u32 pllbr; /* 0x2C PLL B Register */ + u32 mckr; /* 0x30 Master Clock Register */ + u32 reserved2[3]; + u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */ + u32 reserved3[4]; + u32 ier; /* 0x60 Interrupt Enable Register */ + u32 idr; /* 0x64 Interrupt Disable Register */ + u32 sr; /* 0x68 Status Register */ + u32 imr; /* 0x6C Interrupt Mask Register */ + u32 reserved4[4]; + u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */ + u32 reserved5[21]; + u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */ + u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */ + u32 reserved8[5]; +} at91_pmc_t; + +#endif /* end not assembly */ + +#define AT91_PMC_MOR_MOSCEN 0x01 +#define AT91_PMC_MOR_OSCBYPASS 0x02 +#define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8) + +#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) +#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) +#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) +#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) +#define AT91_PMC_PLLAR_29 0x20000000 +#define AT91_PMC_PLLBR_USBDIV_1 0x00000000 +#define AT91_PMC_PLLBR_USBDIV_2 0x10000000 +#define AT91_PMC_PLLBR_USBDIV_4 0x20000000 + +#define AT91_PMC_MCKR_CSS_SLOW 0x00000000 +#define AT91_PMC_MCKR_CSS_MAIN 0x00000001 +#define AT91_PMC_MCKR_CSS_PLLA 0x00000002 +#define AT91_PMC_MCKR_CSS_PLLB 0x00000003 +#define AT91_PMC_MCKR_CSS_MASK 0x00000003 + +#define AT91_PMC_MCKR_PRES_1 0x00000000 +#define AT91_PMC_MCKR_PRES_2 0x00000004 +#define AT91_PMC_MCKR_PRES_4 0x00000008 +#define AT91_PMC_MCKR_PRES_8 0x0000000C +#define AT91_PMC_MCKR_PRES_16 0x00000010 +#define AT91_PMC_MCKR_PRES_32 0x00000014 +#define AT91_PMC_MCKR_PRES_64 0x00000018 +#define AT91_PMC_MCKR_PRES_MASK 0x0000001C + +#define AT91_PMC_MCKR_MDIV_1 0x00000000 +#define AT91_PMC_MCKR_MDIV_2 0x00000100 +#define AT91_PMC_MCKR_MDIV_4 0x00000200 +#define AT91_PMC_MCKR_MDIV_MASK 0x00000300 + +#define AT91_PMC_MCKR_PLLADIV_1 0x00001000 +#define AT91_PMC_MCKR_PLLADIV_2 0x00002000 + +#define AT91_PMC_IXR_MOSCS 0x00000001 +#define AT91_PMC_IXR_LOCKA 0x00000002 +#define AT91_PMC_IXR_LOCKB 0x00000004 +#define AT91_PMC_IXR_MCKRDY 0x00000008 +#define AT91_PMC_IXR_LOCKU 0x00000040 +#define AT91_PMC_IXR_PCKRDY0 0x00000100 +#define AT91_PMC_IXR_PCKRDY1 0x00000200 +#define AT91_PMC_IXR_PCKRDY2 0x00000400 +#define AT91_PMC_IXR_PCKRDY3 0x00000800 + +#ifdef CONFIG_AT91_LEGACY + #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ @@ -117,4 +207,5 @@ #define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ +#endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/include/asm-arm/arch-at91/at91_rstc.h b/include/asm-arm/arch-at91/at91_rstc.h index e49caef..9ff2c5b 100644 --- a/include/asm-arm/arch-at91/at91_rstc.h +++ b/include/asm-arm/arch-at91/at91_rstc.h @@ -16,11 +16,37 @@ #ifndef AT91_RSTC_H #define AT91_RSTC_H +#define AT91_ASM_RSTC_MR (AT91_RSTC_BASE + 0x08) + +#ifndef __ASSEMBLY__ + +typedef struct at91_rstc { + u32 cr; /* Reset Controller Control Register */ + u32 sr; /* Reset Controller Status Register */ + u32 mr; /* Reset Controller Mode Register */ +} at91_rstc_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_RSTC_KEY 0xA5000000 + +#define AT91_RSTC_CR_PROCRST 0x00000001 +#define AT91_RSTC_CR_PERRST 0x00000004 +#define AT91_RSTC_CR_EXTRST 0x00000008 + +#define AT91_RSTC_MR_URSTEN 0x00000001 +#define AT91_RSTC_MR_URSTIEN 0x00000010 +#define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8) +#define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00 + +#define AT91_RSTC_SR_NRSTL 0x00010000 + +#ifdef CONFIG_AT91_LEGACY + #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ -#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ @@ -38,4 +64,6 @@ #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ +#endif /* CONFIG_AT91_LEGACY */ + #endif diff --git a/include/asm-arm/arch-at91/at91_spi.h b/include/asm-arm/arch-at91/at91_spi.h index 30643c6..c520e89 100644 --- a/include/asm-arm/arch-at91/at91_spi.h +++ b/include/asm-arm/arch-at91/at91_spi.h @@ -16,6 +16,25 @@ #ifndef AT91_SPI_H #define AT91_SPI_H +#include + +typedef struct at91_spi { + u32 cr; /* 0x00 Control Register */ + u32 mr; /* 0x04 Mode Register */ + u32 rdr; /* 0x08 Receive Data Register */ + u32 tdr; /* 0x0C Transmit Data Register */ + u32 sr; /* 0x10 Status Register */ + u32 ier; /* 0x14 Interrupt Enable Register */ + u32 idr; /* 0x18 Interrupt Disable Register */ + u32 imr; /* 0x1C Interrupt Mask Register */ + u32 reserve1[4]; + u32 csr[4]; /* 0x30 Chip Select Register 0-3 */ + u32 reserve2[48]; + at91_pdc_t pdc; +} at91_spi_t; + +#ifdef CONFIG_AT91_LEGACY + #define AT91_SPI_CR 0x00 /* Control Register */ #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ #define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ @@ -102,4 +121,6 @@ #define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */ +#endif /* CONFIG_AT91_LEGACY */ + #endif diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h index 7e18537..cf08daf 100644 --- a/include/asm-arm/arch-at91/at91_wdt.h +++ b/include/asm-arm/arch-at91/at91_wdt.h @@ -17,6 +17,34 @@ #ifndef AT91_WDT_H #define AT91_WDT_H +#ifdef __ASSEMBLY__ + +#define AT91_ASM_WDT_MR (AT91_WDT_BASE + 0x04) + +#else + +typedef struct at91_wdt { + u32 cr; + u32 mr; + u32 sr; +} at91_wdt_t; + +#endif + +#define AT91_WDT_CR_WDRSTT 1 +#define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */ + +#define AT91_WDT_MR_WDV(x) (x & 0xfff) +#define AT91_WDT_MR_WDFIEN 0x00001000 +#define AT91_WDT_MR_WDRSTEN 0x00002000 +#define AT91_WDT_MR_WDRPROC 0x00004000 +#define AT91_WDT_MR_WDDIS 0x00008000 +#define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16) +#define AT91_WDT_MR_WDDBGHLT 0x10000000 +#define AT91_WDT_MR_WDIDLEHLT 0x20000000 + +#ifdef CONFIG_AT91_LEGACY + #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ #define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ @@ -35,4 +63,5 @@ #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ +#endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h index b128ac5..658124b 100644 --- a/include/asm-arm/arch-at91/at91cap9.h +++ b/include/asm-arm/arch-at91/at91cap9.h @@ -53,6 +53,13 @@ #define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ #define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91_PIO_BASE 0xfffff200 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 +#define AT91_PIT_BASE 0xfffffd30 + +#ifdef CONFIG_AT91_LEGACY + /* * User Peripheral physical base addresses. */ @@ -119,6 +126,7 @@ #define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3) #define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3) +#endif /* CONFIG_AT91_LEGACY */ /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h index 73975f4..7ca6078 100644 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ b/include/asm-arm/arch-at91/at91sam9260.h @@ -49,6 +49,18 @@ #define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ #define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ +#define AT91_EMAC_BASE 0xfffc4000 +#define AT91_SDRAMC_BASE 0xffffea00 +#define AT91_SMC_BASE 0xffffec00 +#define AT91_MATRIX_BASE 0xffffee00 +#define AT91_PIO_BASE 0xfffff400 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 + +#ifdef CONFIG_AT91_LEGACY + /* * User Peripheral physical base addresses. */ @@ -105,6 +117,8 @@ #define AT91_USART4 AT91SAM9260_BASE_US4 #define AT91_USART5 AT91SAM9260_BASE_US5 +#endif /* CONFIG_AT91_LEGACY */ + /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h index b303e07..1d8cab6 100644 --- a/include/asm-arm/arch-at91/at91sam9261.h +++ b/include/asm-arm/arch-at91/at91sam9261.h @@ -43,6 +43,16 @@ #define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ #define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ +#define AT91_SDRAMC_BASE 0xffffea00 +#define AT91_SMC_BASE 0xffffec00 +#define AT91_MATRIX_BASE 0xffffee00 +#define AT91_PIO_BASE 0xfffff400 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 + +#ifdef CONFIG_AT91_LEGACY /* * User Peripheral physical base addresses. @@ -64,7 +74,6 @@ #define AT91SAM9261_BASE_SPI1 0xfffcc000 #define AT91_BASE_SYS 0xffffea00 - /* * System Peripherals (offset from AT91_BASE_SYS) */ @@ -88,6 +97,7 @@ #define AT91_USART1 AT91SAM9261_BASE_US1 #define AT91_USART2 AT91SAM9261_BASE_US2 +#endif /* CONFIG_AT91_LEGACY */ /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h index 966a683..b26b7b4 100644 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ b/include/asm-arm/arch-at91/at91sam9263.h @@ -47,6 +47,24 @@ #define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ #define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91_EMAC_BASE 0xfffbc000 +#define AT91_ECC0_BASE 0xffffe000 +#define AT91_SDRAMC0_BASE 0xffffe200 +#define AT91_SMC0_BASE 0xffffe400 +#define AT91_ECC1_BASE 0xffffe600 +#define AT91_SDRAMC1_BASE 0xffffe800 +#define AT91_SMC1_BASE 0xffffea00 +#define AT91_MATRIX_BASE 0xffffec00 +#define AT91_CCFG_BASE 0xffffed10 +#define AT91_DBGU_BASE 0xffffee00 +#define AT91_AIC_BASE 0xfffff000 +#define AT91_PIO_BASE 0xfffff200 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 + +#ifdef CONFIG_AT91_LEGACY /* * User Peripheral physical base addresses. @@ -108,6 +126,8 @@ #define AT91_SMC AT91_SMC0 #define AT91_SDRAMC AT91_SDRAMC0 +#endif /* CONFIG_AT91_LEGACY */ + /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9_sdramc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h index 5af2b54..c3da3a6 100644 --- a/include/asm-arm/arch-at91/at91sam9_sdramc.h +++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h @@ -17,6 +17,19 @@ #ifndef AT91SAM9_SDRAMC_H #define AT91SAM9_SDRAMC_H +#ifdef __ASSEMBLY__ + +#ifndef AT91_SDRAMC_BASE +#define AT91_SDRAMC_BASE AT91_SDRAMC0_BASE +#endif + +#define AT91_ASM_SDRAMC_MR AT91_SDRAMC_BASE +#define AT91_ASM_SDRAMC_TR (AT91_SDRAMC_BASE + 0x04) +#define AT91_ASM_SDRAMC_CR (AT91_SDRAMC_BASE + 0x08) +#define AT91_ASM_SDRAMC_MDR (AT91_SDRAMC_BASE + 0x24) + +#endif + /* SDRAM Controller (SDRAMC) registers */ #define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ diff --git a/include/asm-arm/arch-at91/at91sam9_smc.h b/include/asm-arm/arch-at91/at91sam9_smc.h index d64511b..d180c8a 100644 --- a/include/asm-arm/arch-at91/at91sam9_smc.h +++ b/include/asm-arm/arch-at91/at91sam9_smc.h @@ -16,6 +16,68 @@ #ifndef AT91SAM9_SMC_H #define AT91SAM9_SMC_H +#ifdef __ASSEMBLY__ + +#ifndef AT91_SMC_BASE +#define AT91_SMC_BASE AT91_SMC0_BASE +#endif + +#define AT91_ASM_SMC_SETUP0 AT91_SMC_BASE +#define AT91_ASM_SMC_PULSE0 (AT91_SMC_BASE + 0x04) +#define AT91_ASM_SMC_CYCLE0 (AT91_SMC_BASE + 0x08) +#define AT91_ASM_SMC_MODE0 (AT91_SMC_BASE + 0x0C) + +#else + +typedef struct at91_cs { + u32 setup; /* 0x00 SMC Setup Register */ + u32 pulse; /* 0x04 SMC Pulse Register */ + u32 cycle; /* 0x08 SMC Cycle Register */ + u32 mode; /* 0x0C SMC Mode Register */ +} at91_cs_t; + +typedef struct at91_smc { + at91_cs_t cs[8]; +} at91_smc_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_SMC_SETUP_NWE(x) (x & 0x3f) +#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) +#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) +#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) + +#define AT91_SMC_PULSE_NWE(x) (x & 0x7f) +#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) +#define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) +#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) + +#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) +#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) + +#define AT91_SMC_MODE_RM_NCS 0x00000000 +#define AT91_SMC_MODE_RM_NRD 0x00000001 +#define AT91_SMC_MODE_WM_NCS 0x00000000 +#define AT91_SMC_MODE_WM_NWE 0x00000002 + +#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 +#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 +#define AT91_SMC_MODE_EXNW_READY 0x00000030 + +#define AT91_SMC_MODE_BAT 0x00000100 +#define AT91_SMC_MODE_DBW_8 0x00000000 +#define AT91_SMC_MODE_DBW_16 0x00001000 +#define AT91_SMC_MODE_DBW_32 0x00002000 +#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) +#define AT91_SMC_MODE_TDF 0x00100000 +#define AT91_SMC_MODE_PMEN 0x01000000 +#define AT91_SMC_MODE_PS_4 0x00000000 +#define AT91_SMC_MODE_PS_8 0x10000000 +#define AT91_SMC_MODE_PS_16 0x20000000 +#define AT91_SMC_MODE_PS_32 0x30000000 + +#ifdef CONFIG_AT91_LEGACY + #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ #define AT91_SMC_NWESETUP_(x) ((x) << 0) @@ -74,3 +136,4 @@ #endif #endif +#endif diff --git a/include/asm-arm/arch-at91/at91sam9g45.h b/include/asm-arm/arch-at91/at91sam9g45.h index 0feed9c..99c03f7 100644 --- a/include/asm-arm/arch-at91/at91sam9g45.h +++ b/include/asm-arm/arch-at91/at91sam9g45.h @@ -51,6 +51,17 @@ #define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ #define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ +#define AT91_EMAC_BASE 0xfffbc000 +#define AT91_SMC_BASE 0xffffe800 +#define AT91_MATRIX_BASE 0xffffea00 +#define AT91_PIO_BASE 0xfffff200 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 + +#ifdef CONFIG_AT91_LEGACY + /* * User Peripheral physical base addresses. */ @@ -114,6 +125,8 @@ #define AT91_USART2 AT91SAM9G45_BASE_US2 #define AT91_USART3 AT91SAM9G45_BASE_US3 +#endif + /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h index 4dd8037..12054f6 100644 --- a/include/asm-arm/arch-at91/at91sam9rl.h +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -44,6 +44,16 @@ #define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ #define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91_SDRAMC_BASE 0xffffea00 +#define AT91_SMC_BASE 0xffffec00 +#define AT91_MATRIX_BASE 0xffffee00 +#define AT91_PIO_BASE 0xfffff400 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 + +#ifdef CONFIG_AT91_LEGACY /* * User Peripheral physical base addresses. @@ -68,7 +78,6 @@ #define AT91SAM9RL_BASE_AC97C 0xfffd8000 #define AT91_BASE_SYS 0xffffc000 - /* * System Peripherals (offset from AT91_BASE_SYS) */ @@ -99,6 +108,7 @@ #define AT91_USART2 AT91SAM9RL_BASE_US2 #define AT91_USART3 AT91SAM9RL_BASE_US3 +#endif /* CONFIG_AT91_LEGACY */ /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/gpio.h b/include/asm-arm/arch-at91/gpio.h index e2d375b..bc53171 100644 --- a/include/asm-arm/arch-at91/gpio.h +++ b/include/asm-arm/arch-at91/gpio.h @@ -18,6 +18,8 @@ #include #include +#ifdef CONFIG_AT91_LEGACY + #define PIN_BASE 32 #define MAX_GPIO_BANKS 5 @@ -365,3 +367,4 @@ static inline int at91_get_gpio_value(unsigned pin) } #endif +#endif diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h index f09b2df..38d185e 100644 --- a/include/asm-arm/arch-at91/io.h +++ b/include/asm-arm/arch-at91/io.h @@ -23,6 +23,8 @@ #include +#ifdef CONFIG_AT91_LEGACY + static inline unsigned int at91_sys_read(unsigned int reg_offset) { void *addr = (void *)AT91_BASE_SYS; @@ -36,5 +38,6 @@ static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) __raw_writel(value, addr + reg_offset); } +#endif #endif -- cgit v1.1 From ea8fbba73184a40437bdeccd888cf448d5f1105e Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Wed, 3 Feb 2010 22:46:16 +0100 Subject: add a new AT91 GPIO driver * add a real AT91 GPIO driver instead of header inline code * resolve the mixing of port and pins * change board config files to use new driver * add macros to gpio to realize backward compatibility Signed-off-by: Jens Scharsig --- drivers/gpio/Makefile | 1 + drivers/gpio/at91_gpio.c | 214 +++++++++++++++++++++++++++++++++++ include/asm-arm/arch-at91/at91_pio.h | 14 ++- include/asm-arm/arch-at91/gpio.h | 168 +++------------------------ include/configs/afeb9260.h | 1 + include/configs/at91cap9adk.h | 1 + include/configs/at91sam9260ek.h | 1 + include/configs/at91sam9261ek.h | 1 + include/configs/at91sam9263ek.h | 1 + include/configs/at91sam9m10g45ek.h | 1 + include/configs/at91sam9rlek.h | 1 + include/configs/cpu9260.h | 1 + include/configs/meesc.h | 1 + include/configs/pm9261.h | 1 + include/configs/pm9263.h | 1 + include/configs/sbc35_a9g20.h | 1 + include/configs/tny_a9260.h | 1 + 17 files changed, 258 insertions(+), 152 deletions(-) create mode 100644 drivers/gpio/at91_gpio.c diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index acba56c..d966082 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libgpio.a +COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c new file mode 100644 index 0000000..c0a97bc --- /dev/null +++ b/drivers/gpio/at91_gpio.c @@ -0,0 +1,214 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) + * + * Copyright (C) 2005 HP Labs + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + u32 mask; + + if ((port < AT91_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + if (use_pullup) + writel(1 << pin, &pio->port[port].puer); + else + writel(1 << pin, &pio->port[port].pudr); + writel(mask, &pio->port[port].per); + } + return 0; +} + +/* + * mux the pin to the "GPIO" peripheral role. + */ +int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + u32 mask; + + if ((port < AT91_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(mask, &pio->port[port].per); + } + return 0; +} + +/* + * mux the pin to the "A" internal peripheral role. + */ +int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + u32 mask; + + if ((port < AT91_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(mask, &pio->port[port].asr); + writel(mask, &pio->port[port].pdr); + } + return 0; +} + +/* + * mux the pin to the "B" internal peripheral role. + */ +int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + u32 mask; + + if ((port < AT91_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(mask, &pio->port[port].bsr); + writel(mask, &pio->port[port].pdr); + } + return 0; +} + +/* + * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and + * configure it for an input. + */ +int at91_set_pio_input(unsigned port, u32 pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + u32 mask; + + if ((port < AT91_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(mask, &pio->port[port].odr); + writel(mask, &pio->port[port].per); + } + return 0; +} + +/* + * mux the pin to the gpio controller (instead of "A" or "B" peripheral), + * and configure it for an output. + */ +int at91_set_pio_output(unsigned port, u32 pin, int value) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + u32 mask; + + if ((port < AT91_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + writel(mask, &pio->port[port].pudr); + if (value) + writel(mask, &pio->port[port].sodr); + else + writel(mask, &pio->port[port].codr); + writel(mask, &pio->port[port].oer); + writel(mask, &pio->port[port].per); + } + return 0; +} + +/* + * enable/disable the glitch filter. mostly used with IRQ handling. + */ +int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + u32 mask; + + if ((port < AT91_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + if (is_on) + writel(mask, &pio->port[port].ifer); + else + writel(mask, &pio->port[port].ifdr); + } + return 0; +} + +/* + * enable/disable the multi-driver. This is only valid for output and + * allows the output pin to run as an open collector output. + */ +int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + u32 mask; + + if ((port < AT91_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + if (is_on) + writel(mask, &pio->port[port].mder); + else + writel(mask, &pio->port[port].mddr); + } + return 0; +} + +/* + * assuming the pin is muxed as a gpio output, set its value. + */ +int at91_set_pio_value(unsigned port, unsigned pin, int value) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + u32 mask; + + if ((port < AT91_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + if (value) + writel(mask, &pio->port[port].sodr); + else + writel(mask, &pio->port[port].codr); + } + return 0; +} + +/* + * read the pin's value (works even if it's not muxed as a gpio). + */ +int at91_get_pio_value(unsigned port, unsigned pin) +{ + u32 pdsr = 0; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + u32 mask; + + if ((port < AT91_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + pdsr = readl(&pio->port[port].pdsr) & mask; + } + return pdsr != 0; +} diff --git a/include/asm-arm/arch-at91/at91_pio.h b/include/asm-arm/arch-at91/at91_pio.h index 92c3717..e5946ca 100644 --- a/include/asm-arm/arch-at91/at91_pio.h +++ b/include/asm-arm/arch-at91/at91_pio.h @@ -100,10 +100,20 @@ typedef union at91_pio { at91_port_t port[AT91_PIO_PORTS]; } at91_pio_t; +#ifdef CONFIG_AT91_GPIO +int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); +int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); +int at91_set_pio_output(unsigned port, unsigned pin, int value); +int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); +int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on); +int at91_set_pio_value(unsigned port, unsigned pin, int value); +int at91_get_pio_value(unsigned port, unsigned pin); +#endif #endif -#define AT91_PIN_TO_MASK(x) (1< Date: Wed, 3 Feb 2010 22:46:46 +0100 Subject: convert all at91 files to use at91_gpio driver syntax * convert all files cpu/../at91 to use at91_gpio driver syntax * change AT91_PINP([A-F])(\d+) to AT91_PIO_PORT\1, \2 this makes all 160 AT91_PINPxxx defines obsolete * AT91_PINPxxx defines and gpio.h can be remove, if all boards converted to new SoC access Signed-off-by: Jens Scharsig --- cpu/arm926ejs/at91/at91cap9_devices.c | 100 +++++++++++++------------- cpu/arm926ejs/at91/at91sam9260_devices.c | 100 +++++++++++++------------- cpu/arm926ejs/at91/at91sam9261_devices.c | 60 ++++++++-------- cpu/arm926ejs/at91/at91sam9263_devices.c | 104 ++++++++++++++-------------- cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 96 ++++++++++++------------- cpu/arm926ejs/at91/at91sam9rl_devices.c | 38 +++++----- 6 files changed, 249 insertions(+), 249 deletions(-) diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c index 39e405f..518a8d7 100644 --- a/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/cpu/arm926ejs/at91/at91cap9_devices.c @@ -34,29 +34,29 @@ void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0); } void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1); } void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2); } void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ + at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); } @@ -82,71 +82,71 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ + at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ + at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0); if (cs_mask & (1 << 0)) { - at91_set_B_periph(AT91_PIN_PA5, 1); + at91_set_b_periph(AT91_PIO_PORTA, 5, 1); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PA3, 1); + at91_set_b_periph(AT91_PIO_PORTA, 3, 1); } if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PD0, 1); + at91_set_b_periph(AT91_PIO_PORTD, 0, 1); } if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PD1, 1); + at91_set_b_periph(AT91_PIO_PORTD, 1, 1); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PA5, 1); + at91_set_pio_output(AT91_PIO_PORTA, 5, 1); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PA3, 1); + at91_set_pio_output(AT91_PIO_PORTA, 3, 1); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PD0, 1); + at91_set_pio_output(AT91_PIO_PORTD, 0, 1); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PD1, 1); + at91_set_pio_output(AT91_PIO_PORTD, 1, 1); } } void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI1); if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB15, 1); + at91_set_a_periph(AT91_PIO_PORTB, 15, 1); } if (cs_mask & (1 << 1)) { - at91_set_A_periph(AT91_PIN_PB16, 1); + at91_set_a_periph(AT91_PIO_PORTB, 16, 1); } if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PB17, 1); + at91_set_a_periph(AT91_PIO_PORTB, 17, 1); } if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PB18, 1); + at91_set_a_periph(AT91_PIO_PORTB, 18, 1); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PB15, 1); + at91_set_pio_output(AT91_PIO_PORTB, 15, 1); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PB16, 1); + at91_set_pio_output(AT91_PIO_PORTB, 16, 1); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PB17, 1); + at91_set_pio_output(AT91_PIO_PORTB, 17, 1); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PB18, 1); + at91_set_pio_output(AT91_PIO_PORTB, 18, 1); } } @@ -155,26 +155,26 @@ void at91_spi1_hw_init(unsigned long cs_mask) #ifdef CONFIG_MACB void at91_macb_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */ - at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */ - at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */ - at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */ - at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */ - at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */ - at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */ - at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */ - at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */ - at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */ + at91_set_a_periph(AT91_PIO_PORTB, 21, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTB, 22, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTB, 25, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 26, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 27, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTB, 23, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 24, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* EMDC */ #ifndef CONFIG_RMII - at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */ - at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ - at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ - at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ - at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ - at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ - at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ + at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ECRS */ + at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */ + at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */ + at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */ + at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */ + at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */ + at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */ + at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */ #endif } #endif @@ -182,8 +182,8 @@ void at91_macb_hw_init(void) #ifdef CONFIG_AT91_CAN void at91_can_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA12, 0); /* CAN_TX */ - at91_set_A_periph(AT91_PIN_PA13, 1); /* CAN_RX */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* CAN_TX */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* CAN_RX */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_CAN); diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c index f86cb99..68c1974 100644 --- a/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -30,29 +30,29 @@ void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); } void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); } void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); } void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */ + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); } @@ -78,71 +78,71 @@ void at91_serial_hw_init(void) #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0); if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_a_periph(AT91_PIO_PORTA, 3, 1); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PC11, 1); + at91_set_b_periph(AT91_PIO_PORTC, 11, 1); } if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PC16, 1); + at91_set_b_periph(AT91_PIO_PORTC, 16, 1); } if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PC17, 1); + at91_set_b_periph(AT91_PIO_PORTC, 17, 1); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PA3, 1); + at91_set_pio_output(AT91_PIO_PORTA, 3, 1); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PC11, 1); + at91_set_pio_output(AT91_PIO_PORTC, 11, 1); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PC16, 1); + at91_set_pio_output(AT91_PIO_PORTC, 16, 1); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PC17, 1); + at91_set_pio_output(AT91_PIO_PORTC, 17, 1); } } void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI1_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI1); if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB3, 1); + at91_set_a_periph(AT91_PIO_PORTB, 3, 1); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PC5, 1); + at91_set_b_periph(AT91_PIO_PORTC, 5, 1); } if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PC4, 1); + at91_set_b_periph(AT91_PIO_PORTC, 4, 1); } if (cs_mask & (1 << 3)) { - at91_set_gpio_output(AT91_PIN_PC3, 1); + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PB3, 1); + at91_set_pio_output(AT91_PIO_PORTB, 3, 1); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PC5, 1); + at91_set_pio_output(AT91_PIO_PORTC, 5, 1); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PC4, 1); + at91_set_pio_output(AT91_PIO_PORTC, 4, 1); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PC3, 1); + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); } } #endif @@ -150,35 +150,35 @@ void at91_spi1_hw_init(unsigned long cs_mask) #ifdef CONFIG_MACB void at91_macb_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ - at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ - at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ - at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ - at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ - at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ - at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ - at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ - at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ - at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* EMDC */ #ifndef CONFIG_RMII - at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ - at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ - at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ - at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ - at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ + at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ECRS */ + at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECOL */ + at91_set_b_periph(AT91_PIO_PORTA, 25, 0); /* ERX2 */ + at91_set_b_periph(AT91_PIO_PORTA, 26, 0); /* ERX3 */ + at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ERXCK */ #if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260) /* * use PA10, PA11 for ETX2, ETX3. * PA23 and PA24 are for TWI EEPROM */ - at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */ + at91_set_b_periph(AT91_PIO_PORTA, 10, 0); /* ETX2 */ + at91_set_b_periph(AT91_PIO_PORTA, 11, 0); /* ETX3 */ #else - at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */ + at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */ + at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */ #endif - at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ + at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */ #endif } #endif diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c index 16d411f..286e72a 100644 --- a/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -30,29 +30,29 @@ void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0); } void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1); } void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2); } void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); } @@ -78,71 +78,71 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0); if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_a_periph(AT91_PIO_PORTA, 3, 1); } if (cs_mask & (1 << 1)) { - at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_a_periph(AT91_PIO_PORTA, 4, 1); } if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PA5, 1); + at91_set_a_periph(AT91_PIO_PORTA, 5, 1); } if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PA6, 1); + at91_set_a_periph(AT91_PIO_PORTA, 6, 1); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PA3, 1); + at91_set_pio_output(AT91_PIO_PORTA, 3, 1); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PA4, 1); + at91_set_pio_output(AT91_PIO_PORTA, 4, 1); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PA5, 1); + at91_set_pio_output(AT91_PIO_PORTA, 5, 1); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PA6, 1); + at91_set_pio_output(AT91_PIO_PORTA, 6, 1); } } void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 31, 0); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* SPI1_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1); if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB28, 1); + at91_set_a_periph(AT91_PIO_PORTB, 28, 1); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PA24, 1); + at91_set_b_periph(AT91_PIO_PORTA, 24, 1); } if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PA25, 1); + at91_set_b_periph(AT91_PIO_PORTA, 25, 1); } if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PA26, 1); + at91_set_a_periph(AT91_PIO_PORTA, 26, 1); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PB28, 1); + at91_set_pio_output(AT91_PIO_PORTB, 28, 1); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PA24, 1); + at91_set_pio_output(AT91_PIO_PORTA, 24, 1); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PA25, 1); + at91_set_pio_output(AT91_PIO_PORTA, 25, 1); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PA26, 1); + at91_set_pio_output(AT91_PIO_PORTA, 26, 1); } } #endif diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c index f72efdf..90bdcc2 100644 --- a/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -34,29 +34,29 @@ void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0); } void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1); } void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2); } void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ + at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); } @@ -82,71 +82,71 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ + at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ + at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0); if (cs_mask & (1 << 0)) { - at91_set_B_periph(AT91_PIN_PA5, 1); + at91_set_b_periph(AT91_PIO_PORTA, 5, 1); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PA3, 1); + at91_set_b_periph(AT91_PIO_PORTA, 3, 1); } if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_b_periph(AT91_PIO_PORTA, 4, 1); } if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PB11, 1); + at91_set_b_periph(AT91_PIO_PORTB, 11, 1); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PA5, 1); + at91_set_pio_output(AT91_PIO_PORTA, 5, 1); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PA3, 1); + at91_set_pio_output(AT91_PIO_PORTA, 3, 1); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PA4, 1); + at91_set_pio_output(AT91_PIO_PORTA, 4, 1); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PB11, 1); + at91_set_pio_output(AT91_PIO_PORTB, 11, 1); } } void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI1); if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB15, 1); + at91_set_a_periph(AT91_PIO_PORTB, 15, 1); } if (cs_mask & (1 << 1)) { - at91_set_A_periph(AT91_PIN_PB16, 1); + at91_set_a_periph(AT91_PIO_PORTB, 16, 1); } if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PB17, 1); + at91_set_a_periph(AT91_PIO_PORTB, 17, 1); } if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PB18, 1); + at91_set_a_periph(AT91_PIO_PORTB, 18, 1); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PB15, 1); + at91_set_pio_output(AT91_PIO_PORTB, 15, 1); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PB16, 1); + at91_set_pio_output(AT91_PIO_PORTB, 16, 1); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PB17, 1); + at91_set_pio_output(AT91_PIO_PORTB, 17, 1); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PB18, 1); + at91_set_pio_output(AT91_PIO_PORTB, 18, 1); } } #endif @@ -154,26 +154,26 @@ void at91_spi1_hw_init(unsigned long cs_mask) #ifdef CONFIG_MACB void at91_macb_hw_init(void) { - at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */ - at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */ - at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */ - at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */ - at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */ - at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */ - at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */ - at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */ - at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ - at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ + at91_set_a_periph(AT91_PIO_PORTE, 21, 0); /* ETXCK_EREFCK */ + at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTE, 25, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTE, 26, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTE, 27, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTE, 28, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTE, 23, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTE, 24, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTE, 30, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTE, 29, 0); /* EMDC */ #ifndef CONFIG_RMII - at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ - at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ - at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ - at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ - at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ - at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ - at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ + at91_set_a_periph(AT91_PIO_PORTE, 22, 0); /* ECRS */ + at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */ + at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */ + at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */ + at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */ + at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */ + at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */ + at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */ #endif } #endif @@ -182,16 +182,16 @@ void at91_macb_hw_init(void) void at91_uhp_hw_init(void) { /* Enable VBus on UHP ports */ - at91_set_gpio_output(AT91_PIN_PA21, 0); - at91_set_gpio_output(AT91_PIN_PA24, 0); + at91_set_pio_output(AT91_PIO_PORTA, 21, 0); + at91_set_pio_output(AT91_PIO_PORTA, 24, 0); } #endif #ifdef CONFIG_AT91_CAN void at91_can_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA13, 0); /* CAN_TX */ - at91_set_A_periph(AT91_PIN_PA14, 1); /* CAN_RX */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_CAN); diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 98d90f2..6881e46 100644 --- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -30,29 +30,29 @@ void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0); } void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1); } void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD6, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PD7, 0); /* RXD2 */ + at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2); } void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);; } @@ -78,71 +78,71 @@ void at91_serial_hw_init(void) #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI0_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0); if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB3, 0); + at91_set_a_periph(AT91_PIO_PORTB, 3, 0); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PB18, 0); + at91_set_b_periph(AT91_PIO_PORTB, 18, 0); } if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PB19, 0); + at91_set_b_periph(AT91_PIO_PORTB, 19, 0); } if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PD27, 0); + at91_set_b_periph(AT91_PIO_PORTD, 27, 0); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PB3, 0); + at91_set_pio_output(AT91_PIO_PORTB, 3, 0); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PB18, 0); + at91_set_pio_output(AT91_PIO_PORTB, 18, 0); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PB19, 0); + at91_set_pio_output(AT91_PIO_PORTB, 19, 0); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PD27, 0); + at91_set_pio_output(AT91_PIO_PORTD, 27, 0); } } void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* SPI1_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI1); if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB17, 0); + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PD28, 0); + at91_set_b_periph(AT91_PIO_PORTD, 28, 0); } if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PD18, 0); + at91_set_a_periph(AT91_PIO_PORTD, 18, 0); } if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PD19, 0); + at91_set_a_periph(AT91_PIO_PORTD, 19, 0); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PB17, 0); + at91_set_pio_output(AT91_PIO_PORTB, 17, 0); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PD28, 0); + at91_set_pio_output(AT91_PIO_PORTD, 28, 0); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PD18, 0); + at91_set_pio_output(AT91_PIO_PORTD, 18, 0); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PD19, 0); + at91_set_pio_output(AT91_PIO_PORTD, 19, 0); } } @@ -151,25 +151,25 @@ void at91_spi1_hw_init(unsigned long cs_mask) #ifdef CONFIG_MACB void at91_macb_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */ - at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */ - at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ - at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ - at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */ - at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */ - at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */ - at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */ - at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */ - at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */ + at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */ #ifndef CONFIG_RMII - at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */ - at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */ - at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */ - at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */ - at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */ - at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */ - at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */ + at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */ + at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */ + at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */ + at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */ + at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */ + at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */ + at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */ + at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */ #endif } #endif diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c index ebed193..d74e144 100644 --- a/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -30,29 +30,29 @@ void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0); } void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1); } void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2); } void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */ + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); } @@ -78,36 +78,36 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */ + at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI); if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PA28, 1); + at91_set_a_periph(AT91_PIO_PORTA, 28, 1); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PB7, 1); + at91_set_b_periph(AT91_PIO_PORTB, 7, 1); } if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PD8, 1); + at91_set_a_periph(AT91_PIO_PORTD, 8, 1); } if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PD9, 1); + at91_set_b_periph(AT91_PIO_PORTD, 9, 1); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PA28, 1); + at91_set_pio_output(AT91_PIO_PORTA, 28, 1); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PB7, 1); + at91_set_pio_output(AT91_PIO_PORTB, 7, 1); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PD8, 1); + at91_set_pio_output(AT91_PIO_PORTD, 8, 1); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PD9, 1); + at91_set_pio_output(AT91_PIO_PORTD, 9, 1); } } #endif -- cgit v1.1 From 0cf0b93161beb3f3ed5e37e6112aedf15da17e8a Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Wed, 3 Feb 2010 22:46:58 +0100 Subject: convert common files to new SoC access * add's a warning to all files, which need update to new SoC access * convert common files in cpu/../at91 and a lot of drivers to use c stucture SoC access Signed-off-by: Jens Scharsig --- cpu/arm926ejs/at91/at91cap9_devices.c | 28 ++++++--- cpu/arm926ejs/at91/at91sam9260_devices.c | 24 ++++++-- cpu/arm926ejs/at91/at91sam9261_devices.c | 24 ++++++-- cpu/arm926ejs/at91/at91sam9263_devices.c | 33 +++++++--- cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 24 ++++++-- cpu/arm926ejs/at91/at91sam9rl_devices.c | 20 ++++-- cpu/arm926ejs/at91/clock.c | 51 +++++++++------- cpu/arm926ejs/at91/cpu.c | 4 ++ cpu/arm926ejs/at91/led.c | 1 + cpu/arm926ejs/at91/lowlevel_init.S | 95 ++++++++++++++--------------- cpu/arm926ejs/at91/reset.c | 8 ++- cpu/arm926ejs/at91/timer.c | 17 ++++-- drivers/i2c/soft_i2c.c | 11 ++-- drivers/serial/at91rm9200_usart.c | 8 +++ drivers/serial/atmel_usart.c | 4 ++ drivers/spi/atmel_dataflash_spi.c | 4 ++ drivers/usb/host/ohci-at91.c | 5 ++ drivers/video/bus_vcxk.c | 22 ++++++- include/i2c.h | 5 ++ 19 files changed, 261 insertions(+), 127 deletions(-) diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c index 518a8d7..2d878fd 100644 --- a/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/cpu/arm926ejs/at91/at91cap9_devices.c @@ -34,30 +34,38 @@ void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0); + writel(1 << AT91CAP9_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1); + writel(1 << AT91CAP9_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2); + writel(1 << AT91CAP9_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -82,12 +90,14 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0); + writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_b_periph(AT91_PIO_PORTA, 5, 1); @@ -117,12 +127,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI1); + writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 15, 1); @@ -182,10 +194,12 @@ void at91_macb_hw_init(void) #ifdef CONFIG_AT91_CAN void at91_can_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* CAN_TX */ at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* CAN_RX */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_CAN); + writel(1 << AT91CAP9_ID_CAN, &pmc->pcer); } #endif diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c index 68c1974..77d49ab 100644 --- a/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -30,30 +30,38 @@ void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); + writel(1 << AT91SAM9260_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); + writel(1 << AT91SAM9260_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); + writel(1 << AT91SAM9260_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -78,12 +86,14 @@ void at91_serial_hw_init(void) #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0); + writel(1 << AT91SAM9260_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); @@ -113,12 +123,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI1_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI1); + writel(1 << AT91SAM9260_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 3, 1); diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c index 286e72a..b4353ef 100644 --- a/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -30,30 +30,38 @@ void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0); + writel(1 << AT91SAM9261_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1); + writel(1 << AT91SAM9261_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2); + writel(1 << AT91SAM9261_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -78,12 +86,14 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0); + writel(1 << AT91SAM9261_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); @@ -113,12 +123,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 31, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* SPI1_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1); + writel(1 << AT91SAM9261_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 28, 1); diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c index 90bdcc2..deda3e5 100644 --- a/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -27,37 +27,46 @@ */ #include +#include +#include #include #include -#include -#include +#include void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0); + writel(1 << AT91SAM9263_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1); + writel(1 << AT91SAM9263_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2); + writel(1 << AT91SAM9263_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -82,12 +91,14 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0); + writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_b_periph(AT91_PIO_PORTA, 5, 1); @@ -117,12 +128,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI1); + writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 15, 1); @@ -190,10 +203,12 @@ void at91_uhp_hw_init(void) #ifdef CONFIG_AT91_CAN void at91_can_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */ at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_CAN); + writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer); } #endif diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 6881e46..4ad9b1f 100644 --- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -30,30 +30,38 @@ void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0); + writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1); + writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2); + writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);; + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -78,12 +86,14 @@ void at91_serial_hw_init(void) #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0); + writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 3, 0); @@ -113,12 +123,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* SPI1_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI1); + writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 17, 0); diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c index d74e144..4f570f4 100644 --- a/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -30,30 +30,38 @@ void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0); + writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1); + writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2); + writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -78,12 +86,14 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI); + writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 28, 1); diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c index 574f488..7e03907 100644 --- a/cpu/arm926ejs/at91/clock.c +++ b/cpu/arm926ejs/at91/clock.c @@ -13,9 +13,9 @@ #include #include +#include #include #include -#include static unsigned long cpu_clk_rate_hz; static unsigned long main_clk_rate_hz; @@ -57,14 +57,14 @@ u32 get_pllb_init(void) static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { - case AT91_PMC_CSS_SLOW: - return AT91_SLOW_CLOCK; - case AT91_PMC_CSS_MAIN: - return main_clk_rate_hz; - case AT91_PMC_CSS_PLLA: - return plla_rate_hz; - case AT91_PMC_CSS_PLLB: - return pllb_rate_hz; + case AT91_PMC_MCKR_CSS_SLOW: + return AT91_SLOW_CLOCK; + case AT91_PMC_MCKR_CSS_MAIN: + return main_clk_rate_hz; + case AT91_PMC_MCKR_CSS_PLLA: + return plla_rate_hz; + case AT91_PMC_MCKR_CSS_PLLB: + return pllb_rate_hz; } return 0; @@ -146,6 +146,7 @@ static u32 at91_pll_rate(u32 freq, u32 reg) int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; #ifndef AT91_MAIN_CLOCK unsigned tmp; /* @@ -164,7 +165,7 @@ int at91_clock_init(unsigned long main_clock) main_clk_rate_hz = main_clock; /* report if PLLA is more than mildly overclocked */ - plla_rate_hz = at91_pll_rate(main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); #ifdef CONFIG_USB_ATMEL /* @@ -174,7 +175,7 @@ int at91_clock_init(unsigned long main_clock) * REVISIT: assumes MCK doesn't derive from PLLB! */ at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | - AT91_PMC_USB96M; + AT91_PMC_PLLBR_USBDIV_2; pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init); #endif @@ -182,28 +183,32 @@ int at91_clock_init(unsigned long main_clock) * MCK and CPU derive from one of those primary clocks. * For now, assume this parentage won't change. */ - mckr = at91_sys_read(AT91_PMC_MCKR); + mckr = readl(&pmc->mckr); #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) /* plla divisor by 2 */ plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); #endif - freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS); + mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); + freq = mck_rate_hz; - freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ + freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ #if defined(CONFIG_AT91RM9200) - mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + /* mdiv */ + mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #elif defined(CONFIG_AT91SAM9G20) - mck_rate_hz = (mckr & AT91_PMC_MDIV) ? - freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ - if (mckr & AT91_PMC_PDIV) - freq /= 2; /* processor clock division */ + /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ + mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? + freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; + if (mckr & AT91_PMC_MCKR_MDIV_MASK) + freq /= 2; /* processor clock division */ #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) - mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? - freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3 + ? freq / 3 + : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #else - mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #endif cpu_clk_rate_hz = freq; - return 0; + return 0; } diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c index f2f7b62..993b299 100644 --- a/cpu/arm926ejs/at91/cpu.c +++ b/cpu/arm926ejs/at91/cpu.c @@ -22,6 +22,10 @@ */ #include +#ifdef CONFIG_AT91_LEGACY +#warning Your board is using legacy SoC access. Please update! +#endif + #include #include #include diff --git a/cpu/arm926ejs/at91/led.c b/cpu/arm926ejs/at91/led.c index be68f59..0a315c4 100644 --- a/cpu/arm926ejs/at91/led.c +++ b/cpu/arm926ejs/at91/led.c @@ -24,6 +24,7 @@ #include #include +#include #include #include diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S index f11ebc6..559c35c 100644 --- a/cpu/arm926ejs/at91/lowlevel_init.S +++ b/cpu/arm926ejs/at91/lowlevel_init.S @@ -27,15 +27,20 @@ */ #include -#include #include #include -#include -#include #include -#include +#include +#include #include #include +#include +#ifdef CONFIG_AT91_LEGACY +#include +#endif +#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL +#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL +#endif _TEXT_BASE: .word TEXT_BASE @@ -75,7 +80,7 @@ POS1: * - Check if the PLL is already initialized * ---------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r1, =(AT91_ASM_PMC_MCKR) ldr r0, [r1] and r0, r0, #3 cmp r0, #0 @@ -85,18 +90,18 @@ POS1: * - Enable the Main Oscillator * --------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) - ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) + ldr r1, =(AT91_ASM_PMC_MOR) + ldr r2, =(AT91_ASM_PMC_SR) /* Main oscillator Enable register PMC_MOR: */ ldr r0, =CONFIG_SYS_MOR_VAL str r0, [r1] /* Reading the PMC Status to detect when the Main Oscillator is enabled */ - mov r4, #AT91_PMC_MOSCS + mov r4, #AT91_PMC_IXR_MOSCS MOSCS_Loop: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_MOSCS + cmp r3, #AT91_PMC_IXR_MOSCS bne MOSCS_Loop /* ---------------------------------------------------------------------------- @@ -105,16 +110,16 @@ MOSCS_Loop: * Setup PLLA * ---------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) + ldr r1, =(AT91_ASM_PMC_PLLAR) ldr r0, =CONFIG_SYS_PLLAR_VAL str r0, [r1] /* Reading the PMC Status register to detect when the PLLA is locked */ - mov r4, #AT91_PMC_LOCKA + mov r4, #AT91_PMC_IXR_LOCKA MOSCS_Loop1: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_LOCKA + cmp r3, #AT91_PMC_IXR_LOCKA bne MOSCS_Loop1 /* ---------------------------------------------------------------------------- @@ -123,38 +128,37 @@ MOSCS_Loop1: * - Switch on the Main Oscillator * ---------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r1, =(AT91_ASM_PMC_MCKR) /* -Master Clock Controller register PMC_MCKR */ ldr r0, =CONFIG_SYS_MCKR1_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY + mov r4, #AT91_PMC_IXR_MCKRDY MCKRDY_Loop: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY + cmp r3, #AT91_PMC_IXR_MCKRDY bne MCKRDY_Loop ldr r0, =CONFIG_SYS_MCKR2_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY + mov r4, #AT91_PMC_IXR_MCKRDY MCKRDY_Loop1: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY + cmp r3, #AT91_PMC_IXR_MCKRDY bne MCKRDY_Loop1 - PLL_setup_end: /* ---------------------------------------------------------------------------- * - memory control configuration 2 * ---------------------------------------------------------------------------- */ - ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR) + ldr r0, =(AT91_ASM_SDRAMC_TR) ldr r1, [r0] cmp r1, #0 bne SDRAM_setup_end @@ -166,7 +170,6 @@ PLL_setup_end: sub r2, r2, r1 add r0, r0, r5 add r2, r2, r5 - 2: /* the address */ ldr r1, [r0], #4 @@ -183,60 +186,53 @@ SDRAM_setup_end: .ltorg SMRDATA: - .word (AT91_BASE_SYS + AT91_WDT_MR) + .word AT91_ASM_WDT_MR .word CONFIG_SYS_WDTC_WDMR_VAL - /* configure PIOx as EBI0 D[16-31] */ #if defined(CONFIG_AT91SAM9263) - .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR) + .word AT91_ASM_PIOD_PDR .word CONFIG_SYS_PIOD_PDR_VAL1 - .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR) + .word AT91_ASM_PIOD_PUDR .word CONFIG_SYS_PIOD_PPUDR_VAL - .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) + .word AT91_ASM_PIOD_ASR .word CONFIG_SYS_PIOD_PPUDR_VAL #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ || defined(CONFIG_AT91SAM9G20) - .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) + .word AT91_ASM_PIOC_PDR .word CONFIG_SYS_PIOC_PDR_VAL1 - .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) + .word AT91_ASM_PIOC_PUDR .word CONFIG_SYS_PIOC_PPUDR_VAL #endif - -#if defined(AT91_MATRIX_EBI0CSA) - .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA) - .word CONFIG_SYS_MATRIX_EBI0CSA_VAL -#else /* AT91_MATRIX_EBICSA */ - .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA) + .word AT91_ASM_MATRIX_CSA0 .word CONFIG_SYS_MATRIX_EBICSA_VAL -#endif /* flash */ - .word (AT91_BASE_SYS + AT91_SMC_MODE(0)) + .word AT91_ASM_SMC_MODE0 .word CONFIG_SYS_SMC0_MODE0_VAL - .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0)) + .word AT91_ASM_SMC_CYCLE0 .word CONFIG_SYS_SMC0_CYCLE0_VAL - .word (AT91_BASE_SYS + AT91_SMC_PULSE(0)) + .word AT91_ASM_SMC_PULSE0 .word CONFIG_SYS_SMC0_PULSE0_VAL - .word (AT91_BASE_SYS + AT91_SMC_SETUP(0)) + .word AT91_ASM_SMC_SETUP0 .word CONFIG_SYS_SMC0_SETUP0_VAL SMRDATA1: - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_CR) + .word AT91_ASM_SDRAMC_CR .word CONFIG_SYS_SDRC_CR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MDR) + .word AT91_ASM_SDRAMC_MDR .word CONFIG_SYS_SDRC_MDR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL2 @@ -254,26 +250,25 @@ SMRDATA1: .word CONFIG_SYS_SDRAM_VAL8 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL9 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL4 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL10 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL5 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL11 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL2 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL12 /* User reset enable*/ - .word (AT91_BASE_SYS + AT91_RSTC_MR) + .word AT91_ASM_RSTC_MR .word CONFIG_SYS_RSTC_RMR_VAL #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP /* MATRIX_MCFG - REMAP all masters */ - .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0) + .word AT91_ASM_MATRIX_MCFG .word 0x1FF #endif - SMRDATA2: .word 0 diff --git a/cpu/arm926ejs/at91/reset.c b/cpu/arm926ejs/at91/reset.c index f963e14..1b67e77 100644 --- a/cpu/arm926ejs/at91/reset.c +++ b/cpu/arm926ejs/at91/reset.c @@ -32,10 +32,12 @@ */ void reset_cpu(ulong ignored) { + at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; + /* this is the way Linux does it */ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | - AT91_RSTC_PROCRST | - AT91_RSTC_PERRST); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | AT91_RSTC_CR_PERRST, + &rstc->cr); while (1); /* Never reached */ diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c index 7352b5c..d21eebf 100644 --- a/cpu/arm926ejs/at91/timer.c +++ b/cpu/arm926ejs/at91/timer.c @@ -35,8 +35,6 @@ * setting the 20 bit counter period to its maximum (0xfffff). */ #define TIMER_LOAD_VAL 0xfffff -#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR) -#define READ_TIMER at91_sys_read(AT91_PIT_PIIR) static ulong timestamp; static ulong lastinc; @@ -61,14 +59,16 @@ static inline unsigned long long usec_to_tick(unsigned long long usec) /* nothing really to do with interrupts, just starts up a counter. */ int timer_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; /* * Enable PITC Clock * The clock is already enabled for system controller in boot */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); /* Enable PITC */ - at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN); + writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); reset_timer_masked(); @@ -82,7 +82,9 @@ int timer_init(void) */ unsigned long long get_ticks(void) { - ulong now = READ_TIMER; + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + + ulong now = readl(&pit->piir); if (now >= lastinc) /* normal mode (non roll) */ /* move stamp forward with absolut diff ticks */ @@ -96,7 +98,10 @@ unsigned long long get_ticks(void) void reset_timer_masked(void) { /* reset time */ - lastinc = READ_TIMER; /* capture current incrementer value time */ + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + + /* capture current incrementer value time */ + lastinc = readl(&pit->piir); timestamp = 0; /* start "advancing" time stamp from 0 */ } diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 9a48783..e0cf1e1 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -30,14 +30,15 @@ #include #include #endif -#ifdef CONFIG_AT91RM9200 /* need this for the at91rm9200 */ +#if defined(CONFIG_AT91RM9200) || \ + defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ + defined(CONFIG_AT91SAM9263) #include #include -#endif -#ifdef CONFIG_AT91SAM9263 /* only valid for AT91SAM9263 */ -#include +#include +#ifdef CONFIG_AT91_LEGACY #include -#include +#endif #endif #ifdef CONFIG_IXP425 /* only valid for IXP425 */ #include diff --git a/drivers/serial/at91rm9200_usart.c b/drivers/serial/at91rm9200_usart.c index 858bde9..05ebbc3 100644 --- a/drivers/serial/at91rm9200_usart.c +++ b/drivers/serial/at91rm9200_usart.c @@ -30,8 +30,16 @@ */ #include + +#ifndef CONFIG_AT91_LEGACY #include #include +#define CONFIG_AT91_LEGACY +#include +#warning Please update to use C structur SoC access ! +#else +#include +#endif DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index f50552a..cad3412 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -16,6 +16,10 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include #include diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 3a648e6..4a5c4aa 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -20,6 +20,10 @@ */ #include +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include #include #include diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 226859a..29f3ba1 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -25,6 +25,11 @@ #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif + #include #include #include diff --git a/drivers/video/bus_vcxk.c b/drivers/video/bus_vcxk.c index 7726bb3..67a59a7 100644 --- a/drivers/video/bus_vcxk.c +++ b/drivers/video/bus_vcxk.c @@ -31,9 +31,29 @@ vu_long *vcxk_bws_long = ((vu_long *) (CONFIG_SYS_VCXK_BASE)); #ifdef CONFIG_AT91RM9200 #include + #include + #ifndef VCBITMASK #define VCBITMASK(bitno) (0x0001 << (bitno % 16)) #endif +#ifndef CONFIG_AT91_LEGACY +at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; +#define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ + do { \ + writel(PIN, &pio->PORT.per); \ + writel(PIN, &pio->PORT.DDR); \ + writel(PIN, &pio->PORT.mddr); \ + if (!I0O1) \ + writel(PIN, &pio->PORT.puer); \ + } while (0); + +#define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); +#define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); + +#define VCXK_ACKNOWLEDGE \ + (!(readl(&pio->CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT.pdsr) & \ + CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN)) +#else #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ ((AT91PS_PIO) PORT)->PIO_PER = PIN; \ ((AT91PS_PIO) PORT)->DDR = PIN; \ @@ -46,7 +66,7 @@ vu_long *vcxk_bws_long = ((vu_long *) (CONFIG_SYS_VCXK_BASE)); #define VCXK_ACKNOWLEDGE \ (!(((AT91PS_PIO) CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT)->\ PIO_PDSR & CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN)) - +#endif #elif defined(CONFIG_MCF52x2) #include #ifndef VCBITMASK diff --git a/include/i2c.h b/include/i2c.h index b754769..31088b6 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -74,6 +74,11 @@ # define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); # elif defined(CONFIG_8xx) # define I2C_SOFT_DECLARATIONS volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + +# elif (defined(CONFIG_AT91RM9200) || \ + defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ + defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY) +# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; # else # define I2C_SOFT_DECLARATIONS # endif -- cgit v1.1 From 1b34f00c28a3023693d9b31e7bd1a9212af8352f Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Wed, 3 Feb 2010 22:47:18 +0100 Subject: update at91sam9263ek board to new SoC access * convert at91sam9263ek board to use c stucture SoC access * change gpio access to at91_gpio syntax Signed-off-by: Jens Scharsig --- board/atmel/at91sam9263ek/at91sam9263ek.c | 151 +++++++++++++++--------------- board/atmel/at91sam9263ek/led.c | 21 +++-- include/configs/at91sam9263ek.h | 88 ++++++++--------- 3 files changed, 132 insertions(+), 128 deletions(-) diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 0b7065b..8ab45af 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -25,13 +25,13 @@ #include #include #include -#include #include #include #include #include +#include +#include #include -#include #include #include #include @@ -52,49 +52,57 @@ DECLARE_GLOBAL_DATA_PTR; static void at91sam9263ek_nand_hw_init(void) { unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + /* Enable CS3 */ + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBI0CSA); - at91_sys_write(AT91_MATRIX_EBI0CSA, - csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | - 1 << AT91SAM9263_ID_PIOCDE); + writel(1 << AT91SAM9263_ID_PIOA | 1 << AT91SAM9263_ID_PIOCDE, + &pmc->pcer); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif #ifdef CONFIG_MACB static void at91sam9263ek_macb_hw_init(void) { - unsigned long rstc; - + unsigned long erstl; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); /* * Disable pull-up on: @@ -104,35 +112,27 @@ static void at91sam9263ek_macb_hw_init(void) * * PHY has internal pull-down */ - writel(pin_to_mask(AT91_PIN_PC25), - pin_to_controller(AT91_PIN_PC0) + PIO_PUDR); - writel(pin_to_mask(AT91_PIN_PE25) | - pin_to_mask(AT91_PIN_PE26), - pin_to_controller(AT91_PIN_PE0) + PIO_PUDR); - rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + writel(1 << 25, &pio->pioc.pudr); + writel((1 << 25) | (1 <<26), &pio->pioe.pudr); - /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + /* Need to reset PHY -> 500ms reset */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PC25), - pin_to_controller(AT91_PIN_PC0) + PIO_PUER); - writel(pin_to_mask(AT91_PIN_PE25) | - pin_to_mask(AT91_PIN_PE26), - pin_to_controller(AT91_PIN_PE0) + PIO_PUER); + writel(1 << 25, &pio->pioc.puer); + writel((1 << 25) | (1 <<26), &pio->pioe.puer); at91_macb_hw_init(); } @@ -158,41 +158,42 @@ vidinfo_t panel_info = { void lcd_enable(void) { - at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */ + at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */ } void lcd_disable(void) { - at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */ + at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */ } static void at91sam9263ek_lcd_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ - at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ - at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ - at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ - at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ - at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ - at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ - at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ - at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ - at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ - - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC); - + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ + at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ + at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ + at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ + + writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer); gd->fb_base = AT91SAM9263_SRAM0_BASE; } @@ -258,7 +259,7 @@ int board_init(void) at91sam9263ek_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */ + at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */ at91_spi0_hw_init(1 << 0); #endif #ifdef CONFIG_MACB @@ -297,7 +298,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *) AT91_EMAC_BASE, 0x00); #endif return rc; } diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c index 82c5388..fa1f05b 100644 --- a/board/atmel/at91sam9263ek/led.c +++ b/board/atmel/at91sam9263ek/led.c @@ -23,22 +23,25 @@ */ #include -#include +#include #include +#include #include #include void coloured_LED_init(void) { /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB | - 1 << AT91SAM9263_ID_PIOCDE); + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_set_gpio_output(CONFIG_RED_LED, 1); - at91_set_gpio_output(CONFIG_GREEN_LED, 1); - at91_set_gpio_output(CONFIG_YELLOW_LED, 1); + writel(1 << AT91SAM9263_ID_PIOB | 1 << AT91SAM9263_ID_PIOCDE, + &pmc->pcer); - at91_set_gpio_value(CONFIG_RED_LED, 0); - at91_set_gpio_value(CONFIG_GREEN_LED, 1); - at91_set_gpio_value(CONFIG_YELLOW_LED, 1); + at91_set_pio_output(CONFIG_RED_LED, 1); + at91_set_pio_output(CONFIG_GREEN_LED, 1); + at91_set_pio_output(CONFIG_YELLOW_LED, 1); + + at91_set_pio_value(CONFIG_RED_LED, 0); + at91_set_pio_value(CONFIG_GREEN_LED, 1); + at91_set_pio_value(CONFIG_YELLOW_LED, 1); } diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index e39762b..5a46d6a 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -27,8 +27,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY - /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define CONFIG_SYS_HZ 1000 @@ -72,9 +70,9 @@ /* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */ -#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */ -#define CONFIG_YELLOW_LED AT91_PIN_PC29 /* this is the user2 led */ +#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* the power led */ +#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* the user1 led */ +#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 29 /* the user2 led */ #define CONFIG_BOOTDELAY 3 @@ -150,39 +148,36 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define MASTER_PLL_MUL 171 #define MASTER_PLL_DIV 14 +#define MASTER_PLL_OUT 3 /* clocks */ #define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ - AT91_PMC_PLLCOUNT | /* PLL Counter */ \ - (2 << 28) | /* PLL Clock Frequency Range */ \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) + (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLAR_29 | \ + AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ + AT91_PMC_PLLXR_PLLCOUNT(63) | \ + AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ + AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) + (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) + (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) /* define PDC[31:16] as DATA[31:16] */ #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ - (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \ - AT91_MATRIX_EBI0_CS1A_SDRAMC) +#define CONFIG_SYS_MATRIX_EBICSA_VAL \ + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ + AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ @@ -224,33 +219,32 @@ #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) #define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) #define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ #define CONFIG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) + AT91_RSTC_MR_URSTEN | \ + AT91_RSTC_MR_ERSTL(15)) /* Disable Watchdog */ #define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xfff) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xfff)) + #endif #else @@ -267,9 +261,15 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 +/* +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +*/ + +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Ethernet */ -- cgit v1.1 From 98250e8e17fc76b3981708c6e63d41f875bf0359 Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Wed, 3 Feb 2010 22:47:35 +0100 Subject: prepare joining at91rm9200 into at91 * prepare joining at91 and at91rm9200 * add modified copy of soc files to cpu/arm920t/at91 to make possible to compile at91rm9200 boards in at91 tree instead of at91rm9200 * add header files with c structure defs for AT91 MC, ST and TC * the new cpu files are using at91 c structure soc access * please read README.soc-at91 for details Signed-off-by: Jens Scharsig --- cpu/arm920t/at91/Makefile | 47 ++++++++++ cpu/arm920t/at91/lowlevel_init.S | 164 +++++++++++++++++++++++++++++++++ cpu/arm920t/at91/reset.c | 59 ++++++++++++ cpu/arm920t/at91/timer.c | 163 ++++++++++++++++++++++++++++++++ cpu/arm920t/cpu.c | 4 + doc/README.at91-soc | 23 +++++ include/asm-arm/arch-at91/at91_mc.h | 97 +++++++++++++++++++ include/asm-arm/arch-at91/at91_pio.h | 14 ++- include/asm-arm/arch-at91/at91_st.h | 46 +++++++++ include/asm-arm/arch-at91/at91_tc.h | 77 ++++++++++++++++ include/asm-arm/arch-at91/at91rm9200.h | 135 +++++++++++++++++++++++++++ include/asm-arm/arch-at91/hardware.h | 2 +- 12 files changed, 825 insertions(+), 6 deletions(-) create mode 100644 cpu/arm920t/at91/Makefile create mode 100644 cpu/arm920t/at91/lowlevel_init.S create mode 100644 cpu/arm920t/at91/reset.c create mode 100644 cpu/arm920t/at91/timer.c create mode 100644 include/asm-arm/arch-at91/at91_mc.h create mode 100644 include/asm-arm/arch-at91/at91_st.h create mode 100644 include/asm-arm/arch-at91/at91_tc.h create mode 100644 include/asm-arm/arch-at91/at91rm9200.h diff --git a/cpu/arm920t/at91/Makefile b/cpu/arm920t/at91/Makefile new file mode 100644 index 0000000..d8a4383 --- /dev/null +++ b/cpu/arm920t/at91/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +SOBJS += lowlevel_init.o +COBJS += reset.o +COBJS += timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm920t/at91/lowlevel_init.S b/cpu/arm920t/at91/lowlevel_init.S new file mode 100644 index 0000000..22fc86c --- /dev/null +++ b/cpu/arm920t/at91/lowlevel_init.S @@ -0,0 +1,164 @@ +/* + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the at91rm9200dk board by + * (C) Copyright 2004 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +#include +#include +#include +#include + +#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */ + +_MTEXT_BASE: +#undef START_FROM_MEM +#ifdef START_FROM_MEM + .word TEXT_BASE-PHYS_FLASH_1 +#else + .word TEXT_BASE +#endif + +.globl lowlevel_init +lowlevel_init: + ldr r1, =AT91_ASM_PMC_MOR + /* Main oscillator Enable register */ +#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR + ldr r0, =0x0000FF01 /* Enable main oscillator */ +#else + ldr r0, =0x0000FF00 /* Disable main oscillator */ +#endif + str r0, [r1] /*AT91C_CKGR_MOR] */ + /* Add loop to compensate Main Oscillator startup time */ + ldr r0, =0x00000010 +LoopOsc: + subs r0, r0, #1 + bhi LoopOsc + + /* memory control configuration */ + /* this isn't very elegant, but what the heck */ + ldr r0, =SMRDATA + ldr r1, _MTEXT_BASE + sub r0, r0, r1 + add r2, r0, #80 +pllloop: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne pllloop + /* delay - this is all done by guess */ + ldr r0, =0x00010000 + /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */ +lock: + subs r0, r0, #1 + bhi lock + ldr r0, =SMRDATA1 + ldr r1, _MTEXT_BASE + sub r0, r0, r1 + add r2, r0, #176 +sdinit: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne sdinit + + /* switch from FastBus to Asynchronous clock mode */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #ARM920T_CONTROL + mcr p15, 0, r0, c1, c0, 0 + + /* everything is fine now */ + mov pc, lr + + .ltorg + +SMRDATA: + .word AT91_ASM_MC_EBI_CFG + .word CONFIG_SYS_EBI_CFGR_VAL + .word AT91_ASM_MC_SMC_CSR0 + .word CONFIG_SYS_SMC_CSR0_VAL + .word AT91_ASM_PMC_PLLAR + .word CONFIG_SYS_PLLAR_VAL + .word AT91_ASM_PMC_PLLBR + .word CONFIG_SYS_PLLBR_VAL + .word AT91_ASM_PMC_MCKR + .word CONFIG_SYS_MCKR_VAL + /* here there's a delay */ +SMRDATA1: + .word AT91_ASM_PIOC_ASR + .word CONFIG_SYS_PIOC_ASR_VAL + .word AT91_ASM_PIOC_BSR + .word CONFIG_SYS_PIOC_BSR_VAL + .word AT91_ASM_PIOC_PDR + .word CONFIG_SYS_PIOC_PDR_VAL + .word AT91_ASM_MC_EBI_CSA + .word CONFIG_SYS_EBI_CSA_VAL + .word AT91_ASM_MC_SDRAMC_CR + .word CONFIG_SYS_SDRC_CR_VAL + .word AT91_ASM_MC_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word AT91_ASM_MC_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL1 + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word AT91_ASM_MC_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL2 + .word CONFIG_SYS_SDRAM1 + .word CONFIG_SYS_SDRAM_VAL + .word AT91_ASM_MC_SDRAMC_TR + .word CONFIG_SYS_SDRC_TR_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word AT91_ASM_MC_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL3 + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + /* SMRDATA1 is 176 bytes long */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/cpu/arm920t/at91/reset.c b/cpu/arm920t/at91/reset.c new file mode 100644 index 0000000..ce9c156 --- /dev/null +++ b/cpu/arm920t/at91/reset.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2002 + * Lineo, Inc. + * Bernhard Kuhn + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +void board_reset(void) __attribute__((__weak__)); + +void reset_cpu(ulong ignored) +{ + at91_st_t *st = (at91_st_t *) AT91_ST_BASE; +#if defined(CONFIG_AT91RM9200_USART) + /*shutdown the console to avoid strange chars during reset */ + serial_exit(); +#endif + + if (board_reset) + board_reset(); + + /* Reset the cpu by setting up the watchdog timer */ + writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2), + &st->wdmr); + writel(AT91_ST_CR_WDRST, &st->cr); + /* and let it timeout */ + while (1) + ; + /* Never reached */ +} diff --git a/cpu/arm920t/at91/timer.c b/cpu/arm920t/at91/timer.c new file mode 100644 index 0000000..91377d4 --- /dev/null +++ b/cpu/arm920t/at91/timer.c @@ -0,0 +1,163 @@ +/* + * (C) Copyright 2002 + * Lineo, Inc. + * Bernhard Kuhn + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include +#include +#include +#include + +/* the number of clocks per CONFIG_SYS_HZ */ +#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) + +static u32 timestamp; +static u32 lastinc; + +int timer_init(void) +{ + at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + /* enables TC1.0 clock */ + writel(1 << AT91_ID_TC0, &pmc->pcer); /* enable clock */ + + writel(0, &tc->bcr); + writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE | + AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr); + + writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr); + /* set to MCLK/2 and restart the timer + when the value in TC_RC is reached */ + writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr); + + writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */ + writel(TIMER_LOAD_VAL, &tc->tc[0].rc); + + writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr); + lastinc = 0; + timestamp = 0; + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void __udelay(unsigned long usec) +{ + udelay_masked(usec); +} + +void reset_timer_masked(void) +{ + /* reset time */ + at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE; + lastinc = readl(&tc->tc[0].cv) & 0x0000ffff; + timestamp = 0; +} + +ulong get_timer_raw(void) +{ + at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE; + u32 now; + + now = readl(&tc->tc[0].cv) & 0x0000ffff; + + if (now >= lastinc) { + /* normal mode */ + timestamp += now - lastinc; + } else { + /* we have an overflow ... */ + timestamp += now + TIMER_LOAD_VAL - lastinc; + } + lastinc = now; + + return timestamp; +} + +ulong get_timer_masked(void) +{ + return get_timer_raw()/TIMER_LOAD_VAL; +} + +void udelay_masked(unsigned long usec) +{ + u32 tmo; + u32 endtime; + signed long diff; + + tmo = CONFIG_SYS_HZ_CLOCK / 1000; + tmo *= usec; + tmo /= 1000; + + endtime = get_timer_raw() + tmo; + + do { + u32 now = get_timer_raw(); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c index 34adb11..be82c87 100644 --- a/cpu/arm920t/cpu.c +++ b/cpu/arm920t/cpu.c @@ -33,6 +33,10 @@ #include #include +#ifdef CONFIG_AT91_LEGACY +#warning Your board is using legacy AT91RM9200 SoC access. Please update! +#endif + static void cache_flush(void); int cleanup_before_linux (void) diff --git a/doc/README.at91-soc b/doc/README.at91-soc index bed035c..425fc58 100644 --- a/doc/README.at91-soc +++ b/doc/README.at91-soc @@ -39,3 +39,26 @@ The method for updating 3. add new structures for SoC access 4. Convert arch, driver and boards file to new SoC 5. remove legacy code, if all boards and drives are ready + + Join AT91 and AT91RM9200 SoC +============================== + +Approximately 95 percent of AT91 and AT91RM9200 SoC parts are the same. +So, we should use the chance, to join both archs togetter. + +To do this follow step needed: + +1. change Makefile + @$(MKCONFIG) $(@:_config=) arm arm920t board vendor at91rm9200 + to + @$(MKCONFIG) $(@:_config=) arm arm920t board vendor at91 +2. remove CONFIG_AT91_LEGACY in board config +3. convert boards file to new SoC access +4. convert or change drivers + +To support the joining process, a new SoC dir (at91) has been adding to +arm920t arch directory. This directory contains files like at91rm9200 dir, but +uses the new c structure Soc access. The advantage of this is, we don't merge +old Soc access code and new code while the board are not converted. +Finally we can delete the whole at91rm9200 dir, if all board support the +new AT91-SoC access. diff --git a/include/asm-arm/arch-at91/at91_mc.h b/include/asm-arm/arch-at91/at91_mc.h new file mode 100644 index 0000000..acfbd10 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_mc.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef AT91_MC_H +#define AT91_MC_H + +#define AT91_ASM_MC_EBI_CSA (AT91_MC_BASE + 0x60) +#define AT91_ASM_MC_EBI_CFG (AT91_MC_BASE + 0x64) +#define AT91_ASM_MC_SMC_CSR0 (AT91_MC_BASE + 0x70) +#define AT91_ASM_MC_SDRAMC_MR (AT91_MC_BASE + 0x90) +#define AT91_ASM_MC_SDRAMC_TR (AT91_MC_BASE + 0x94) +#define AT91_ASM_MC_SDRAMC_CR (AT91_MC_BASE + 0x98) + +#ifndef __ASSEMBLY__ + +typedef struct at91_ebi { + u32 csa; /* 0x00 Chip Select Assignment Register */ + u32 cfgr; /* 0x04 Configuration Register */ + u32 reserved[2]; +} __attribute__ ((packed)) at91_ebi_t; + +#define AT91_EBI_CSA_CS0A 0x0001 +#define AT91_EBI_CSA_CS1A 0x0002 + +#define AT91_EBI_CSA_CS3A 0x0008 +#define AT91_EBI_CSA_CS4A 0x0010 + +typedef struct at91_sdramc { + u32 mr; /* 0x00 SDRAMC Mode Register */ + u32 tr; /* 0x04 SDRAMC Refresh Timer Register */ + u32 cr; /* 0x08 SDRAMC Configuration Register */ + u32 ssr; /* 0x0C SDRAMC Self Refresh Register */ + u32 lpr; /* 0x10 SDRAMC Low Power Register */ + u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */ + u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */ + u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ + u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ + u32 reserved[3]; +} __attribute__ ((packed)) at91_sdramc_t; + +typedef struct at91_smc { + u32 csr[8]; /* 0x00 SDRAMC Mode Register */ +} __attribute__ ((packed)) at91_smc_t; + +#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28) +#define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24) +#define AT91_SMC_CSR_ACSS_STANDARD 0x00000000 +#define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000 +#define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000 +#define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000 +#define AT91_SMC_CSR_DRP 0x00008000 +#define AT91_SMC_CSR_DBW_8 0x00004000 +#define AT91_SMC_CSR_DBW_16 0x00002000 +#define AT91_SMC_CSR_BAT_8 0x00000000 +#define AT91_SMC_CSR_BAT_16 0x00001000 +#define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8) +#define AT91_SMC_CSR_WSEN 0x00000080 +#define AT91_SMC_CSR_NWS(x) (x & 0x7F) + +typedef struct at91_bfc { + u32 mr; /* 0x00 SDRAMC Mode Register */ +} __attribute__ ((packed)) at91_bfc_t; + +typedef struct at91_mc { + u32 rcr; /* 0x00 MC Remap Control Register */ + u32 asr; /* 0x04 MC Abort Status Register */ + u32 aasr; /* 0x08 MC Abort Address Status Reg */ + u32 mpr; /* 0x0C MC Master Priority Register */ + u32 reserved1[20]; /* 0x10-0x5C */ + at91_ebi_t ebi; /* 0x60 - 0x6C EBI */ + at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */ + at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */ + at91_bfc_t bfc; /* 0xC0 BFC User Interface */ + u32 reserved2[15]; +} __attribute__ ((packed)) at91_mc_t; + +#endif +#endif diff --git a/include/asm-arm/arch-at91/at91_pio.h b/include/asm-arm/arch-at91/at91_pio.h index e5946ca..f7915a3 100644 --- a/include/asm-arm/arch-at91/at91_pio.h +++ b/include/asm-arm/arch-at91/at91_pio.h @@ -19,17 +19,21 @@ #define AT91_ASM_PIO_RANGE 0x200 +#define AT91_ASM_PIOC_ASR \ + (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) +#define AT91_ASM_PIOC_BSR \ + (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74) #define AT91_ASM_PIOC_PDR \ - (AT91_PIO_BASE + AT91_PIO_PORTC*AT91_ASM_PIO_RANGE + 0x04) + (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04) #define AT91_ASM_PIOC_PUDR \ - (AT91_PIO_BASE + AT91_PIO_PORTC*AT91_ASM_PIO_RANGE + 0x60) + (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60) #define AT91_ASM_PIOD_PDR \ - (AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x04) + (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04) #define AT91_ASM_PIOD_PUDR \ - (AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x60) + (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60) #define AT91_ASM_PIOD_ASR \ - (AT91_PIO_BASE + AT91_PIO_PORTD*AT91_ASM_PIO_RANGE + 0x70) + (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70) #ifndef __ASSEMBLY__ diff --git a/include/asm-arm/arch-at91/at91_st.h b/include/asm-arm/arch-at91/at91_st.h new file mode 100644 index 0000000..53f9320 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_st.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef AT91_ST_H +#define AT91_ST_H + +typedef struct at91_st { + + u32 cr; + u32 pimr; + u32 wdmr; + u32 rtmr; + u32 sr; + u32 ier; + u32 idr; + u32 imr; + u32 rtar; + u32 crtr; +} __attribute__ ((packed)) at91_st_t ; + +#define AT91_ST_CR_WDRST 1 + +#define AT91_ST_WDMR_WDV(x) (x & 0xFFFF) +#define AT91_ST_WDMR_RSTEN 0x00010000 +#define AT91_ST_WDMR_EXTEN 0x00020000 + +#endif diff --git a/include/asm-arm/arch-at91/at91_tc.h b/include/asm-arm/arch-at91/at91_tc.h new file mode 100644 index 0000000..1e180ad --- /dev/null +++ b/include/asm-arm/arch-at91/at91_tc.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef AT91_TC_H +#define AT91_TC_H + +typedef struct at91_tcc { + u32 ccr; /* 0x00 Channel Control Register */ + u32 cmr; /* 0x04 Channel Mode Register */ + u32 reserved1[2]; + u32 cv; /* 0x10 Counter Value */ + u32 ra; /* 0x14 Register A */ + u32 rb; /* 0x18 Register B */ + u32 rc; /* 0x1C Register C */ + u32 sr; /* 0x20 Status Register */ + u32 ier; /* 0x24 Interrupt Enable Register */ + u32 idr; /* 0x28 Interrupt Disable Register */ + u32 imr; /* 0x2C Interrupt Mask Register */ + u32 reserved3[4]; +} __attribute__ ((packed)) at91_tcc_t; + +#define AT91_TC_CCR_CLKEN 0x00000001 +#define AT91_TC_CCR_CLKDIS 0x00000002 +#define AT91_TC_CCR_SWTRG 0x00000004 + +#define AT91_TC_CMR_CPCTRG 0x00004000 + +#define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000 +#define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001 +#define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002 +#define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003 +#define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004 +#define AT91_TC_CMR_TCCLKS_XC0 0x00000005 +#define AT91_TC_CMR_TCCLKS_XC1 0x00000006 +#define AT91_TC_CMR_TCCLKS_XC2 0x00000007 + +typedef struct at91_tc { + at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */ + u32 bcr; /* 0xC0 TC Block Control Register */ + u32 bmr; /* 0xC4 TC Block Mode Register */ +} __attribute__ ((packed)) at91_tc_t; + +#define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000 +#define AT91_TC_BMR_TC0XC0S_NONE 0x00000001 +#define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002 +#define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003 + +#define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000 +#define AT91_TC_BMR_TC1XC1S_NONE 0x00000004 +#define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008 +#define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C + +#define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000 +#define AT91_TC_BMR_TC2XC2S_NONE 0x00000010 +#define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020 +#define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030 + +#endif diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h new file mode 100644 index 0000000..990f5a6 --- /dev/null +++ b/include/asm-arm/arch-at91/at91rm9200.h @@ -0,0 +1,135 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __AT91RM9200_H__ +#define __AT91RM9200_H__ + +/* Periperial Identifiers */ + +#define AT91_ID_SYS 1 /* System Peripheral */ +#define AT91_ID_PIOA 2 /* PIO port A */ +#define AT91_ID_PIOB 3 /* PIO port B */ +#define AT91_ID_PIOC 4 /* PIO port C */ +#define AT91_ID_PIOD 5 /* PIO port D BGA only */ +#define AT91_ID_USART0 6 /* USART 0 */ +#define AT91_ID_USART1 7 /* USART 1 */ +#define AT91_ID_USART2 8 /* USART 2 */ +#define AT91_ID_USART3 9 /* USART 3 */ +#define AT91_ID_MCI 10 /* Multimedia Card Interface */ +#define AT91_ID_UDP 11 /* USB Device Port */ +#define AT91_ID_TWI 12 /* Two Wire Interface */ +#define AT91_ID_SPI 13 /* Serial Peripheral Interface */ +#define AT91_ID_SSC0 14 /* Synch. Serial Controller 0 */ +#define AT91_ID_SSC1 15 /* Synch. Serial Controller 1 */ +#define AT91_ID_SSC2 16 /* Synch. Serial Controller 2 */ +#define AT91_ID_TC0 17 /* Timer Counter 0 */ +#define AT91_ID_TC1 18 /* Timer Counter 1 */ +#define AT91_ID_TC2 19 /* Timer Counter 2 */ +#define AT91_ID_TC3 20 /* Timer Counter 3 */ +#define AT91_ID_TC4 21 /* Timer Counter 4 */ +#define AT91_ID_TC5 22 /* Timer Counter 5 */ +#define AT91_ID_UHP 23 /* OHCI USB Host Port */ +#define AT91_ID_EMAC 24 /* Ethernet MAC */ +#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller */ +#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller */ +#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller */ +#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller */ +#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller */ +#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller */ +#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller */ + +#define AT91_USB_HOST_BASE 0x00300000 + +#define AT91_TC_BASE 0xFFFA0000 +#define AT91_UDP_BASE 0xFFFB0000 +#define AT91_MCI_BASE 0xFFFB4000 +#define AT91_TWI_BASE 0xFFFB8000 +#define AT91_EMAC_BASE 0xFFFBC000 +#define AT91_USART_BASE 0xFFFC0000 /* 4x 0x4000 Offset */ +#define AT91_SCC_BASE 0xFFFD0000 /* 4x 0x4000 Offset */ +#define AT91_SPI_BASE 0xFFFE0000 + +#define AT91_AIC_BASE 0xFFFFF000 +#define AT91_DBGU_BASE 0xFFFFF200 +#define AT91_PIO_BASE 0xFFFFF400 /* 4x 0x200 Offset */ +#define AT91_PMC_BASE 0xFFFFFC00 +#define AT91_ST_BASE 0xFFFFFD00 +#define AT91_ST_BASE 0xFFFFFD00 +#define AT91_RTC_BASE 0xFFFFFE00 +#define AT91_MC_BASE 0xFFFFFF00 + + +/* AT91RM9200 Periperial Multiplexing A */ +/* Port A */ +#define AT91_PMX_AA_EREFCK 0x00000080 +#define AT91_PMX_AA_ETXCK 0x00000080 +#define AT91_PMX_AA_ETXEN 0x00000100 +#define AT91_PMX_AA_ETX0 0x00000200 +#define AT91_PMX_AA_ETX1 0x00000400 +#define AT91_PMX_AA_ECRS 0x00000800 +#define AT91_PMX_AA_ECRSDV 0x00000800 +#define AT91_PMX_AA_ERX0 0x00001000 +#define AT91_PMX_AA_ERX1 0x00002000 +#define AT91_PMX_AA_ERXER 0x00004000 +#define AT91_PMX_AA_EMDC 0x00008000 +#define AT91_PMX_AA_EMDIO 0x00010000 + +#define AT91_PMX_AA_TXD2 0x00810000 + +#define AT91_PMX_AA_TWD 0x02000000 +#define AT91_PMX_AA_TWCK 0x04000000 + +/* Port B */ +#define AT91_PMX_BA_ERXCK 0x00080000 +#define AT91_PMX_BA_ECOL 0x00040000 +#define AT91_PMX_BA_ERXDV 0x00020000 +#define AT91_PMX_BA_ERX3 0x00010000 +#define AT91_PMX_BA_ERX2 0x00008000 +#define AT91_PMX_BA_ETXER 0x00004000 +#define AT91_PMX_BA_ETX3 0x00002000 +#define AT91_PMX_BA_ETX2 0x00001000 + +/* Port B */ + +#define AT91_PMX_CA_BFCK 0x00000001 +#define AT91_PMX_CA_BFRDY 0x00000002 +#define AT91_PMX_CA_SMOE 0x00000002 +#define AT91_PMX_CA_BFAVD 0x00000004 +#define AT91_PMX_CA_BFBAA 0x00000008 +#define AT91_PMX_CA_SMWE 0x00000008 +#define AT91_PMX_CA_BFOE 0x00000010 +#define AT91_PMX_CA_BFWE 0x00000020 +#define AT91_PMX_CA_NWAIT 0x00000040 +#define AT91_PMX_CA_A23 0x00000080 +#define AT91_PMX_CA_A24 0x00000100 +#define AT91_PMX_CA_A25 0x00000200 +#define AT91_PMX_CA_CFRNW 0x00000200 +#define AT91_PMX_CA_NCS4 0x00000400 +#define AT91_PMX_CA_CFCS 0x00000400 +#define AT91_PMX_CA_NCS5 0x00000800 +#define AT91_PMX_CA_CFCE1 0x00001000 +#define AT91_PMX_CA_NCS6 0x00001000 +#define AT91_PMX_CA_CFCE2 0x00002000 +#define AT91_PMX_CA_NCS7 0x00002000 +#define AT91_PMX_CA_D16_31 0xFFFF0000 + +#define AT91_CPU_NAME "AT91RM9200" + +#endif diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index de06a10..4ddb315 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -17,7 +17,7 @@ #include #if defined(CONFIG_AT91RM9200) -#include +#include #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) #include #define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 -- cgit v1.1 From 6799a80f7644d78988187390dfd37352f20ad710 Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Wed, 3 Feb 2010 22:47:57 +0100 Subject: new at91_emac network driver (NET_MULTI api) * add's at91_emac (AT91RM9200) network driver (NET_MULTI api) * enable driver with CONFIG_DRIVER_AT91EMAC * generic PHY initialization * modify AT91RM9200 boards to use NET_MULTI driver * the drivers has been tested with LXT971 Phy and DM9161 Phy at MII and RMII interface Signed-off-by: Jens Scharsig --- include/asm-arm/arch-at91/at91_emac.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/include/asm-arm/arch-at91/at91_emac.h b/include/asm-arm/arch-at91/at91_emac.h index 4b96f04..45ae333 100644 --- a/include/asm-arm/arch-at91/at91_emac.h +++ b/include/asm-arm/arch-at91/at91_emac.h @@ -1,6 +1,4 @@ /* - * Memory Setup stuff - taken from blob memsetup.S - * * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) * * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC)) @@ -15,7 +13,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License -- cgit v1.1 From 77e7273c40315abd2f3c17ad8d46a78950e3e65f Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Wed, 3 Feb 2010 22:48:09 +0100 Subject: new board (eb_cpux9k2) * new board (eb_cpux9k2) * support for EB+CPUx9K2 board by BuS Elektronik GmbH & Co. KG * select via make eb_cpux9k2_config * this also demonstrates, how to use boards with AT91RM9200 cpu in at91 arch tree Signed-off-by: Jens Scharsig --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/BuS/eb_cpux9k2/Makefile | 50 +++++ board/BuS/eb_cpux9k2/config.mk | 1 + board/BuS/eb_cpux9k2/cpux9k2.c | 387 ++++++++++++++++++++++++++++++++++++++ include/configs/eb_cpux9k2.h | 415 +++++++++++++++++++++++++++++++++++++++++ 7 files changed, 861 insertions(+) create mode 100644 board/BuS/eb_cpux9k2/Makefile create mode 100644 board/BuS/eb_cpux9k2/config.mk create mode 100644 board/BuS/eb_cpux9k2/cpux9k2.c create mode 100644 include/configs/eb_cpux9k2.h diff --git a/MAINTAINERS b/MAINTAINERS index 05bb396..dd1579e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -712,6 +712,10 @@ Steve Sakoman omap3_overo ARM CORTEX-A8 (OMAP3xx SoC) +Jens Scharsig + + eb_cpux9k2 ARM920T (AT91RM9200 SoC) + Robert Schwebel csb226 xscale diff --git a/MAKEALL b/MAKEALL index dec9212..1e660b6 100755 --- a/MAKEALL +++ b/MAKEALL @@ -663,6 +663,7 @@ LIST_at91=" \ CPU9260 \ CPU9G20 \ csb637 \ + eb_cpux9k2 \ kb9202 \ meesc \ mp2usb \ diff --git a/Makefile b/Makefile index 8ce248d..524b9da 100644 --- a/Makefile +++ b/Makefile @@ -2714,6 +2714,9 @@ CPUAT91_config : unconfig csb637_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t csb637 NULL at91rm9200 +eb_cpux9k2_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t eb_cpux9k2 BuS at91 + kb9202_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t kb9202 NULL at91rm9200 diff --git a/board/BuS/eb_cpux9k2/Makefile b/board/BuS/eb_cpux9k2/Makefile new file mode 100644 index 0000000..8171a7d --- /dev/null +++ b/board/BuS/eb_cpux9k2/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := cpux9k2.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/BuS/eb_cpux9k2/config.mk b/board/BuS/eb_cpux9k2/config.mk new file mode 100644 index 0000000..ff2cfd1 --- /dev/null +++ b/board/BuS/eb_cpux9k2/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c new file mode 100644 index 0000000..1f22275 --- /dev/null +++ b/board/BuS/eb_cpux9k2/cpux9k2.c @@ -0,0 +1,387 @@ +/* + * (C) Copyright 2008-2009 + * BuS Elektronik GmbH & Co. KG + * Jens Scharsig + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_STATUS_LED +#include +#endif + +#ifdef CONFIG_VIDEO +#include + +extern unsigned long display_width; +extern unsigned long display_height; +#endif + +#ifdef CONFIG_CMD_NAND +void cpux9k2_nand_hw_init(void); +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init(void) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + /* Enable Ctrlc */ + console_init_f(); + + /* Correct IRDA resistor problem / Set PA23_TXD in Output */ + writel(AT91_PMX_AA_TXD2, &pio->pioa.oer); + + gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_STATUS_LED + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); +#endif +#ifdef CONFIG_CMD_NAND + cpux9k2_nand_hw_init(); +#endif + return 0; +} + +#ifdef CONFIG_MISC_INIT_R + +int misc_init_r(void) +{ + uchar mac[8]; + uchar tm; + uchar midx; + uchar macn6, macn7; + +#ifdef CONFIG_NET_MULTI + if (getenv("ethaddr") == NULL) { + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x00, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (uchar *) &mac, sizeof(mac)) != 0) { + puts("Error reading MAC from EEPROM\n"); + } else { + tm = 0; + macn6 = 0; + macn7 = 0xFF; + for (midx = 0; midx < 6; midx++) { + if ((mac[midx] != 0) && (mac[midx] != 0xFF)) + tm++; + macn6 += mac[midx]; + macn7 ^= mac[midx]; + } + if ((macn6 != mac[6]) || (macn7 != mac[7])) + tm = 0; + if (tm) + eth_setenv_enetaddr("ethaddr", mac); + else + puts("Error: invalid MAC at EEPROM\n"); + } + } +#endif + gd->jt[XF_do_reset] = (void *) do_reset; + +#ifdef CONFIG_STATUS_LED + status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); +#endif + return 0; +} +#endif + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ + udelay(10000); + eth_init(gd->bd); +} +#endif + +/* + * DRAM initialisations + */ + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = + get_ram_size((volatile long *) PHYS_SDRAM, PHYS_SDRAM_SIZE); + return 0; +} + +/* + * Ethernet initialisations + */ + +#ifdef CONFIG_DRIVER_AT91EMAC +int board_eth_init(bd_t *bis) +{ + int rc = 0; + rc = at91emac_register(bis, (u32) AT91_EMAC_BASE); + return rc; +} +#endif + +/* + * Disk On Chip (NAND) Millenium initialization. + * The NAND lives in the CS2* space + */ +#if defined(CONFIG_CMD_NAND) + +#define MASK_ALE (1 << 22) /* our ALE is AD22 */ +#define MASK_CLE (1 << 21) /* our CLE is AD21 */ + +void cpux9k2_nand_hw_init(void) +{ + unsigned long csr; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE; + + /* Setup Smart Media, fitst enable the address range of CS3 */ + writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa); + + /* RWH = 1 | RWS = 0 | TDF = 1 | NWS = 3 */ + csr = AT91_SMC_CSR_RWHOLD(1) | AT91_SMC_CSR_TDF(1) | + AT91_SMC_CSR_NWS(3) | + AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_8 | + AT91_SMC_CSR_WSEN; + writel(csr, &mc->smc.csr[3]); + + writel(AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE, &pio->pioc.asr); + writel(AT91_PMX_CA_BFCK | AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE, + &pio->pioc.pdr); + + /* Configure PC2 as input (signal Nand READY ) */ + writel(AT91_PMX_CA_BFAVD, &pio->pioc.per); + writel(AT91_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */ + writel(AT91_PMX_CA_BFCK, &pio->pioc.codr); + + /* PIOC clock enabling */ + writel(1 << AT91_ID_PIOC, &pmc->pcer); +} + +static void board_nand_hwcontrol(struct mtd_info *mtd, + int cmd, unsigned int ctrl) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + if ((ctrl & NAND_NCE)) + writel(1, &pio->pioc.codr); + else + writel(1, &pio->pioc.sodr); + + this->IO_ADDR_W = (void *) IO_ADDR_W; + } + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int board_nand_dev_ready(struct mtd_info *mtd) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0); +} + +int board_nand_init(struct nand_chip *nand) +{ + cpux9k2_nand_hw_init(); + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = board_nand_hwcontrol; + nand->dev_ready = board_nand_dev_ready; + nand->chip_delay = 20; + return 0; +} + +#endif + +#if defined(CONFIG_VIDEO) +/* + * drv_video_init + * FUNCTION: initialize VCxK device + */ + +int drv_video_init(void) +{ +#ifdef CONFIG_SPLASH_SCREEN + unsigned long splash; +#endif + char *s; + unsigned long csr; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE; + + printf("Init Video as "); + s = getenv("displaywidth"); + if (s != NULL) + display_width = simple_strtoul(s, NULL, 10); + else + display_width = 256; + s = getenv("displayheight"); + if (s != NULL) + display_height = simple_strtoul(s, NULL, 10); + else + display_height = 256; + printf("%ld x %ld pixel matrix\n", display_width, display_height); + + /* RWH = 7 | RWS =7 | TDF = 15 | NWS = 0x7F */ + csr = AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) | + AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) | + AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 | + AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN; + writel(csr, &mc->smc.csr[2]); + writel(1 << AT91_ID_PIOB, &pmc->pcer); + + vcxk_init(display_width, display_height); +#ifdef CONFIG_SPLASH_SCREEN + s = getenv("splashimage"); + if (s != NULL) { + splash = simple_strtoul(s, NULL, 16); + printf("use splashimage: %lx\n", splash); + video_display_bitmap(splash, 0, 0); + } +#endif + return 0; +} +#endif + +#ifdef CONFIG_SOFT_I2C + +void i2c_init_board(void) +{ + u32 pin; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + + writel(1 << AT91_ID_PIOA, &pmc->pcer); + pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + writel(pin, &pio->pioa.idr); + writel(pin, &pio->pioa.pudr); + writel(pin, &pio->pioa.per); + writel(pin, &pio->pioa.oer); + writel(pin, &pio->pioa.sodr); +} + +#endif + +/*--------------------------------------------------------------------------*/ + +#ifdef CONFIG_STATUS_LED + +void __led_toggle(led_id_t mask) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + + if (readl(&pio->piod.odsr) & mask) + writel(mask, &pio->piod.codr); + else + writel(mask, &pio->piod.codr); +} + +void __led_init(led_id_t mask, int state) +{ + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + + writel(1 << AT91_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */ + /* Disable peripherals on LEDs */ + writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per); + /* Enable pins as outputs */ + writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.oer); + /* Turn all LEDs OFF */ + writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.sodr); + + __led_set(mask, state); +} + +void __led_set(led_id_t mask, int state) +{ + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + if (state == STATUS_LED_ON) + writel(mask, &pio->piod.codr); + else + writel(mask, &pio->piod.sodr); +} + +#endif + +/*---------------------------------------------------------------------------*/ + +int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = 0; + ulong side; + ulong bright; + + switch (argc) { + case 3: + side = simple_strtoul(argv[1], NULL, 10); + bright = simple_strtoul(argv[2], NULL, 10); + if ((side >= 0) && (side <= 3) && + (bright >= 0) && (bright <= 1000)) { + vcxk_setbrightness(side, bright); + rcode = 0; + } else { + printf("parameters out of range\n"); + printf("Usage:\n%s\n", cmdtp->usage); + rcode = 1; + } + break; + default: + printf("Usage:\n%s\n", cmdtp->usage); + rcode = 1; + break; + } + return rcode; +} + +/*---------------------------------------------------------------------------*/ + +U_BOOT_CMD( + bright, 3, 0, do_brightness, + "bright - sets the display brightness\n", + " <0..1000>\n side: 0/3=both; 1=first; 2=second\n" +); + +/* EOF cpu9k2.c */ diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h new file mode 100644 index 0000000..4ff4a85 --- /dev/null +++ b/include/configs/eb_cpux9k2.h @@ -0,0 +1,415 @@ +/* + * (C) Copyright 2008-2009 + * BuS Elektronik GmbH & Co. KG + * Jens Scharsig + * + * Configuation settings for the EB+CPUx9K2 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _CONFIG_EB_CPUx9K2_H_ +#define _CONFIG_EB_CPUx9K2_H_ + +/*--------------------------------------------------------------------------*/ + +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ +#define CONFIG_EB_CPUX9K2 1 /* on an EP+CPUX9K2 Board */ +#define USE_920T_MMU 1 + +#define CONFIG_VERSION_VARIABLE 1 +#define CONFIG_IDENT_STRING " on EB+CPUx9K2" + +#include /* needed for port definitions */ + +#define CONFIG_MISC_INIT_R + +/*--------------------------------------------------------------------------*/ + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ + +#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ +#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1 +#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */ + + +#define CONFIG_BOOT_RETRY_TIME 30 +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +/* + * ARM asynchronous clock + */ + +#define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */ +#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */ + +/* + * Size of malloc() pool + */ + +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 520*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * sdram + */ + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + PHYS_SDRAM_SIZE - 0x00400000 - \ + CONFIG_SYS_MALLOC_LEN) + +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ + +/* + * Command line configuration + */ + +#include + +#define CONFIG_CMD_BMP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_I2C_CMD_NO_FLAT +#define CONFIG_I2C_CMD_TREE + +#define CONFIG_SYS_LONGHELP + +/* + * Filesystems + */ + +#define CONFIG_JFFS2_NAND 1 + +#ifndef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_OFFSET 0 +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#else +#define MTDIDS_DEFAULT "nor0=0,nand0=1" +#define MTDPARTS_DEFAULT "mtdparts=" \ + "0:" \ + "384k(U-Boot)," \ + "128k(Env)," \ + "128k(Splash)," \ + "4M(Kernel)," \ + "-(FS)" \ + ";" \ + "1:" \ + "-(jffs2)" +#endif /* CONFIG_JFFS2_CMDLINE */ + +/* + * Hardware drivers + */ + +/* + * UART/CONSOLE + */ + +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 } + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_AT91RM9200_USART +#define CONFIG_DBGU /* define DBGU as console */ + +/* + * network + */ +#define CONFIG_NET_MULTI 1 + +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_RESET_PHY_R 1 + +#define CONFIG_DRIVER_AT91EMAC 1 +#define CONFIG_DRIVER_AT91EMAC_QUIET 1 +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#define CONFIG_MII 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * I2C-Bus + */ + +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ + +#ifndef CONFIG_HARD_I2C +#define CONFIG_SOFT_I2C + +/* Software I2C driver configuration */ + +#define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */ +#define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */ + +#define CONFIG_SYS_I2C_INIT_BOARD + +#define I2C_INIT i2c_init_board(); +#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr); +#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder); +#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0) +#define I2C_SDA(bit) \ + if (bit) \ + writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \ + else \ + writel(AT91_PMX_AA_TWD, &pio->pioa.codr); +#define I2C_SCL(bit) \ + if (bit) \ + writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \ + else \ + writel(AT91_PMX_AA_TWCK, &pio->pioa.codr); + +#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) + +#endif /* CONFIG_HARD_I2C */ + +/* I2C-RTC */ + +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_DS1338 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#endif + +/* EEPROM */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + +/* FLASH organization */ + +/* NOR-FLASH */ + +#define CONFIG_FLASH_CFI_DRIVER 1 + +#define PHYS_FLASH_1 0x10000000 +#define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_SYS_FLASH_ERASE_TOUT 6000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 + +/* NAND */ + +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 + +/* Status LED's */ + +#define CONFIG_STATUS_LED 1 +#define CONFIG_BOARD_SPECIFIC_LED 1 + +#define STATUS_LED_BOOT 1 +#define STATUS_LED_ACTIVE 0 + +#define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */ +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */ +#define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */ +#define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */ +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4) + +#define CONFIG_VIDEO 1 + +/* Options */ + +#ifdef CONFIG_VIDEO + +#define CONFIG_VIDEO_VCXK 1 + +#define CONFIG_SPLASH_SCREEN 1 + +#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4 +#define CONFIG_SYS_VCXK_BASE 0x30000000 + +#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3) +#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob +#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr + +#define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5) +#define CONFIG_SYS_VCXK_ENABLE_PORT piob +#define CONFIG_SYS_VCXK_ENABLE_DDR oer + +#define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2) +#define CONFIG_SYS_VCXK_REQUEST_PORT piob +#define CONFIG_SYS_VCXK_REQUEST_DDR oer + +#define CONFIG_SYS_VCXK_INVERT_PIN (1<<4) +#define CONFIG_SYS_VCXK_INVERT_PORT piob +#define CONFIG_SYS_VCXK_INVERT_DDR oer + +#define CONFIG_SYS_VCXK_RESET_PIN (1<<6) +#define CONFIG_SYS_VCXK_RESET_PORT piob +#define CONFIG_SYS_VCXK_RESET_DDR oer + +#endif /* CONFIG_VIDEO */ + +/* Environment */ + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) +#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTCOMMAND "run nfsboot" + +#define CONFIG_NFSBOOTCOMMAND \ + "dhcp $(copy_addr) uImage_cpux9k2;" \ + "run bootargsdefaults;" \ + "set bootargs $(bootargs) boot=nfs " \ + ";echo $(bootargs)" \ + ";bootm" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "displaywidth=256\0" \ + "displayheight=512\0" \ + "displaybsteps=1023\0" \ + "ubootaddr=10000000\0" \ + "splashimage=10080000\0" \ + "kerneladdr=100A0000\0" \ + "kernelsize=00400000\0" \ + "rootfsaddr=104A0000\0" \ + "copy_addr=21200000\0" \ + "rootfssize=00B60000\0" \ + "bootargsdefaults=set bootargs " \ + "console=ttyS0,115200 " \ + "video=vcxk_fb:xres:${displaywidth}," \ + "yres:${displayheight}," \ + "bres:${displaybsteps} " \ + "mem=62M " \ + "panic=10 " \ + "uboot=\\\"${ver}\\\" " \ + "\0" \ + "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \ + "dhcp $(copy_addr) uImage_cpux9k2;" \ + "erase $(kerneladdr) +$(kernelsize);" \ + "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \ + "protect on $(kerneladdr) +$(kernelsize)" \ + "\0" \ + "update_root=protect off $(rootfsaddr) +$(rootfssize);" \ + "dhcp $(copy_addr) rfs;" \ + "erase $(rootfsaddr) +$(rootfssize);" \ + "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ + "\0" \ + "update_uboot=protect off 10000000 1005FFFF;" \ + "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \ + "erase 10000000 1005FFFF;" \ + "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ + "protect on 10000000 1005FFFF;reset\0" \ + "update_splash=protect off $(splashimage) +20000;" \ + "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \ + "erase $(splashimage) +20000;" \ + "cp.b $(fileaddr) 10080000 $(filesize);" \ + "protect on $(splashimage) +20000;reset\0" \ + "emergency=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=emergency " \ + ";bootm $(kerneladdr)\0" \ + "netemergency=run bootargsdefaults;" \ + "dhcp $(copy_addr) uImage_cpux9k2;" \ + "set bootargs $(bootargs) root=initramfs boot=emergency " \ + ";bootm $(copy_addr)\0" \ + "norboot=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=local " \ + ";bootm $(kerneladdr)\0" \ + "nandboot=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=nand " \ + ";bootm $(kerneladdr)\0" \ + "uu=run update_uboot\0" \ + "ur=run update_root;run nk\0" \ + "nk=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \ + "boot=local " \ + ";echo $(bootargs)" \ + ";dhcp uImage_cpux9k2;bootm\0" \ + "nn=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \ + "boot=nand " \ + ";echo $(bootargs)" \ + ";dhcp uImage_cpux9k2;bootm\0" \ + " " + +/*--------------------------------------------------------------------------*/ + +#endif + +/* EOF */ -- cgit v1.1 From 4c006dd1501283eecaea813a0e5e225e9ee6fdeb Mon Sep 17 00:00:00 2001 From: Michael Zaidman Date: Mon, 15 Feb 2010 10:02:32 +0200 Subject: Bug: do_reset issued via netconsole does not reset mpc83xx cpu. The do_reset routine in the cpu/mpc83xx/cpu.c file does not reset the mpc83xx cpu when issued via netconsole. Moving the console output "resetting the board." to the beginning of the routine before disabling interrupts solved the problem. Signed-off-by: Michael Zaidman Acked-by: Detlev Zundel Signed-off-by: Kim Phillips --- cpu/mpc83xx/cpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index e38a372..51180d6 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -199,7 +199,10 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + puts("Resetting the board.\n"); + #ifdef MPC83xx_RESET + /* Interrupts and MMU off */ __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); @@ -214,9 +217,6 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* confirm Reset Control Reg is enabled */ while(!((immap->reset.rcer) & RCER_CRE)); - printf("Resetting the board."); - printf("\n"); - udelay(200); /* perform reset, only one bit */ @@ -238,8 +238,6 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) */ addr = CONFIG_SYS_RESET_ADDRESS; - printf("resetting the board."); - printf("\n"); ((void (*)(void)) addr) (); #endif /* MPC83xx_RESET */ -- cgit v1.1 From ecd1a09b81f2ed6e6ba7bd1d0bfb0cc3d0ea2ad0 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 18 Feb 2010 19:28:12 -0600 Subject: mpc83xx: remove hardcoded network addresses from config files and avoid e.g., two identical boards from causing random networking conflicts when hooked up to the same network. Signed-off-by: Kim Phillips --- include/configs/MPC8313ERDB.h | 7 ------- include/configs/MPC8315ERDB.h | 2 -- include/configs/MPC8323ERDB.h | 6 ------ include/configs/MPC832XEMDS.h | 2 -- include/configs/MPC8349EMDS.h | 8 -------- include/configs/MPC8349ITX.h | 12 ------------ include/configs/MPC8360EMDS.h | 2 -- include/configs/MPC8360ERDK.h | 8 -------- include/configs/MPC837XEMDS.h | 2 -- include/configs/MPC837XERDB.h | 12 ------------ include/configs/sbc8349.h | 8 -------- 11 files changed, 69 deletions(-) diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 0a4ba29..1478ec8 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -580,13 +580,6 @@ */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_ETHADDR 00:E0:0C:00:95:01 -#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 - -#define CONFIG_IPADDR 10.0.0.2 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 -#define CONFIG_NETMASK 255.0.0.0 #define CONFIG_NETDEV eth1 #define CONFIG_HOSTNAME mpc8313erdb diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index cfed4ca..a8570ce 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -616,9 +616,7 @@ #if defined(CONFIG_TSEC_ENET) #define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 04:00:00:00:00:0A #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 04:00:00:00:00:0B #endif #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 8e6f7ce..4046f80 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -525,17 +525,11 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ -#define CONFIG_ETHADDR 00:04:9f:ef:03:01 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ -#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */ -#define CONFIG_IPADDR 10.0.0.2 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 -#define CONFIG_NETMASK 255.0.0.0 #define CONFIG_NETDEV eth1 #define CONFIG_HOSTNAME mpc8323erdb diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 1adac64..2ad5f60 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -544,9 +544,7 @@ #if defined(CONFIG_UEC_ETH) #define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:04:9f:ef:03:01 #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 #endif #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 6361c45..bf28d9e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -685,22 +685,14 @@ #define CONFIG_ENV_OVERWRITE #if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:04:9f:ef:23:33 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH0 -#define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 #endif -#define CONFIG_IPADDR 192.168.1.253 - #define CONFIG_HOSTNAME mpc8349emds #define CONFIG_ROOTPATH /nfsroot/rootfs #define CONFIG_BOOTFILE uImage -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index eaa59fd..52e2851 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -678,18 +678,6 @@ boards, we say we have two, but don't display a message if we find only one. */ */ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:E0:0C:00:8C:01 -#endif - -#ifdef CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 -#endif - -#define CONFIG_IPADDR 192.168.1.253 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.252.0 #define CONFIG_NETDEV eth0 #ifdef CONFIG_MPC8349ITX diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 6fa7287..b9b5eab 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -587,9 +587,7 @@ #if defined(CONFIG_UEC_ETH) #define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:04:9f:ef:01:01 #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02 #endif #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index c6f1409..c7bc9cd 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -506,10 +506,6 @@ #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 #define CONFIG_HAS_ETH3 -#define CONFIG_ETHADDR 00:04:9f:ef:01:01 -#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02 -#define CONFIG_ETH2ADDR 00:04:9f:ef:01:03 -#define CONFIG_ETH3ADDR 00:04:9f:ef:01:04 #endif #define CONFIG_BAUDRATE 115200 @@ -518,10 +514,6 @@ #define CONFIG_HOSTNAME mpc8360erdk #define CONFIG_BOOTFILE uImage -#define CONFIG_IPADDR 10.0.0.99 -#define CONFIG_SERVERIP 10.0.0.2 -#define CONFIG_GATEWAYIP 10.0.0.2 -#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_ROOTPATH /nfsroot/ #define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 63f1d85..65d49ec 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -637,9 +637,7 @@ extern int board_pci_host_broken(void); #if defined(CONFIG_TSEC_ENET) #define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:E0:0C:00:83:79 #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:83:78 #endif #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 913184c..ca60272 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -643,20 +643,8 @@ */ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:04:9f:ef:04:01 -#endif - -#ifdef CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02 -#endif - #define CONFIG_HAS_FSL_DR_USB -#define CONFIG_IPADDR 10.0.0.2 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 -#define CONFIG_NETMASK 255.0.0.0 #define CONFIG_NETDEV eth1 #define CONFIG_HOSTNAME mpc837x_rdb diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 7bef119..4ea65ce 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -631,21 +631,13 @@ #if defined(CONFIG_TSEC_ENET) #define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:a0:1e:a0:13:8d #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e #endif -#define CONFIG_IPADDR 192.168.1.234 - #define CONFIG_HOSTNAME SBC8349 #define CONFIG_ROOTPATH /tftpboot/rootfs #define CONFIG_BOOTFILE uImage -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -- cgit v1.1 From 5b28e913f4519870ad2ca06cd7845b053f78bf0f Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 5 Feb 2010 15:16:02 +0100 Subject: mkimage: SEGFAULT with imximage on 64 bit systems Running mkimage to generate an imximage produces a SEGFAULT on 64 bit machines due to pointer arithmetic limited to 32 bit. Signed-off-by: Stefano Babic Acked-by: Kim Phillips --- tools/imximage.c | 30 ++++++++++++++---------------- tools/imximage.h | 2 +- 2 files changed, 15 insertions(+), 17 deletions(-) diff --git a/tools/imximage.c b/tools/imximage.c index 59923ff..43da678 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -101,22 +101,23 @@ static void imximage_print_header(const void *ptr) struct imx_header *imx_hdr = (struct imx_header *) ptr; flash_header_t *hdr = &imx_hdr->fhdr; uint32_t size; - flash_cfg_parms_t *ext_header; + uint32_t length; + dcd_t *dcd = &imx_hdr->dcd_table; size = imx_hdr->dcd_table.preamble.length; if (size > (MAX_HW_CFG_SIZE * sizeof(dcd_type_addr_data_t))) { fprintf(stderr, "Error: Image corrupt DCD size %d exceed maximum %d\n", - size / sizeof(dcd_type_addr_data_t), MAX_HW_CFG_SIZE); + (uint32_t)(size / sizeof(dcd_type_addr_data_t)), + MAX_HW_CFG_SIZE); exit(EXIT_FAILURE); } - ext_header = (flash_cfg_parms_t *) ((uint32_t)&imx_hdr->dcd_table + - sizeof(dcd_preamble_t) + size); + length = dcd->preamble.length / sizeof(dcd_type_addr_data_t); printf("Image Type: Freescale IMX Boot Image\n"); printf("Data Size: "); - genimg_print_size(ext_header->length); + genimg_print_size(dcd->addr_data[length].type); printf("Load Address: %08x\n", (unsigned int)hdr->app_dest_ptr); printf("Entry Point: %08x\n", (unsigned int)hdr->app_code_jump_vector); } @@ -237,7 +238,7 @@ static uint32_t imximage_parse_cfg_file(struct imx_header *imxhdr, char *name) dcd->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t); fclose(fd); - return dcd->preamble.length; + return dcd_len; } static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, @@ -246,7 +247,7 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, struct imx_header *hdr = (struct imx_header *)ptr; flash_header_t *fhdr = &hdr->fhdr; int dcd_len; - flash_cfg_parms_t *ext_header; + dcd_t *dcd = &hdr->dcd_table; uint32_t base_offset; /* Set default offset */ @@ -264,24 +265,21 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, fhdr->app_code_jump_vector = params->ep; base_offset = fhdr->app_dest_ptr + hdr->flash_offset ; - fhdr->dcd_ptr_ptr = (uint32_t) ((uint32_t)&fhdr->dcd_ptr - - (uint32_t)&fhdr->app_code_jump_vector) + base_offset ; + fhdr->dcd_ptr_ptr = (uint32_t) (offsetof(flash_header_t, dcd_ptr) - + offsetof(flash_header_t, app_code_jump_vector) + + base_offset); fhdr->dcd_ptr = base_offset + - ((uint32_t)&hdr->dcd_table - - (uint32_t)&hdr->fhdr); + offsetof(struct imx_header, dcd_table); /* The external flash header must be at the end of the DCD table */ - ext_header = (flash_cfg_parms_t *) ((uint32_t)&hdr->dcd_table + - dcd_len + - sizeof(dcd_preamble_t)); - ext_header->length = sbuf->st_size + + dcd->addr_data[dcd_len].type = sbuf->st_size + hdr->flash_offset + sizeof(struct imx_header); /* Security feature are not supported */ fhdr->app_code_csf = 0; - fhdr->super_root_key = NULL; + fhdr->super_root_key = 0; } diff --git a/tools/imximage.h b/tools/imximage.h index c579f51..b4d926d 100644 --- a/tools/imximage.h +++ b/tools/imximage.h @@ -81,7 +81,7 @@ typedef struct { uint32_t app_code_barker; uint32_t app_code_csf; uint32_t dcd_ptr_ptr; - hab_rsa_public_key *super_root_key; + uint32_t super_root_key; uint32_t dcd_ptr; uint32_t app_dest_ptr; } flash_header_t; -- cgit v1.1 From 0ad22703f06af5fe100cfe6f08b1f32ea89cd5b1 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 22 Feb 2010 19:37:56 -0600 Subject: tools: fix imximage warning Fix build warning: Configuring for MPC837XEMDS board... imximage.c: In function `imximage_parse_cfg_file': imximage.c:146: warning: passing argument 2 of `getline' from incompatible pointer type /usr/include/bits/stdio.h:116: note: expected `size_t *' but argument is of type `uint32_t *' Signed-off-by: Kim Phillips --- tools/imximage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/imximage.c b/tools/imximage.c index 43da678..df2d8c4 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -129,7 +129,7 @@ static uint32_t imximage_parse_cfg_file(struct imx_header *imxhdr, char *name) char *token, *saveptr1, *saveptr2; int lineno = 0; int fld, value; - uint32_t len; + size_t len; int dcd_len = 0; dcd_t *dcd = &imxhdr->dcd_table; int32_t cmd; -- cgit v1.1 From f3651764e57e353251695691677bd95ba5a420bc Mon Sep 17 00:00:00 2001 From: Frans Meulenbroeks Date: Mon, 22 Feb 2010 22:49:06 +0100 Subject: cmd_itest.c: fix pointer dereferencing fix pointer dereferencing if the size is .b and .w an 8 or 16 bit access is done. Signed-off-by: Frans Meulenbroeks Acked-by: Detlev Zundel --- common/cmd_itest.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/common/cmd_itest.c b/common/cmd_itest.c index 5b301bf..58c5e7b 100644 --- a/common/cmd_itest.c +++ b/common/cmd_itest.c @@ -66,12 +66,17 @@ op_tbl_t op_table [] = { static long evalexp(char *s, int w) { - long l, *p; + long l = 0; + long *p; /* if the parameter starts with a * then assume is a pointer to the value we want */ if (s[0] == '*') { p = (long *)simple_strtoul(&s[1], NULL, 16); - l = *p; + switch (w) { + case 1: return((long)(*(unsigned char *)p)); + case 2: return((long)(*(unsigned short *)p)); + case 4: return(*p); + } } else { l = simple_strtoul(s, NULL, 16); } -- cgit v1.1 From 87800f72414b830756aefc757dd191688febacf9 Mon Sep 17 00:00:00 2001 From: Eugene O'Brien Date: Wed, 24 Feb 2010 14:10:24 -0500 Subject: ppc4xx: Corrected EBC register bit definitions Corrected the bit field positions of the external master priority low and the external master priority high values in the EBC configuration register. These bit field positions differ between PPC405 and PPC440 processors Signed-off-by: Eugene O'Brien Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-ebc.h | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h index 9680f70..9c17e46 100644 --- a/include/asm-ppc/ppc4xx-ebc.h +++ b/include/asm-ppc/ppc4xx-ebc.h @@ -25,14 +25,24 @@ #define _PPC4xx_EBC_H_ /* - * Currently there are two register layout versions for the - * IBM EBC core used on 4xx PPC's: + * Currently there are two register layout versions for the IBM EBC core + * used on 4xx PPC's. The following grouping lists the first layout. + * Within this group there is a slight variation concerning the bit field + * position of the EMPL and EMPH fields: */ #if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define CONFIG_EBC_PPC4xx_IBM_VER1 +#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ + defined(CONFIG_405EP) +#define EBC_CFG_EMPH_POS 8 +#define EBC_CFG_EMPL_POS 6 +#else +#define EBC_CFG_EMPH_POS 6 +#define EBC_CFG_EMPL_POS 8 +#endif #endif /* @@ -143,10 +153,12 @@ #define EBC_CFG_EBTC_MASK PPC_REG_VAL(0, 0x1) #define EBC_CFG_EBTC_HI PPC_REG_VAL(0, 0x0) #define EBC_CFG_EBTC_DRIVEN PPC_REG_VAL(0, 0x1) -#define EBC_CFG_EMPH_MASK PPC_REG_VAL(6, 0x3) -#define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(6, (static_cast(u32, n)) & 0x3) -#define EBC_CFG_EMPL_MASK PPC_REG_VAL(8, 0x3) -#define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x3) +#define EBC_CFG_EMPH_MASK PPC_REG_VAL(EBC_CFG_EMPH_POS, 0x3) +#define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(EBC_CFG_EMPH_POS, \ + (static_cast(u32, n)) & 0x3) +#define EBC_CFG_EMPL_MASK PPC_REG_VAL(EBC_CFG_EMPL_POS, 0x3) +#define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(EBC_CFG_EMPH_POS, \ + (static_cast(u32, n)) & 0x3) #define EBC_CFG_CSTC_MASK PPC_REG_VAL(9, 0x1) #define EBC_CFG_CSTC_HI PPC_REG_VAL(9, 0x0) #define EBC_CFG_CSTC_DRIVEN PPC_REG_VAL(9, 0x1) -- cgit v1.1 From 4e7e12dfa103cb8ec6dc7547dd1c9976337dc1fd Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 22 Feb 2010 19:39:16 -0600 Subject: mpc83xx: vme8349: fix incorrect BR0_PRELIM port size comment commit 98d92d8c9f4021629a45261ad5ec3f3595f3a27a "sbc8349: fix incorrect comment" missed this one. Signed-off-by: Kim Phillips --- include/configs/vme8349.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index dbc15b2..7603300 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -118,7 +118,7 @@ #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - (2 << BR_PS_SHIFT) | /* 32bit */ \ + (2 << BR_PS_SHIFT) | /* 16bit */ \ BR_V) /* valid */ #define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */ @@ -128,7 +128,7 @@ #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - (2 << BR_PS_SHIFT) | /* 32bit */ \ + (2 << BR_PS_SHIFT) | /* 16bit */ \ BR_V) /* valid */ #define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */ -- cgit v1.1 From fe389da6ae739816879606ecde4ab25f4292377d Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 1 Mar 2010 11:10:17 -0600 Subject: mpc83xx: fix out-of-tree mpc8315 nand build commit 2e95004deb6e33e33bf1b8a92a38cd2115bac4c2 "mpc83xx: Add NAND boot support for MPC8315E-RDB boards" symlinked nand_spl/board/freescale/mpc8315erdb to mpc8313erdb in order to not duplicate code. Since the main makefile builds nand_spl/board/$(BOARDDIR) (which makes sense), and the board Makefile and linker script are the only two necessary files to enable out-of-tree building, and other boards have duplicated nand makefiles (e.g. 8536ds & 8569mds), it only seems prudent to copy these two files in the name of the 8315 too. Signed-off-by: Kim Phillips Cc: Anton Vorontsov Cc: Wolfgang Denk --- Makefile | 3 - nand_spl/board/freescale/mpc8315erdb/Makefile | 108 ++++++++++++++++++++++++ nand_spl/board/freescale/mpc8315erdb/u-boot.lds | 52 ++++++++++++ 3 files changed, 160 insertions(+), 3 deletions(-) create mode 100644 nand_spl/board/freescale/mpc8315erdb/Makefile create mode 100644 nand_spl/board/freescale/mpc8315erdb/u-boot.lds diff --git a/Makefile b/Makefile index 524b9da..16b549c 100644 --- a/Makefile +++ b/Makefile @@ -2272,9 +2272,6 @@ MPC8313ERDB_NAND_66_config: unconfig MPC8315ERDB_NAND_config \ MPC8315ERDB_config: unconfig - @if [ "$(findstring _NAND_,$@)" ] ; then \ - ln -sf mpc8313erdb nand_spl/board/freescale/mpc8315erdb ; \ - fi ; @$(MKCONFIG) -t $(@:_config=) MPC8315ERDB ppc mpc83xx mpc8315erdb freescale MPC8323ERDB_config: unconfig diff --git a/nand_spl/board/freescale/mpc8315erdb/Makefile b/nand_spl/board/freescale/mpc8315erdb/Makefile new file mode 100644 index 0000000..a13e7e2 --- /dev/null +++ b/nand_spl/board/freescale/mpc8315erdb/Makefile @@ -0,0 +1,108 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# (C) Copyright 2008 Freescale Semiconductor +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +TEXT_BASE := 0xfff00000 +PAD_TO := 0xfff04000 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o ticks.o +COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \ + time.o cache.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +$(nandobj)u-boot.lds: $(LDSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + +# create symbolic links for common files + +$(obj)start.S: + ln -sf $(SRCTREE)/cpu/mpc83xx/start.S $(obj)start.S + +$(obj)nand_boot_fsl_elbc.c: + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)sdram.c: + ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $(obj)sdram.c + +$(obj)$(BOARD).c: + ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $(obj)$(BOARD).c + +$(obj)ns16550.c: + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)nand_init.c: + ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $(obj)nand_init.c + +$(obj)cache.c: + ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + +$(obj)time.c: + ln -sf $(SRCTREE)/lib_ppc/time.c $(obj)time.c + +$(obj)ticks.S: + ln -sf $(SRCTREE)/lib_ppc/ticks.S $(obj)ticks.S + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/mpc8315erdb/u-boot.lds b/nand_spl/board/freescale/mpc8315erdb/u-boot.lds new file mode 100644 index 0000000..ad82589 --- /dev/null +++ b/nand_spl/board/freescale/mpc8315erdb/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = 0xfff00000; + .text : { + *(.text*) + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + . = ALIGN(8); + .data : { + *(.data*) + *(.sdata*) + _GOT2_TABLE_ = .; + *(.got2) + __got2_entries = (. - _GOT2_TABLE_) >> 2; + } + + . = ALIGN(8); + __bss_start = .; + .bss (NOLOAD) : { *(.*bss) } + _end = .; +} +ENTRY(_start) +ASSERT(_end <= 0xfff01000, "NAND bootstrap too big"); -- cgit v1.1 From da5e083590bb62ca6d7f08d3714d07ba736da863 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 8 Feb 2010 11:50:16 +0900 Subject: sh: Add asm/unaligned.h and asm/unaligned-sh4a.h from Linux kernel zlib.c demands asm/unaligned.h. But, SH does not have these. This commit add asm/unaligned.h and asm/unaligned-sh4a.h from Linux kernel and modifyf for u-boot. Signed-off-by: Nobuhiro Iwamatsu --- include/asm-sh/unaligned-sh4a.h | 258 ++++++++++++++++++++++++++++++++++++++++ include/asm-sh/unaligned.h | 25 ++++ 2 files changed, 283 insertions(+) create mode 100644 include/asm-sh/unaligned-sh4a.h create mode 100644 include/asm-sh/unaligned.h diff --git a/include/asm-sh/unaligned-sh4a.h b/include/asm-sh/unaligned-sh4a.h new file mode 100644 index 0000000..9f4dd25 --- /dev/null +++ b/include/asm-sh/unaligned-sh4a.h @@ -0,0 +1,258 @@ +#ifndef __ASM_SH_UNALIGNED_SH4A_H +#define __ASM_SH_UNALIGNED_SH4A_H + +/* + * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only. + * Support for 64-bit accesses are done through shifting and masking + * relative to the endianness. Unaligned stores are not supported by the + * instruction encoding, so these continue to use the packed + * struct. + * + * The same note as with the movli.l/movco.l pair applies here, as long + * as the load is gauranteed to be inlined, nothing else will hook in to + * r0 and we get the return value for free. + * + * NOTE: Due to the fact we require r0 encoding, care should be taken to + * avoid mixing these heavily with other r0 consumers, such as the atomic + * ops. Failure to adhere to this can result in the compiler running out + * of spill registers and blowing up when building at low optimization + * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777. + */ +#include +#include + +static __always_inline u32 __get_unaligned_cpu32(const u8 *p) +{ + unsigned long unaligned; + + __asm__ __volatile__ ( + "movua.l @%1, %0\n\t" + : "=z" (unaligned) + : "r" (p) + ); + + return unaligned; +} + +struct __una_u16 { u16 x __attribute__((packed)); }; +struct __una_u32 { u32 x __attribute__((packed)); }; +struct __una_u64 { u64 x __attribute__((packed)); }; + +static inline u16 __get_unaligned_cpu16(const u8 *p) +{ +#ifdef __LITTLE_ENDIAN + return p[0] | p[1] << 8; +#else + return p[0] << 8 | p[1]; +#endif +} + +/* + * Even though movua.l supports auto-increment on the read side, it can + * only store to r0 due to instruction encoding constraints, so just let + * the compiler sort it out on its own. + */ +static inline u64 __get_unaligned_cpu64(const u8 *p) +{ +#ifdef __LITTLE_ENDIAN + return (u64)__get_unaligned_cpu32(p + 4) << 32 | + __get_unaligned_cpu32(p); +#else + return (u64)__get_unaligned_cpu32(p) << 32 | + __get_unaligned_cpu32(p + 4); +#endif +} + +static inline u16 get_unaligned_le16(const void *p) +{ + return le16_to_cpu(__get_unaligned_cpu16(p)); +} + +static inline u32 get_unaligned_le32(const void *p) +{ + return le32_to_cpu(__get_unaligned_cpu32(p)); +} + +static inline u64 get_unaligned_le64(const void *p) +{ + return le64_to_cpu(__get_unaligned_cpu64(p)); +} + +static inline u16 get_unaligned_be16(const void *p) +{ + return be16_to_cpu(__get_unaligned_cpu16(p)); +} + +static inline u32 get_unaligned_be32(const void *p) +{ + return be32_to_cpu(__get_unaligned_cpu32(p)); +} + +static inline u64 get_unaligned_be64(const void *p) +{ + return be64_to_cpu(__get_unaligned_cpu64(p)); +} + +static inline void __put_le16_noalign(u8 *p, u16 val) +{ + *p++ = val; + *p++ = val >> 8; +} + +static inline void __put_le32_noalign(u8 *p, u32 val) +{ + __put_le16_noalign(p, val); + __put_le16_noalign(p + 2, val >> 16); +} + +static inline void __put_le64_noalign(u8 *p, u64 val) +{ + __put_le32_noalign(p, val); + __put_le32_noalign(p + 4, val >> 32); +} + +static inline void __put_be16_noalign(u8 *p, u16 val) +{ + *p++ = val >> 8; + *p++ = val; +} + +static inline void __put_be32_noalign(u8 *p, u32 val) +{ + __put_be16_noalign(p, val >> 16); + __put_be16_noalign(p + 2, val); +} + +static inline void __put_be64_noalign(u8 *p, u64 val) +{ + __put_be32_noalign(p, val >> 32); + __put_be32_noalign(p + 4, val); +} + +static inline void put_unaligned_le16(u16 val, void *p) +{ +#ifdef __LITTLE_ENDIAN + ((struct __una_u16 *)p)->x = val; +#else + __put_le16_noalign(p, val); +#endif +} + +static inline void put_unaligned_le32(u32 val, void *p) +{ +#ifdef __LITTLE_ENDIAN + ((struct __una_u32 *)p)->x = val; +#else + __put_le32_noalign(p, val); +#endif +} + +static inline void put_unaligned_le64(u64 val, void *p) +{ +#ifdef __LITTLE_ENDIAN + ((struct __una_u64 *)p)->x = val; +#else + __put_le64_noalign(p, val); +#endif +} + +static inline void put_unaligned_be16(u16 val, void *p) +{ +#ifdef __BIG_ENDIAN + ((struct __una_u16 *)p)->x = val; +#else + __put_be16_noalign(p, val); +#endif +} + +static inline void put_unaligned_be32(u32 val, void *p) +{ +#ifdef __BIG_ENDIAN + ((struct __una_u32 *)p)->x = val; +#else + __put_be32_noalign(p, val); +#endif +} + +static inline void put_unaligned_be64(u64 val, void *p) +{ +#ifdef __BIG_ENDIAN + ((struct __una_u64 *)p)->x = val; +#else + __put_be64_noalign(p, val); +#endif +} + +/* + * Cause a link-time error if we try an unaligned access other than + * 1,2,4 or 8 bytes long + */ +extern void __bad_unaligned_access_size(void); + +#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({ \ + __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \ + __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)), \ + __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)), \ + __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)), \ + __bad_unaligned_access_size())))); \ + })) + +#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({ \ + __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \ + __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)), \ + __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)), \ + __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)), \ + __bad_unaligned_access_size())))); \ + })) + +#define __put_unaligned_le(val, ptr) ({ \ + void *__gu_p = (ptr); \ + switch (sizeof(*(ptr))) { \ + case 1: \ + *(u8 *)__gu_p = (__force u8)(val); \ + break; \ + case 2: \ + put_unaligned_le16((__force u16)(val), __gu_p); \ + break; \ + case 4: \ + put_unaligned_le32((__force u32)(val), __gu_p); \ + break; \ + case 8: \ + put_unaligned_le64((__force u64)(val), __gu_p); \ + break; \ + default: \ + __bad_unaligned_access_size(); \ + break; \ + } \ + (void)0; }) + +#define __put_unaligned_be(val, ptr) ({ \ + void *__gu_p = (ptr); \ + switch (sizeof(*(ptr))) { \ + case 1: \ + *(u8 *)__gu_p = (__force u8)(val); \ + break; \ + case 2: \ + put_unaligned_be16((__force u16)(val), __gu_p); \ + break; \ + case 4: \ + put_unaligned_be32((__force u32)(val), __gu_p); \ + break; \ + case 8: \ + put_unaligned_be64((__force u64)(val), __gu_p); \ + break; \ + default: \ + __bad_unaligned_access_size(); \ + break; \ + } \ + (void)0; }) + +#ifdef __LITTLE_ENDIAN +# define get_unaligned __get_unaligned_le +# define put_unaligned __put_unaligned_le +#else +# define get_unaligned __get_unaligned_be +# define put_unaligned __put_unaligned_be +#endif + +#endif /* __ASM_SH_UNALIGNED_SH4A_H */ diff --git a/include/asm-sh/unaligned.h b/include/asm-sh/unaligned.h new file mode 100644 index 0000000..2e0d164 --- /dev/null +++ b/include/asm-sh/unaligned.h @@ -0,0 +1,25 @@ +#ifndef _ASM_SH_UNALIGNED_H +#define _ASM_SH_UNALIGNED_H + +/* Copy from linux-kernel. */ + +#ifdef CONFIG_CPU_SH4A +/* SH-4A can handle unaligned loads in a relatively neutered fashion. */ +#include +#else +/* Otherwise, SH can't handle unaligned accesses. */ +#include +#if defined(__BIG_ENDIAN__) +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#elif defined(__LITTLE_ENDIAN__) +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#endif + +#include +#include +#include +#endif + +#endif /* _ASM_SH_UNALIGNED_H */ -- cgit v1.1 From 870bf3ee60320b58f8970ffe3ddebda0e8ac62f7 Mon Sep 17 00:00:00 2001 From: Wolfgang Wegner Date: Wed, 9 Dec 2009 17:32:12 -0500 Subject: add include/asm-m68k/unaligned.h lib_generic/zlib.c needs include/asm/unaligned.h since commit cd514aeb996e2f7aefbe1f78481965d9d074aed4, which broke compilation for Coldfire/M68K. This patch adds the missing header for these architectures. Signed-off-by: Wolfgang Wegner --- include/asm-m68k/unaligned.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 include/asm-m68k/unaligned.h diff --git a/include/asm-m68k/unaligned.h b/include/asm-m68k/unaligned.h new file mode 100644 index 0000000..328aa0c --- /dev/null +++ b/include/asm-m68k/unaligned.h @@ -0,0 +1,15 @@ +#ifndef _ASM_M68K_UNALIGNED_H +#define _ASM_M68K_UNALIGNED_H + +#ifdef CONFIG_COLDFIRE +#include +#else +#include +#endif + +#include + +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be + +#endif /* _ASM_M68K_UNALIGNED_H */ -- cgit v1.1 From 992d7129500d239d684c15fa2d61e0a8f2e64457 Mon Sep 17 00:00:00 2001 From: Wolfgang Wegner Date: Wed, 28 Oct 2009 15:11:00 -0500 Subject: MCF532x: make icache_enable use CONFIG_SYS_SDRAM_SIZE in cpu/mcf532x/start.S, the function icache_enable enables the cache for a fixed 32MB region starting at the SDRAM start address; this patch changes the function to cover the region defined by CONFIG_SYS_SDRAM_SIZE Signed-off-by: Wolfgang Wegner --- cpu/mcf532x/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index a46c47a..ff13a9f 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -280,7 +280,7 @@ _int_handler: icache_enable: move.l #0x01000000, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ - move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 + move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000 + ((CONFIG_SYS_SDRAM_SIZE & 0x1fe0) << 11)), %d0 movec %d0, %ACR0 /* Enable cache */ move.l #0x80000200, %d0 /* Setup cache mask */ -- cgit v1.1 From bb907ab51fd04255923b7ecf9dab352078808351 Mon Sep 17 00:00:00 2001 From: Richard Retanubun Date: Mon, 26 Oct 2009 14:19:17 -0400 Subject: MCF5271-only: Added a weak board_reset function to allow custom reset This patch adds a board_reset function to allow boards to specify their own custom reset sequence (e.g. resetting by timing out watchdog). Tested only on MCF5271, can be expanded if needed. Based on Mike Frysinger's suggestion on: http://article.gmane.org/gmane.comp.boot-loaders.u-boot/70304 Signed-off-by: Richard Retanubun --- cpu/mcf52x2/cpu.c | 6 ++++++ cpu/mcf52x2/cpu.h | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 cpu/mcf52x2/cpu.h diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index 2cfe631..c4c5d50 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -33,6 +33,7 @@ #include #include #include +#include "cpu.h" DECLARE_GLOBAL_DATA_PTR; @@ -143,6 +144,11 @@ int checkcpu(void) int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) { + /* Call the board specific reset actions first. */ + if(board_reset) { + board_reset(); + } + mbar_writeByte(MCF_RCM_RCR, MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); return 0; diff --git a/cpu/mcf52x2/cpu.h b/cpu/mcf52x2/cpu.h new file mode 100644 index 0000000..c1227eb --- /dev/null +++ b/cpu/mcf52x2/cpu.h @@ -0,0 +1,33 @@ +/* + * cpu.h + * + * Copyright (c) 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CPU_H_ +#define _CPU_H_ + +#include + +/* Use this to create board specific reset functions */ +void board_reset(void) __attribute__((__weak__)); + +#endif /* _CPU_H_ */ -- cgit v1.1 From c7de810c79a00aa6fc08900ee0bb57bd295db733 Mon Sep 17 00:00:00 2001 From: Wolfgang Wegner Date: Tue, 2 Mar 2010 10:59:20 +0100 Subject: allow MCF532x to use CONFIG_MONITOR_IS_IN_RAM CONFIG_MONITOR_IS_IN_RAM is broken for MCF532x. This patch fixes this by conditionally - removing the vector table at the beginning of code - not overwriting the vector base register - removing the code to re-set the PLL, which effectively disables SDRAM access Signed-off-by: Wolfgang Wegner --- cpu/mcf532x/speed.c | 3 +++ cpu/mcf532x/start.S | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c index 0d378e6..67f08c7 100644 --- a/cpu/mcf532x/speed.c +++ b/cpu/mcf532x/speed.c @@ -204,6 +204,8 @@ int clock_pll(int fsys, int flags) fout = ((fref * mfd) / (BUSDIV * 4)); #endif +/* must not tamper with SDRAMC if running from SDRAM */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) /* * Check to see if the SDRAM has already been initialized. * If it has then the SDRAM needs to be put into self refresh @@ -254,6 +256,7 @@ int clock_pll(int fsys, int flags) /* wait for DQS logic to relock */ for (i = 0; i < 0x200; i++) ; +#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */ return fout; } diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index ff13a9f..5b134aa 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -45,6 +45,7 @@ addl #60,%sp; /* space for 15 regs */ \ rte; +#if !defined(CONFIG_MONITOR_IS_IN_RAM) .text /* * Vector table. This is used for initial platform startup. @@ -121,6 +122,7 @@ vector192_255: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */ .text @@ -130,9 +132,11 @@ _start: nop move.w #0x2700,%sr /* Mask off Interrupt */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) /* Set vector base register at the beginning of the Flash */ move.l #CONFIG_SYS_FLASH_BASE, %d0 movec %d0, %VBR +#endif move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 -- cgit v1.1 From 8f9a221045a4ace14fe006e1353c593619d1001a Mon Sep 17 00:00:00 2001 From: Wolfgang Wegner Date: Tue, 2 Mar 2010 10:59:19 +0100 Subject: ] fix monitor protection for CONFIG_MONITOR_IS_IN_RAM For platforms with flash below ram addresses, the current check to activate monitor protection is wrong/insufficient. This patch fixes CONFIG_MONITOR_IS_IN_RAM for these systems by adding a check for this configuration. Signed-off-by: Wolfgang Wegner Signed-off-by: Stefan Roese --- drivers/mtd/cfi_flash.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 24eb33f..fdba297 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1980,7 +1980,8 @@ unsigned long flash_init (void) } /* Monitor protection ON by default */ -#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) +#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ + (!defined(CONFIG_MONITOR_IS_IN_RAM)) flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, -- cgit v1.1 From b29ff6277239f5c8bc9366e74afac5a36ab3b23e Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Mon, 8 Feb 2010 14:15:15 -0500 Subject: NetStar: eeprom - undefined reference to `memset' Defining partially initialized struct eth_device on stack means gcc has to zero out it, and some gcc versions optimize this with an implicit call to memset. Move definition to data section to avoid that (it has also nice side effect that we need not to pass it to helper functions anymore) Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- board/netstar/eeprom.c | 68 +++++++++++++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 31 deletions(-) diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c index adb01b9..ad301eb 100644 --- a/board/netstar/eeprom.c +++ b/board/netstar/eeprom.c @@ -28,40 +28,50 @@ #include #include "../drivers/net/smc91111.h" -static u16 read_eeprom_reg(struct eth_device *dev, u16 reg) +static struct eth_device dev = { + .iobase = CONFIG_SMC91111_BASE +}; + +static u16 read_eeprom_reg(u16 reg) { int timeout; - SMC_SELECT_BANK(dev, 2); - SMC_outw(dev, reg, PTR_REG); + SMC_SELECT_BANK(&dev, 2); + SMC_outw(&dev, reg, PTR_REG); + + SMC_SELECT_BANK(&dev, 1); + SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT | + CTL_RELOAD, CTL_REG); - SMC_SELECT_BANK(dev, 1); - SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, - CTL_REG); timeout = 100; - while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout) + + while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout) udelay(100); if (timeout == 0) { printf("Timeout Reading EEPROM register %02x\n", reg); return 0; } - return SMC_inw (dev, GP_REG); + return SMC_inw(&dev, GP_REG); } -static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg) +static int write_eeprom_reg(u16 value, u16 reg) { int timeout; - SMC_SELECT_BANK(dev, 2); - SMC_outw(dev, reg, PTR_REG); + SMC_SELECT_BANK(&dev, 2); + SMC_outw(&dev, reg, PTR_REG); + + SMC_SELECT_BANK(&dev, 1); + + SMC_outw(&dev, value, GP_REG); + SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT | + CTL_STORE, CTL_REG); - SMC_SELECT_BANK(dev, 1); - SMC_outw(dev, value, GP_REG); - SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); timeout = 100; - while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout) - udelay (100); + + while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout) + udelay(100); if (timeout == 0) { printf("Timeout Writing EEPROM register %02x\n", reg); return 0; @@ -70,17 +80,17 @@ static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg) return 1; } -static int write_data(struct eth_device *dev, u16 *buf, int len) +static int write_data(u16 *buf, int len) { u16 reg = 0x23; while (len--) - write_eeprom_reg(dev, *buf++, reg++); + write_eeprom_reg(*buf++, reg++); return 0; } -static int verify_macaddr(struct eth_device *dev, char *s) +static int verify_macaddr(char *s) { u16 reg; int i, err = 0; @@ -88,7 +98,7 @@ static int verify_macaddr(struct eth_device *dev, char *s) printf("MAC Address: "); err = i = 0; for (i = 0; i < 3; i++) { - reg = read_eeprom_reg(dev, 0x20 + i); + reg = read_eeprom_reg(0x20 + i); printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); if (s) err |= reg != ((u16 *)s)[i]; @@ -97,7 +107,7 @@ static int verify_macaddr(struct eth_device *dev, char *s) return err ? 0 : 1; } -static int set_mac(struct eth_device *dev, char *s) +static int set_mac(char *s) { int i; char *e, eaddr[6]; @@ -109,7 +119,7 @@ static int set_mac(struct eth_device *dev, char *s) } for (i = 0; i < 3; i++) - write_eeprom_reg(dev, *(((u16 *)eaddr) + i), 0x20 + i); + write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); return 0; } @@ -145,10 +155,6 @@ int eeprom(int argc, char *argv[]) int i, len, ret; unsigned char buf[58], *p; - struct eth_device dev = { - .iobase = CONFIG_SMC91111_BASE - }; - app_startup(argv); if (get_version() != XF_VERSION) { printf("Wrong XF_VERSION.\n"); @@ -157,14 +163,14 @@ int eeprom(int argc, char *argv[]) return 1; } - if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) { + if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) { printf("SMSC91111 not found.\n"); return 2; } /* Called without parameters - print MAC address */ if (argc < 2) { - verify_macaddr(&dev, NULL); + verify_macaddr(NULL); return 0; } @@ -198,8 +204,8 @@ int eeprom(int argc, char *argv[]) } /* First argument (MAC) is mandatory */ - set_mac(&dev, argv[1]); - if (verify_macaddr(&dev, argv[1])) { + set_mac(argv[1]); + if (verify_macaddr(argv[1])) { printf("*** MAC address does not match! ***\n"); return 4; } @@ -207,7 +213,7 @@ int eeprom(int argc, char *argv[]) while (len--) *p++ = 0; - write_data(&dev, (u16 *)buf, sizeof(buf) >> 1); + write_data((u16 *)buf, sizeof(buf) >> 1); return 0; } -- cgit v1.1 From 308d463eaf6f4ada00193306a6e643298d1990d8 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Mon, 8 Feb 2010 14:15:43 -0500 Subject: NetStar: eeprom - be less verbose Use shorter yet descriptive messages, replace printf() with puts() where appropriate. This saves few bytes. Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- board/netstar/eeprom.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c index ad301eb..aca4458 100644 --- a/board/netstar/eeprom.c +++ b/board/netstar/eeprom.c @@ -48,7 +48,7 @@ static u16 read_eeprom_reg(u16 reg) while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout) udelay(100); if (timeout == 0) { - printf("Timeout Reading EEPROM register %02x\n", reg); + printf("Timeout reading register %02x\n", reg); return 0; } @@ -73,7 +73,7 @@ static int write_eeprom_reg(u16 value, u16 reg) while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout) udelay(100); if (timeout == 0) { - printf("Timeout Writing EEPROM register %02x\n", reg); + printf("Timeout writing register %02x\n", reg); return 0; } @@ -95,8 +95,7 @@ static int verify_macaddr(char *s) u16 reg; int i, err = 0; - printf("MAC Address: "); - err = i = 0; + puts("HWaddr: "); for (i = 0; i < 3; i++) { reg = read_eeprom_reg(0x20 + i); printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); @@ -156,15 +155,15 @@ int eeprom(int argc, char *argv[]) unsigned char buf[58], *p; app_startup(argv); - if (get_version() != XF_VERSION) { - printf("Wrong XF_VERSION.\n"); - printf("Application expects ABI version %d\n", XF_VERSION); - printf("Actual U-Boot ABI version %d\n", (int)get_version()); + i = get_version(); + if (i != XF_VERSION) { + printf("Using ABI version %d, but U-Boot provides %d\n", + XF_VERSION, i); return 1; } if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) { - printf("SMSC91111 not found.\n"); + puts("SMSC91111 not found\n"); return 2; } @@ -176,9 +175,9 @@ int eeprom(int argc, char *argv[]) /* Print help message */ if (argv[1][1] == 'h') { - printf("NetStar EEPROM writer\n"); - printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); - printf("Usage:\n\t [] [<...>]\n"); + puts("NetStar EEPROM writer\n" + "Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n" + "Usage:\n\t [] [<...>]\n"); return 0; } @@ -195,7 +194,7 @@ int eeprom(int argc, char *argv[]) printf("Element %d: odd character count\n", i - 1); return 3; case -3: - printf("Out of EEPROM memory\n"); + puts("Out of EEPROM memory\n"); return 3; default: p += ret; @@ -206,7 +205,7 @@ int eeprom(int argc, char *argv[]) /* First argument (MAC) is mandatory */ set_mac(argv[1]); if (verify_macaddr(argv[1])) { - printf("*** MAC address does not match! ***\n"); + puts("*** HWaddr does not match! ***\n"); return 4; } -- cgit v1.1 From 3a67566c1def7d2eb935b31b3b282ba893c3f330 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Mon, 8 Feb 2010 14:15:47 -0500 Subject: NetStar: eeprom - fix linker error linking eeprom with libgeneric.a is not really needed and causes following error: ../../lib_generic/libgeneric.a(string.o): In function `strcmp': lib_generic/string.c:152: multiple definition of `strcmp' ../../examples/standalone/libstubs.a(stubs.o):include/_exports.h:24: first defined here Remove eeprom linker script as well and generate entry point object (to start application by jumping on its beginning) on the fly. Out-of-tree build tested as well. Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- board/netstar/Makefile | 54 ++++++++++++++++++++------------------------ board/netstar/eeprom.lds | 51 ----------------------------------------- board/netstar/eeprom_start.S | 13 ----------- 3 files changed, 25 insertions(+), 93 deletions(-) delete mode 100644 board/netstar/eeprom.lds delete mode 100644 board/netstar/eeprom_start.S diff --git a/board/netstar/Makefile b/board/netstar/Makefile index 11578b7..c435762 100644 --- a/board/netstar/Makefile +++ b/board/netstar/Makefile @@ -29,20 +29,15 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS := netstar.o -SOBJS := setup.o crcek.o +SOBJS := setup.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c \ - eeprom_start.S +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) - LOAD_ADDR = 0x10400000 -LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds -lnk = $(if $(obj),$(obj),.) -HOSTCFLAGS = -Wall -pedantic -I$(TOPDIR)/include +######################################################################### all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \ $(obj)crcek.srec $(obj)crcek.bin $(obj)crcit @@ -50,41 +45,42 @@ all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \ $(LIB): $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $^ -$(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o $(obj)u-boot.lds - cd $(lnk) && $(LD) -T $(obj)u-boot.lds -g -Ttext $(LOAD_ADDR) \ - -o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \ +$(obj)eeprom_start.o: + echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ - + +$(obj)eeprom: $(obj)eeprom_start.o $(obj)eeprom.o + $(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \ -L$(obj)../../examples/standalone -lstubs \ - -L$(obj)../../lib_generic -lgeneric \ - -L$(gcclibdir) -lgcc - $(OBJCOPY) -O srec $(<:.o=) $@ + $(PLATFORM_LIBS) -$(obj)eeprom.bin: $(obj)eeprom.srec - $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null +$(obj)eeprom.srec: $(obj)eeprom + $(OBJCOPY) -S -O srec $(<:.o=) $@ + +$(obj)eeprom.bin: $(obj)eeprom + $(OBJCOPY) -S -O binary $< $@ $(obj)crcek.srec: $(obj)crcek.o - $(LD) -g -Ttext 0x00000000 \ - -o $(<:.o=) -e crcek $^ - $(OBJCOPY) -O srec $(<:.o=) $@ + $(LD) -g -Ttext 0x00000000 -e crcek -o $(<:.o=) $^ + $(OBJCOPY) -S -O srec $(<:.o=) $@ $(obj)crcek.bin: $(obj)crcek.srec - $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null + $(OBJCOPY) -I srec -O binary $< $@ $(obj)crcit: $(obj)crcit.o $(obj)crc32.o $(HOSTCC) $(HOSTCFLAGS) -o $@ $^ -$(obj)crcit.o: crcit.c +$(obj)crcit.o: crcit.c $(HOSTCC) $(HOSTCFLAGS) -o $@ -c $< -$(obj)crc32.o: $(SRCTREE)/lib_generic/crc32.c - $(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -o $@ -c $< - -$(obj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +$(obj)crc32.o: $(SRCTREE)/lib_generic/crc32.c + $(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -I$(TOPDIR)/include \ + -o $@ -c $< clean: - rm -f $(SOBJS) $(OBJS) $(obj)eeprom $(obj)eeprom.srec \ - $(obj)eeprom.bin $(obj)crcek $(obj)crcek.srec \ - $(obj)crcek.bin $(obj)u-boot.lds + rm -f $(SOBJS) $(OBJS) \ + $(obj)eeprom_start.o $(obj)eeprom.o \ + $(obj)eeprom $(obj)eeprom.srec $(obj)eeprom.bin \ + $(obj)crcek.o $(obj)crcek $(obj)crcek.srec $(obj)crcek.bin distclean: clean rm -f $(LIB) core *.bak $(obj).depend diff --git a/board/netstar/eeprom.lds b/board/netstar/eeprom.lds deleted file mode 100644 index 1e48494..0000000 --- a/board/netstar/eeprom.lds +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * (C) Copyright 2005 - * Ladislav Michl, 2N Telekomunikace, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = ALIGN(4); - .text : - { - eeprom_start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/board/netstar/eeprom_start.S b/board/netstar/eeprom_start.S deleted file mode 100644 index 3609382..0000000 --- a/board/netstar/eeprom_start.S +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2005 2N Telekomunikace - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -.globl _start -_start: b eeprom - -.end -- cgit v1.1 From de9a1e0d08301ea4925ee137af240424b107a608 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Mon, 8 Feb 2010 14:17:45 -0500 Subject: NetStar: fix default environment Correct switching partitions after upgrade and make it more readable. Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- include/configs/netstar.h | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/include/configs/netstar.h b/include/configs/netstar.h index 884dc09..df9402a 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -156,7 +156,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_RUN - /* * BOOTP options */ @@ -173,26 +172,27 @@ #define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ #define CONFIG_BOOTCOMMAND "run fboot" #define CONFIG_PREBOOT "run setup" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autostart=yes\0" \ - "ospart=0\0" \ - "setup=setenv bootargs console=ttyS0,$baudrate " \ - "$mtdparts\0" \ - "setpart=" \ - "if test -n $swapos; then " \ - "setenv swapos; saveenv; " \ - "else " \ - "if test $ospart -eq 0; then setenv ospart 1;" \ - "else setenv ospart 0; fi; " \ - "fi\0" \ - "nfsargs=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ - "nfsroot=$rootpath root=/dev/nfs\0" \ - "flashargs=run setpart;setenv bootargs $bootargs " \ - "root=mtd:rootfs$ospart ro " \ - "rootfstype=jffs2\0" \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ - "fboot=run flashargs;nboot kernel$ospart\0" \ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autostart=yes\0" \ + "ospart=0\0" \ + "setup=setenv bootargs console=ttyS0,$baudrate $mtdparts\0" \ + "setpart=" \ + "if test -n $swapos; then " \ + "setenv swapos; saveenv; " \ + "if test $ospart -eq 0; then " \ + "setenv ospart 1; " \ + "else " \ + "setenv ospart 0; " \ + "fi; " \ + "fi\0" \ + "nfsargs=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ + "nfsroot=$rootpath root=/dev/nfs\0" \ + "flashargs=run setpart;setenv bootargs $bootargs " \ + "root=mtd:rootfs$ospart ro " \ + "rootfstype=jffs2\0" \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ + "fboot=run flashargs;nboot kernel$ospart\0" \ "nboot=bootp;run nfsargs;tftp\0" #if 0 /* feel free to disable for development */ -- cgit v1.1 From d8775d03f3f0116241cfb45c7ef27fd080904c4a Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Mon, 8 Feb 2010 14:19:06 -0500 Subject: NetStar: make mtdparts default ready for recent kernels Recent kernels are using generic NAND and NOR drivers. Change default mtdparts to reflect it. Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- include/configs/netstar.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/include/configs/netstar.h b/include/configs/netstar.h index df9402a..edda3ce 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -133,11 +133,10 @@ #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0" +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=gen_nand.0" #define MTDPARTS_DEFAULT "mtdparts=" \ - "omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \ - "omapnand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)" - + "physmap-flash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \ + "gen_nand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)" /* * Command line configuration. -- cgit v1.1 From 37cffdad06af5a4538dd090794f213292135adbc Mon Sep 17 00:00:00 2001 From: Nick Thompson Date: Wed, 17 Feb 2010 20:37:24 -0500 Subject: da830evm: Add support for TI EMAC Adds support for ethernet networking on the da830evm platform. This platform uses an SoC EMAC interface and a 3 port ethernet switch as a PHY with an RMII interface. The PHY also has a i2c interface for configuring the switch functions. Signed-off-by: Nick Thompson Signed-off-by: Sandeep Paulraj --- board/davinci/da830evm/da830evm.c | 65 +++++++++++++++++++++++++++++++- include/asm-arm/arch-davinci/emac_defs.h | 1 + include/configs/da830evm.h | 1 + 3 files changed, 65 insertions(+), 2 deletions(-) diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da830evm/da830evm.c index aac5c5c..ed668af 100644 --- a/board/davinci/da830evm/da830evm.c +++ b/board/davinci/da830evm/da830evm.c @@ -34,8 +34,11 @@ #include #include +#include +#include #include #include +#include #include #include "../common/misc.h" @@ -69,6 +72,20 @@ static const struct pinmux_config emifa_nand_pins[] = { { pinmux[18], 1, 5 }, }; +/* EMAC PHY interface pins */ +static const struct pinmux_config emac_pins[] = { + { pinmux[9], 0, 5 }, + { pinmux[10], 2, 1 }, + { pinmux[10], 2, 2 }, + { pinmux[10], 2, 3 }, + { pinmux[10], 2, 4 }, + { pinmux[10], 2, 5 }, + { pinmux[10], 2, 6 }, + { pinmux[10], 2, 7 }, + { pinmux[11], 2, 0 }, + { pinmux[11], 2, 1 }, +}; + /* UART pin muxer settings */ static const struct pinmux_config uart_pins[] = { { pinmux[8], 2, 7 }, @@ -77,8 +94,8 @@ static const struct pinmux_config uart_pins[] = { /* I2C pin muxer settings */ static const struct pinmux_config i2c_pins[] = { - { pinmux[9], 2, 3 }, - { pinmux[9], 2, 4 } + { pinmux[8], 2, 3 }, + { pinmux[8], 2, 4 } }; /* USB0_DRVVBUS pin muxer settings */ @@ -98,6 +115,9 @@ static const struct pinmux_resource pinmuxes[] = { #ifdef CONFIG_USE_NAND PINMUX_ITEM(emifa_nand_pins), #endif +#if defined(CONFIG_DRIVER_TI_EMAC) + PINMUX_ITEM(emac_pins), +#endif }; int board_init(void) @@ -169,3 +189,44 @@ int board_init(void) return(0); } + +#if defined(CONFIG_DRIVER_TI_EMAC) + +#define PHY_SW_I2C_ADDR 0x5f /* Address of PHY on i2c bus */ + +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(bd_t *bis) +{ + u_int8_t mac_addr[6]; + u_int8_t switch_start_cmd[2] = { 0x01, 0x23 }; + + /* Read Ethernet MAC address from EEPROM */ + if (dvevm_read_mac_address(mac_addr)) + /* set address env if not already set */ + dv_configure_mac_address(mac_addr); + + /* read the address back from env */ + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) + return -1; + + /* provide the resulting addr to the driver */ + davinci_eth_set_mac_addr(mac_addr); + + /* enable the Ethernet switch in the 3 port PHY */ + if (i2c_write(PHY_SW_I2C_ADDR, 0, 0, + switch_start_cmd, sizeof(switch_start_cmd))) { + printf("Ethernet switch start failed!\n"); + return -1; + } + + /* finally, initialise the driver */ + if (!davinci_emac_initialize()) { + printf("Error: Ethernet init failed!\n"); + return -1; + } + + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/include/asm-arm/arch-davinci/emac_defs.h index e313263..b0ec8f5 100644 --- a/include/asm-arm/arch-davinci/emac_defs.h +++ b/include/asm-arm/arch-davinci/emac_defs.h @@ -367,6 +367,7 @@ typedef struct { int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); +void davinci_eth_set_mac_addr(const u_int8_t *addr); typedef struct { diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 65747fb..0f58e11 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -27,6 +27,7 @@ /* * Board */ +#define CONFIG_DRIVER_TI_EMAC /* * SoC Configuration -- cgit v1.1 From 3fca29294abd73915de2bd0fcf2650e03cc9becc Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Wed, 17 Feb 2010 21:09:21 -0500 Subject: DaVinci: Adding entry to MAKEALL for DM365 EVM The patch adds an entry for the DM365 EVM to MAKEALL Signed-off-by: Sandeep Paulraj --- MAKEALL | 1 + 1 file changed, 1 insertion(+) diff --git a/MAKEALL b/MAKEALL index 1e660b6..6ddf7e0 100755 --- a/MAKEALL +++ b/MAKEALL @@ -599,6 +599,7 @@ LIST_ARM9=" \ davinci_sonata \ davinci_dm355evm \ davinci_dm355leopard \ + davinci_dm365evm \ davinci_dm6467evm \ " -- cgit v1.1 From 779b534385adf0a1efdd8b40dbacae11598575b8 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Wed, 17 Feb 2010 21:13:53 -0500 Subject: netstar.h: do not exceed 80 columns Limit line length to 80 characters mostly by removing obvious and sometimes misleading comments. Fix indentation, too. Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- include/configs/netstar.h | 65 ++++++++++++++++++++++------------------------- 1 file changed, 31 insertions(+), 34 deletions(-) diff --git a/include/configs/netstar.h b/include/configs/netstar.h index edda3ce..c63c846 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -27,17 +27,13 @@ #include -/* - * High Level Configuration Options - * (easy to change) - */ #define CONFIG_ARM925T 1 /* This is an arm925t CPU */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP1510 1 /* which is in a 5910 */ /* Input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */ -#define CONFIG_XTAL_FREQ 12000000 +#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz */ +#define CONFIG_XTAL_FREQ 12000000 /* 12MHz */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -54,10 +50,10 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x10000000 +#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) +#define PHYS_FLASH_1 0x00000000 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) @@ -66,23 +62,23 @@ * Environment settings */ #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR 0x4000 -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_SECT_SIZE (8 * 1024) -#define CONFIG_ENV_ADDR_REDUND 0x6000 -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_ADDR 0x4000 +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SECT_SIZE (8 * 1024) +#define CONFIG_ENV_ADDR_REDUND 0x6000 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_OVERWRITE /* * Size of malloc() pool */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* * The stack size is set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (1 * 1024 * 1024) /* regular stack */ +#define CONFIG_STACKSIZE (1 * 1024 * 1024) /* * Hardware drivers @@ -90,8 +86,8 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ +#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) +#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE #define CONFIG_NET_MULTI #define CONFIG_SMC91111 @@ -128,10 +124,10 @@ /*#define CONFIG_SKIP_LOWLEVEL_INIT */ /* - * partitions (mtdparts command line support) + * Partitions (mtdparts command line support) */ #define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_DEVICE #define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=gen_nand.0" #define MTDPARTS_DEFAULT "mtdparts=" \ @@ -139,7 +135,7 @@ "gen_nand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)" /* - * Command line configuration. + * Command line configuration */ #define CONFIG_CMD_BDI #define CONFIG_CMD_BOOTD @@ -204,12 +200,13 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " @@ -217,9 +214,9 @@ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \ - (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE) + (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE) -#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x400000) /* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1. * This time is further subdivided by a local divisor. @@ -228,9 +225,9 @@ #define CONFIG_SYS_PTV 7 #define CONFIG_SYS_HZ 1000 -#define OMAP5910_DPLL_DIV 1 -#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ - (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) +#define OMAP5910_DPLL_DIV 1 +#define OMAP5910_DPLL_MUL \ + ((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) #define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ #define OMAP5910_LCD_DIV 2 /* CKL/4 */ @@ -240,7 +237,7 @@ #define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ #define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ -#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */ +#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b */ #define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ (OMAP5910_LCD_DIV << 2) | \ (OMAP5910_ARM_DIV << 4) | \ -- cgit v1.1 From a32c1e0ecd563c65c617b0eb9080a10d286bb0b4 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Wed, 17 Feb 2010 21:29:39 -0500 Subject: VoiceBlue: limit line lenght to 80 characters Reindent configuration header to limit line lenght to 80 characters by removing obvious and sometimes misleading comments. Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- include/configs/voiceblue.h | 168 +++++++++++++++++++++----------------------- 1 file changed, 82 insertions(+), 86 deletions(-) diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h index 0dde65d..d46717c 100644 --- a/include/configs/voiceblue.h +++ b/include/configs/voiceblue.h @@ -31,8 +31,8 @@ #define CONFIG_OMAP1510 1 /* which is in a 5910 */ /* Input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */ -#define CONFIG_XTAL_FREQ 12000000 +#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz */ +#define CONFIG_XTAL_FREQ 12000000 /* 12MHz */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -48,55 +48,53 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x10000000 +#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) +#define PHYS_FLASH_1 0x0000000 -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ - -/* - * FLASH organization - */ -#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/* FIXME: Does not work on AMD flash */ -/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */ /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max # of sectors on one chip */ - -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* * Environment settings */ #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_OVERWRITE /* * Size of malloc() pool and stack */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) -#define CONFIG_STACKSIZE (1 * 1024 * 1024) -#define PHYS_SDRAM_1_RESERVED (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE) +#define CONFIG_STACKSIZE (1 * 1024 * 1024) /* * Hardware drivers */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) +#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE + #define CONFIG_NET_MULTI #define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE 0x08000300 +#define CONFIG_SMC91111_BASE 0x08000300 + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_HARD_I2C #define CONFIG_SYS_I2C_SPEED 100000 @@ -104,24 +102,16 @@ #define CONFIG_DRIVER_OMAP1510_I2C #define CONFIG_RTC_DS1307 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* - * Command line configuration. + * Command line configuration */ #include @@ -138,7 +128,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_RUN - /* * BOOTP options */ @@ -147,36 +136,39 @@ #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_BOOTPATH - #define CONFIG_LOOPW #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ -#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ +#define CONFIG_SYS_AUTOLOAD "n" #define CONFIG_BOOTCOMMAND "run nboot" #define CONFIG_PREBOOT "run setup" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "silent=1\0" \ - "ospart=0\0" \ - "bootfile=/boot/uImage\0" \ - "setpart=" \ - "if test -n $swapos; then " \ - "setenv swapos; saveenv; " \ - "if test $ospart -eq 0; then setenv ospart 1; else setenv ospart 0; fi; "\ - "fi\0" \ - "setup=setenv bootargs console=ttyS0,$baudrate " \ - "mtdparts=$mtdparts\0" \ - "nfsargs=setenv bootargs $bootargs " \ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "silent=1\0" \ + "ospart=0\0" \ + "bootfile=/boot/uImage\0" \ + "setpart=" \ + "if test -n $swapos; then " \ + "setenv swapos; saveenv; " \ + "if test $ospart -eq 0; then " \ + "setenv ospart 1; " \ + "else " \ + "setenv ospart 0; " \ + "fi; " \ + "fi\0" \ + "setup=setenv bootargs console=ttyS0,$baudrate " \ + "mtdparts=$mtdparts\0" \ + "nfsargs=setenv bootargs $bootargs " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ - "nfsroot=$rootpath root=/dev/nfs\0" \ - "flashargs=run setpart; setenv bootargs $bootargs " \ - "root=mtd:data$ospart ro " \ - "rootfstype=jffs2\0" \ - "initrdargs=setenv bootargs $bootargs " \ + "nfsroot=$rootpath root=/dev/nfs\0" \ + "flashargs=run setpart; setenv bootargs $bootargs " \ + "root=mtd:data$ospart ro " \ + "rootfstype=jffs2\0" \ + "initrdargs=setenv bootargs $bootargs " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ - "fboot=run flashargs; chpart data$ospart; fsload; bootm\0" \ - "mboot=bootp; run initrdargs; tftp; bootm\0" \ + "fboot=run flashargs; chpart data$ospart; fsload; bootm\0" \ + "mboot=bootp; run initrdargs; tftp; bootm\0" \ "nboot=bootp; run nfsargs; tftp; bootm\0" #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ @@ -188,14 +180,14 @@ #endif /* - * JFFS2 partitions (mtdparts command line support) + * Partitions (mtdparts command line support) */ #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=omapflash.0" -#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)" - +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ + "256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)" /* * Miscellaneous configurable options @@ -203,26 +195,30 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1) +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \ + (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)) +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x400000) -/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1. +/* + * The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1. * This time is further subdivided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ +#define CONFIG_SYS_HZ 1000 -#define OMAP5910_DPLL_DIV 1 -#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ - (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) +#define OMAP5910_DPLL_DIV 1 +#define OMAP5910_DPLL_MUL \ + ((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) #define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ #define OMAP5910_LCD_DIV 2 /* CKL/4 */ -- cgit v1.1 From 5c97a1de196fdcbe9d098948ecf4fccfbea23b78 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Wed, 17 Feb 2010 21:29:45 -0500 Subject: VoiceBlue: fix linker errors linking eeprom with libgeneric.a is not really needed and causes following error: ../../lib_generic/libgeneric.a(string.o): In function `strcmp': /home/ladis/src/u-boot-ti/lib_generic/string.c:152: multiple definition of `strcmp' ../../examples/standalone/libstubs.a(stubs.o):include/_exports.h:24: first defined here make[1]: *** [eeprom.srec] Error 1 Fix undefined reference to memset generated by some versions of gcc to zero out initialized structure on the stack: eeprom.o: In function `eeprom': board/voiceblue/eeprom.c:152: undefined reference to `memset' make[1]: *** [eeprom] Error 1 Signed-off-by: Ladislav Michl Signed-off-by: Sandeep Paulraj --- board/voiceblue/Makefile | 33 +++++++------- board/voiceblue/eeprom.c | 97 ++++++++++++++++++++++-------------------- board/voiceblue/eeprom.lds | 51 ---------------------- board/voiceblue/eeprom_start.S | 11 ----- 4 files changed, 65 insertions(+), 127 deletions(-) delete mode 100644 board/voiceblue/eeprom.lds delete mode 100644 board/voiceblue/eeprom_start.S diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile index 121c717..0067f05 100644 --- a/board/voiceblue/Makefile +++ b/board/voiceblue/Makefile @@ -29,40 +29,37 @@ LIB = $(obj)lib$(BOARD).a COBJS := voiceblue.o SOBJS := setup.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c eeprom_start.S +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) - LOAD_ADDR = 0x10400000 -LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds -lnk = $(if $(obj),$(obj),.) + +######################################################################### all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $^ + +$(obj)eeprom_start.o: + echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ - -$(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o $(obj)u-boot.lds - cd $(lnk) && $(LD) -T $(obj)u-boot.lds -g -Ttext $(LOAD_ADDR) \ - -o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \ +$(obj)eeprom: $(obj)eeprom_start.o $(obj)eeprom.o + $(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \ -L$(obj)../../examples/standalone -lstubs \ - -L$(obj)../../lib_generic -lgeneric \ - -L$(gcclibdir) -lgcc - $(OBJCOPY) -O srec $(<:.o=) $@ + $(PLATFORM_LIBS) -$(obj)eeprom.bin: $(obj)eeprom.srec - $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null +$(obj)eeprom.srec: $(obj)eeprom + $(OBJCOPY) -S -O srec $(<:.o=) $@ -$(obj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +$(obj)eeprom.bin: $(obj)eeprom + $(OBJCOPY) -S -O binary $< $@ clean: rm -f $(SOBJS) $(OBJS) $(obj)eeprom \ $(obj)eeprom.srec $(obj)eeprom.bin \ - $(obj)eeprom.o $(obj)eeprom_start.o \ - $(obj)u-boot.lds + $(obj)eeprom.o $(obj)eeprom_start.o distclean: clean rm -f $(LIB) core *.bak $(obj).depend diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c index 2ae46d1..f7e0ba5 100644 --- a/board/voiceblue/eeprom.c +++ b/board/voiceblue/eeprom.c @@ -22,75 +22,82 @@ * Some code shamelessly stolen back from Robin Getz. */ -#define DEBUG - #include #include #include #include #include "../drivers/net/smc91111.h" -static u16 read_eeprom_reg(struct eth_device *dev, u16 reg) +static struct eth_device dev = { + .iobase = CONFIG_SMC91111_BASE +}; + +static u16 read_eeprom_reg(u16 reg) { int timeout; - SMC_SELECT_BANK(dev, 2); - SMC_outw(dev, reg, PTR_REG); + SMC_SELECT_BANK(&dev, 2); + SMC_outw(&dev, reg, PTR_REG); + + SMC_SELECT_BANK(&dev, 1); + SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT | + CTL_RELOAD, CTL_REG); - SMC_SELECT_BANK(dev, 1); - SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, - CTL_REG); timeout = 100; - while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout) + + while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout) udelay(100); if (timeout == 0) { - printf("Timeout Reading EEPROM register %02x\n", reg); + printf("Timeout reading register %02x\n", reg); return 0; } - return SMC_inw (dev, GP_REG); + return SMC_inw(&dev, GP_REG); } -static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg) +static int write_eeprom_reg(u16 value, u16 reg) { int timeout; - SMC_SELECT_BANK(dev, 2); - SMC_outw(dev, reg, PTR_REG); + SMC_SELECT_BANK(&dev, 2); + SMC_outw(&dev, reg, PTR_REG); + + SMC_SELECT_BANK(&dev, 1); + + SMC_outw(&dev, value, GP_REG); + SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT | + CTL_STORE, CTL_REG); - SMC_SELECT_BANK(dev, 1); - SMC_outw(dev, value, GP_REG); - SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); timeout = 100; - while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout) - udelay (100); + + while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout) + udelay(100); if (timeout == 0) { - printf("Timeout Writing EEPROM register %02x\n", reg); + printf("Timeout writing register %02x\n", reg); return 0; } return 1; } -static int write_data(struct eth_device *dev, u16 *buf, int len) +static int write_data(u16 *buf, int len) { u16 reg = 0x23; while (len--) - write_eeprom_reg(dev, *buf++, reg++); + write_eeprom_reg(*buf++, reg++); return 0; } -static int verify_macaddr(struct eth_device *dev, char *s) +static int verify_macaddr(char *s) { u16 reg; int i, err = 0; - printf("MAC Address: "); - err = i = 0; + puts("HWaddr: "); for (i = 0; i < 3; i++) { - reg = read_eeprom_reg(dev, 0x20 + i); + reg = read_eeprom_reg(0x20 + i); printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); if (s) err |= reg != ((u16 *)s)[i]; @@ -99,7 +106,7 @@ static int verify_macaddr(struct eth_device *dev, char *s) return err ? 0 : 1; } -static int set_mac(struct eth_device *dev, char *s) +static int set_mac(char *s) { int i; char *e, eaddr[6]; @@ -111,7 +118,7 @@ static int set_mac(struct eth_device *dev, char *s) } for (i = 0; i < 3; i++) - write_eeprom_reg(dev, *(((u16 *)eaddr) + i), 0x20 + i); + write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); return 0; } @@ -147,34 +154,30 @@ int eeprom(int argc, char *argv[]) int i, len, ret; unsigned char buf[58], *p; - struct eth_device dev = { - .iobase = CONFIG_SMC91111_BASE - }; - app_startup(argv); - if (get_version() != XF_VERSION) { - printf("Wrong XF_VERSION.\n"); - printf("Application expects ABI version %d\n", XF_VERSION); - printf("Actual U-Boot ABI version %d\n", (int)get_version()); + i = get_version(); + if (i != XF_VERSION) { + printf("Using ABI version %d, but U-Boot provides %d\n", + XF_VERSION, i); return 1; } - if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) { - printf("SMSC91111 not found.\n"); + if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) { + puts("SMSC91111 not found\n"); return 2; } /* Called without parameters - print MAC address */ if (argc < 2) { - verify_macaddr(&dev, NULL); + verify_macaddr(NULL); return 0; } /* Print help message */ if (argv[1][1] == 'h') { - printf("VoiceBlue EEPROM writer\n"); - printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); - printf("Usage:\n\t [] [<...>]\n"); + puts("VoiceBlue EEPROM writer\n" + "Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n" + "Usage:\n\t [] [<...>]\n"); return 0; } @@ -191,7 +194,7 @@ int eeprom(int argc, char *argv[]) printf("Element %d: odd character count\n", i - 1); return 3; case -3: - printf("Out of EEPROM memory\n"); + puts("Out of EEPROM memory\n"); return 3; default: p += ret; @@ -200,16 +203,16 @@ int eeprom(int argc, char *argv[]) } /* First argument (MAC) is mandatory */ - set_mac(&dev, argv[1]); - if (verify_macaddr(&dev, argv[1])) { - printf("*** MAC address does not match! ***\n"); + set_mac(argv[1]); + if (verify_macaddr(argv[1])) { + puts("*** HWaddr does not match! ***\n"); return 4; } while (len--) *p++ = 0; - write_data(&dev, (u16 *)buf, sizeof(buf) >> 1); + write_data((u16 *)buf, sizeof(buf) >> 1); return 0; } diff --git a/board/voiceblue/eeprom.lds b/board/voiceblue/eeprom.lds deleted file mode 100644 index 1e48494..0000000 --- a/board/voiceblue/eeprom.lds +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * (C) Copyright 2005 - * Ladislav Michl, 2N Telekomunikace, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = ALIGN(4); - .text : - { - eeprom_start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/board/voiceblue/eeprom_start.S b/board/voiceblue/eeprom_start.S deleted file mode 100644 index 8f88de5..0000000 --- a/board/voiceblue/eeprom_start.S +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2005 2N Telekomunikace - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -.globl _start -_start: b eeprom -- cgit v1.1 From 7c966a8bdfdab80cafbfed035d7ae6ea6f58f756 Mon Sep 17 00:00:00 2001 From: Achim Ehrlich Date: Wed, 24 Feb 2010 10:29:16 +0100 Subject: ARM change name of defines for AT91 arm926ejs Configuration defines should be preceeded with CONFIG_SYS_. Renamed some at91 specific defines to conform to this naming convention: AT91_CPU_NAME to CONFIG_SYS_AT91_CPU_NAME AT91_MAIN_CLOCK to CONFIG_SYS_AT91_MAIN_CLOCK Signed-off-by: Achim Ehrlich --- board/atmel/at91cap9adk/at91cap9adk.c | 2 +- board/atmel/at91sam9261ek/at91sam9261ek.c | 2 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 2 +- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 2 +- board/atmel/at91sam9rlek/at91sam9rlek.c | 2 +- board/esd/otc570/otc570.c | 2 +- board/ronetix/pm9261/pm9261.c | 2 +- board/ronetix/pm9263/pm9263.c | 2 +- cpu/arm926ejs/at91/clock.c | 2 +- cpu/arm926ejs/at91/cpu.c | 8 ++++---- include/asm-arm/arch-at91/at91cap9.h | 2 +- include/asm-arm/arch-at91/at91rm9200.h | 2 +- include/asm-arm/arch-at91/at91sam9260.h | 4 ++-- include/asm-arm/arch-at91/at91sam9261.h | 2 +- include/asm-arm/arch-at91/at91sam9263.h | 2 +- include/asm-arm/arch-at91/at91sam9g45.h | 2 +- include/asm-arm/arch-at91/at91sam9rl.h | 2 +- include/configs/afeb9260.h | 2 +- include/configs/at91cap9adk.h | 2 +- include/configs/at91sam9260ek.h | 2 +- include/configs/at91sam9261ek.h | 2 +- include/configs/at91sam9263ek.h | 2 +- include/configs/at91sam9m10g45ek.h | 2 +- include/configs/at91sam9rlek.h | 2 +- include/configs/cpu9260.h | 2 +- include/configs/pm9261.h | 4 ++-- include/configs/pm9263.h | 2 +- include/configs/sbc35_a9g20.h | 2 +- include/configs/tny_a9260.h | 2 +- 29 files changed, 34 insertions(+), 34 deletions(-) diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c index 9f73df6..258d1ea 100644 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ b/board/atmel/at91cap9adk/at91cap9adk.c @@ -282,7 +282,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - AT91_CPU_NAME, + CONFIG_SYS_AT91_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 7ead2b8..de5cfae 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -217,7 +217,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - AT91_CPU_NAME, + CONFIG_SYS_AT91_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 8ab45af..5cd7aa7 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -218,7 +218,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - AT91_CPU_NAME, + CONFIG_SYS_AT91_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 45a14a9..edfb627 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -217,7 +217,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - AT91_CPU_NAME, + CONFIG_SYS_AT91_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 7013ba2..e374917 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -157,7 +157,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - AT91_CPU_NAME, + CONFIG_SYS_AT91_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c index 056df37..3fe28cb 100644 --- a/board/esd/otc570/otc570.c +++ b/board/esd/otc570/otc570.c @@ -219,7 +219,7 @@ void lcd_show_board_info(void) nand_size += nand_info[i].size; lcd_printf("\n%s\n", U_BOOT_VERSION); - lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME, + lcd_printf("%s CPU at %s MHz\n", CONFIG_SYS_AT91_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 6915b9b..8662339 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -189,7 +189,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2009 Ronetix GmbH\n"); lcd_printf ("support@ronetix.at\n"); lcd_printf ("%s CPU at %s MHz", - AT91_CPU_NAME, + CONFIG_SYS_AT91_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 29555f8..23ea154 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -304,7 +304,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2009 Ronetix GmbH\n"); lcd_printf ("support@ronetix.at\n"); lcd_printf ("%s CPU at %s MHz", - AT91_CPU_NAME, + CONFIG_SYS_AT91_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c index 7e03907..444d42d 100644 --- a/cpu/arm926ejs/at91/clock.c +++ b/cpu/arm926ejs/at91/clock.c @@ -147,7 +147,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; -#ifndef AT91_MAIN_CLOCK +#ifndef CONFIG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c index 993b299..1094f8c 100644 --- a/cpu/arm926ejs/at91/cpu.c +++ b/cpu/arm926ejs/at91/cpu.c @@ -31,13 +31,13 @@ #include #include -#ifndef AT91_MAIN_CLOCK -#define AT91_MAIN_CLOCK 0 +#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 0 #endif int arch_cpu_init(void) { - return at91_clock_init(AT91_MAIN_CLOCK); + return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); } #if defined(CONFIG_DISPLAY_CPUINFO) @@ -45,7 +45,7 @@ int print_cpuinfo(void) { char buf[32]; - printf("CPU: %s\n", AT91_CPU_NAME); + printf("CPU: %s\n", CONFIG_SYS_AT91_CPU_NAME); printf("Crystal frequency: %8s MHz\n", strmhz(buf, get_main_clk_rate())); printf("CPU clock : %8s MHz\n", diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h index 658124b..5af6fdc 100644 --- a/include/asm-arm/arch-at91/at91cap9.h +++ b/include/asm-arm/arch-at91/at91cap9.h @@ -145,6 +145,6 @@ /* * Cpu Name */ -#define AT91_CPU_NAME "AT91CAP9" +#define CONFIG_SYS_AT91_CPU_NAME "AT91CAP9" #endif diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h index 990f5a6..1bee6f2 100644 --- a/include/asm-arm/arch-at91/at91rm9200.h +++ b/include/asm-arm/arch-at91/at91rm9200.h @@ -130,6 +130,6 @@ #define AT91_PMX_CA_NCS7 0x00002000 #define AT91_PMX_CA_D16_31 0xFFFF0000 -#define AT91_CPU_NAME "AT91RM9200" +#define CONFIG_SYS_AT91_CPU_NAME "AT91RM9200" #endif diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h index 7ca6078..a60a081 100644 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ b/include/asm-arm/arch-at91/at91sam9260.h @@ -139,9 +139,9 @@ * Cpu Name */ #if defined(CONFIG_AT91SAM9260) -#define AT91_CPU_NAME "AT91SAM9260" +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260" #elif defined(CONFIG_AT91SAM9G20) -#define AT91_CPU_NAME "AT91SAM9G20" +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20" #endif #endif diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h index 1d8cab6..2952292 100644 --- a/include/asm-arm/arch-at91/at91sam9261.h +++ b/include/asm-arm/arch-at91/at91sam9261.h @@ -114,6 +114,6 @@ /* * Cpu Name */ -#define AT91_CPU_NAME "AT91SAM9261" +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" #endif diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h index b26b7b4..c177bd0 100644 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ b/include/asm-arm/arch-at91/at91sam9263.h @@ -147,6 +147,6 @@ /* * Cpu Name */ -#define AT91_CPU_NAME "AT91SAM9263" +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" #endif diff --git a/include/asm-arm/arch-at91/at91sam9g45.h b/include/asm-arm/arch-at91/at91sam9g45.h index 99c03f7..445f4b2 100644 --- a/include/asm-arm/arch-at91/at91sam9g45.h +++ b/include/asm-arm/arch-at91/at91sam9g45.h @@ -147,6 +147,6 @@ /* * Cpu Name */ -#define AT91_CPU_NAME "AT91SAM9G45" +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" #endif diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h index 12054f6..8eb0d4f 100644 --- a/include/asm-arm/arch-at91/at91sam9rl.h +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -125,6 +125,6 @@ /* * Cpu Name */ -#define AT91_CPU_NAME "AT91SAM9RL" +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9RL" #endif diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 9f8c567..24484fd 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -29,7 +29,7 @@ #define CONFIG_AT91_LEGACY /* ARM asynchronous clock */ -#define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ #define CONFIG_SYS_HZ 1000 #define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index 9da5846..44c2870 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -30,7 +30,7 @@ #define CONFIG_AT91_LEGACY /* ARM asynchronous clock */ -#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index ff1e5b3..b89242b 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -30,7 +30,7 @@ #define CONFIG_AT91_LEGACY /* ARM asynchronous clock */ -#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 63b55d2..df8181b 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -30,7 +30,7 @@ #define CONFIG_AT91_LEGACY /* ARM asynchronous clock */ -#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 5a46d6a..5cafa1e 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -28,7 +28,7 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index ce21831..44c5496 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -30,7 +30,7 @@ #define CONFIG_AT91_LEGACY /* ARM asynchronous clock */ -#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 95f3d6c..e8fcd66 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -30,7 +30,7 @@ #define CONFIG_AT91_LEGACY /* ARM asynchronous clock */ -#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h index 38f34c2..fb6f79a 100644 --- a/include/configs/cpu9260.h +++ b/include/configs/cpu9260.h @@ -35,7 +35,7 @@ #define CONFIG_DISPLAY_CPUINFO 1 -#define AT91_MAIN_CLOCK 18432000 +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 8ee132b..47bb8c0 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -31,14 +31,14 @@ #define CONFIG_AT91_LEGACY /* ARM asynchronous clock */ -#define AT91_CPU_NAME "AT91SAM9261" +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" #define CONFIG_DISPLAY_BOARDINFO #define MASTER_PLL_DIV 15 #define MASTER_PLL_MUL 162 #define MAIN_PLL_DIV 2 -#define AT91_MAIN_CLOCK 18432000 +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index a6fdcaa..807dba8 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -37,7 +37,7 @@ #define MASTER_PLL_DIV 6 #define MASTER_PLL_MUL 65 #define MAIN_PLL_DIV 2 /* 2 or 4 */ -#define AT91_MAIN_CLOCK 18432000 +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index 1f2ff9e..b9f27cc 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -41,7 +41,7 @@ #endif /* ARM asynchronous clock */ -#define AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */ #define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h index a159a40..5af2af3 100644 --- a/include/configs/tny_a9260.h +++ b/include/configs/tny_a9260.h @@ -51,7 +51,7 @@ #endif /* ARM asynchronous clock */ -#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -- cgit v1.1 From 041d42e789aba20296ffcde92173f100a9592880 Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Tue, 23 Feb 2010 23:56:36 -0500 Subject: OMAP3: workaround for ARM Cortex-A8 erratum 725233 725233: PLD instructions executed with PLD data forwarding enabled can result in a processor deadlock This deadlock can happen when NEON load instructions are used together with cache preload instructions (PLD). The problematic conditions can be triggered in-the-wild by NEON optimized functions from pixman library (http://cgit.freedesktop.org/pixman), which perform dynamic adjustment of prefetch distance. The workaround disables PLD data forwarding by setting PLD_FWD bit in L2 Cache Auxiliary Control Register as recommended in ARM Cortex-A8 errata list. The deadlock can only happen on r1pX revisions of Cortex-A8 (used in OMAP34xx/OMAP35xx). Performance impact of the workaround is practically non-existant. Signed-off-by: Siarhei Siamashka Signed-off-by: Sandeep Paulraj --- cpu/arm_cortexa8/omap3/board.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 2aa69b3..7b78fa4 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -146,6 +146,12 @@ void setup_auxcr() __asm__ __volatile__("orr r0, r0, #1 << 5"); /* SMI instruction to call ROM Code API */ __asm__ __volatile__(".word 0xE1600070"); + /* Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) */ + __asm__ __volatile__("mov r12, #0x2"); + __asm__ __volatile__("mrc p15, 1, r0, c9, c0, 2"); + __asm__ __volatile__("orr r0, r0, #1 << 27"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); __asm__ __volatile__("mov r0, %0":"=r"(i)); __asm__ __volatile__("mov r12, %0":"=r"(j)); } -- cgit v1.1 From d9f505e3cddbb7afce26dcfe0fd19b207ee57c09 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 24 Feb 2010 00:22:00 +0100 Subject: ep93xx: Fix calculation of sys ticks in clk_to_systicks() ep93xx: Use unsigned long long for calculation of sys ticks in clk_to_systicks() for proper handling of large intermediate values Signed-off-by: Matthias Kaehlcke --- cpu/arm920t/ep93xx/timer.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c index 6d969d9..98c759c 100644 --- a/cpu/arm920t/ep93xx/timer.c +++ b/cpu/arm920t/ep93xx/timer.c @@ -31,6 +31,7 @@ #include #include #include +#include #define TIMER_CLKSEL (1 << 3) #define TIMER_MODE (1 << 6) @@ -44,9 +45,10 @@ static ulong lastdec; static inline unsigned long clk_to_systicks(unsigned long clk_ticks) { - unsigned long sys_ticks = (clk_ticks * CONFIG_SYS_HZ) / TIMER_FREQ; + unsigned long long sys_ticks = (clk_ticks * CONFIG_SYS_HZ); + do_div(sys_ticks, TIMER_FREQ); - return sys_ticks; + return (unsigned long)sys_ticks; } static inline unsigned long usecs_to_ticks(unsigned long usecs) -- cgit v1.1 From c7ad13a24295ded880d7bcd17181df4a5f3bac58 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 24 Feb 2010 00:22:09 +0100 Subject: ep93xx: Refactoring of timer code ep93xx: Refactoring of the timer code, including the following changes * use a free running timer instead of a periodical one * use unsigned long long for total number of ticks * hold the timer state in a structure instead of separate variables * increment the timer counter instead of decrementing it * remove unused function udelay_masked() * remove unused function set_timer() Signed-off-by: Matthias Kaehlcke --- cpu/arm920t/ep93xx/timer.c | 70 +++++++++++++++++----------------------------- 1 file changed, 26 insertions(+), 44 deletions(-) diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c index 98c759c..b1a01a0 100644 --- a/cpu/arm920t/ep93xx/timer.c +++ b/cpu/arm920t/ep93xx/timer.c @@ -34,16 +34,18 @@ #include #define TIMER_CLKSEL (1 << 3) -#define TIMER_MODE (1 << 6) #define TIMER_ENABLE (1 << 7) -#define TIMER_FREQ 508469 -#define TIMER_LOAD_VAL (TIMER_FREQ / CONFIG_SYS_HZ) +#define TIMER_FREQ 508469 +#define TIMER_MAX_VAL 0xFFFFFFFF -static ulong timestamp; -static ulong lastdec; +static struct ep93xx_timer +{ + unsigned long long ticks; + unsigned long last_update; +} timer; -static inline unsigned long clk_to_systicks(unsigned long clk_ticks) +static inline unsigned long clk_to_systicks(unsigned long long clk_ticks) { unsigned long long sys_ticks = (clk_ticks * CONFIG_SYS_HZ); do_div(sys_ticks, TIMER_FREQ); @@ -57,10 +59,10 @@ static inline unsigned long usecs_to_ticks(unsigned long usecs) if (usecs >= 1000) { ticks = usecs / 1000; - ticks *= (TIMER_LOAD_VAL * CONFIG_SYS_HZ); + ticks *= TIMER_FREQ; ticks /= 1000; } else { - ticks = usecs * TIMER_LOAD_VAL * CONFIG_SYS_HZ; + ticks = usecs * TIMER_FREQ; ticks /= (1000 * 1000); } @@ -71,7 +73,7 @@ static inline unsigned long read_timer(void) { struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; - return readl(&timer->timer3.value); + return TIMER_MAX_VAL - readl(&timer->timer3.value); } /* @@ -81,17 +83,15 @@ unsigned long long get_ticks(void) { const unsigned long now = read_timer(); - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } + if (now >= timer.last_update) + timer.ticks += now - timer.last_update; + else + /* an overflow occurred */ + timer.ticks += TIMER_MAX_VAL - timer.last_update + now; - lastdec = now; + timer.last_update = now; - return timestamp; + return timer.ticks; } unsigned long get_timer_masked(void) @@ -106,8 +106,8 @@ unsigned long get_timer(unsigned long base) void reset_timer_masked(void) { - lastdec = read_timer(); - timestamp = 0; + timer.last_update = read_timer(); + timer.ticks = 0; } void reset_timer(void) @@ -115,28 +115,11 @@ void reset_timer(void) reset_timer_masked(); } -void set_timer(unsigned long t) -{ - timestamp = t; -} - void __udelay(unsigned long usec) { - const unsigned long ticks = usecs_to_ticks(usec); - const unsigned long target = clk_to_systicks(ticks) + get_timer(0); - - while (get_timer_masked() < target) - /* noop */; -} - -void udelay_masked(unsigned long usec) -{ - const unsigned long ticks = usecs_to_ticks(usec); - const unsigned long target = clk_to_systicks(ticks) + get_timer(0); - - reset_timer_masked(); + const unsigned long target = get_ticks() + usecs_to_ticks(usec); - while (get_timer_masked() < target) + while (get_ticks() < target) /* noop */; } @@ -147,12 +130,11 @@ int timer_init(void) /* use timer 3 with 508KHz and free running */ writel(TIMER_CLKSEL, &timer->timer3.control); - /* auto load, manual update of Timer 3 */ - lastdec = TIMER_LOAD_VAL; - writel(TIMER_LOAD_VAL, &timer->timer3.load); + /* set initial timer value 3 */ + writel(TIMER_MAX_VAL, &timer->timer3.load); - /* Enable the timer and periodic mode */ - writel(TIMER_ENABLE | TIMER_MODE | TIMER_CLKSEL, + /* Enable the timer */ + writel(TIMER_ENABLE | TIMER_CLKSEL, &timer->timer3.control); reset_timer_masked(); -- cgit v1.1 From 5f353484093876d7021f20fa4bd63f82d32941b9 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Thu, 25 Feb 2010 12:05:32 -0600 Subject: ARM Update mach-types Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit aea187c46f7d03ce985e55eb1398d0776a15b928 Signed-off-by: Tom Rix --- include/asm-arm/mach-types.h | 1028 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1021 insertions(+), 7 deletions(-) diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 3b46327..4622557 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -2253,7 +2253,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_ORATISMADI 2269 #define MACH_TYPE_ORATISOT16 2270 #define MACH_TYPE_ORATISDESK 2271 -#define MACH_TYPE_V2P_CA9 2272 +#define MACH_TYPE_VEXPRESS 2272 #define MACH_TYPE_SINTEXO 2273 #define MACH_TYPE_CM3389 2274 #define MACH_TYPE_OMAP3_CIO 2275 @@ -2621,6 +2621,84 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_LUX_SFT9 2638 #define MACH_TYPE_NEMID_TB 2639 #define MACH_TYPE_TERRIER 2640 +#define MACH_TYPE_TURBOT 2641 +#define MACH_TYPE_SANDDAB 2642 +#define MACH_TYPE_MX35_CICADA 2643 +#define MACH_TYPE_GHI2703D 2644 +#define MACH_TYPE_LUX_SFX9 2645 +#define MACH_TYPE_LUX_SF9G 2646 +#define MACH_TYPE_LUX_EDK9 2647 +#define MACH_TYPE_HW90240 2648 +#define MACH_TYPE_DM365_LEOPARD 2649 +#define MACH_TYPE_MITYOMAPL138 2650 +#define MACH_TYPE_SCAT110 2651 +#define MACH_TYPE_ACER_A1 2652 +#define MACH_TYPE_CMCONTROL 2653 +#define MACH_TYPE_PELCO_LAMAR 2654 +#define MACH_TYPE_RFP43 2655 +#define MACH_TYPE_SK86R0301 2656 +#define MACH_TYPE_CTPXA 2657 +#define MACH_TYPE_EPB_ARM9_A 2658 +#define MACH_TYPE_GURUPLUG 2659 +#define MACH_TYPE_SPEAR310 2660 +#define MACH_TYPE_SPEAR320 2661 +#define MACH_TYPE_ROBOTX 2662 +#define MACH_TYPE_LSXHL 2663 +#define MACH_TYPE_SMARTLITE 2664 +#define MACH_TYPE_CWS2 2665 +#define MACH_TYPE_M619 2666 +#define MACH_TYPE_SMARTVIEW 2667 +#define MACH_TYPE_LSA_SALSA 2668 +#define MACH_TYPE_KIZBOX 2669 +#define MACH_TYPE_HTCCHARMER 2670 +#define MACH_TYPE_GUF_NESO_LT 2671 +#define MACH_TYPE_PM9G45 2672 +#define MACH_TYPE_HTCPANTHER 2673 +#define MACH_TYPE_HTCPANTHER_CDMA 2674 +#define MACH_TYPE_REB01 2675 +#define MACH_TYPE_AQUILA 2676 +#define MACH_TYPE_SPARK_SLS_HW2 2677 +#define MACH_TYPE_ESATA_SHEEVAPLUG 2678 +#define MACH_TYPE_SURF7X30 2679 +#define MACH_TYPE_MICRO2440 2680 +#define MACH_TYPE_AM2440 2681 +#define MACH_TYPE_TQ2440 2682 +#define MACH_TYPE_LPC2478OEM 2683 +#define MACH_TYPE_AK880X 2684 +#define MACH_TYPE_COBRA3530 2685 +#define MACH_TYPE_PMPPB 2686 +#define MACH_TYPE_U6715 2687 +#define MACH_TYPE_AXAR1500_SENDER 2688 +#define MACH_TYPE_G30_DVB 2689 +#define MACH_TYPE_VC088X 2690 +#define MACH_TYPE_MIOA702 2691 +#define MACH_TYPE_HPMIN 2692 +#define MACH_TYPE_AK880XAK 2693 +#define MACH_TYPE_ARM926TOMAP850 2694 +#define MACH_TYPE_LKEVM 2695 +#define MACH_TYPE_MW6410 2696 +#define MACH_TYPE_TERASTATION_WXL 2697 +#define MACH_TYPE_CPU8000E 2698 +#define MACH_TYPE_CATANIA 2699 +#define MACH_TYPE_TOKYO 2700 +#define MACH_TYPE_MSM7201A_SURF 2701 +#define MACH_TYPE_MSM7201A_FFA 2702 +#define MACH_TYPE_MSM7X25_SURF 2703 +#define MACH_TYPE_MSM7X25_FFA 2704 +#define MACH_TYPE_MSM7X27_SURF 2705 +#define MACH_TYPE_MSM7X27_FFA 2706 +#define MACH_TYPE_MSM7X30_FFA 2707 +#define MACH_TYPE_QSD8X50_SURF 2708 +#define MACH_TYPE_QSD8X50_COMET 2709 +#define MACH_TYPE_QSD8X50_FFA 2710 +#define MACH_TYPE_QSD8X50A_SURF 2711 +#define MACH_TYPE_QSD8X50A_FFA 2712 +#define MACH_TYPE_XGCP10 2713 +#define MACH_TYPE_MCGWUMTS2A 2714 +#define MACH_TYPE_MOBIKT 2715 +#define MACH_TYPE_MX53_EVK 2716 +#define MACH_TYPE_IGEP0030 2717 +#define MACH_TYPE_AXELL_H40_H50_CTRL 2718 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -29514,16 +29592,16 @@ extern unsigned int __machine_arch_type; # define machine_is_oratisdesk() (0) #endif -#ifdef CONFIG_MACH_V2P_CA9 +#ifdef CONFIG_MACH_VEXPRESS # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_V2P_CA9 +# define machine_arch_type MACH_TYPE_VEXPRESS # endif -# define machine_is_v2_ca9() (machine_arch_type == MACH_TYPE_V2P_CA9) +# define machine_is_vexpress() (machine_arch_type == MACH_TYPE_VEXPRESS) #else -# define machine_is_v2_ca9() (0) +# define machine_is_vexpress() (0) #endif #ifdef CONFIG_MACH_SINTEXO @@ -33901,9 +33979,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_LUX_SFT9 # endif -# define machine_is_lux_sft9() (machine_arch_type == MACH_TYPE_LUX_SFT9) +# define machine_is_lux_sf9() (machine_arch_type == MACH_TYPE_LUX_SFT9) #else -# define machine_is_lux_sft9() (0) +# define machine_is_lux_sf9() (0) #endif #ifdef CONFIG_MACH_NEMID_TB @@ -33930,6 +34008,942 @@ extern unsigned int __machine_arch_type; # define machine_is_terrier() (0) #endif +#ifdef CONFIG_MACH_TURBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TURBOT +# endif +# define machine_is_turbot() (machine_arch_type == MACH_TYPE_TURBOT) +#else +# define machine_is_turbot() (0) +#endif + +#ifdef CONFIG_MACH_SANDDAB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANDDAB +# endif +# define machine_is_sanddab() (machine_arch_type == MACH_TYPE_SANDDAB) +#else +# define machine_is_sanddab() (0) +#endif + +#ifdef CONFIG_MACH_MX35_CICADA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX35_CICADA +# endif +# define machine_is_mx35_cicada() (machine_arch_type == MACH_TYPE_MX35_CICADA) +#else +# define machine_is_mx35_cicada() (0) +#endif + +#ifdef CONFIG_MACH_GHI2703D +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GHI2703D +# endif +# define machine_is_ghi2703d() (machine_arch_type == MACH_TYPE_GHI2703D) +#else +# define machine_is_ghi2703d() (0) +#endif + +#ifdef CONFIG_MACH_LUX_SFX9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_SFX9 +# endif +# define machine_is_lux_sfx9() (machine_arch_type == MACH_TYPE_LUX_SFX9) +#else +# define machine_is_lux_sfx9() (0) +#endif + +#ifdef CONFIG_MACH_LUX_SF9G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_SF9G +# endif +# define machine_is_lux_sf9g() (machine_arch_type == MACH_TYPE_LUX_SF9G) +#else +# define machine_is_lux_sf9g() (0) +#endif + +#ifdef CONFIG_MACH_LUX_EDK9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_EDK9 +# endif +# define machine_is_lux_edk9() (machine_arch_type == MACH_TYPE_LUX_EDK9) +#else +# define machine_is_lux_edk9() (0) +#endif + +#ifdef CONFIG_MACH_HW90240 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW90240 +# endif +# define machine_is_hw90240() (machine_arch_type == MACH_TYPE_HW90240) +#else +# define machine_is_hw90240() (0) +#endif + +#ifdef CONFIG_MACH_DM365_LEOPARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM365_LEOPARD +# endif +# define machine_is_dm365_leopard() (machine_arch_type == MACH_TYPE_DM365_LEOPARD) +#else +# define machine_is_dm365_leopard() (0) +#endif + +#ifdef CONFIG_MACH_MITYOMAPL138 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MITYOMAPL138 +# endif +# define machine_is_mityomapl138() (machine_arch_type == MACH_TYPE_MITYOMAPL138) +#else +# define machine_is_mityomapl138() (0) +#endif + +#ifdef CONFIG_MACH_SCAT110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCAT110 +# endif +# define machine_is_scat110() (machine_arch_type == MACH_TYPE_SCAT110) +#else +# define machine_is_scat110() (0) +#endif + +#ifdef CONFIG_MACH_ACER_A1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_A1 +# endif +# define machine_is_acer_a1() (machine_arch_type == MACH_TYPE_ACER_A1) +#else +# define machine_is_acer_a1() (0) +#endif + +#ifdef CONFIG_MACH_CMCONTROL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMCONTROL +# endif +# define machine_is_cmcontrol() (machine_arch_type == MACH_TYPE_CMCONTROL) +#else +# define machine_is_cmcontrol() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_LAMAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_LAMAR +# endif +# define machine_is_pelco_lamar() (machine_arch_type == MACH_TYPE_PELCO_LAMAR) +#else +# define machine_is_pelco_lamar() (0) +#endif + +#ifdef CONFIG_MACH_RFP43 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RFP43 +# endif +# define machine_is_rfp43() (machine_arch_type == MACH_TYPE_RFP43) +#else +# define machine_is_rfp43() (0) +#endif + +#ifdef CONFIG_MACH_SK86R0301 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SK86R0301 +# endif +# define machine_is_sk86r0301() (machine_arch_type == MACH_TYPE_SK86R0301) +#else +# define machine_is_sk86r0301() (0) +#endif + +#ifdef CONFIG_MACH_CTPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTPXA +# endif +# define machine_is_ctpxa() (machine_arch_type == MACH_TYPE_CTPXA) +#else +# define machine_is_ctpxa() (0) +#endif + +#ifdef CONFIG_MACH_EPB_ARM9_A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPB_ARM9_A +# endif +# define machine_is_epb_arm9_a() (machine_arch_type == MACH_TYPE_EPB_ARM9_A) +#else +# define machine_is_epb_arm9_a() (0) +#endif + +#ifdef CONFIG_MACH_GURUPLUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GURUPLUG +# endif +# define machine_is_guruplug() (machine_arch_type == MACH_TYPE_GURUPLUG) +#else +# define machine_is_guruplug() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR310 +# endif +# define machine_is_spear310() (machine_arch_type == MACH_TYPE_SPEAR310) +#else +# define machine_is_spear310() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR320 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR320 +# endif +# define machine_is_spear320() (machine_arch_type == MACH_TYPE_SPEAR320) +#else +# define machine_is_spear320() (0) +#endif + +#ifdef CONFIG_MACH_ROBOTX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROBOTX +# endif +# define machine_is_robotx() (machine_arch_type == MACH_TYPE_ROBOTX) +#else +# define machine_is_robotx() (0) +#endif + +#ifdef CONFIG_MACH_LSXHL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LSXHL +# endif +# define machine_is_lsxhl() (machine_arch_type == MACH_TYPE_LSXHL) +#else +# define machine_is_lsxhl() (0) +#endif + +#ifdef CONFIG_MACH_SMARTLITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTLITE +# endif +# define machine_is_smartlite() (machine_arch_type == MACH_TYPE_SMARTLITE) +#else +# define machine_is_smartlite() (0) +#endif + +#ifdef CONFIG_MACH_CWS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWS2 +# endif +# define machine_is_cws2() (machine_arch_type == MACH_TYPE_CWS2) +#else +# define machine_is_cws2() (0) +#endif + +#ifdef CONFIG_MACH_M619 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M619 +# endif +# define machine_is_m619() (machine_arch_type == MACH_TYPE_M619) +#else +# define machine_is_m619() (0) +#endif + +#ifdef CONFIG_MACH_SMARTVIEW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTVIEW +# endif +# define machine_is_smartview() (machine_arch_type == MACH_TYPE_SMARTVIEW) +#else +# define machine_is_smartview() (0) +#endif + +#ifdef CONFIG_MACH_LSA_SALSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LSA_SALSA +# endif +# define machine_is_lsa_salsa() (machine_arch_type == MACH_TYPE_LSA_SALSA) +#else +# define machine_is_lsa_salsa() (0) +#endif + +#ifdef CONFIG_MACH_KIZBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIZBOX +# endif +# define machine_is_kizbox() (machine_arch_type == MACH_TYPE_KIZBOX) +#else +# define machine_is_kizbox() (0) +#endif + +#ifdef CONFIG_MACH_HTCCHARMER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCCHARMER +# endif +# define machine_is_htccharmer() (machine_arch_type == MACH_TYPE_HTCCHARMER) +#else +# define machine_is_htccharmer() (0) +#endif + +#ifdef CONFIG_MACH_GUF_NESO_LT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GUF_NESO_LT +# endif +# define machine_is_guf_neso_lt() (machine_arch_type == MACH_TYPE_GUF_NESO_LT) +#else +# define machine_is_guf_neso_lt() (0) +#endif + +#ifdef CONFIG_MACH_PM9G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PM9G45 +# endif +# define machine_is_pm9g45() (machine_arch_type == MACH_TYPE_PM9G45) +#else +# define machine_is_pm9g45() (0) +#endif + +#ifdef CONFIG_MACH_HTCPANTHER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPANTHER +# endif +# define machine_is_htcpanther() (machine_arch_type == MACH_TYPE_HTCPANTHER) +#else +# define machine_is_htcpanther() (0) +#endif + +#ifdef CONFIG_MACH_HTCPANTHER_CDMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPANTHER_CDMA +# endif +# define machine_is_htcpanther_cdma() (machine_arch_type == MACH_TYPE_HTCPANTHER_CDMA) +#else +# define machine_is_htcpanther_cdma() (0) +#endif + +#ifdef CONFIG_MACH_REB01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REB01 +# endif +# define machine_is_reb01() (machine_arch_type == MACH_TYPE_REB01) +#else +# define machine_is_reb01() (0) +#endif + +#ifdef CONFIG_MACH_AQUILA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AQUILA +# endif +# define machine_is_aquila() (machine_arch_type == MACH_TYPE_AQUILA) +#else +# define machine_is_aquila() (0) +#endif + +#ifdef CONFIG_MACH_SPARK_SLS_HW2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPARK_SLS_HW2 +# endif +# define machine_is_spark_sls_hw2() (machine_arch_type == MACH_TYPE_SPARK_SLS_HW2) +#else +# define machine_is_spark_sls_hw2() (0) +#endif + +#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESATA_SHEEVAPLUG +# endif +# define machine_is_sheeva_esata() (machine_arch_type == MACH_TYPE_ESATA_SHEEVAPLUG) +#else +# define machine_is_sheeva_esata() (0) +#endif + +#ifdef CONFIG_MACH_SURF7X30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SURF7X30 +# endif +# define machine_is_msm7x30_surf() (machine_arch_type == MACH_TYPE_SURF7X30) +#else +# define machine_is_msm7x30_surf() (0) +#endif + +#ifdef CONFIG_MACH_MICRO2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICRO2440 +# endif +# define machine_is_micro2440() (machine_arch_type == MACH_TYPE_MICRO2440) +#else +# define machine_is_micro2440() (0) +#endif + +#ifdef CONFIG_MACH_AM2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AM2440 +# endif +# define machine_is_am2440() (machine_arch_type == MACH_TYPE_AM2440) +#else +# define machine_is_am2440() (0) +#endif + +#ifdef CONFIG_MACH_TQ2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TQ2440 +# endif +# define machine_is_tq2440() (machine_arch_type == MACH_TYPE_TQ2440) +#else +# define machine_is_tq2440() (0) +#endif + +#ifdef CONFIG_MACH_LPC2478OEM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC2478OEM +# endif +# define machine_is_lpc2478oem() (machine_arch_type == MACH_TYPE_LPC2478OEM) +#else +# define machine_is_lpc2478oem() (0) +#endif + +#ifdef CONFIG_MACH_AK880X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AK880X +# endif +# define machine_is_ak880x() (machine_arch_type == MACH_TYPE_AK880X) +#else +# define machine_is_ak880x() (0) +#endif + +#ifdef CONFIG_MACH_COBRA3530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COBRA3530 +# endif +# define machine_is_cobra3530() (machine_arch_type == MACH_TYPE_COBRA3530) +#else +# define machine_is_cobra3530() (0) +#endif + +#ifdef CONFIG_MACH_PMPPB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PMPPB +# endif +# define machine_is_pmppb() (machine_arch_type == MACH_TYPE_PMPPB) +#else +# define machine_is_pmppb() (0) +#endif + +#ifdef CONFIG_MACH_U6715 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U6715 +# endif +# define machine_is_u6715() (machine_arch_type == MACH_TYPE_U6715) +#else +# define machine_is_u6715() (0) +#endif + +#ifdef CONFIG_MACH_AXAR1500_SENDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXAR1500_SENDER +# endif +# define machine_is_axar1500_sender() (machine_arch_type == MACH_TYPE_AXAR1500_SENDER) +#else +# define machine_is_axar1500_sender() (0) +#endif + +#ifdef CONFIG_MACH_G30_DVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G30_DVB +# endif +# define machine_is_g30_dvb() (machine_arch_type == MACH_TYPE_G30_DVB) +#else +# define machine_is_g30_dvb() (0) +#endif + +#ifdef CONFIG_MACH_VC088X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VC088X +# endif +# define machine_is_vc088x() (machine_arch_type == MACH_TYPE_VC088X) +#else +# define machine_is_vc088x() (0) +#endif + +#ifdef CONFIG_MACH_MIOA702 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIOA702 +# endif +# define machine_is_mioa702() (machine_arch_type == MACH_TYPE_MIOA702) +#else +# define machine_is_mioa702() (0) +#endif + +#ifdef CONFIG_MACH_HPMIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPMIN +# endif +# define machine_is_hpmin() (machine_arch_type == MACH_TYPE_HPMIN) +#else +# define machine_is_hpmin() (0) +#endif + +#ifdef CONFIG_MACH_AK880XAK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AK880XAK +# endif +# define machine_is_ak880xak() (machine_arch_type == MACH_TYPE_AK880XAK) +#else +# define machine_is_ak880xak() (0) +#endif + +#ifdef CONFIG_MACH_ARM926TOMAP850 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM926TOMAP850 +# endif +# define machine_is_arm926tomap850() (machine_arch_type == MACH_TYPE_ARM926TOMAP850) +#else +# define machine_is_arm926tomap850() (0) +#endif + +#ifdef CONFIG_MACH_LKEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LKEVM +# endif +# define machine_is_lkevm() (machine_arch_type == MACH_TYPE_LKEVM) +#else +# define machine_is_lkevm() (0) +#endif + +#ifdef CONFIG_MACH_MW6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MW6410 +# endif +# define machine_is_mw6410() (machine_arch_type == MACH_TYPE_MW6410) +#else +# define machine_is_mw6410() (0) +#endif + +#ifdef CONFIG_MACH_TERASTATION_WXL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TERASTATION_WXL +# endif +# define machine_is_terastation_wxl() (machine_arch_type == MACH_TYPE_TERASTATION_WXL) +#else +# define machine_is_terastation_wxl() (0) +#endif + +#ifdef CONFIG_MACH_CPU8000E +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPU8000E +# endif +# define machine_is_cpu8000e() (machine_arch_type == MACH_TYPE_CPU8000E) +#else +# define machine_is_cpu8000e() (0) +#endif + +#ifdef CONFIG_MACH_CATANIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATANIA +# endif +# define machine_is_catania() (machine_arch_type == MACH_TYPE_CATANIA) +#else +# define machine_is_catania() (0) +#endif + +#ifdef CONFIG_MACH_TOKYO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOKYO +# endif +# define machine_is_tokyo() (machine_arch_type == MACH_TYPE_TOKYO) +#else +# define machine_is_tokyo() (0) +#endif + +#ifdef CONFIG_MACH_MSM7201A_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7201A_SURF +# endif +# define machine_is_msm7201a_surf() (machine_arch_type == MACH_TYPE_MSM7201A_SURF) +#else +# define machine_is_msm7201a_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM7201A_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7201A_FFA +# endif +# define machine_is_msm7201a_ffa() (machine_arch_type == MACH_TYPE_MSM7201A_FFA) +#else +# define machine_is_msm7201a_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X25_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X25_SURF +# endif +# define machine_is_msm7x25_surf() (machine_arch_type == MACH_TYPE_MSM7X25_SURF) +#else +# define machine_is_msm7x25_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X25_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X25_FFA +# endif +# define machine_is_msm7x25_ffa() (machine_arch_type == MACH_TYPE_MSM7X25_FFA) +#else +# define machine_is_msm7x25_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X27_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X27_SURF +# endif +# define machine_is_msm7x27_surf() (machine_arch_type == MACH_TYPE_MSM7X27_SURF) +#else +# define machine_is_msm7x27_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X27_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X27_FFA +# endif +# define machine_is_msm7x27_ffa() (machine_arch_type == MACH_TYPE_MSM7X27_FFA) +#else +# define machine_is_msm7x27_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X30_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X30_FFA +# endif +# define machine_is_msm7x30_ffa() (machine_arch_type == MACH_TYPE_MSM7X30_FFA) +#else +# define machine_is_msm7x30_ffa() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_SURF +# endif +# define machine_is_qsd8x50_surf() (machine_arch_type == MACH_TYPE_QSD8X50_SURF) +#else +# define machine_is_qsd8x50_surf() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_COMET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_COMET +# endif +# define machine_is_qsd8x50_comet() (machine_arch_type == MACH_TYPE_QSD8X50_COMET) +#else +# define machine_is_qsd8x50_comet() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_FFA +# endif +# define machine_is_qsd8x50_ffa() (machine_arch_type == MACH_TYPE_QSD8X50_FFA) +#else +# define machine_is_qsd8x50_ffa() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_SURF +# endif +# define machine_is_qsd8x50a_surf() (machine_arch_type == MACH_TYPE_QSD8X50A_SURF) +#else +# define machine_is_qsd8x50a_surf() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_FFA +# endif +# define machine_is_qsd8x50a_ffa() (machine_arch_type == MACH_TYPE_QSD8X50A_FFA) +#else +# define machine_is_qsd8x50a_ffa() (0) +#endif + +#ifdef CONFIG_MACH_XGCP10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XGCP10 +# endif +# define machine_is_adx_xgcp10() (machine_arch_type == MACH_TYPE_XGCP10) +#else +# define machine_is_adx_xgcp10() (0) +#endif + +#ifdef CONFIG_MACH_MCGWUMTS2A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCGWUMTS2A +# endif +# define machine_is_mcgwumts2a() (machine_arch_type == MACH_TYPE_MCGWUMTS2A) +#else +# define machine_is_mcgwumts2a() (0) +#endif + +#ifdef CONFIG_MACH_MOBIKT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOBIKT +# endif +# define machine_is_mobikt() (machine_arch_type == MACH_TYPE_MOBIKT) +#else +# define machine_is_mobikt() (0) +#endif + +#ifdef CONFIG_MACH_MX53_EVK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX53_EVK +# endif +# define machine_is_mx53_evk() (machine_arch_type == MACH_TYPE_MX53_EVK) +#else +# define machine_is_mx53_evk() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0030 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0030 +# endif +# define machine_is_igep0030() (machine_arch_type == MACH_TYPE_IGEP0030) +#else +# define machine_is_igep0030() (0) +#endif + +#ifdef CONFIG_MACH_AXELL_H40_H50_CTRL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXELL_H40_H50_CTRL +# endif +# define machine_is_axell_h40_h50_ctrl() (machine_arch_type == MACH_TYPE_AXELL_H40_H50_CTRL) +#else +# define machine_is_axell_h40_h50_ctrl() (0) +#endif + /* * These have not yet been registered */ -- cgit v1.1 From cade7d9577d4d17f55404b5e60cd5e5b0b605c31 Mon Sep 17 00:00:00 2001 From: Anders Darander Date: Thu, 25 Feb 2010 15:57:03 +0100 Subject: Add bootcount to AT91 Use AT91_GPBR 3 as a bootcount register. The bootmagic and the bootcount shares AT91_GPBR 3. Signed-off-by: Anders Darander --- cpu/arm926ejs/at91/cpu.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c index 1094f8c..141a7d1 100644 --- a/cpu/arm926ejs/at91/cpu.c +++ b/cpu/arm926ejs/at91/cpu.c @@ -35,6 +35,13 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 0 #endif +/* + * The at91sam9260 has 4 GPBR (0-3), we'll use the last one, nr 3, + * to keep track of the bootcount. + */ +#define AT91_GPBR_BOOTCOUNT_REGISTER 3 +#define AT91_BOOTCOUNT_ADDRESS (AT91_GPBR + 4*AT91_GPBR_BOOTCOUNT_REGISTER) + int arch_cpu_init(void) { return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); @@ -56,3 +63,30 @@ int print_cpuinfo(void) return 0; } #endif + +#ifdef CONFIG_BOOTCOUNT_LIMIT +/* + * Just as the mpc5xxx, we combine the BOOTCOUNT_MAGIC and boocount + * in one 32-bit register. This is done, as the AT91SAM9260 only has + * 4 GPBR. + */ +void bootcount_store (ulong a) +{ + volatile ulong *save_addr = + (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS); + + *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff); +} + +ulong bootcount_load (void) +{ + volatile ulong *save_addr = + (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS); + + if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) + return 0; + else + return (*save_addr & 0x0000ffff); +} + +#endif /* CONFIG_BOOTCOUNT_LIMIT */ -- cgit v1.1 From 18ba012b9b919a7c264dc6299f954d7f53d06605 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 24 Feb 2010 19:45:39 +0100 Subject: edb93xx: Fix SDRAM initialization edb93xx: Fix SDRAM initialization by issuing a precharge all command before forcing the precharge and select mode register update mode before programming the mode registers. Write to the SDRAM banks in order to force a precharge, reading causes the edb93xx boards to hang Signed-off-by: Matthias Kaehlcke --- board/edb93xx/sdram_cfg.c | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c index 6155f0e..440ad11 100644 --- a/board/edb93xx/sdram_cfg.c +++ b/board/edb93xx/sdram_cfg.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Matthias Kaehlcke + * Copyright (C) 2009, 2010 Matthias Kaehlcke * * Copyright (C) 2006 Dominic Rath * @@ -30,9 +30,9 @@ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL)) #define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \ - (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) + (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0 -static void force_precharge(void); +static void precharge_all_banks(void); static void setup_refresh_timer(void); static void program_mode_registers(void); @@ -47,7 +47,7 @@ void sdram_cfg(void) early_udelay(200); - force_precharge(); + precharge_all_banks(); setup_refresh_timer(); @@ -57,19 +57,37 @@ void sdram_cfg(void) writel(GLCONFIG_CKE, &sdram->glconfig); } -static void force_precharge(void) +static void precharge_all_banks(void) { + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; + + /* Issue PRECHARGE ALL commands */ + writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig); + /* - * Errata most EP93xx revisions say that PRECHARGE ALL isn't always - * issued. + * Errata of most EP93xx revisions say that PRECHARGE ALL isn't always + * issued * - * Do a read from each bank to make sure they're precharged + * Cirrus proposes a workaround which consists in performing a read from + * each bank to force the precharge. This causes some boards to hang. + * Writing to the SDRAM banks instead of reading has the same + * side-effect (the SDRAM controller issues the necessary precharges), + * but is known to work on all supported boards */ PRECHARGE_BANK(0); + +#if (CONFIG_NR_DRAM_BANKS >= 2) PRECHARGE_BANK(1); +#endif + +#if (CONFIG_NR_DRAM_BANKS >= 3) PRECHARGE_BANK(2); +#endif + +#if (CONFIG_NR_DRAM_BANKS == 4) PRECHARGE_BANK(3); +#endif } static void setup_refresh_timer(void) @@ -101,6 +119,11 @@ static void setup_refresh_timer(void) static void program_mode_registers(void) { + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; + + /* Select mode register update mode */ + writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); + /* * The mode registers are programmed by performing a read from each * SDRAM bank. The value of the address that is read defines the value -- cgit v1.1 From 64fdf452a85718935d82416d141be144b262c542 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 20 Jan 2010 18:19:32 +0100 Subject: MX51: Add initial support for the Freescale MX51 The patch add initial support for the Freescale i.MX51 processor (family arm cortex_a8). Signed-off-by: Stefano Babic Signed-off-by: Fred Fan --- cpu/arm_cortexa8/mx51/Makefile | 48 ++++++ cpu/arm_cortexa8/mx51/clock.c | 293 ++++++++++++++++++++++++++++++++++ cpu/arm_cortexa8/mx51/iomux.c | 165 +++++++++++++++++++ cpu/arm_cortexa8/mx51/lowlevel_init.S | 289 +++++++++++++++++++++++++++++++++ cpu/arm_cortexa8/mx51/soc.c | 109 +++++++++++++ cpu/arm_cortexa8/mx51/timer.c | 119 ++++++++++++++ cpu/arm_cortexa8/mx51/u-boot.lds | 61 +++++++ include/asm-arm/arch-mx51/clock.h | 31 ++++ 8 files changed, 1115 insertions(+) create mode 100644 cpu/arm_cortexa8/mx51/Makefile create mode 100644 cpu/arm_cortexa8/mx51/clock.c create mode 100644 cpu/arm_cortexa8/mx51/iomux.c create mode 100644 cpu/arm_cortexa8/mx51/lowlevel_init.S create mode 100644 cpu/arm_cortexa8/mx51/soc.c create mode 100644 cpu/arm_cortexa8/mx51/timer.c create mode 100644 cpu/arm_cortexa8/mx51/u-boot.lds create mode 100644 include/asm-arm/arch-mx51/clock.h diff --git a/cpu/arm_cortexa8/mx51/Makefile b/cpu/arm_cortexa8/mx51/Makefile new file mode 100644 index 0000000..4d82293 --- /dev/null +++ b/cpu/arm_cortexa8/mx51/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = soc.o clock.o iomux.o timer.o +SOBJS = lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm_cortexa8/mx51/clock.c b/cpu/arm_cortexa8/mx51/clock.c new file mode 100644 index 0000000..3c6f0c0 --- /dev/null +++ b/cpu/arm_cortexa8/mx51/clock.c @@ -0,0 +1,293 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +enum pll_clocks { + PLL1_CLOCK = 0, + PLL2_CLOCK, + PLL3_CLOCK, + PLL_CLOCKS, +}; + +struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { + [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR, + [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR, + [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR, +}; + +struct mxc_ccm_reg *mxc_ccm = MXC_CCM_BASE; + +/* + * Calculate the frequency of this pll. + */ +static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq) +{ + u32 mfi, mfn, mfd, pd; + + mfn = __raw_readl(&pll->mfn); + mfd = __raw_readl(&pll->mfd) + 1; + mfi = __raw_readl(&pll->op); + pd = (mfi & 0xF) + 1; + mfi = (mfi >> 4) & 0xF; + mfi = (mfi >= 5) ? mfi : 5; + + return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; +} + +/* + * Get mcu main rate + */ +u32 get_mcu_main_clk(void) +{ + u32 reg, freq; + + reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >> + MXC_CCM_CACRR_ARM_PODF_OFFSET; + freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ); + return freq / (reg + 1); +} + +/* + * Get the rate of peripheral's root clock. + */ +static u32 get_periph_clk(void) +{ + u32 reg; + + reg = __raw_readl(&mxc_ccm->cbcdr); + if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL)) + return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); + reg = __raw_readl(&mxc_ccm->cbcmr); + switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { + case 0: + return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ); + case 1: + return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ); + default: + return 0; + } + /* NOTREACHED */ +} + +/* + * Get the rate of ipg clock. + */ +static u32 get_ipg_clk(void) +{ + u32 ahb_podf, ipg_podf; + + ahb_podf = __raw_readl(&mxc_ccm->cbcdr); + ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >> + MXC_CCM_CBCDR_IPG_PODF_OFFSET; + ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >> + MXC_CCM_CBCDR_AHB_PODF_OFFSET; + return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1)); +} + +/* + * Get the rate of ipg_per clock. + */ +static u32 get_ipg_per_clk(void) +{ + u32 pred1, pred2, podf; + + if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) + return get_ipg_clk(); + /* Fixme: not handle what about lpm*/ + podf = __raw_readl(&mxc_ccm->cbcdr); + pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET; + pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET; + podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET; + + return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); +} + +/* + * Get the rate of uart clk. + */ +static u32 get_uart_clk(void) +{ + unsigned int freq, reg, pred, podf; + + reg = __raw_readl(&mxc_ccm->cscmr1); + switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >> + MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) { + case 0x0: + freq = decode_pll(mxc_plls[PLL1_CLOCK], + CONFIG_MX51_HCLK_FREQ); + break; + case 0x1: + freq = decode_pll(mxc_plls[PLL2_CLOCK], + CONFIG_MX51_HCLK_FREQ); + break; + case 0x2: + freq = decode_pll(mxc_plls[PLL3_CLOCK], + CONFIG_MX51_HCLK_FREQ); + break; + default: + return 66500000; + } + + reg = __raw_readl(&mxc_ccm->cscdr1); + + pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET; + + podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; + freq /= (pred + 1) * (podf + 1); + + return freq; +} + +/* + * This function returns the low power audio clock. + */ +u32 get_lp_apm(void) +{ + u32 ret_val = 0; + u32 ccsr = __raw_readl(&mxc_ccm->ccsr); + + if (((ccsr >> 9) & 1) == 0) + ret_val = CONFIG_MX51_HCLK_FREQ; + else + ret_val = ((32768 * 1024)); + + return ret_val; +} + +/* + * get cspi clock rate. + */ +u32 imx_get_cspiclk(void) +{ + u32 ret_val = 0, pdf, pre_pdf, clk_sel; + u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1); + u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2); + + pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \ + >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; + pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \ + >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; + clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \ + >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; + + switch (clk_sel) { + case 0: + ret_val = decode_pll(mxc_plls[PLL1_CLOCK], + CONFIG_MX51_HCLK_FREQ) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case 1: + ret_val = decode_pll(mxc_plls[PLL2_CLOCK], + CONFIG_MX51_HCLK_FREQ) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case 2: + ret_val = decode_pll(mxc_plls[PLL3_CLOCK], + CONFIG_MX51_HCLK_FREQ) / + ((pre_pdf + 1) * (pdf + 1)); + break; + default: + ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1)); + break; + } + + return ret_val; +} + +/* + * The API of get mxc clockes. + */ +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_mcu_main_clk(); + case MXC_AHB_CLK: + break; + case MXC_IPG_CLK: + return get_ipg_clk(); + case MXC_IPG_PERCLK: + return get_ipg_per_clk(); + case MXC_UART_CLK: + return get_uart_clk(); + case MXC_CSPI_CLK: + return imx_get_cspiclk(); + case MXC_FEC_CLK: + return decode_pll(mxc_plls[PLL1_CLOCK], + CONFIG_MX51_HCLK_FREQ); + default: + break; + } + return -1; +} + +u32 imx_get_uartclk(void) +{ + return get_uart_clk(); +} + + +u32 imx_get_fecclk(void) +{ + return mxc_get_clock(MXC_IPG_CLK); +} + +/* + * Dump some core clockes. + */ +int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u32 freq; + + freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ); + printf("mx51 pll1: %dMHz\n", freq / 1000000); + freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); + printf("mx51 pll2: %dMHz\n", freq / 1000000); + freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ); + printf("mx51 pll3: %dMHz\n", freq / 1000000); + printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK)); + printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK)); + + return 0; +} + +/***************************************************/ + +U_BOOT_CMD( + clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx51_showclocks, + "display mx51 clocks\n", + "" +); diff --git a/cpu/arm_cortexa8/mx51/iomux.c b/cpu/arm_cortexa8/mx51/iomux.c new file mode 100644 index 0000000..fc39e8a --- /dev/null +++ b/cpu/arm_cortexa8/mx51/iomux.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* IOMUX register (base) addresses */ +enum iomux_reg_addr { + IOMUXGPR0 = IOMUXC_BASE_ADDR, + IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004, + IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR, + IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END, + IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START, + IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR, +}; + +#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1) + +/* Get the iomux register address of this pin */ +static inline u32 get_mux_reg(iomux_pin_name_t pin) +{ + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + + if (is_soc_rev(CHIP_REV_2_0) < 0) { + /* + * Fixup register address: + * i.MX51 TO1 has offset with the register + * which is define as TO2. + */ + if ((pin == MX51_PIN_NANDF_RB5) || + (pin == MX51_PIN_NANDF_RB6) || + (pin == MX51_PIN_NANDF_RB7)) + ; /* Do nothing */ + else if (mux_reg >= 0x2FC) + mux_reg += 8; + else if (mux_reg >= 0x130) + mux_reg += 0xC; + } + mux_reg += IOMUXSW_MUX_CTL; + return mux_reg; +} + +/* Get the pad register address of this pin */ +static inline u32 get_pad_reg(iomux_pin_name_t pin) +{ + u32 pad_reg = PIN_TO_IOMUX_PAD(pin); + + if (is_soc_rev(CHIP_REV_2_0) < 0) { + /* + * Fixup register address: + * i.MX51 TO1 has offset with the register + * which is define as TO2. + */ + if ((pin == MX51_PIN_NANDF_RB5) || + (pin == MX51_PIN_NANDF_RB6) || + (pin == MX51_PIN_NANDF_RB7)) + ; /* Do nothing */ + else if (pad_reg == 0x4D0 - PAD_I_START) + pad_reg += 0x4C; + else if (pad_reg == 0x860 - PAD_I_START) + pad_reg += 0x9C; + else if (pad_reg >= 0x804 - PAD_I_START) + pad_reg += 0xB0; + else if (pad_reg >= 0x7FC - PAD_I_START) + pad_reg += 0xB4; + else if (pad_reg >= 0x4E4 - PAD_I_START) + pad_reg += 0xCC; + else + pad_reg += 8; + } + pad_reg += IOMUXSW_PAD_CTL; + return pad_reg; +} + +/* Get the last iomux register address */ +static inline u32 get_mux_end(void) +{ + if (is_soc_rev(CHIP_REV_2_0) < 0) + return IOMUXC_BASE_ADDR + (0x3F8 - 4); + else + return IOMUXC_BASE_ADDR + (0x3F0 - 4); +} + +/* + * This function is used to configure a pin through the IOMUX module. + * @param pin a pin number as defined in iomux_pin_name_t + * @param cfg an output function as defined in iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 mux_reg = get_mux_reg(pin); + + if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL)) + return ; + if (cfg == IOMUX_CONFIG_GPIO) + writel(PIN_TO_ALT_GPIO(pin), mux_reg); + else + writel(cfg, mux_reg); +} + +/* + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by iomux_pin_name_t + * @param cfg an input function as defined in iomux_pin_cfg_t + * + */ +void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + iomux_config_mux(pin, cfg); +} + +/* + * Release ownership for an IO pin + * + * @param pin a name defined by iomux_pin_name_t + * @param cfg an input function as defined in iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ +} + +/* + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in iomux_pin_name_t + * @param config the ORed value of elements defined in iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = get_pad_reg(pin); + writel(config, pad_reg); +} + +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin) +{ + u32 pad_reg = get_pad_reg(pin); + return readl(pad_reg); +} diff --git a/cpu/arm_cortexa8/mx51/lowlevel_init.S b/cpu/arm_cortexa8/mx51/lowlevel_init.S new file mode 100644 index 0000000..680a90e --- /dev/null +++ b/cpu/arm_cortexa8/mx51/lowlevel_init.S @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* explicitly disable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #0x2 + mcr 15, 0, r0, c1, c0, 1 + + /* reconfigure L2 cache aux control reg */ + mov r0, #0xC0 /* tag RAM */ + add r0, r0, #0x4 /* data RAM */ + orr r0, r0, #(1 << 24) /* disable write allocate delay */ + orr r0, r0, #(1 << 23) /* disable write allocate combine */ + orr r0, r0, #(1 << 22) /* disable write allocate */ + + cmp r3, #0x10 /* r3 contains the silicon rev */ + + /* disable write combine for TO 2 and lower revs */ + orrls r0, r0, #(1 << 25) + + mcr 15, 1, r0, c9, c0, 2 +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x0] + str r1, [r0, #0x4] + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ +.endm /* init_aips */ + +/* M4IF setup */ +.macro init_m4if + /* VPU and IPU given higher priority (0x4) + * IPU accesses with ID=0x1 given highest priority (=0xA) + */ + ldr r0, =M4IF_BASE_ADDR + + ldr r1, =0x00000203 + str r1, [r0, #0x40] + + ldr r1, =0x0 + str r1, [r0, #0x44] + + ldr r1, =0x00120125 + str r1, [r0, #0x9C] + + ldr r1, =0x001901A3 + str r1, [r0, #0x48] + +.endm /* init_m4if */ + +.macro setup_pll pll, freq + ldr r2, =\pll + ldr r1, =0x00001232 + str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ + mov r1, #0x2 + str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + + str r3, [r2, #PLL_DP_OP] + str r3, [r2, #PLL_DP_HFS_OP] + + str r4, [r2, #PLL_DP_MFD] + str r4, [r2, #PLL_DP_HFS_MFD] + + str r5, [r2, #PLL_DP_MFN] + str r5, [r2, #PLL_DP_HFS_MFN] + + ldr r1, =0x00001232 + str r1, [r2, #PLL_DP_CTL] +1: ldr r1, [r2, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endm + +.macro init_clock + ldr r0, =CCM_BASE_ADDR + + /* Gate of clocks to the peripherals first */ + ldr r1, =0x3FFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + ldr r1, =0x0 + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + + ldr r1, =0x00030000 + str r1, [r0, #CLKCTL_CCGR4] + ldr r1, =0x00FFF030 + str r1, [r0, #CLKCTL_CCGR5] + ldr r1, =0x00000300 + str r1, [r0, #CLKCTL_CCGR6] + + /* Disable IPU and HSC dividers */ + mov r1, #0x60000 + str r1, [r0, #CLKCTL_CCDR] + + /* Make sure to switch the DDR away from PLL 1 */ + ldr r1, =0x19239145 + str r1, [r0, #CLKCTL_CBCDR] + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + /* Switch ARM to step clock */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + mov r3, #DP_OP_800 + mov r4, #DP_MFD_800 + mov r5, #DP_MFN_800 + setup_pll PLL1_BASE_ADDR + + mov r3, #DP_OP_665 + mov r4, #DP_MFD_665 + mov r5, #DP_MFN_665 + setup_pll PLL3_BASE_ADDR + + /* Switch peripheral to PLL 3 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x000010C0 + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, =0x13239145 + str r1, [r0, #CLKCTL_CBCDR] + mov r3, #DP_OP_665 + mov r4, #DP_MFD_665 + mov r5, #DP_MFN_665 + setup_pll PLL2_BASE_ADDR + + /* Switch peripheral to PLL2 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x19239145 + str r1, [r0, #CLKCTL_CBCDR] + ldr r1, =0x000020C0 + str r1, [r0, #CLKCTL_CBCMR] + + mov r3, #DP_OP_216 + mov r4, #DP_MFD_216 + mov r5, #DP_MFN_216 + setup_pll PLL3_BASE_ADDR + + + /* Set the platform clock dividers */ + ldr r0, =ARM_BASE_ADDR + ldr r1, =0x00000725 + str r1, [r0, #0x14] + + ldr r0, =CCM_BASE_ADDR + + /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 + movls r1, #0x1 + movhi r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* Switch ARM back to PLL 1 */ + mov r1, #0 + str r1, [r0, #CLKCTL_CCSR] + + /* setup the rest */ + /* Use lp_apm (24MHz) source for perclk */ + ldr r1, =0x000020C2 + str r1, [r0, #CLKCTL_CBCMR] + /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ + ldr r1, =0x59E35100 + str r1, [r0, #CLKCTL_CBCDR] + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + + /* Use PLL 2 for UART's, get 66.5MHz from it */ + ldr r1, =0xA5A2A020 + str r1, [r0, #CLKCTL_CSCMR1] + ldr r1, =0x00C30321 + str r1, [r0, #CLKCTL_CSCDR1] + + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + mov r1, #0x0 + str r1, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +.endm + +.macro setup_wdog + ldr r0, =WDOG1_BASE_ADDR + mov r1, #0x30 + strh r1, [r0] +.endm + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + ldr r0, =GPIO1_BASE_ADDR + ldr r1, [r0, #0x0] + orr r1, r1, #(1 << 23) + str r1, [r0, #0x0] + ldr r1, [r0, #0x4] + orr r1, r1, #(1 << 23) + str r1, [r0, #0x4] + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */ + bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop + nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endif + + init_l2cc + + init_aips + + init_m4if + + init_clock + + /* return from mxc_nand_load */ + /* r12 saved upper lr*/ + mov pc,lr + +/* Board level setting value */ +DDR_PERCHARGE_CMD: .word 0x04008008 +DDR_REFRESH_CMD: .word 0x00008010 +DDR_LMR1_W: .word 0x00338018 +DDR_LMR_CMD: .word 0xB2220000 +DDR_TIMING_W: .word 0xB02567A9 +DDR_MISC_W: .word 0x000A0104 diff --git a/cpu/arm_cortexa8/mx51/soc.c b/cpu/arm_cortexa8/mx51/soc.c new file mode 100644 index 0000000..5e69301 --- /dev/null +++ b/cpu/arm_cortexa8/mx51/soc.c @@ -0,0 +1,109 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +u32 get_cpu_rev(void) +{ + int reg; + int system_rev; + + reg = __raw_readl(ROM_SI_REV); + switch (reg) { + case 0x02: + system_rev = 0x51000 | CHIP_REV_1_1; + break; + case 0x10: + if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) + system_rev = 0x51000 | CHIP_REV_2_5; + else + system_rev = 0x51000 | CHIP_REV_2_0; + break; + case 0x20: + system_rev = 0x51000 | CHIP_REV_3_0; + break; + return system_rev; + default: + system_rev = 0x51000 | CHIP_REV_1_0; + break; + } + return system_rev; +} + + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + printf("CPU: Freescale i.MX51 family %d.%dV at %d MHz\n", + (cpurev & 0xF0) >> 4, + (cpurev & 0x0F) >> 4, + get_mcu_main_clk() / 1000000); + return 0; +} +#endif + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +#if defined(CONFIG_FEC_MXC) +extern int fecmxc_initialize(bd_t *bis); +#endif + +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + +#if defined(CONFIG_FEC_MXC) + rc = fecmxc_initialize(bis); +#endif + + return rc; +} + +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_FSL_ESDHC + return fsl_esdhc_mmc_init(bis); +#else + return 0; +#endif +} + + +void reset_cpu(ulong addr) +{ + __raw_writew(4, WDOG1_BASE_ADDR); +} diff --git a/cpu/arm_cortexa8/mx51/timer.c b/cpu/arm_cortexa8/mx51/timer.c new file mode 100644 index 0000000..8ecfec6 --- /dev/null +++ b/cpu/arm_cortexa8/mx51/timer.c @@ -0,0 +1,119 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* General purpose timers registers */ +struct mxc_gpt { + unsigned int control; + unsigned int prescaler; + unsigned int status; + unsigned int nouse[6]; + unsigned int counter; +}; + +static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1<<15) /* Software reset */ +#define GPTCR_FRR (1<<9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ +#define GPTCR_TEN (1) /* Timer enable */ + +static ulong timestamp; +static ulong lastinc; + +int timer_init(void) +{ + int i; + + /* setup GP Timer 1 */ + __raw_writel(GPTCR_SWR, &cur_gpt->control); + + /* We have no udelay by now */ + for (i = 0; i < 100; i++) + __raw_writel(0, &cur_gpt->control); + + __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ + + /* Freerun Mode, PERCLK1 input */ + i = __raw_readl(&cur_gpt->control); + __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); + reset_timer_masked(); + return 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +void reset_timer_masked(void) +{ + ulong val = __raw_readl(&cur_gpt->counter); + lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ); + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong val = __raw_readl(&cur_gpt->counter); + val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ); + if (val >= lastinc) + timestamp += (val - lastinc); + else + timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ)) + - lastinc) + val; + lastinc = val; + return val; +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void __udelay(unsigned long usec) +{ + unsigned long now, start, tmo; + tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000; + + if (!tmo) + tmo = 1; + + now = start = readl(&cur_gpt->counter); + + while ((now - start) < tmo) + now = readl(&cur_gpt->counter); + +} diff --git a/cpu/arm_cortexa8/mx51/u-boot.lds b/cpu/arm_cortexa8/mx51/u-boot.lds new file mode 100644 index 0000000..84c173a --- /dev/null +++ b/cpu/arm_cortexa8/mx51/u-boot.lds @@ -0,0 +1,61 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm_cortexa8/start.o + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/include/asm-arm/arch-mx51/clock.h b/include/asm-arm/arch-mx51/clock.h new file mode 100644 index 0000000..449a191 --- /dev/null +++ b/include/asm-arm/arch-mx51/clock.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H +unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); + +ulong imx_get_uartclk(void); +ulong imx_get_fecclk(void); + +#endif /* __ASM_ARCH_CLOCK_H */ -- cgit v1.1 From fb87a1ed9205bf5f843e1f264198ce946602deda Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 20 Jan 2010 18:19:51 +0100 Subject: MX51: Add register definitions The patch add header files to support the Freescale i.MX51 processor, setting definitions for internal registers. Signed-off-by: Stefano Babic Signed-off-by: Fred Fan --- include/asm-arm/arch-mx51/asm-offsets.h | 50 ++++++ include/asm-arm/arch-mx51/crm_regs.h | 192 ++++++++++++++++++++++ include/asm-arm/arch-mx51/imx-regs.h | 282 ++++++++++++++++++++++++++++++++ 3 files changed, 524 insertions(+) create mode 100644 include/asm-arm/arch-mx51/asm-offsets.h create mode 100644 include/asm-arm/arch-mx51/crm_regs.h create mode 100644 include/asm-arm/arch-mx51/imx-regs.h diff --git a/include/asm-arm/arch-mx51/asm-offsets.h b/include/asm-arm/arch-mx51/asm-offsets.h new file mode 100644 index 0000000..3a83fa0 --- /dev/null +++ b/include/asm-arm/arch-mx51/asm-offsets.h @@ -0,0 +1,50 @@ +/* + * needed for cpu/arm_cortexa8/mx51/lowlevel_init.S + * + * These should be auto-generated + */ +/* CCM */ +#define CLKCTL_CCR 0x00 +#define CLKCTL_CCDR 0x04 +#define CLKCTL_CSR 0x08 +#define CLKCTL_CCSR 0x0C +#define CLKCTL_CACRR 0x10 +#define CLKCTL_CBCDR 0x14 +#define CLKCTL_CBCMR 0x18 +#define CLKCTL_CSCMR1 0x1C +#define CLKCTL_CSCMR2 0x20 +#define CLKCTL_CSCDR1 0x24 +#define CLKCTL_CS1CDR 0x28 +#define CLKCTL_CS2CDR 0x2C +#define CLKCTL_CDCDR 0x30 +#define CLKCTL_CHSCCDR 0x34 +#define CLKCTL_CSCDR2 0x38 +#define CLKCTL_CSCDR3 0x3C +#define CLKCTL_CSCDR4 0x40 +#define CLKCTL_CWDR 0x44 +#define CLKCTL_CDHIPR 0x48 +#define CLKCTL_CDCR 0x4C +#define CLKCTL_CTOR 0x50 +#define CLKCTL_CLPCR 0x54 +#define CLKCTL_CISR 0x58 +#define CLKCTL_CIMR 0x5C +#define CLKCTL_CCOSR 0x60 +#define CLKCTL_CGPR 0x64 +#define CLKCTL_CCGR0 0x68 +#define CLKCTL_CCGR1 0x6C +#define CLKCTL_CCGR2 0x70 +#define CLKCTL_CCGR3 0x74 +#define CLKCTL_CCGR4 0x78 +#define CLKCTL_CCGR5 0x7C +#define CLKCTL_CCGR6 0x80 +#define CLKCTL_CMEOR 0x84 + +/* DPLL */ +#define PLL_DP_CTL 0x00 +#define PLL_DP_CONFIG 0x04 +#define PLL_DP_OP 0x08 +#define PLL_DP_MFD 0x0C +#define PLL_DP_MFN 0x10 +#define PLL_DP_HFS_OP 0x1C +#define PLL_DP_HFS_MFD 0x20 +#define PLL_DP_HFS_MFN 0x24 diff --git a/include/asm-arm/arch-mx51/crm_regs.h b/include/asm-arm/arch-mx51/crm_regs.h new file mode 100644 index 0000000..14aa231 --- /dev/null +++ b/include/asm-arm/arch-mx51/crm_regs.h @@ -0,0 +1,192 @@ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ + +#define MXC_CCM_BASE CCM_BASE_ADDR + +/* DPLL register mapping structure */ +struct mxc_pll_reg { + u32 ctrl; + u32 config; + u32 op; + u32 mfd; + u32 mfn; + u32 mfn_minus; + u32 mfn_plus; + u32 hfs_op; + u32 hfs_mfd; + u32 hfs_mfn; + u32 mfn_togc; + u32 destat; +}; + +/* Register maping of CCM*/ +struct mxc_ccm_reg { + u32 ccr; /* 0x0000 */ + u32 ccdr; + u32 csr; + u32 ccsr; + u32 cacrr; /* 0x0010*/ + u32 cbcdr; + u32 cbcmr; + u32 cscmr1; + u32 cscmr2; /* 0x0020 */ + u32 cscdr1; + u32 cs1cdr; + u32 cs2cdr; + u32 cdcdr; /* 0x0030 */ + u32 chscdr; + u32 cscdr2; + u32 cscdr3; + u32 cscdr4; /* 0x0040 */ + u32 cwdr; + u32 cdhipr; + u32 cdcr; + u32 ctor; /* 0x0050 */ + u32 clpcr; + u32 cisr; + u32 cimr; + u32 ccosr; /* 0x0060 */ + u32 cgpr; + u32 CCGR0; + u32 CCGR1; + u32 CCGR2; /* 0x0070 */ + u32 CCGR3; + u32 CCGR4; + u32 CCGR5; + u32 CCGR6; /* 0x0080 */ + u32 cmeor; +}; + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 +#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 + +/* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) +#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26 +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 +#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0 +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F + +/* Define the bits in register CBCMR */ +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 +#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 +#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 + +#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/include/asm-arm/arch-mx51/imx-regs.h b/include/asm-arm/arch-mx51/imx-regs.h new file mode 100644 index 0000000..927eda3 --- /dev/null +++ b/include/asm-arm/arch-mx51/imx-regs.h @@ -0,0 +1,282 @@ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MXC_MX51_H__ +#define __ASM_ARCH_MXC_MX51_H__ + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) +/* + * IRAM + */ +#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */ +/* + * Graphics Memory of GPU + */ +#define GPU_BASE_ADDR 0x20000000 +#define GPU_CTRL_BASE_ADDR 0x30000000 +#define IPU_CTRL_BASE_ADDR 0x40000000 +/* + * Debug + */ +#define DEBUG_BASE_ADDR 0x60000000 +#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) +#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) +#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) +#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) +#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) +#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) +#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) +#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) + +/* + * SPBA global module enabled #0 + */ +#define SPBA0_BASE_ADDR 0x70000000 + +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) +#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) +#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) +#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) +#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) +#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) +#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x73F00000 + +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) +#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) +#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) +#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) +#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) +#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) +#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) +#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) +#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) +#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) +#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) +#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) +#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) +#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) +#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) +#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x83F00000 + +#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) +#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) +#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) +#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) +#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) +#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) +#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) +#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) +#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) +#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) +#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) +#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) +#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) +#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) +#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) +#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) +#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) +#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) +#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) +#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) +#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) +#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) +#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) +#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) +#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) + +#define TZIC_BASE_ADDR 0x8FFFC000 + +/* + * Memory regions and CS + */ +#define CSD0_BASE_ADDR 0x90000000 +#define CSD1_BASE_ADDR 0xA0000000 +#define CS0_BASE_ADDR 0xB0000000 +#define CS1_BASE_ADDR 0xB8000000 +#define CS2_BASE_ADDR 0xC0000000 +#define CS3_BASE_ADDR 0xC8000000 +#define CS4_BASE_ADDR 0xCC000000 +#define CS5_BASE_ADDR 0xCE000000 + +/* + * NFC + */ +#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ + +/*! + * Number of GPIO port as defined in the IC Spec + */ +#define GPIO_PORT_NUM 4 +/*! + * Number of GPIO pins per port + */ +#define GPIO_NUM_PIN 32 + +#define IIM_SREV 0x24 +#define ROM_SI_REV 0x48 + +#define NFC_BUF_SIZE 0x1000 + +/* M4IF */ +#define M4IF_FBPM0 0x40 +#define M4IF_FIDBP 0x48 + +/* Assuming 24MHz input clock with doubler ON */ +/* MFI PDF */ +#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_850 (48 - 1) +#define DP_MFN_850 41 + +#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_800 (3 - 1) +#define DP_MFN_800 1 + +#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) +#define DP_MFD_700 (24 - 1) +#define DP_MFN_700 7 + +#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) +#define DP_MFD_665 (96 - 1) +#define DP_MFN_665 89 + +#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) +#define DP_MFD_532 (24 - 1) +#define DP_MFN_532 13 + +#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) +#define DP_MFD_400 (3 - 1) +#define DP_MFN_400 1 + +#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) +#define DP_MFD_216 (4 - 1) +#define DP_MFN_216 3 + +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 +#define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_5 0x25 +#define CHIP_REV_3_0 0x30 + +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 + +#ifndef __ASSEMBLY__ + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_FEC_CLK, +}; + +struct clkctl { + u32 ccr; + u32 ccdr; + u32 csr; + u32 ccsr; + u32 cacrr; + u32 cbcdr; + u32 cbcmr; + u32 cscmr1; + u32 cscmr2; + u32 cscdr1; + u32 cs1cdr; + u32 cs2cdr; + u32 cdcdr; + u32 chsccdr; + u32 cscdr2; + u32 cscdr3; + u32 cscdr4; + u32 cwdr; + u32 cdhipr; + u32 cdcr; + u32 ctor; + u32 clpcr; + u32 cisr; + u32 cimr; + u32 ccosr; + u32 cgpr; + u32 ccgr0; + u32 ccgr1; + u32 ccgr2; + u32 ccgr3; + u32 ccgr4; + u32 ccgr5; + u32 ccgr6; + u32 cmeor; +}; + +/* WEIM registers */ +struct weim { + u32 csgcr1; + u32 csgcr2; + u32 csrcr1; + u32 csrcr2; + u32 cswcr1; + u32 cswcr2; +}; + +/*! + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS (*((volatile u32 *)(CCM_BASE_ADDR+0x18))) +#define NFMS_BIT 8 +#define NFMS_NF_DWIDTH 14 +#define NFMS_NF_PG_SZ 8 + +extern unsigned int get_board_rev(void); +extern int is_soc_rev(int rev); + +#endif /* __ASSEMBLER__*/ + +#endif /* __ASM_ARCH_MXC_MX51_H__ */ -- cgit v1.1 From 67adcee0e091f0935e7dd722404d2a864cdecbe7 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 20 Jan 2010 18:20:04 +0100 Subject: MX51: Add pin and multiplexer definitions. The patch add header files to support the pin multiplexer of the the Freescale i.MX51 processor. Signed-off-by: Stefano Babic Signed-off-by: Fred Fan --- include/asm-arm/arch-mx51/iomux.h | 193 ++++++++++++++++++ include/asm-arm/arch-mx51/mx51_pins.h | 374 ++++++++++++++++++++++++++++++++++ 2 files changed, 567 insertions(+) create mode 100644 include/asm-arm/arch-mx51/iomux.h create mode 100644 include/asm-arm/arch-mx51/mx51_pins.h diff --git a/include/asm-arm/arch-mx51/iomux.h b/include/asm-arm/arch-mx51/iomux.h new file mode 100644 index 0000000..a41c387 --- /dev/null +++ b/include/asm-arm/arch-mx51/iomux.h @@ -0,0 +1,193 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MACH_MX51_IOMUX_H__ +#define __MACH_MX51_IOMUX_H__ + +#include +#include +#include +#include + +typedef unsigned int iomux_pin_name_t; + +/* various IOMUX output functions */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */ + IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/* various IOMUX pad functions */ +typedef enum iomux_pad_config { + PAD_CTL_SRE_SLOW = 0x0 << 0, /* Slow slew rate */ + PAD_CTL_SRE_FAST = 0x1 << 0, /* Fast slew rate */ + PAD_CTL_DRV_LOW = 0x0 << 1, /* Low drive strength */ + PAD_CTL_DRV_MEDIUM = 0x1 << 1, /* Medium drive strength */ + PAD_CTL_DRV_HIGH = 0x2 << 1, /* High drive strength */ + PAD_CTL_DRV_MAX = 0x3 << 1, /* Max drive strength */ + PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, /* Opendrain disable */ + PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */ + PAD_CTL_100K_PD = 0x0 << 4, /* 100Kohm pulldown */ + PAD_CTL_47K_PU = 0x1 << 4, /* 47Kohm pullup */ + PAD_CTL_100K_PU = 0x2 << 4, /* 100Kohm pullup */ + PAD_CTL_22K_PU = 0x3 << 4, /* 22Kohm pullup */ + PAD_CTL_PUE_KEEPER = 0x0 << 6, /* enable pulldown */ + PAD_CTL_PUE_PULL = 0x1 << 6, /* enable pullup */ + PAD_CTL_PKE_NONE = 0x0 << 7, /* Disable pullup/pulldown */ + PAD_CTL_PKE_ENABLE = 0x1 << 7, /* Enable pullup/pulldown */ + PAD_CTL_HYS_NONE = 0x0 << 8, /* Hysteresis disabled */ + PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */ + PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */ + PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */ + PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */ + PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */ +} iomux_pad_config_t; + +/* various IOMUX input select register index */ +typedef enum iomux_input_select { + MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, + MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, + /* TO2 */ + MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, + /* TO2 */ + MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, + MUX_IN_FEC_FEC_COL_SELECT_INPUT, + MUX_IN_FEC_FEC_CRS_SELECT_INPUT, + MUX_IN_FEC_FEC_MDI_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, + MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, + /* TO2 */ + MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, + /* TO2 */ + MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, + /* TO2 */ + MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, + MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, + MUX_INPUT_NUM_MUX, +} iomux_input_select_t; + +/* various IOMUX input functions */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_config_t; + +void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); + +#endif /* __MACH_MX51_IOMUX_H__ */ diff --git a/include/asm-arm/arch-mx51/mx51_pins.h b/include/asm-arm/arch-mx51/mx51_pins.h new file mode 100644 index 0000000..ca26f41 --- /dev/null +++ b/include/asm-arm/arch-mx51/mx51_pins.h @@ -0,0 +1,374 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MXC_MX51_PINS_H__ +#define __ASM_ARCH_MXC_MX51_PINS_H__ + +#ifndef __ASSEMBLY__ + +/* + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | GPIO_I | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 9 contains MUX_I used to identify the register + * offset (0-based. base is IOMUX_module_base) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The + * similar field definitions are used for the pad control register. + * The IOMUX controller can be split in two parts. At the begeinning, + * there is the register definitions for the multiplexing each pin. + * Then there is a set of registers (PAD_I) to configure each pin + * (pullup, pulldown, etc). + * PAD_I defines the offset of the pad register for each pin. + * GPIO_I defines, if available, the number of gpio that can be + * connected to that pad + * IO_I defines the multiplexer mode required to set the pad in gpio mode + * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs + * + * For example, the MX51_PIN_ETM_D0 is defined in the enumeration: + * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I) + * It means the mux control register is at register offset 0x28. The pad control + * register offset is: 0x250 and also occupy the least significant bits + * within the register. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 +/*! + * Starting bit position within each entry of \b iomux_pins to represent which + * mux mode is for GPIO (0-based) + */ +#define GPIO_I 21 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ + GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ + ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) +#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) +#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) + +#define NON_GPIO_PORT 0x7 +#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) +#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) + +#define NON_MUX_I PIN_TO_MUX_MASK +#define MUX_I_START 0x001C +#define PAD_I_START 0x3F0 +#define INPUT_CTL_START 0x8C4 +#define INPUT_CTL_START_TO1 0x928 +#define MUX_I_END (PAD_I_START - 4) + +#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | \ + ((pi - PAD_I_START) << PAD_I) | \ + ((ga) << GPIO_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, ga, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) +#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) + +/* + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins { + MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8), + MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8), + MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8), + MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8), + MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC), + MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC), + MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC), + MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC), + MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0), + MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0), + MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0), + MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0), + MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC), + MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC), + MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC), + MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC), + MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0), + MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4), + MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8), + MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC), + MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400), + MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404), + MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408), + MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C), + MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410), + MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414), + MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418), + MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C), + MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420), + MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424), + MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428), + MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C), + MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430), + MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434), + MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438), + MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C), + MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440), + MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444), + MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448), + MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C), + MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450), + MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454), + MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458), + MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C), + MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460), + MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464), + MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468), + MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C), + MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470), + MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474), + MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478), + MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C), + MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480), + MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484), + MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488), + MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C), + MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494), + MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0), + MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0), + MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4), + MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8), + MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC), + MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0), + MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4), + MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8), + MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC), + MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500), + MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504), + MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514), + MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND, + MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8), + MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC), + MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0), + MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518), + MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C), + MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520), + MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524), + MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528), + MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C), + MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530), + MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534), + MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538), + MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C), + MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540), + MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544), + MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548), + MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C), + MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550), + MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554), + MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558), + MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C), + MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560), + MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564), + MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568), + MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C), + MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570), + MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574), + MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578), + MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C), + MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580), + MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584), + MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588), + MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C), + MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590), + MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594), + MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598), + MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C), + MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0), + MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4), + MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8), + MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC), + MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0), + MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4), + MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8), + MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860), + MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC), + MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0), + MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4), + MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8), + MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC), + MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0), + MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4), + MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8), + MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC), + MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0), + MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4), + MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C), + MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8), + MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC), + MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0), + MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4), + MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8), + MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC), + MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600), + MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604), + MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608), + MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C), + MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610), + MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614), + MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618), + MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C), + MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620), + MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624), + MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628), + MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C), + MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630), + MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634), + MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638), + MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C), + MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640), + MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644), + MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648), + MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C), + MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650), + MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654), + MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658), + MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C), + MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660), + MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678), + MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C), + MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680), + MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684), + MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688), + MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C), + MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690), + MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694), + MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698), + MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C), + MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0), + MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4), + MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8), + MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC), + MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0), + MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4), + MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8), + MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC), + MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0), + MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4), + MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8), + MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC), + MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0), + MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4), + MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8), + MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC), + MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0), + MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4), + MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8), + MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC), + MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0), + MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4), + MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8), + MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC), + MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700), + MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704), + MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708), + MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C), + MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710), + MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714), + MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718), + MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C), + MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720), + MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724), + MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728), + MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C), + MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734), + MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C), + MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740), + MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744), + MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748), + MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C), + MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750), + MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754), + MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758), + MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C), + MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760), + MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764), + MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768), + MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C), + MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770), + MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774), + MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778), + MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C), + MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780), + MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784), + MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788), + MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C), + MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790), + MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794), + MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798), + MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C), + MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0), + MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4), + MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8), + MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC), + MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0), + MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4), + MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8), + MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC), + MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0), + MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4), + MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8), + MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC), + MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0), + MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4), + MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8), + MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC), + MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804), + MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808), + MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C), + MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810), + MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814), + MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818), +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */ -- cgit v1.1 From 71d64c0e4fa5910c15eca175a8f3b0e1c1d6711c Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 20 Jan 2010 18:20:19 +0100 Subject: serial_mxc: add support for MX51 processor The patch adds support for the Freescale mx51 processor. Signed-off-by: Stefano Babic Signed-off-by: Fred Fan --- drivers/serial/serial_mxc.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index acc5b7d..b21c9c3 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -49,8 +49,18 @@ #define UART_PHYS 0x1001b000 #elif defined(CONFIG_SYS_MX27_UART6) #define UART_PHYS 0x1001c000 +#elif defined(CONFIG_SYS_MX51_UART1) +#define UART_PHYS UART1_BASE_ADDR +#elif defined(CONFIG_SYS_MX51_UART2) +#define UART_PHYS UART2_BASE_ADDR +#elif defined(CONFIG_SYS_MX51_UART3) +#define UART_PHYS UART3_BASE_ADDR #else -#error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver" +#error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver" +#endif + +#ifdef CONFIG_SERIAL_MULTI +#warning "MXC driver does not support MULTI serials." #endif /* Register definitions */ @@ -166,11 +176,7 @@ DECLARE_GLOBAL_DATA_PTR; void serial_setbrg (void) { -#ifdef CONFIG_MX31 - u32 clk = mx31_get_ipg_clk(); -#else - u32 clk = imx_get_perclk1(); -#endif + u32 clk = imx_get_uartclk(); if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; -- cgit v1.1 From 250de12bc2f7842807d25e16971c5bea59c3a4b1 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 20 Jan 2010 18:20:39 +0100 Subject: mmc: check correctness of the voltage mask in ocr Most cards do not answer if some reserved bits in the ocr are set. However, some controllers can set bit 7 (reserved for low voltages), but how to manage low voltages SD card is not yet specified. Signed-off-by: Stefano Babic --- drivers/mmc/mmc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index b69ce15..d91b9b7 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -273,7 +273,15 @@ sd_send_op_cond(struct mmc *mmc) cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; cmd.resp_type = MMC_RSP_R3; - cmd.cmdarg = mmc->voltages; + + /* + * Most cards do not answer if some reserved bits + * in the ocr are set. However, Some controller + * can set bit 7 (reserved for low voltages), but + * how to manage low voltages SD card is not yet + * specified. + */ + cmd.cmdarg = mmc->voltages & 0xff8000; if (mmc->version == SD_VERSION_2) cmd.cmdarg |= OCR_HCS; -- cgit v1.1 From 11fdade294b4d60c19ae861515aabddca1278deb Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 5 Feb 2010 15:04:43 +0100 Subject: MMC: add weak function to detect MMC/SD card Most controllers can check if there is a card in the slot. However, they require pins that could be not available because required by other functions and the detection of a card must be performed in another way. This patch adds a weak function that a board can implement to add its internal custom way to check the presence of a MMC/SD card. Signed-off-by: Stefano Babic --- drivers/mmc/mmc.c | 7 +++++++ include/mmc.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index d91b9b7..3679225 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -36,6 +36,13 @@ static struct list_head mmc_devices; static int cur_dev_num = -1; +int __board_mmc_getcd(u8 *cd, struct mmc *mmc) { + return -1; +} + +int board_mmc_getcd(u8 *cd, struct mmc *mmc)__attribute__((weak, + alias("__board_mmc_getcd"))); + int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { return mmc->send_cmd(mmc, cmd, data); diff --git a/include/mmc.h b/include/mmc.h index 2dc69ab..8973bc7 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -272,6 +272,7 @@ int mmc_init(struct mmc *mmc); int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); struct mmc *find_mmc_device(int dev_num); void print_mmc_devices(char separator); +int board_mmc_getcd(u8 *cd, struct mmc *mmc); #ifndef CONFIG_GENERIC_MMC int mmc_legacy_init(int verbose); -- cgit v1.1 From 69df00f9d9c2f45b4576d1eae79bfac8bebb8821 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 5 Feb 2010 15:07:33 +0100 Subject: ARM: add accessors functions Some Freescale's processors of different architecture have the same peripheral (eSDHC controller in PowerPC and i.MX51). This patch adds accessors for the internal registers of the SOCs, as already implemented in the PowerPC architecture. Signed-off-by: Stefano Babic --- include/asm-arm/io.h | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index fec3a7e..0a4b5be 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -113,6 +113,61 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen); #define __raw_base_readl(base,off) __arch_base_getl(base,off) /* + * Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) +#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) + +#define out_le32(a,v) out_arch(l,le32,a,v) +#define out_le16(a,v) out_arch(w,le16,a,v) + +#define in_le32(a) in_arch(l,le32,a) +#define in_le16(a) in_arch(w,le16,a) + +#define out_be32(a,v) out_arch(l,be32,a,v) +#define out_be16(a,v) out_arch(w,be16,a,v) + +#define in_be32(a) in_arch(l,be32,a) +#define in_be16(a) in_arch(w,be16,a) + +#define out_8(a,v) __raw_writeb(v,a) +#define in_8(a) __raw_readb(a) + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + +/* * Now, pick up the machine-defined IO definitions */ #if 0 /* XXX###XXX */ -- cgit v1.1 From c67bee1460a0da89ef08cbc28375171acc9a4227 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 5 Feb 2010 15:11:27 +0100 Subject: fsl_esdhc: add support for mx51 processor The esdhc controller in the mx51 processor is quite the same as the one in some powerpc processors (MPC83xx, MPC85xx). This patches adapts the driver to support the arm mx51. Signed-off-by: Stefano Babic --- cpu/arm_cortexa8/mx51/Makefile | 2 +- cpu/arm_cortexa8/mx51/speed.c | 38 +++++++++++ drivers/mmc/fsl_esdhc.c | 149 ++++++++++++++++++++++++++++------------- include/asm-arm/global_data.h | 3 + include/fsl_esdhc.h | 27 ++++++++ lib_arm/board.c | 3 + 6 files changed, 173 insertions(+), 49 deletions(-) create mode 100644 cpu/arm_cortexa8/mx51/speed.c diff --git a/cpu/arm_cortexa8/mx51/Makefile b/cpu/arm_cortexa8/mx51/Makefile index 4d82293..7cfaa2c 100644 --- a/cpu/arm_cortexa8/mx51/Makefile +++ b/cpu/arm_cortexa8/mx51/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = soc.o clock.o iomux.o timer.o +COBJS = soc.o clock.o iomux.o timer.o speed.o SOBJS = lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm_cortexa8/mx51/speed.c b/cpu/arm_cortexa8/mx51/speed.c new file mode 100644 index 0000000..10acbbf --- /dev/null +++ b/cpu/arm_cortexa8/mx51/speed.c @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +int get_clocks(void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK); +#endif + return 0; +} diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c6e9e6e..e665b5e 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -37,7 +37,6 @@ #include #include - DECLARE_GLOBAL_DATA_PTR; struct fsl_esdhc { @@ -102,7 +101,8 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) { uint wml_value; int timeout; - struct fsl_esdhc *regs = mmc->priv; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; wml_value = data->blocksize/4; @@ -112,24 +112,24 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) wml_value = 0x100000 | wml_value; - out_be32(®s->dsaddr, (u32)data->dest); + esdhc_write32(®s->dsaddr, (u32)data->dest); } else { if (wml_value > 0x80) wml_value = 0x80; - if ((in_be32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { + if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); return TIMEOUT; } wml_value = wml_value << 16 | 0x10; - out_be32(®s->dsaddr, (u32)data->src); + esdhc_write32(®s->dsaddr, (u32)data->src); } - out_be32(®s->wml, wml_value); + esdhc_write32(®s->wml, wml_value); - out_be32(®s->blkattr, data->blocks << 16 | data->blocksize); + esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); /* Calculate the timeout period for data transactions */ - timeout = __ilog2(mmc->tran_speed/10); + timeout = fls(mmc->tran_speed/10) - 1; timeout -= 13; if (timeout > 14) @@ -138,7 +138,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) if (timeout < 0) timeout = 0; - clrsetbits_be32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); + esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); return 0; } @@ -153,17 +153,20 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { uint xfertyp; uint irqstat; - volatile struct fsl_esdhc *regs = mmc->priv; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; - out_be32(®s->irqstat, -1); + esdhc_write32(®s->irqstat, -1); sync(); /* Wait for the bus to be idle */ - while ((in_be32(®s->prsstat) & PRSSTAT_CICHB) || - (in_be32(®s->prsstat) & PRSSTAT_CIDHB)); + while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || + (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) + ; - while (in_be32(®s->prsstat) & PRSSTAT_DLA); + while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) + ; /* Wait at least 8 SD clock cycles before the next command */ /* @@ -185,14 +188,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) xfertyp = esdhc_xfertyp(cmd, data); /* Send the command */ - out_be32(®s->cmdarg, cmd->cmdarg); - out_be32(®s->xfertyp, xfertyp); + esdhc_write32(®s->cmdarg, cmd->cmdarg); + esdhc_write32(®s->xfertyp, xfertyp); /* Wait for the command to complete */ - while (!(in_be32(®s->irqstat) & IRQSTAT_CC)); + while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC)) + ; - irqstat = in_be32(®s->irqstat); - out_be32(®s->irqstat, irqstat); + irqstat = esdhc_read32(®s->irqstat); + esdhc_write32(®s->irqstat, irqstat); if (irqstat & CMD_ERR) return COMM_ERR; @@ -204,21 +208,21 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (cmd->resp_type & MMC_RSP_136) { u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; - cmdrsp3 = in_be32(®s->cmdrsp3); - cmdrsp2 = in_be32(®s->cmdrsp2); - cmdrsp1 = in_be32(®s->cmdrsp1); - cmdrsp0 = in_be32(®s->cmdrsp0); + cmdrsp3 = esdhc_read32(®s->cmdrsp3); + cmdrsp2 = esdhc_read32(®s->cmdrsp2); + cmdrsp1 = esdhc_read32(®s->cmdrsp1); + cmdrsp0 = esdhc_read32(®s->cmdrsp0); cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); cmd->response[3] = (cmdrsp0 << 8); } else - cmd->response[0] = in_be32(®s->cmdrsp0); + cmd->response[0] = esdhc_read32(®s->cmdrsp0); /* Wait until all of the blocks are transferred */ if (data) { do { - irqstat = in_be32(®s->irqstat); + irqstat = esdhc_read32(®s->irqstat); if (irqstat & DATA_ERR) return COMM_ERR; @@ -226,10 +230,10 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (irqstat & IRQSTAT_DTOE) return TIMEOUT; } while (!(irqstat & IRQSTAT_TC) && - (in_be32(®s->prsstat) & PRSSTAT_DLA)); + (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); } - out_be32(®s->irqstat, -1); + esdhc_write32(®s->irqstat, -1); return 0; } @@ -238,9 +242,13 @@ void set_sysctl(struct mmc *mmc, uint clock) { int sdhc_clk = gd->sdhc_clk; int div, pre_div; - volatile struct fsl_esdhc *regs = mmc->priv; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; uint clk; + if (clock < mmc->f_min) + clock = mmc->f_min; + if (sdhc_clk / 16 > clock) { for (pre_div = 2; pre_div < 256; pre_div *= 2) if ((sdhc_clk / pre_div) <= (clock * 16)) @@ -257,67 +265,105 @@ void set_sysctl(struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); - clrsetbits_be32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); + /* On imx the clock must be stopped before changing frequency */ + if (cfg->clk_enable) + esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); + + esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); udelay(10000); - setbits_be32(®s->sysctl, SYSCTL_PEREN); + clk = SYSCTL_PEREN; + /* On imx systems the clock must be explicitely enabled */ + if (cfg->clk_enable) + clk |= SYSCTL_CKEN; + + esdhc_setbits32(®s->sysctl, clk); } static void esdhc_set_ios(struct mmc *mmc) { - struct fsl_esdhc *regs = mmc->priv; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; /* Set the clock speed */ set_sysctl(mmc, mmc->clock); /* Set the bus width */ - clrbits_be32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); + esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); if (mmc->bus_width == 4) - setbits_be32(®s->proctl, PROCTL_DTW_4); + esdhc_setbits32(®s->proctl, PROCTL_DTW_4); else if (mmc->bus_width == 8) - setbits_be32(®s->proctl, PROCTL_DTW_8); + esdhc_setbits32(®s->proctl, PROCTL_DTW_8); + } static int esdhc_init(struct mmc *mmc) { - struct fsl_esdhc *regs = mmc->priv; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; int timeout = 1000; + int ret = 0; + u8 card_absent; /* Enable cache snooping */ - out_be32(®s->scr, 0x00000040); + if (cfg && !cfg->no_snoop) + esdhc_write32(®s->scr, 0x00000040); + + /* Reset the entire host controller */ + esdhc_write32(®s->sysctl, SYSCTL_RSTA); + + /* Wait until the controller is available */ + while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) + udelay(1000); - out_be32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); + esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */ set_sysctl(mmc, 400000); /* Disable the BRR and BWR bits in IRQSTAT */ - clrbits_be32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); + esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); /* Put the PROCTL reg back to the default */ - out_be32(®s->proctl, PROCTL_INIT); + esdhc_write32(®s->proctl, PROCTL_INIT); - while (!(in_be32(®s->prsstat) & PRSSTAT_CINS) && --timeout) - udelay(1000); + /* Set timout to the maximum value */ + esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); - if (timeout <= 0) - return NO_CARD_ERR; + /* Check if there is a callback for detecting the card */ + if (board_mmc_getcd(&card_absent, mmc)) { + timeout = 1000; + while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && + --timeout) + udelay(1000); - return 0; + if (timeout <= 0) + ret = NO_CARD_ERR; + } else { + if (card_absent) + ret = NO_CARD_ERR; + } + + return ret; } -static int esdhc_initialize(bd_t *bis) +int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) { - struct fsl_esdhc *regs = (struct fsl_esdhc *)CONFIG_SYS_FSL_ESDHC_ADDR; + struct fsl_esdhc *regs; struct mmc *mmc; u32 caps; + if (!cfg) + return -1; + mmc = malloc(sizeof(struct mmc)); sprintf(mmc->name, "FSL_ESDHC"); - mmc->priv = regs; + regs = (struct fsl_esdhc *)cfg->esdhc_base; + + mmc->priv = cfg; mmc->send_cmd = esdhc_send_cmd; mmc->set_ios = esdhc_set_ios; mmc->init = esdhc_init; @@ -346,9 +392,15 @@ static int esdhc_initialize(bd_t *bis) int fsl_esdhc_mmc_init(bd_t *bis) { - return esdhc_initialize(bis); + struct fsl_esdhc_cfg *cfg; + + cfg = malloc(sizeof(struct fsl_esdhc_cfg)); + memset(cfg, 0, sizeof(struct fsl_esdhc_cfg)); + cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; + return fsl_esdhc_initialize(bis, cfg); } +#ifdef CONFIG_OF_LIBFDT void fdt_fixup_esdhc(void *blob, bd_t *bd) { const char *compat = "fsl,esdhc"; @@ -365,3 +417,4 @@ out: do_fixup_by_compat(blob, compat, "status", status, strlen(status) + 1, 1); } +#endif diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h index 8115a24..02cfe45 100644 --- a/include/asm-arm/global_data.h +++ b/include/asm-arm/global_data.h @@ -44,6 +44,9 @@ typedef struct global_data { #ifdef CONFIG_VFD unsigned char vfd_type; /* display type */ #endif +#ifdef CONFIG_FSL_ESDHC + unsigned long sdhc_clk; +#endif #if 0 unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index eac6a2b..01b7dec 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -27,12 +27,15 @@ #define __FSL_ESDHC_H__ #include +#include /* FSL eSDHC-specific constants */ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 #define SYSCTL_CLOCK_MASK 0x0000fff0 +#define SYSCTL_RSTA 0x01000000 +#define SYSCTL_CKEN 0x00000008 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 @@ -142,8 +145,32 @@ #define ESDHC_HOSTCAPBLT_DMAS 0x00400000 #define ESDHC_HOSTCAPBLT_HSS 0x00200000 +struct fsl_esdhc_cfg { + u32 esdhc_base; + u32 no_snoop; + u32 clk_enable; +}; + +/* Select the correct accessors depending on endianess */ +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define esdhc_read32 in_le32 +#define esdhc_write32 out_le32 +#define esdhc_clrsetbits32 clrsetbits_le32 +#define esdhc_clrbits32 clrbits_le32 +#define esdhc_setbits32 setbits_le32 +#elif __BYTE_ORDER == __BIG_ENDIAN +#define esdhc_read32 in_be32 +#define esdhc_write32 out_be32 +#define esdhc_clrsetbits32 clrsetbits_be32 +#define esdhc_clrbits32 clrbits_be32 +#define esdhc_setbits32 setbits_be32 +#else +#error "Endianess is not defined: please fix to continue" +#endif + #ifdef CONFIG_FSL_ESDHC int fsl_esdhc_mmc_init(bd_t *bis); +int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg); void fdt_fixup_esdhc(void *blob, bd_t *bd); #else static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; } diff --git a/lib_arm/board.c b/lib_arm/board.c index e148739..f5660a9 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -243,6 +243,9 @@ init_fnc_t *init_sequence[] = { interrupt_init, /* set up exceptions */ #endif timer_init, /* initialize timer */ +#ifdef CONFIG_FSL_ESDHC + get_clocks, +#endif env_init, /* initialize environment */ init_baudrate, /* initialze baudrate settings */ serial_init, /* serial communications setup */ -- cgit v1.1 From c5fb70c9114bd0a8289444d3d5c7e360eda08232 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 5 Feb 2010 15:13:58 +0100 Subject: Add initial support for Freescale mx51evk board The patch adds initial support for the Freescale mx51evk board. Network (FEC) and SD controller (fsl_esdhc) are supported. Signed-off-by: Stefano Babic Signed-off-by: Fred Fan --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 4 + board/freescale/mx51evk/Makefile | 48 +++++ board/freescale/mx51evk/config.mk | 25 +++ board/freescale/mx51evk/imximage.cfg | 119 ++++++++++ board/freescale/mx51evk/mx51evk.c | 406 +++++++++++++++++++++++++++++++++++ board/freescale/mx51evk/mx51evk.h | 51 +++++ include/configs/mx51evk.h | 172 +++++++++++++++ 9 files changed, 830 insertions(+) create mode 100644 board/freescale/mx51evk/Makefile create mode 100644 board/freescale/mx51evk/config.mk create mode 100644 board/freescale/mx51evk/imximage.cfg create mode 100644 board/freescale/mx51evk/mx51evk.c create mode 100644 board/freescale/mx51evk/mx51evk.h create mode 100644 include/configs/mx51evk.h diff --git a/MAINTAINERS b/MAINTAINERS index dd1579e..160f580 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -150,6 +150,10 @@ Dave Ellis SXNI855T MPC8xx +Fred Fan + + mx51evk i.MX51 + Thomas Frieden AmigaOneG3SE MPC7xx diff --git a/MAKEALL b/MAKEALL index 6ddf7e0..a800310 100755 --- a/MAKEALL +++ b/MAKEALL @@ -633,6 +633,7 @@ LIST_ARM11=" \ ######################################################################### LIST_ARM_CORTEX_A8=" \ devkit8000 \ + mx51evk \ omap3_beagle \ omap3_overo \ omap3_evm \ diff --git a/Makefile b/Makefile index 16b549c..ca399db 100644 --- a/Makefile +++ b/Makefile @@ -3300,6 +3300,9 @@ mx31pdk_nand_config : unconfig fi @$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31 +mx51evk_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51evk freescale mx51 + omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 ti omap24xx @@ -3771,6 +3774,7 @@ clobber: clean $(obj)cscope.* $(obj)*.*~ @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) @rm -f $(obj)u-boot.kwb + @rm -f $(obj)u-boot.imx @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes} @rm -f $(obj)cpu/mpc824x/bedbug_603e.c @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile new file mode 100644 index 0000000..eb12fc5 --- /dev/null +++ b/board/freescale/mx51evk/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx51evk.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx51evk/config.mk b/board/freescale/mx51evk/config.mk new file mode 100644 index 0000000..c8279ec --- /dev/null +++ b/board/freescale/mx51evk/config.mk @@ -0,0 +1,25 @@ +# +# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +LDSCRIPT = cpu/$(CPU)/$(SOC)/u-boot.lds +TEXT_BASE = 0x97800000 +IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg new file mode 100644 index 0000000..db09913 --- /dev/null +++ b/board/freescale/mx51evk/imximage.cfg @@ -0,0 +1,119 @@ +# +# (C Copyright 2009 +# Stefano Babic DENX Software Engineering sbabic@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# Boot Device : one of +# spi_flash, nand, onenand, sd_card + +BOOT_FROM spi + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +# Setting IOMUXC +DATA 4 0x73FA88a0 0x200 +DATA 4 0x73FA850c 0x20c5 +DATA 4 0x73FA8510 0x20c5 +DATA 4 0x73FA883c 0x2 +DATA 4 0x73FA8848 0x2 +DATA 4 0x73FA84b8 0xe7 +DATA 4 0x73FA84bc 0x45 +DATA 4 0x73FA84c0 0x45 +DATA 4 0x73FA84c4 0x45 +DATA 4 0x73FA84c8 0x45 +DATA 4 0x73FA8820 0x0 +DATA 4 0x73FA84a4 0x3 +DATA 4 0x73FA84a8 0x3 +DATA 4 0x73FA84ac 0xe3 +DATA 4 0x73FA84b0 0xe3 +DATA 4 0x73FA84b4 0xe3 +DATA 4 0x73FA84cc 0xe3 +DATA 4 0x73FA84d0 0xe2 + +DATA 4 0x73FA882c 0x6 +DATA 4 0x73FA88a4 0x6 +DATA 4 0x73FA88ac 0x6 +DATA 4 0x73FA88b8 0x6 + +# Setting DDR for micron +# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model +# CAS=3 BL=4 +# ESDCTL_ESDCTL0 +DATA 4 0x83FD9000 0x82a20000 +# ESDCTL_ESDCTL1 +DATA 4 0x83FD9008 0x82a20000 +# ESDCTL_ESDMISC +DATA 4 0x83FD9010 0x000ad0d0 +# ESDCTL_ESDCFG0 +DATA 4 0x83FD9004 0x333574aa +# ESDCTL_ESDCFG1 +DATA 4 0x83FD900C 0x333574aa + +# Init DRAM on CS0 +# ESDCTL_ESDSCR +DATA 4 0x83FD9014 0x04008008 +DATA 4 0x83FD9014 0x0000801a +DATA 4 0x83FD9014 0x0000801b +DATA 4 0x83FD9014 0x00448019 +DATA 4 0x83FD9014 0x07328018 +DATA 4 0x83FD9014 0x04008008 +DATA 4 0x83FD9014 0x00008010 +DATA 4 0x83FD9014 0x00008010 +DATA 4 0x83FD9014 0x06328018 +DATA 4 0x83FD9014 0x03808019 +DATA 4 0x83FD9014 0x00408019 +DATA 4 0x83FD9014 0x00008000 + +# Init DRAM on CS1 +DATA 4 0x83FD9014 0x0400800c +DATA 4 0x83FD9014 0x0000801e +DATA 4 0x83FD9014 0x0000801f +DATA 4 0x83FD9014 0x0000801d +DATA 4 0x83FD9014 0x0732801c +DATA 4 0x83FD9014 0x0400800c +DATA 4 0x83FD9014 0x00008014 +DATA 4 0x83FD9014 0x00008014 +DATA 4 0x83FD9014 0x0632801c +DATA 4 0x83FD9014 0x0380801d +DATA 4 0x83FD9014 0x0040801d +DATA 4 0x83FD9014 0x00008004 + +# Write to CTL0 +DATA 4 0x83FD9000 0xb2a20000 +# Write to CTL1 +DATA 4 0x83FD9008 0xb2a20000 +# ESDMISC +DATA 4 0x83FD9010 0x000ad6d0 +#ESDCTL_ESDCDLYGD +DATA 4 0x83FD9034 0x90000000 +DATA 4 0x83FD9014 0x00000000 diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c new file mode 100644 index 0000000..df0e8ed --- /dev/null +++ b/board/freescale/mx51evk/mx51evk.c @@ -0,0 +1,406 @@ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mx51evk.h" + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; +struct io_board_ctrl *mx51_io_board; + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC2_BASE_ADDR, 1, 1}, +}; +#endif + +u32 get_board_rev(void) +{ + return system_rev; +} + +static inline void set_board_rev(int rev) +{ + system_rev |= (rev & 0xF) << 8; +} + +inline int is_soc_rev(int rev) +{ + return (system_rev & 0xFF) - rev; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + return 0; +} + +static void setup_iomux_uart(void) +{ + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; + + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); +} + +static void setup_expio(void) +{ + u32 reg; + struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; + struct clkctl *pclkctl = (struct clkctl *)CCM_BASE_ADDR; + + /* CS5 setup */ + mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0); + writel(0x00410089, &pweim[5].csgcr1); + writel(0x00000002, &pweim[5].csgcr2); + + /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ + writel(0x32260000, &pweim[5].csrcr1); + + /* APR = 0 */ + writel(0x00000000, &pweim[5].csrcr2); + + /* + * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, + * WCSA=0, WCSN=0 + */ + writel(0x72080F00, &pweim[5].cswcr1); + + mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR + + IO_BOARD_OFFSET); + if ((readw(&mx51_io_board->id1) == 0xAAAA) && + (readw(&mx51_io_board->id2) == 0x5555)) { + if (is_soc_rev(CHIP_REV_2_0) < 0) { + reg = readl(&pclkctl->cbcdr); + reg = (reg & (~0x70000)) | 0x30000; + writel(reg, &pclkctl->cbcdr); + /* make sure divider effective */ + while (readl(&pclkctl->cdhipr) != 0) + ; + writel(0x0, &pclkctl->ccdr); + } + } else { + /* CS1 */ + writel(0x00410089, &pweim[1].csgcr1); + writel(0x00000002, &pweim[1].csgcr2); + /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ + writel(0x32260000, &pweim[1].csrcr1); + /* APR=0 */ + writel(0x00000000, &pweim[1].csrcr2); + /* + * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, + * WEN=0, WCSA=0, WCSN=0 + */ + writel(0x72080F00, &pweim[1].cswcr1); + mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR + + IO_BOARD_OFFSET); + } + + /* Reset interrupt status reg */ + writew(0x1F, &(mx51_io_board->int_rest)); + writew(0x00, &(mx51_io_board->int_rest)); + writew(0xFFFF, &(mx51_io_board->int_mask)); + + /* Reset the XUART and Ethernet controllers */ + reg = readw(&(mx51_io_board->sw_reset)); + reg |= 0x9; + writew(reg, &(mx51_io_board->sw_reset)); + reg &= ~0x9; + writew(reg, &(mx51_io_board->sw_reset)); +} + +static void setup_iomux_fec(void) +{ + /*FEC_MDIO*/ + mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD); + + /*FEC_MDC*/ + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004); + + /* FEC RDATA[3] */ + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); + + /* FEC RDATA[2] */ + mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); + + /* FEC RDATA[1] */ + mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); + + /* FEC RDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); + + /* FEC TDATA[3] */ + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004); + + /* FEC TDATA[2] */ + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004); + + /* FEC TDATA[1] */ + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004); + + /* FEC TDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004); + + /* FEC TX_EN */ + mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004); + + /* FEC TX_ER */ + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004); + + /* FEC TX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180); + + /* FEC TX_COL */ + mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); + + /* FEC RX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); + + /* FEC RX_CRS */ + mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180); + + /* FEC RX_ER */ + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); + + /* FEC RX_DV */ + mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); +} + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) + *cd = readl(GPIO1_BASE_ADDR) & 0x01; + else + *cd = readl(GPIO1_BASE_ADDR) & 0x40; + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + u32 index; + s32 status = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + index++) { + switch (index) { + case 0: + mxc_request_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_GPIO1_0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_0, + PAD_CTL_HYS_ENABLE); + mxc_request_iomux(MX51_PIN_GPIO1_1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_1, + PAD_CTL_HYS_ENABLE); + break; + case 1: + mxc_request_iomux(MX51_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA3, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD2_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_GPIO1_6, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_6, + PAD_CTL_HYS_ENABLE); + mxc_request_iomux(MX51_PIN_GPIO1_5, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_5, + PAD_CTL_HYS_ENABLE); + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + return status; +} +#endif + +int board_init(void) +{ + system_rev = get_cpu_rev(); + + gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE; + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + setup_iomux_uart(); + setup_expio(); + setup_iomux_fec(); + return 0; +} + +int checkboard(void) +{ + puts("Board: MX51EVK "); + + switch (system_rev & 0xff) { + case CHIP_REV_3_0: + puts("3.0 ["); + break; + case CHIP_REV_2_5: + puts("2.5 ["); + break; + case CHIP_REV_2_0: + puts("2.0 ["); + break; + case CHIP_REV_1_1: + puts("1.1 ["); + break; + case CHIP_REV_1_0: + default: + puts("1.0 ["); + break; + } + + switch (__raw_readl(SRC_BASE_ADDR + 0x8)) { + case 0x0001: + puts("POR"); + break; + case 0x0009: + puts("RST"); + break; + case 0x0010: + case 0x0011: + puts("WDOG"); + break; + default: + puts("unknown"); + } + puts("]\n"); + return 0; +} + diff --git a/board/freescale/mx51evk/mx51evk.h b/board/freescale/mx51evk/mx51evk.h new file mode 100644 index 0000000..524cdcc --- /dev/null +++ b/board/freescale/mx51evk/mx51evk.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BOARD_FREESCALE_MX51_EVK_H__ +#define __BOARD_FREESCALE_MX51_EVK_H__ + +#ifndef __ASSEMBLY__ +struct io_board_ctrl { + u16 led_ctrl; /* 0x00 */ + u16 resv1[0x03]; + u16 sb_stat; /* 0x08 */ + u16 resv2[0x03]; + u16 int_stat; /* 0x10 */ + u16 resv3[0x07]; + u16 int_rest; /* 0x20 */ + u16 resv4[0x0B]; + u16 int_mask; /* 0x38 */ + u16 resv5[0x03]; + u16 id1; /* 0x40 */ + u16 resv6[0x03]; + u16 id2; /* 0x48 */ + u16 resv7[0x03]; + u16 version; /* 0x50 */ + u16 resv8[0x03]; + u16 id3; /* 0x58 */ + u16 resv9[0x03]; + u16 sw_reset; /* 0x60 */ +}; +#endif + +#define IO_BOARD_OFFSET (0x20000) +#endif diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h new file mode 100644 index 0000000..903fe6d --- /dev/null +++ b/include/configs/mx51evk.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51EVK Board + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + + /* High Level Configuration Options */ + +#define CONFIG_MX51 /* in a mx51 */ +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ +#define CONFIG_MX51_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_L2_OFF + +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX51_UART1 + +/* + * MMC Configs + * */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +#define CONFIG_MMC + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot_addr=0xa0000000\0" \ + "uboot=u-boot.bin\0" \ + "loadaddr=0x90800000\0" \ + "bootargs_base=setenv bootargs console=tty "\ + "console=ttymxc0,${baudrate}\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX51EVK U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x90000000 +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_IS_NOWHERE + +#endif -- cgit v1.1 From e911c983f4a8d588f831806af37eb56c95512d5d Mon Sep 17 00:00:00 2001 From: John Rigby Date: Mon, 25 Jan 2010 23:12:51 -0700 Subject: mxc_serial replace platform specific clock remove ifdef'd clock selection code from serial_mxc.c and replace with call to imx_get_uartclk Add definitions for imx_get_uartclk to imx31 and imx27 include files. This makes it easier to add new imx platforms. Signed-off-by: John Rigby --- include/asm-arm/arch-mx27/clock.h | 2 ++ include/asm-arm/arch-mx31/mx31.h | 1 + 2 files changed, 3 insertions(+) diff --git a/include/asm-arm/arch-mx27/clock.h b/include/asm-arm/arch-mx27/clock.h index 5fc75c5..472e8f2 100644 --- a/include/asm-arm/arch-mx27/clock.h +++ b/include/asm-arm/arch-mx27/clock.h @@ -36,4 +36,6 @@ ulong imx_get_perclk2(void); ulong imx_get_perclk3(void); ulong imx_get_ahbclk(void); +#define imx_get_uartclk imx_get_perclk1 + #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h index 53b9f27..3cc4b35 100644 --- a/include/asm-arm/arch-mx31/mx31.h +++ b/include/asm-arm/arch-mx31/mx31.h @@ -25,6 +25,7 @@ #define __ASM_ARCH_MX31_H extern u32 mx31_get_ipg_clk(void); +#define imx_get_uartclk mx31_get_ipg_clk extern void mx31_gpio_mux(unsigned long mode); enum mx31_gpio_direction { -- cgit v1.1 From 552ff8f1d9fccf57243a01afe6dbebb982867e20 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Mon, 25 Jan 2010 23:12:56 -0700 Subject: Add support for Freescale MX25 SOC ARM926EJS core with MX31 peripherals. Signed-off-by: John Rigby Earlier Version Signed-off-by: Wolfgang Denk CC: Fred Fan CC: Tom --- cpu/arm926ejs/mx25/Makefile | 46 ++++ cpu/arm926ejs/mx25/generic.c | 263 +++++++++++++++++++ cpu/arm926ejs/mx25/reset.c | 56 ++++ cpu/arm926ejs/mx25/timer.c | 187 ++++++++++++++ drivers/serial/serial_mxc.c | 10 +- include/asm-arm/arch-mx25/clock.h | 35 +++ include/asm-arm/arch-mx25/imx-regs.h | 316 +++++++++++++++++++++++ include/asm-arm/arch-mx25/imx25-pinmux.h | 421 +++++++++++++++++++++++++++++++ 8 files changed, 1329 insertions(+), 5 deletions(-) create mode 100644 cpu/arm926ejs/mx25/Makefile create mode 100644 cpu/arm926ejs/mx25/generic.c create mode 100644 cpu/arm926ejs/mx25/reset.c create mode 100644 cpu/arm926ejs/mx25/timer.c create mode 100644 include/asm-arm/arch-mx25/clock.h create mode 100644 include/asm-arm/arch-mx25/imx-regs.h create mode 100644 include/asm-arm/arch-mx25/imx25-pinmux.h diff --git a/cpu/arm926ejs/mx25/Makefile b/cpu/arm926ejs/mx25/Makefile new file mode 100644 index 0000000..55c1e89 --- /dev/null +++ b/cpu/arm926ejs/mx25/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = generic.o timer.o +MX27OBJS = reset.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS += $(addprefix $(SRCTREE)/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/mx25/generic.c b/cpu/arm926ejs/mx25/generic.c new file mode 100644 index 0000000..694841d --- /dev/null +++ b/cpu/arm926ejs/mx25/generic.c @@ -0,0 +1,263 @@ +/* + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby + * + * Based on mx27/generic.c: + * Copyright (c) 2008 Eric Jarrige + * Copyright (c) 2009 Ilya Yanok + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_MXC_MMC +#include +#endif + +/* + * get the system pll clock in Hz + * + * mfi + mfn / (mfd +1) + * f = 2 * f_ref * -------------------- + * pd + 1 + */ +static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref) +{ + unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT) + & CCM_PLL_MFI_MASK; + unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT) + & CCM_PLL_MFN_MASK; + unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT) + & CCM_PLL_MFD_MASK; + unsigned int pd = (pll >> CCM_PLL_PD_SHIFT) + & CCM_PLL_PD_MASK; + + mfi = mfi <= 5 ? 5 : mfi; + + return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn), + (mfd + 1) * (pd + 1)); +} + +static ulong imx_get_mpllclk (void) +{ + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + ulong fref = 24000000; + + return imx_decode_pll (readl (&ccm->mpctl), fref); +} + +ulong imx_get_armclk (void) +{ + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + ulong cctl = readl (&ccm->cctl); + ulong fref = imx_get_mpllclk (); + ulong div; + + if (cctl & CCM_CCTL_ARM_SRC) + fref = lldiv ((fref * 3), 4); + + div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) + & CCM_CCTL_ARM_DIV_MASK) + 1; + + return lldiv (fref, div); +} + +ulong imx_get_ahbclk (void) +{ + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + ulong cctl = readl (&ccm->cctl); + ulong fref = imx_get_armclk (); + ulong div; + + div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) + & CCM_CCTL_AHB_DIV_MASK) + 1; + + return lldiv (fref, div); +} + +ulong imx_get_perclk (int clk) +{ + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + ulong fref = imx_get_ahbclk (); + ulong div; + + div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]); + div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1; + + return lldiv (fref, div); +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo (void) +{ + char buf[32]; + + printf ("CPU: Freescale i.MX25 at %s MHz\n\n", + strmhz (buf, imx_get_mpllclk ())); + return 0; +} +#endif + +int cpu_eth_init (bd_t * bis) +{ +#if defined(CONFIG_FEC_MXC) + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + ulong val; + + val = readl (&ccm->cgr0); + val |= (1 << 23); + writel (val, &ccm->cgr0); + return fecmxc_initialize (bis); +#else + return 0; +#endif +} + +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init (bd_t * bis) +{ +#ifdef CONFIG_MXC_MMC + return mxc_mmc_init (bis); +#else + return 0; +#endif +} + +#ifdef CONFIG_MXC_UART +void mx25_uart_init_pins (void) +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + u32 inpadctl; + u32 outpadctl; + u32 muxmode0; + + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + muxmode0 = MX25_PIN_MUX_MODE (0); + /* + * set up input pins with hysteresis and 100K pull-ups + */ + inpadctl = MX25_PIN_PAD_CTL_HYS + | MX25_PIN_PAD_CTL_PKE + | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU; + + /* + * set up output pins with 100K pull-downs + * FIXME: need to revisit this + * PUE is ignored if PKE is not set + * so the right value here is likely + * 0x0 for no pull up/down + * or + * 0xc0 for 100k pull down + */ + outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; + + /* UART1 */ + /* rxd */ + writel (muxmode0, &muxctl->pad_uart1_rxd); + writel (inpadctl, &padctl->pad_uart1_rxd); + + /* txd */ + writel (muxmode0, &muxctl->pad_uart1_txd); + writel (outpadctl, &padctl->pad_uart1_txd); + + /* rts */ + writel (muxmode0, &muxctl->pad_uart1_rts); + writel (outpadctl, &padctl->pad_uart1_rts); + + /* cts */ + writel (muxmode0, &muxctl->pad_uart1_cts); + writel (inpadctl, &padctl->pad_uart1_cts); +} +#endif /* CONFIG_MXC_UART */ + +#ifdef CONFIG_FEC_MXC +void mx25_fec_init_pins (void) +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + u32 inpadctl_100kpd; + u32 inpadctl_22kpu; + u32 outpadctl; + u32 muxmode0; + + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + muxmode0 = MX25_PIN_MUX_MODE (0); + inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS + | MX25_PIN_PAD_CTL_PKE + | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; + inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS + | MX25_PIN_PAD_CTL_PKE + | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU; + /* + * set up output pins with 100K pull-downs + * FIXME: need to revisit this + * PUE is ignored if PKE is not set + * so the right value here is likely + * 0x0 for no pull + * or + * 0xc0 for 100k pull down + */ + outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; + + /* FEC_TX_CLK */ + writel (muxmode0, &muxctl->pad_fec_tx_clk); + writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk); + + /* FEC_RX_DV */ + writel (muxmode0, &muxctl->pad_fec_rx_dv); + writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv); + + /* FEC_RDATA0 */ + writel (muxmode0, &muxctl->pad_fec_rdata0); + writel (inpadctl_100kpd, &padctl->pad_fec_rdata0); + + /* FEC_TDATA0 */ + writel (muxmode0, &muxctl->pad_fec_tdata0); + writel (outpadctl, &padctl->pad_fec_tdata0); + + /* FEC_TX_EN */ + writel (muxmode0, &muxctl->pad_fec_tx_en); + writel (outpadctl, &padctl->pad_fec_tx_en); + + /* FEC_MDC */ + writel (muxmode0, &muxctl->pad_fec_mdc); + writel (outpadctl, &padctl->pad_fec_mdc); + + /* FEC_MDIO */ + writel (muxmode0, &muxctl->pad_fec_mdio); + writel (inpadctl_22kpu, &padctl->pad_fec_mdio); + + /* FEC_RDATA1 */ + writel (muxmode0, &muxctl->pad_fec_rdata1); + writel (inpadctl_100kpd, &padctl->pad_fec_rdata1); + + /* FEC_TDATA1 */ + writel (muxmode0, &muxctl->pad_fec_tdata1); + writel (outpadctl, &padctl->pad_fec_tdata1); + +} +#endif /* CONFIG_FEC_MXC */ diff --git a/cpu/arm926ejs/mx25/reset.c b/cpu/arm926ejs/mx25/reset.c new file mode 100644 index 0000000..1e33150 --- /dev/null +++ b/cpu/arm926ejs/mx25/reset.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2009 + * Ilya Yanok, Emcraft Systems Ltd, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Reset the cpu by setting up the watchdog timer and let it time out + */ +void reset_cpu (ulong ignored) +{ + struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; + /* Disable watchdog and set Time-Out field to 0 */ + writel (0x00000000, ®s->wcr); + + /* Write Service Sequence */ + writel (0x00005555, ®s->wsr); + writel (0x0000AAAA, ®s->wsr); + + /* Enable watchdog */ + writel (WCR_WDE, ®s->wcr); + + while (1) ; +} diff --git a/cpu/arm926ejs/mx25/timer.c b/cpu/arm926ejs/mx25/timer.c new file mode 100644 index 0000000..11d41a8 --- /dev/null +++ b/cpu/arm926ejs/mx25/timer.c @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2009 + * Ilya Yanok, Emcraft Systems Ltd, + * + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby + * Add support for MX25 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +static ulong timestamp; +static ulong lastinc; + +/* + * "time" is measured in 1 / CONFIG_SYS_HZ seconds, + * "tick" is internal timer period + */ +#ifdef CONFIG_MX25_TIMER_HIGH_PRECISION +/* ~0.4% error - measured with stop-watch on 100s boot-delay */ +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, CONFIG_MX25_CLK32); + return tick; +} + +static inline unsigned long long time_to_tick(unsigned long long time) +{ + time *= CONFIG_MX25_CLK32; + do_div(time, CONFIG_SYS_HZ); + return time; +} + +static inline unsigned long long us_to_tick(unsigned long long us) +{ + us = us * CONFIG_MX25_CLK32 + 999999; + do_div(us, 1000000); + return us; +} +#else +/* ~2% error */ +#define TICK_PER_TIME ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \ + CONFIG_SYS_HZ) +#define US_PER_TICK (1000000 / CONFIG_MX25_CLK32) + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + do_div(tick, TICK_PER_TIME); + return tick; +} + +static inline unsigned long long time_to_tick(unsigned long long time) +{ + return time * TICK_PER_TIME; +} + +static inline unsigned long long us_to_tick(unsigned long long us) +{ + us += US_PER_TICK - 1; + do_div(us, US_PER_TICK); + return us; +} +#endif + +/* nothing really to do with interrupts, just starts up a counter. */ +/* The 32KHz 32-bit timer overruns in 134217 seconds */ +int timer_init(void) +{ + int i; + struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE; + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + + /* setup GP Timer 1 */ + writel(GPT_CTRL_SWR, &gpt->ctrl); + + writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1); + + for (i = 0; i < 100; i++) + writel(0, &gpt->ctrl); /* We have no udelay by now */ + writel(0, &gpt->pre); /* prescaler = 1 */ + /* Freerun Mode, 32KHz input */ + writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR, + &gpt->ctrl); + writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl); + + return 0; +} + +void reset_timer_masked(void) +{ + struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE; + /* reset time */ + /* capture current incrementer value time */ + lastinc = readl(&gpt->counter); + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +unsigned long long get_ticks (void) +{ + struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE; + ulong now = readl(&gpt->counter); /* current tick value */ + + if (now >= lastinc) { + /* + * normal mode (non roll) + * move stamp forward with absolut diff ticks + */ + timestamp += (now - lastinc); + } else { + /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + } + lastinc = now; + return timestamp; +} + +ulong get_timer_masked (void) +{ + /* + * get_ticks() returns a long long (64 bit), it wraps in + * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in + * 5 * 10^6 days - long enough. + */ + return tick_to_time(get_ticks()); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = time_to_tick(t); +} + +/* delay x useconds AND preserve advance timstamp value */ +void __udelay (unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = us_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; +} diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index b21c9c3..4b93e7b 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -27,15 +27,15 @@ #define __REG(x) (*((volatile u32 *)(x))) -#ifdef CONFIG_SYS_MX31_UART1 +#if defined(CONFIG_SYS_MX31_UART1) || defined(CONFIG_SYS_MX25_UART1) #define UART_PHYS 0x43f90000 -#elif defined(CONFIG_SYS_MX31_UART2) +#elif defined(CONFIG_SYS_MX31_UART2) || defined(CONFIG_SYS_MX25_UART2) #define UART_PHYS 0x43f94000 -#elif defined(CONFIG_SYS_MX31_UART3) +#elif defined(CONFIG_SYS_MX31_UART3) || defined(CONFIG_SYS_MX25_UART3) #define UART_PHYS 0x5000c000 -#elif defined(CONFIG_SYS_MX31_UART4) +#elif defined(CONFIG_SYS_MX31_UART4) || defined(CONFIG_SYS_MX25_UART4) #define UART_PHYS 0x43fb0000 -#elif defined(CONFIG_SYS_MX31_UART5) +#elif defined(CONFIG_SYS_MX31_UART5) || defined(CONFIG_SYS_MX25_UART5) #define UART_PHYS 0x43fb4000 #elif defined(CONFIG_SYS_MX27_UART1) #define UART_PHYS 0x1000a000 diff --git a/include/asm-arm/arch-mx25/clock.h b/include/asm-arm/arch-mx25/clock.h new file mode 100644 index 0000000..b0752e7 --- /dev/null +++ b/include/asm-arm/arch-mx25/clock.h @@ -0,0 +1,35 @@ +/* + * + * (c) 2009 Ilya Yanok, Emcraft Systems + * + * Modified for mx25 by John Rigby + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +ulong imx_get_perclk(int clk); +ulong imx_get_ahbclk(void); + +#define imx_get_uartclk() imx_get_perclk(15) + + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/include/asm-arm/arch-mx25/imx-regs.h b/include/asm-arm/arch-mx25/imx-regs.h new file mode 100644 index 0000000..f709bd8 --- /dev/null +++ b/include/asm-arm/arch-mx25/imx-regs.h @@ -0,0 +1,316 @@ +/* + * Copyright (C) 2009, DENX Software Engineering + * Author: John Rigby + * and arch-mx27/imx-regs.h + * Copyright (C) 2007 Pengutronix, + * Sascha Hauer + * Copyright (C) 2009 Ilya Yanok, + * Emcraft Systems + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMX_REGS_H +#define _IMX_REGS_H + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_FEC_MXC +extern void mx25_fec_init_pins(void); +#endif + +/* Clock Control Module (CCM) registers */ +struct ccm_regs { + u32 mpctl; /* Core PLL Control */ + u32 upctl; /* USB PLL Control */ + u32 cctl; /* Clock Control */ + u32 cgr0; /* Clock Gating Control 0 */ + u32 cgr1; /* Clock Gating Control 1 */ + u32 cgr2; /* Clock Gating Control 2 */ + u32 pcdr[4]; /* PER Clock Dividers */ + u32 rcsr; /* CCM Status */ + u32 crdr; /* CCM Reset and Debug */ + u32 dcvr0; /* DPTC Comparator Value 0 */ + u32 dcvr1; /* DPTC Comparator Value 1 */ + u32 dcvr2; /* DPTC Comparator Value 2 */ + u32 dcvr3; /* DPTC Comparator Value 3 */ + u32 ltr0; /* Load Tracking 0 */ + u32 ltr1; /* Load Tracking 1 */ + u32 ltr2; /* Load Tracking 2 */ + u32 ltr3; /* Load Tracking 3 */ + u32 ltbr0; /* Load Tracking Buffer 0 */ + u32 ltbr1; /* Load Tracking Buffer 1 */ + u32 pcmr0; /* Power Management Control 0 */ + u32 pcmr1; /* Power Management Control 1 */ + u32 pcmr2; /* Power Management Control 2 */ + u32 mcr; /* Miscellaneous Control */ + u32 lpimr0; /* Low Power Interrupt Mask 0 */ + u32 lpimr1; /* Low Power Interrupt Mask 1 */ +}; + +/* Enhanced SDRAM Controller (ESDRAMC) registers */ +struct esdramc_regs { + u32 ctl0; /* control 0 */ + u32 cfg0; /* configuration 0 */ + u32 ctl1; /* control 1 */ + u32 cfg1; /* configuration 1 */ + u32 misc; /* miscellaneous */ + u32 pad[3]; + u32 cdly1; /* Delay Line 1 configuration debug */ + u32 cdly2; /* delay line 2 configuration debug */ + u32 cdly3; /* delay line 3 configuration debug */ + u32 cdly4; /* delay line 4 configuration debug */ + u32 cdly5; /* delay line 5 configuration debug */ + u32 cdlyl; /* delay line cycle length debug */ +}; + +/* GPIO registers */ +struct gpio_regs { + u32 dr; /* data */ + u32 dir; /* direction */ + u32 psr; /* pad satus */ + u32 icr1; /* interrupt config 1 */ + u32 icr2; /* interrupt config 2 */ + u32 imr; /* interrupt mask */ + u32 isr; /* interrupt status */ + u32 edge_sel; /* edge select */ +}; + +/* General Purpose Timer (GPT) registers */ +struct gpt_regs { + u32 ctrl; /* control */ + u32 pre; /* prescaler */ + u32 stat; /* status */ + u32 intr; /* interrupt */ + u32 cmp[3]; /* output compare 1-3 */ + u32 capt[2]; /* input capture 1-2 */ + u32 counter; /* counter */ +}; + +/* Watchdog Timer (WDOG) registers */ +struct wdog_regs { + u32 wcr; /* Control */ + u32 wsr; /* Service */ + u32 wrsr; /* Reset Status */ + u32 wicr; /* Interrupt Control */ + u32 wmcr; /* Misc Control */ +}; + +/* IIM control registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prog_p; + u32 res1[0x1f5]; + u32 iim_bank_area0[0x20]; + u32 res2[0xe0]; + u32 iim_bank_area1[0x20]; + u32 res3[0xe0]; + u32 iim_bank_area2[0x20]; +}; +#endif + +/* AIPS 1 */ +#define IMX_AIPS1_BASE (0x43F00000) +#define IMX_MAX_BASE (0x43F04000) +#define IMX_CLKCTL_BASE (0x43F08000) +#define IMX_ETB_SLOT4_BASE (0x43F0C000) +#define IMX_ETB_SLOT5_BASE (0x43F10000) +#define IMX_ECT_CTIO_BASE (0x43F18000) +#define IMX_I2C_BASE (0x43F80000) +#define IMX_I2C3_BASE (0x43F84000) +#define IMX_CAN1_BASE (0x43F88000) +#define IMX_CAN2_BASE (0x43F8C000) +#define IMX_UART1_BASE (0x43F90000) +#define IMX_UART2_BASE (0x43F94000) +#define IMX_I2C2_BASE (0x43F98000) +#define IMX_OWIRE_BASE (0x43F9C000) +#define IMX_CSPI1_BASE (0x43FA4000) +#define IMX_KPP_BASE (0x43FA8000) +#define IMX_IOPADMUX_BASE (0x43FAC000) +#define IMX_IOPADCTL_BASE (0x43FAC22C) +#define IMX_IOPADGRPCTL_BASE (0x43FAC418) +#define IMX_IOPADINPUTSEL_BASE (0x43FAC460) +#define IMX_AUDMUX_BASE (0x43FB0000) +#define IMX_ECT_IP1_BASE (0x43FB8000) +#define IMX_ECT_IP2_BASE (0x43FBC000) + +/* SPBA */ +#define IMX_SPBA_BASE (0x50000000) +#define IMX_CSPI3_BASE (0x50004000) +#define IMX_UART4_BASE (0x50008000) +#define IMX_UART3_BASE (0x5000C000) +#define IMX_CSPI2_BASE (0x50010000) +#define IMX_SSI2_BASE (0x50014000) +#define IMX_ESAI_BASE (0x50018000) +#define IMX_ATA_DMA_BASE (0x50020000) +#define IMX_SIM1_BASE (0x50024000) +#define IMX_SIM2_BASE (0x50028000) +#define IMX_UART5_BASE (0x5002C000) +#define IMX_TSC_BASE (0x50030000) +#define IMX_SSI1_BASE (0x50034000) +#define IMX_FEC_BASE (0x50038000) +#define IMX_SPBA_CTRL_BASE (0x5003C000) + +/* AIPS 2 */ +#define IMX_AIPS2_BASE (0x53F00000) +#define IMX_CCM_BASE (0x53F80000) +#define IMX_GPT4_BASE (0x53F84000) +#define IMX_GPT3_BASE (0x53F88000) +#define IMX_GPT2_BASE (0x53F8C000) +#define IMX_GPT1_BASE (0x53F90000) +#define IMX_EPIT1_BASE (0x53F94000) +#define IMX_EPIT2_BASE (0x53F98000) +#define IMX_GPIO4_BASE (0x53F9C000) +#define IMX_PWM2_BASE (0x53FA0000) +#define IMX_GPIO3_BASE (0x53FA4000) +#define IMX_PWM3_BASE (0x53FA8000) +#define IMX_SCC_BASE (0x53FAC000) +#define IMX_SCM_BASE (0x53FAE000) +#define IMX_SMN_BASE (0x53FAF000) +#define IMX_RNGD_BASE (0x53FB0000) +#define IMX_MMC_SDHC1_BASE (0x53FB4000) +#define IMX_MMC_SDHC2_BASE (0x53FB8000) +#define IMX_LCDC_BASE (0x53FBC000) +#define IMX_SLCDC_BASE (0x53FC0000) +#define IMX_PWM4_BASE (0x53FC8000) +#define IMX_GPIO1_BASE (0x53FCC000) +#define IMX_GPIO2_BASE (0x53FD0000) +#define IMX_SDMA_BASE (0x53FD4000) +#define IMX_WDT_BASE (0x53FDC000) +#define IMX_PWM1_BASE (0x53FE0000) +#define IMX_RTIC_BASE (0x53FEC000) +#define IMX_IIM_BASE (0x53FF0000) +#define IMX_USB_BASE (0x53FF4000) +#define IMX_CSI_BASE (0x53FF8000) +#define IMX_DRYICE_BASE (0x53FFC000) + +#define IMX_ARM926_ROMPATCH (0x60000000) +#define IMX_ARM926_ASIC (0x68000000) + +/* 128K Internal Static RAM */ +#define IMX_RAM_BASE (0x78000000) + +/* SDRAM BANKS */ +#define IMX_SDRAM_BANK0_BASE (0x80000000) +#define IMX_SDRAM_BANK1_BASE (0x90000000) + +#define IMX_WEIM_CS0 (0xA0000000) +#define IMX_WEIM_CS1 (0xA8000000) +#define IMX_WEIM_CS2 (0xB0000000) +#define IMX_WEIM_CS3 (0xB2000000) +#define IMX_WEIM_CS4 (0xB4000000) +#define IMX_ESDRAMC_BASE (0xB8001000) +#define IMX_WEIM_CTRL_BASE (0xB8002000) +#define IMX_M3IF_CTRL_BASE (0xB8003000) +#define IMX_EMI_CTRL_BASE (0xB8004000) + +/* NAND Flash Controller */ +#define IMX_NFC_BASE (0xBB000000) +#define NFC_BASE_ADDR IMX_NFC_BASE + +/* CCM bitfields */ +#define CCM_PLL_MFI_SHIFT 10 +#define CCM_PLL_MFI_MASK 0xf +#define CCM_PLL_MFN_SHIFT 0 +#define CCM_PLL_MFN_MASK 0x3ff +#define CCM_PLL_MFD_SHIFT 16 +#define CCM_PLL_MFD_MASK 0x3ff +#define CCM_PLL_PD_SHIFT 26 +#define CCM_PLL_PD_MASK 0xf +#define CCM_CCTL_ARM_DIV_SHIFT 30 +#define CCM_CCTL_ARM_DIV_MASK 3 +#define CCM_CCTL_AHB_DIV_SHIFT 28 +#define CCM_CCTL_AHB_DIV_MASK 3 +#define CCM_CCTL_ARM_SRC (1 << 14) +#define CCM_CGR1_GPT1 (1 << 19) +#define CCM_PERCLK_REG(clk) (clk / 4) +#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4)) +#define CCM_PERCLK_MASK 0x3f +#define CCM_RCSR_NF_16BIT_SEL (1 << 14) +#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) + +/* ESDRAM Controller register bitfields */ +#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) +#define ESDCTL_BL (1 << 7) +#define ESDCTL_FP (1 << 8) +#define ESDCTL_PWDT(x) (((x) & 3) << 10) +#define ESDCTL_SREFR(x) (((x) & 7) << 13) +#define ESDCTL_DSIZ_16_UPPER (0 << 16) +#define ESDCTL_DSIZ_16_LOWER (1 << 16) +#define ESDCTL_DSIZ_32 (2 << 16) +#define ESDCTL_COL8 (0 << 20) +#define ESDCTL_COL9 (1 << 20) +#define ESDCTL_COL10 (2 << 20) +#define ESDCTL_ROW11 (0 << 24) +#define ESDCTL_ROW12 (1 << 24) +#define ESDCTL_ROW13 (2 << 24) +#define ESDCTL_ROW14 (3 << 24) +#define ESDCTL_ROW15 (4 << 24) +#define ESDCTL_SP (1 << 27) +#define ESDCTL_SMODE_NORMAL (0 << 28) +#define ESDCTL_SMODE_PRECHARGE (1 << 28) +#define ESDCTL_SMODE_AUTO_REF (2 << 28) +#define ESDCTL_SMODE_LOAD_MODE (3 << 28) +#define ESDCTL_SMODE_MAN_REF (4 << 28) +#define ESDCTL_SDE (1 << 31) + +#define ESDCFG_TRC(x) (((x) & 0xf) << 0) +#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) +#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) +#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) +#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) +#define ESDCFG_TWR (1 << 15) +#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) +#define ESDCFG_TRP(x) (((x) & 0x3) << 18) +#define ESDCFG_TWTR (1 << 20) +#define ESDCFG_TXP(x) (((x) & 0x3) << 21) + +#define ESDMISC_RST (1 << 1) +#define ESDMISC_MDDREN (1 << 2) +#define ESDMISC_MDDR_DL_RST (1 << 3) +#define ESDMISC_MDDR_MDIS (1 << 4) +#define ESDMISC_LHD (1 << 5) +#define ESDMISC_MA10_SHARE (1 << 6) +#define ESDMISC_SDRAM_RDY (1 << 31) + +/* GPT bits */ +#define GPT_CTRL_SWR (1 << 15) /* Software reset */ +#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */ +#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */ +#define GPT_CTRL_TEN 1 /* Timer enable */ + +/* WDOG enable */ +#define WCR_WDE 0x04 + +/* FUSE bank offsets */ +#define IIM0_MAC 0x1a + +#endif /* _IMX_REGS_H */ diff --git a/include/asm-arm/arch-mx25/imx25-pinmux.h b/include/asm-arm/arch-mx25/imx25-pinmux.h new file mode 100644 index 0000000..a4c658b --- /dev/null +++ b/include/asm-arm/arch-mx25/imx25-pinmux.h @@ -0,0 +1,421 @@ +/* + * iopin settings are controlled by four different sets of registers + * iopad mux control + * individual iopad setup (voltage select, pull/keep, drive strength ...) + * group iopad setup (same as above but for groups of signals) + * input select when multiple inputs are possible + */ + +/* + * software pad mux control + */ +/* SW Input On (Loopback) */ +#define MX25_PIN_MUX_SION (1 << 4) +/* MUX Mode (0-7) */ +#define MX25_PIN_MUX_MODE(mode) ((mode & 0x7) << 0) +struct iomuxc_mux_ctl { + u32 gpr1; + u32 observe_int_mux; + u32 pad_a10; + u32 pad_a13; + u32 pad_a14; + u32 pad_a15; + u32 pad_a16; + u32 pad_a17; + u32 pad_a18; + u32 pad_a19; + u32 pad_a20; + u32 pad_a21; + u32 pad_a22; + u32 pad_a23; + u32 pad_a24; + u32 pad_a25; + u32 pad_eb0; + u32 pad_eb1; + u32 pad_oe; + u32 pad_cs0; + u32 pad_cs1; + u32 pad_cs4; + u32 pad_cs5; + u32 pad_nf_ce0; + u32 pad_ecb; + u32 pad_lba; + u32 pad_bclk; + u32 pad_rw; + u32 pad_nfwe_b; + u32 pad_nfre_b; + u32 pad_nfale; + u32 pad_nfcle; + u32 pad_nfwp_b; + u32 pad_nfrb; + u32 pad_d15; + u32 pad_d14; + u32 pad_d13; + u32 pad_d12; + u32 pad_d11; + u32 pad_d10; + u32 pad_d9; + u32 pad_d8; + u32 pad_d7; + u32 pad_d6; + u32 pad_d5; + u32 pad_d4; + u32 pad_d3; + u32 pad_d2; + u32 pad_d1; + u32 pad_d0; + u32 pad_ld0; + u32 pad_ld1; + u32 pad_ld2; + u32 pad_ld3; + u32 pad_ld4; + u32 pad_ld5; + u32 pad_ld6; + u32 pad_ld7; + u32 pad_ld8; + u32 pad_ld9; + u32 pad_ld10; + u32 pad_ld11; + u32 pad_ld12; + u32 pad_ld13; + u32 pad_ld14; + u32 pad_ld15; + u32 pad_hsync; + u32 pad_vsync; + u32 pad_lsclk; + u32 pad_oe_acd; + u32 pad_contrast; + u32 pad_pwm; + u32 pad_csi_d2; + u32 pad_csi_d3; + u32 pad_csi_d4; + u32 pad_csi_d5; + u32 pad_csi_d6; + u32 pad_csi_d7; + u32 pad_csi_d8; + u32 pad_csi_d9; + u32 pad_csi_mclk; + u32 pad_csi_vsync; + u32 pad_csi_hsync; + u32 pad_csi_pixclk; + u32 pad_i2c1_clk; + u32 pad_i2c1_dat; + u32 pad_cspi1_mosi; + u32 pad_cspi1_miso; + u32 pad_cspi1_ss0; + u32 pad_cspi1_ss1; + u32 pad_cspi1_sclk; + u32 pad_cspi1_rdy; + u32 pad_uart1_rxd; + u32 pad_uart1_txd; + u32 pad_uart1_rts; + u32 pad_uart1_cts; + u32 pad_uart2_rxd; + u32 pad_uart2_txd; + u32 pad_uart2_rts; + u32 pad_uart2_cts; + u32 pad_sd1_cmd; + u32 pad_sd1_clk; + u32 pad_sd1_data0; + u32 pad_sd1_data1; + u32 pad_sd1_data2; + u32 pad_sd1_data3; + u32 pad_kpp_row0; + u32 pad_kpp_row1; + u32 pad_kpp_row2; + u32 pad_kpp_row3; + u32 pad_kpp_col0; + u32 pad_kpp_col1; + u32 pad_kpp_col2; + u32 pad_kpp_col3; + u32 pad_fec_mdc; + u32 pad_fec_mdio; + u32 pad_fec_tdata0; + u32 pad_fec_tdata1; + u32 pad_fec_tx_en; + u32 pad_fec_rdata0; + u32 pad_fec_rdata1; + u32 pad_fec_rx_dv; + u32 pad_fec_tx_clk; + u32 pad_rtck; + u32 pad_de_b; + u32 pad_gpio_a; + u32 pad_gpio_b; + u32 pad_gpio_c; + u32 pad_gpio_d; + u32 pad_gpio_e; + u32 pad_gpio_f; + u32 pad_ext_armclk; + u32 pad_upll_bypclk; + u32 pad_vstby_req; + u32 pad_vstby_ack; + u32 pad_power_fail; + u32 pad_clko; + u32 pad_boot_mode0; + u32 pad_boot_mode1; +}; + +/* + * software pad control + */ +/* Select 3.3 or 1.8 volts */ +#define MX25_PIN_PAD_CTL_DVS_33 (0 << 13) +#define MX25_PIN_PAD_CTL_DVS_18 (1 << 13) +/* Enable hysteresis */ +#define MX25_PIN_PAD_CTL_HYS (1 << 8) +/* Enable pull/keeper */ +#define MX25_PIN_PAD_CTL_PKE (1 << 7) +/* 0 - keeper / 1 - pull */ +#define MX25_PIN_PAD_CTL_PUE (1 << 6) +/* pull up/down strength */ +#define MX25_PIN_PAD_CTL_100K_PD (0 << 4) +#define MX25_PIN_PAD_CTL_47K_PU (1 << 4) +#define MX25_PIN_PAD_CTL_100K_PU (2 << 4) +#define MX25_PIN_PAD_CTL_22K_PU (3 << 4) +/* open drain control */ +#define MX25_PIN_PAD_CTL_OD (1 << 3) +/* drive strength */ +#define MX25_PIN_PAD_CTL_DS_NOM (0 << 1) +#define MX25_PIN_PAD_CTL_DS_HIGH (1 << 1) +#define MX25_PIN_PAD_CTL_DS_MAX (2 << 1) +#define MX25_PIN_PAD_CTL_DS_MAX11 (3 << 1) +/* slew rate */ +#define MX25_PIN_PAD_CTL_SRE_SLOW (0 << 0) +#define MX25_PIN_PAD_CTL_SRE_FAST (1 << 0) +struct iomuxc_pad_ctl { + u32 pad_a13; + u32 pad_a14; + u32 pad_a15; + u32 pad_a17; + u32 pad_a18; + u32 pad_a19; + u32 pad_a20; + u32 pad_a21; + u32 pad_a23; + u32 pad_a24; + u32 pad_a25; + u32 pad_eb0; + u32 pad_eb1; + u32 pad_oe; + u32 pad_cs4; + u32 pad_cs5; + u32 pad_nf_ce0; + u32 pad_ecb; + u32 pad_lba; + u32 pad_rw; + u32 pad_nfrb; + u32 pad_d15; + u32 pad_d14; + u32 pad_d13; + u32 pad_d12; + u32 pad_d11; + u32 pad_d10; + u32 pad_d9; + u32 pad_d8; + u32 pad_d7; + u32 pad_d6; + u32 pad_d5; + u32 pad_d4; + u32 pad_d3; + u32 pad_d2; + u32 pad_d1; + u32 pad_d0; + u32 pad_ld0; + u32 pad_ld1; + u32 pad_ld2; + u32 pad_ld3; + u32 pad_ld4; + u32 pad_ld5; + u32 pad_ld6; + u32 pad_ld7; + u32 pad_ld8; + u32 pad_ld9; + u32 pad_ld10; + u32 pad_ld11; + u32 pad_ld12; + u32 pad_ld13; + u32 pad_ld14; + u32 pad_ld15; + u32 pad_hsync; + u32 pad_vsync; + u32 pad_lsclk; + u32 pad_oe_acd; + u32 pad_contrast; + u32 pad_pwm; + u32 pad_csi_d2; + u32 pad_csi_d3; + u32 pad_csi_d4; + u32 pad_csi_d5; + u32 pad_csi_d6; + u32 pad_csi_d7; + u32 pad_csi_d8; + u32 pad_csi_d9; + u32 pad_csi_mclk; + u32 pad_csi_vsync; + u32 pad_csi_hsync; + u32 pad_csi_pixclk; + u32 pad_i2c1_clk; + u32 pad_i2c1_dat; + u32 pad_cspi1_mosi; + u32 pad_cspi1_miso; + u32 pad_cspi1_ss0; + u32 pad_cspi1_ss1; + u32 pad_cspi1_sclk; + u32 pad_cspi1_rdy; + u32 pad_uart1_rxd; + u32 pad_uart1_txd; + u32 pad_uart1_rts; + u32 pad_uart1_cts; + u32 pad_uart2_rxd; + u32 pad_uart2_txd; + u32 pad_uart2_rts; + u32 pad_uart2_cts; + u32 pad_sd1_cmd; + u32 pad_sd1_clk; + u32 pad_sd1_data0; + u32 pad_sd1_data1; + u32 pad_sd1_data2; + u32 pad_sd1_data3; + u32 pad_kpp_row0; + u32 pad_kpp_row1; + u32 pad_kpp_row2; + u32 pad_kpp_row3; + u32 pad_kpp_col0; + u32 pad_kpp_col1; + u32 pad_kpp_col2; + u32 pad_kpp_col3; + u32 pad_fec_mdc; + u32 pad_fec_mdio; + u32 pad_fec_tdata0; + u32 pad_fec_tdata1; + u32 pad_fec_tx_en; + u32 pad_fec_rdata0; + u32 pad_fec_rdata1; + u32 pad_fec_rx_dv; + u32 pad_fec_tx_clk; + u32 pad_rtck; + u32 pad_tdo; + u32 pad_de_b; + u32 pad_gpio_a; + u32 pad_gpio_b; + u32 pad_gpio_c; + u32 pad_gpio_d; + u32 pad_gpio_e; + u32 pad_gpio_f; + u32 pad_vstby_req; + u32 pad_vstby_ack; + u32 pad_power_fail; + u32 pad_clko; +}; + + +/* + * Pad group drive strength and voltage select + * Same fields as iomuxc_pad_ctl plus ddr type + */ +/* Select DDR type */ +#define MX25_PIN_PAD_CTL_DDR_18 (0 << 11) +#define MX25_PIN_PAD_CTL_DDR_33 (1 << 11) +#define MX25_PIN_PAD_CTL_DDR_MAX (2 << 11) +struct iomuxc_pad_grp_ctl { + u32 grp_dvs_misc; + u32 grp_dse_fec; + u32 grp_dvs_jtag; + u32 grp_dse_nfc; + u32 grp_dse_csi; + u32 grp_dse_weim; + u32 grp_dse_ddr; + u32 grp_dvs_crm; + u32 grp_dse_kpp; + u32 grp_dse_sdhc1; + u32 grp_dse_lcd; + u32 grp_dse_uart; + u32 grp_dvs_nfc; + u32 grp_dvs_csi; + u32 grp_dse_cspi1; + u32 grp_ddrtype; + u32 grp_dvs_sdhc1; + u32 grp_dvs_lcd; +}; + +/* + * Pad input select control + * Select which pad to connect to an input port + * where multiple pads can function as given input + */ +#define MX25_PAD_INPUT_SELECT_DAISY(in) ((in & 0x7) << 0) +struct iomuxc_pad_input_select { + u32 audmux_p4_input_da_amx; + u32 audmux_p4_input_db_amx; + u32 audmux_p4_input_rxclk_amx; + u32 audmux_p4_input_rxfs_amx; + u32 audmux_p4_input_txclk_amx; + u32 audmux_p4_input_txfs_amx; + u32 audmux_p7_input_da_amx; + u32 audmux_p7_input_txfs_amx; + u32 can1_ipp_ind_canrx; + u32 can2_ipp_ind_canrx; + u32 csi_ipp_csi_d_0; + u32 csi_ipp_csi_d_1; + u32 cspi1_ipp_ind_ss3_b; + u32 cspi2_ipp_cspi_clk_in; + u32 cspi2_ipp_ind_dataready_b; + u32 cspi2_ipp_ind_miso; + u32 cspi2_ipp_ind_mosi; + u32 cspi2_ipp_ind_ss0_b; + u32 cspi2_ipp_ind_ss1_b; + u32 cspi3_ipp_cspi_clk_in; + u32 cspi3_ipp_ind_dataready_b; + u32 cspi3_ipp_ind_miso; + u32 cspi3_ipp_ind_mosi; + u32 cspi3_ipp_ind_ss0_b; + u32 cspi3_ipp_ind_ss1_b; + u32 cspi3_ipp_ind_ss2_b; + u32 cspi3_ipp_ind_ss3_b; + u32 esdhc1_ipp_dat4_in; + u32 esdhc1_ipp_dat5_in; + u32 esdhc1_ipp_dat6_in; + u32 esdhc1_ipp_dat7_in; + u32 esdhc2_ipp_card_clk_in; + u32 esdhc2_ipp_cmd_in; + u32 esdhc2_ipp_dat0_in; + u32 esdhc2_ipp_dat1_in; + u32 esdhc2_ipp_dat2_in; + u32 esdhc2_ipp_dat3_in; + u32 esdhc2_ipp_dat4_in; + u32 esdhc2_ipp_dat5_in; + u32 esdhc2_ipp_dat6_in; + u32 esdhc2_ipp_dat7_in; + u32 fec_fec_col; + u32 fec_fec_crs; + u32 fec_fec_rdata_2; + u32 fec_fec_rdata_3; + u32 fec_fec_rx_clk; + u32 fec_fec_rx_er; + u32 i2c2_ipp_scl_in; + u32 i2c2_ipp_sda_in; + u32 i2c3_ipp_scl_in; + u32 i2c3_ipp_sda_in; + u32 kpp_ipp_ind_col_4; + u32 kpp_ipp_ind_col_5; + u32 kpp_ipp_ind_col_6; + u32 kpp_ipp_ind_col_7; + u32 kpp_ipp_ind_row_4; + u32 kpp_ipp_ind_row_5; + u32 kpp_ipp_ind_row_6; + u32 kpp_ipp_ind_row_7; + u32 sim1_pin_sim_rcvd1_in; + u32 sim1_pin_sim_simpd1; + u32 sim1_sim_rcvd1_io; + u32 sim2_pin_sim_rcvd1_in; + u32 sim2_pin_sim_simpd1; + u32 sim2_sim_rcvd1_io; + u32 uart3_ipp_uart_rts_b; + u32 uart3_ipp_uart_rxd_mux; + u32 uart4_ipp_uart_rts_b; + u32 uart4_ipp_uart_rxd_mux; + u32 uart5_ipp_uart_rts_b; + u32 uart5_ipp_uart_rxd_mux; + u32 usb_top_ipp_ind_otg_usb_oc; + u32 usb_top_ipp_ind_uh2_usb_oc; +}; -- cgit v1.1 From cb17b92de03416cf4d5db5bd27ef4ae17f95e707 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Mon, 25 Jan 2010 23:12:55 -0700 Subject: fec_mxc: cleanup and factor out MX27 dependencies general cleanup move clock init to cpu_eth_init in cpu/arm926ejs/mx27/generic.c make MX27 specific phy init conditional on CONFIG_MX27 replace call to imx_get_ahbclk with one to imx_get_fecclk and define imx_get_fecclk in include/asm-arm/arch-mx27/clock.h Signed-off-by: John Rigby CC: Ben Warren CC: Fred Fan CC: Tom --- cpu/arm926ejs/mx27/generic.c | 5 +++++ drivers/net/fec_mxc.c | 15 +++++++++------ include/asm-arm/arch-mx27/clock.h | 1 + 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c index da05c55..30cf544 100644 --- a/cpu/arm926ejs/mx27/generic.c +++ b/cpu/arm926ejs/mx27/generic.c @@ -166,6 +166,11 @@ int print_cpuinfo (void) int cpu_eth_init(bd_t *bis) { #if defined(CONFIG_FEC_MXC) + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + /* enable FEC clock */ + writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1); + writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0); return fecmxc_initialize(bis); #else return 0; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 446076f..e027894 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -162,7 +162,9 @@ static int miiphy_restart_aneg(struct eth_device *dev) * Wake up from sleep if necessary * Reset PHY, then delay 300ns */ +#ifdef CONFIG_MX27 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF); +#endif miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR, PHY_BMCR_RESET); udelay(1000); @@ -363,7 +365,8 @@ static int fec_open(struct eth_device *edev) /* * Enable FEC-Lite controller */ - writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); + writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, + &fec->eth->ecntrl); miiphy_wait_aneg(edev); miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR); @@ -490,7 +493,7 @@ static void fec_halt(struct eth_device *dev) /* * issue graceful stop command to the FEC transmitter if necessary */ - writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl), + writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), &fec->eth->x_cntrl); debug("eth_halt: wait for stop regs\n"); @@ -498,7 +501,7 @@ static void fec_halt(struct eth_device *dev) * wait for graceful stop to register */ while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) - ; /* FIXME ensure time */ + udelay(1); /* * Disable SmartDMA tasks @@ -510,7 +513,7 @@ static void fec_halt(struct eth_device *dev) * Disable the Ethernet Controller * Note: this will also reset the BD index counter! */ - writel(0, &fec->eth->ecntrl); + writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); fec->rbd_index = 0; fec->tbd_index = 0; debug("eth_halt: done\n"); @@ -569,7 +572,7 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length) * wait until frame is sent . */ while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { - /* FIXME: Timeout */ + udelay(1); } debug("fec_send: status 0x%x index %d\n", readw(&fec->tbd_base[fec->tbd_index].status), @@ -688,7 +691,7 @@ static int fec_probe(bd_t *bd) fec->xcv_type = MII100; /* Reset chip. */ - writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl); + writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); while (readl(&fec->eth->ecntrl) & 1) udelay(10); diff --git a/include/asm-arm/arch-mx27/clock.h b/include/asm-arm/arch-mx27/clock.h index 472e8f2..7e9c7aa 100644 --- a/include/asm-arm/arch-mx27/clock.h +++ b/include/asm-arm/arch-mx27/clock.h @@ -37,5 +37,6 @@ ulong imx_get_perclk3(void); ulong imx_get_ahbclk(void); #define imx_get_uartclk imx_get_perclk1 +#define imx_get_fecclk imx_get_ahbclk #endif /* __ASM_ARCH_CLOCK_H */ -- cgit v1.1 From 740d6ae5b982496fcea0666b2207cb34cc0e6015 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Mon, 25 Jan 2010 23:12:57 -0700 Subject: fec_mxc: add MX25 support Use RMII for MX25 Add code to init gasket that enables RMII Signed-off-by: John Rigby CC: Ben Warren --- drivers/net/fec_mxc.c | 31 ++++++++++++++++++++++++++++++- drivers/net/fec_mxc.h | 32 ++++++++++++++++++++++++++++++-- include/asm-arm/arch-mx25/clock.h | 1 + 3 files changed, 61 insertions(+), 3 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index e027894..5af9cdb 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -367,6 +367,34 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); +#ifdef CONFIG_MX25 + udelay(100); + /* + * setup the MII gasket for RMII mode + */ + + /* disable the gasket */ + writew(0, &fec->eth->miigsk_enr); + + /* wait for the gasket to be disabled */ + while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) + udelay(2); + + /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ + writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); + + /* re-enable the gasket */ + writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); + + /* wait until MII gasket is ready */ + int max_loops = 10; + while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { + if (--max_loops <= 0) { + printf("WAIT for MII Gasket ready timed out\n"); + break; + } + } +#endif miiphy_wait_aneg(edev); miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR); @@ -513,7 +541,8 @@ static void fec_halt(struct eth_device *dev) * Disable the Ethernet Controller * Note: this will also reset the BD index counter! */ - writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); + writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, + &fec->eth->ecntrl); fec->rbd_index = 0; fec->tbd_index = 0; debug("eth_halt: done\n"); diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 6cb1bfc..5d0d69d 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -145,9 +145,17 @@ struct ethernet_regs { uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */ uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ - uint32_t res14[6]; /* MBAR_ETH + 0x2E4-2FC */ - + uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */ + +#ifdef CONFIG_MX25 + uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */ + uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ + uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */ + uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */ + uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */ +#else uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */ +#endif }; #define FEC_IEVENT_HBERR 0x80000000 @@ -196,6 +204,26 @@ struct ethernet_regs { #define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */ #define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */ +#ifdef CONFIG_MX25 +/* defines for MIIGSK */ +/* RMII frequency control: 0=50MHz, 1=5MHz */ +#define MIIGSK_CFGR_FRCONT (1 << 6) +/* loopback mode */ +#define MIIGSK_CFGR_LBMODE (1 << 4) +/* echo mode */ +#define MIIGSK_CFGR_EMODE (1 << 3) +/* MII gasket mode field */ +#define MIIGSK_CFGR_IF_MODE_MASK (3 << 0) +/* MMI/7-Wire mode */ +#define MIIGSK_CFGR_IF_MODE_MII (0 << 0) +/* RMII mode */ +#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0) +/* reflects MIIGSK Enable bit (RO) */ +#define MIIGSK_ENR_READY (1 << 2) +/* enable MIGSK (set by default) */ +#define MIIGSK_ENR_EN (1 << 1) +#endif + /** * @brief Descriptor buffer alignment * diff --git a/include/asm-arm/arch-mx25/clock.h b/include/asm-arm/arch-mx25/clock.h index b0752e7..c59f588 100644 --- a/include/asm-arm/arch-mx25/clock.h +++ b/include/asm-arm/arch-mx25/clock.h @@ -30,6 +30,7 @@ ulong imx_get_perclk(int clk); ulong imx_get_ahbclk(void); #define imx_get_uartclk() imx_get_perclk(15) +#define imx_get_fecclk() (imx_get_ahbclk()/2) #endif /* __ASM_ARCH_CLOCK_H */ -- cgit v1.1 From 6895d4510a7758595b85b48a7f449bd61dfc812f Mon Sep 17 00:00:00 2001 From: John Rigby Date: Mon, 25 Jan 2010 23:12:58 -0700 Subject: Add support for KARO TX25 board This is an i.MX25 base board with only NAND so it uses nand_spl to boot. Signed-off-by: John Rigby Tune configuration, add support for (redundant) environment in NAND. Signed-off-by: Wolfgang Denk Acked-by: Wolfgang Denk CC: Fred Fan CC: Tom --- MAINTAINERS | 4 + Makefile | 4 + board/karo/tx25/Makefile | 51 ++++++++++ board/karo/tx25/config.mk | 5 + board/karo/tx25/lowlevel_init.S | 131 ++++++++++++++++++++++++++ board/karo/tx25/tx25.c | 176 +++++++++++++++++++++++++++++++++++ include/configs/tx25.h | 179 ++++++++++++++++++++++++++++++++++++ nand_spl/board/karo/tx25/Makefile | 78 ++++++++++++++++ nand_spl/board/karo/tx25/config.mk | 1 + nand_spl/board/karo/tx25/u-boot.lds | 58 ++++++++++++ 10 files changed, 687 insertions(+) create mode 100644 board/karo/tx25/Makefile create mode 100644 board/karo/tx25/config.mk create mode 100644 board/karo/tx25/lowlevel_init.S create mode 100644 board/karo/tx25/tx25.c create mode 100644 include/configs/tx25.h create mode 100644 nand_spl/board/karo/tx25/Makefile create mode 100644 nand_spl/board/karo/tx25/config.mk create mode 100644 nand_spl/board/karo/tx25/u-boot.lds diff --git a/MAINTAINERS b/MAINTAINERS index 160f580..d6f78de 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -701,6 +701,10 @@ Tom Rix omap3_zoom2 ARM CORTEX-A8 (OMAP3xx SoC) +John Rigby + + tx25 i.MX25 + Stefan Roese ixdpg425 xscale diff --git a/Makefile b/Makefile index ca399db..bd0151f 100644 --- a/Makefile +++ b/Makefile @@ -3100,6 +3100,10 @@ trab_old_config: unconfig } @$(MKCONFIG) -a $(call xtract_trab,$@) arm arm920t trab NULL s3c24x0 +tx25_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs tx25 karo mx25 + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + VCMA9_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t vcma9 mpl s3c24x0 diff --git a/board/karo/tx25/Makefile b/board/karo/tx25/Makefile new file mode 100644 index 0000000..b0e610f --- /dev/null +++ b/board/karo/tx25/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 DENX Software Engineering +# Author: John Rigby +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := tx25.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/board/karo/tx25/config.mk b/board/karo/tx25/config.mk new file mode 100644 index 0000000..732a14a --- /dev/null +++ b/board/karo/tx25/config.mk @@ -0,0 +1,5 @@ +ifdef CONFIG_NAND_SPL +TEXT_BASE = 0x81ec0000 +else +TEXT_BASE = 0x81f00000 +endif diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S new file mode 100644 index 0000000..823df10 --- /dev/null +++ b/board/karo/tx25/lowlevel_init.S @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby + * + * Based on U-Boot and RedBoot sources for several different i.mx + * platforms. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.macro init_aips + write32 0x43f00000, 0x77777777 + write32 0x43f00004, 0x77777777 + write32 0x43f00000, 0x77777777 + write32 0x53f00004, 0x77777777 +.endm + +.macro init_max + write32 0x43f04000, 0x43210 + write32 0x43f04100, 0x43210 + write32 0x43f04200, 0x43210 + write32 0x43f04300, 0x43210 + write32 0x43f04400, 0x43210 + + write32 0x43f04010, 0x10 + write32 0x43f04110, 0x10 + write32 0x43f04210, 0x10 + write32 0x43f04310, 0x10 + write32 0x43f04410, 0x10 + + write32 0x43f04800, 0x0 + write32 0x43f04900, 0x0 + write32 0x43f04a00, 0x0 + write32 0x43f04b00, 0x0 + write32 0x43f04c00, 0x0 +.endm + +.macro init_m3if + write32 0xb8003000, 0x1 +.endm + +.macro init_clocks + /* + * clocks + * + * first enable CLKO debug output + * 0x40000000 enables the debug CLKO signal + * 0x05000000 sets CLKO divider to 6 + * 0x00600000 makes CLKO parent clk the USB clk + */ + write32 0x53f80064, 0x45600000 + write32 0x53f80008, 0x20034000 + + /* + * enable all implemented clocks in all three + * clock control registers + */ + write32 0x53f8000c, 0x1fffffff + write32 0x53f80010, 0xffffffff + write32 0x53f80014, 0xfdfff +.endm + +.macro init_ddrtype + /* + * ddr_type is 3.3v SDRAM + */ + write32 0x43fac454, 0x800 +.endm + +/* + * sdram controller init + */ +.macro init_sdram_bank bankaddr, ctl, cfg + ldr r0, =0xb8001000 + ldr r2, =\bankaddr + /* + * reset SDRAM controller + * then wait for initialization to complete + */ + ldr r1, =(1 << 1) + str r1, [r0, #0x10] +1: ldr r3, [r0, #0x10] + tst r3, #(1 << 31) + beq 1b + + ldr r1, =0x95728 + str r1, [r0, #\cfg] /* config */ + + ldr r1, =0x92116480 /* control | precharge */ + str r1, [r0, #\ctl] /* write command to controller */ + str r1, [r2, #0x400] /* command encoded in address */ + + ldr r1, =0xa2116480 /* auto refresh */ + str r1, [r0, #\ctl] + ldrb r3, [r2] /* read dram twice to auto refresh */ + ldrb r3, [r2] + + ldr r1, =0xb2116480 /* control | load mode */ + str r1, [r0, #\ctl] /* write command to controller */ + strb r1, [r2, #0x33] /* command encoded in address */ + + ldr r1, =0x82116480 /* control | normal (0)*/ + str r1, [r0, #\ctl] /* write command to controller */ +.endm + +.globl lowlevel_init +lowlevel_init: + init_aips + init_max + init_m3if + init_clocks + + init_sdram_bank 0x80000000, 0x0, 0x4 + + init_sdram_bank 0x90000000, 0x8, 0xc + mov pc, lr diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c new file mode 100644 index 0000000..4d6a96d --- /dev/null +++ b/board/karo/tx25/tx25.c @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby + * + * Based on imx27lite.c: + * Copyright (C) 2008,2009 Eric Jarrige + * Copyright (C) 2009 Ilya Yanok + * And: + * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include +#include +#include + +static void mdelay(int n) +{ + while (n-- > 0) + udelay(1000); +} + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_FEC_MXC +void tx25_fec_init(void) +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + u32 val; + u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); + struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE; + struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE; + u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode; + + debug("tx25_fec_init\n"); + /* + * fec pin init is generic + */ + mx25_fec_init_pins(); + + /* + * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. + * + * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13 + * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11 + */ + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + + writel(gpio_mux_mode, &muxctl->pad_d13); + writel(gpio_mux_mode, &muxctl->pad_d11); + + writel(0x0, &padctl->pad_d13); + writel(0x0, &padctl->pad_d11); + + /* drop PHY power and assert reset (low) */ + val = readl(&gpio4->dr) & ~((1 << 7) | (1 << 9)); + writel(val, &gpio4->dr); + val = readl(&gpio4->dir) | (1 << 7) | (1 << 9); + writel(val, &gpio4->dir); + + mdelay(5); + + debug("resetting phy\n"); + + /* turn on PHY power leaving reset asserted */ + val = readl(&gpio4->dr) | 1 << 9; + writel(val, &gpio4->dr); + + mdelay(10); + + /* + * Setup some strapping pins that are latched by the PHY + * as reset goes high. + * + * Set PHY mode to 111 + * mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5 + * mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5 + * mode2 is tied high so nothing to do + * + * Turn on RMII mode + * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode + */ + /* + * save three current mux modes and set each to gpio mode + */ + saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0); + saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1); + saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv); + + writel(gpio_mux_mode, &muxctl->pad_fec_rdata0); + writel(gpio_mux_mode, &muxctl->pad_fec_rdata1); + writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv); + + /* + * set each to 1 and make each an output + */ + val = readl(&gpio3->dr) | (1 << 10) | (1 << 11) | (1 << 12); + writel(val, &gpio3->dr); + val = readl(&gpio3->dir) | (1 << 10) | (1 << 11) | (1 << 12); + writel(val, &gpio3->dir); + + mdelay(22); /* this value came from RedBoot */ + + /* + * deassert PHY reset + */ + val = readl(&gpio4->dr) | 1 << 7; + writel(val, &gpio4->dr); + writel(val, &gpio4->dr); + + mdelay(5); + + /* + * set FEC pins back + */ + writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0); + writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1); + writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv); +} +#else +#define tx25_fec_init() +#endif + +int board_init() +{ +#ifdef CONFIG_MXC_UART + extern void mx25_uart_init_pins(void); + + mx25_uart_init_pins(); +#endif + return 0; +} + +int board_late_init(void) +{ + tx25_fec_init(); + return 0; +} + +int dram_init (void) +{ + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#if CONFIG_NR_DRAM_BANKS > 1 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); +#endif + + return 0; +} + +int checkboard(void) +{ + printf("KARO TX25\n"); + return 0; +} diff --git a/include/configs/tx25.h b/include/configs/tx25.h new file mode 100644 index 0000000..c8188ca --- /dev/null +++ b/include/configs/tx25.h @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + +/* + * KARO TX25 board - SoC Configuration + */ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_MX25 +#define CONFIG_TX25 +#define CONFIG_MX25_CLK32 32000 /* OSC32K frequency */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */ + +/* NAND BOOT is the only boot method */ +#define CONFIG_NAND_U_BOOT + +#ifdef CONFIG_NAND_SPL +/* Start copying real U-boot from the second page */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 +/* Load U-Boot to this address */ +#define CONFIG_SYS_NAND_U_BOOT_DST 0x81f00000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST + +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_SPARE_SIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#else +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT +#endif + +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Memory Info + */ +/* malloc() len */ +#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ +/* reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +/* + * Board has 2 32MB banks of DRAM but there is a bug when using + * both so only the first is configured + */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x02000000 +#if (CONFIG_NR_DRAM_BANKS == 2) +#define PHYS_SDRAM_2 0x90000000 +#define PHYS_SDRAM_2_SIZE 0x02000000 +#endif +/* 8MB DRAM test */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000) +#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */ + +/* + * Serial Info + */ +#define CONFIG_MXC_UART 1 +#define CONFIG_SYS_MX25_UART1 1 +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Flash & Environment + */ +/* No NOR flash present */ +#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN +#define CONFIG_ENV_SIZE (128 * 1024) /* 128 kB NAND block size */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) + +/* NAND */ +#define CONFIG_NAND_MXC +#define CONFIG_NAND_MXC_V1_1 +#define CONFIG_MXC_NAND_REGS_BASE (0xBB000000) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE (0xBB000000) +#define CONFIG_JFFS2_NAND +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_LARGEPAGE + +#define CONFIG_SYS_64BIT_VSPRINTF + +/* U-Boot general configuration */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Print buffer sz */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +/* U-Boot commands */ +#include +#define CONFIG_CMD_NAND + +/* + * Ethernet + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x1f +#define CONFIG_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_MULTI +#define BOARD_LATE_INIT +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttymxc0,${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ + "u-boot=tx25/u-boot.bin\0" \ + "kernel_addr_r=" xstr(CONFIG_LOADADDR) "\0" \ + "hostname=tx25\0" \ + "bootfile=tx25/uImage\0" \ + "rootpath=/opt/eldk/arm\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm\0" \ + "bootcmd=run net_nfs\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \ + "upd=run load update\0" \ + +#endif /* __CONFIG_H */ diff --git a/nand_spl/board/karo/tx25/Makefile b/nand_spl/board/karo/tx25/Makefile new file mode 100644 index 0000000..ae71f66 --- /dev/null +++ b/nand_spl/board/karo/tx25/Makefile @@ -0,0 +1,78 @@ +# +# (C) Copyright 2009 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundatio; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +CONFIG_NAND_SPL = y + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL + +SOBJS = start.o lowlevel_init.o +COBJS = nand_boot_fsl_nfc.o + +SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c +SRCS += $(SRCTREE)/cpu/arm926ejs/start.S +SRCS += $(SRCTREE)/board/karo/tx25/lowlevel_init.S +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $@ + +$(nandobj)u-boot.lds: $(LDSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + +######################################################################### + +$(obj)%.o: $(SRCTREE)/cpu/arm926ejs/%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(SRCTREE)/board/karo/tx25/%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(SRCTREE)/nand_spl/%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/karo/tx25/config.mk b/nand_spl/board/karo/tx25/config.mk new file mode 100644 index 0000000..68afbf1 --- /dev/null +++ b/nand_spl/board/karo/tx25/config.mk @@ -0,0 +1 @@ +PAD_TO := 2048 diff --git a/nand_spl/board/karo/tx25/u-boot.lds b/nand_spl/board/karo/tx25/u-boot.lds new file mode 100644 index 0000000..423bed3 --- /dev/null +++ b/nand_spl/board/karo/tx25/u-boot.lds @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + start.o (.text) + lowlevel_init.o (.text) + nand_boot_fsl_nfc.o (.text) + *(.text) + . = 2K; + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} -- cgit v1.1 From 67fa8c25f5c2d23932c0f31b035281d6abbb0965 Mon Sep 17 00:00:00 2001 From: Heiko Schocher <[hs@denx.de]> Date: Mon, 22 Feb 2010 16:43:02 +0530 Subject: arm: add support for the suen3 board from keymile Add support for the ARM part of the mgcoge2, named suen3. This board is based on the Marvell Kirkwood (88F6281) SoC. As there come more board variants, common config options are collected in include/configs/km_arm.h. Also, this board use common code for all keymile boards, which is stored in board/keymile/common/common.c Signed-off-by: Holger Brunck Signed-off-by: Stefan Roese Signed-off-by: Heiko Schocher --- MAINTAINERS | 2 +- MAKEALL | 1 + Makefile | 3 + board/keymile/common/common.c | 6 +- board/keymile/km_arm/Makefile | 51 ++++++ board/keymile/km_arm/config.mk | 28 ++++ board/keymile/km_arm/km_arm.c | 324 ++++++++++++++++++++++++++++++++++++++ board/keymile/km_arm/kwbimage.cfg | 176 +++++++++++++++++++++ include/configs/km_arm.h | 191 ++++++++++++++++++++++ include/configs/suen3.h | 103 ++++++++++++ 10 files changed, 882 insertions(+), 3 deletions(-) create mode 100644 board/keymile/km_arm/Makefile create mode 100644 board/keymile/km_arm/config.mk create mode 100644 board/keymile/km_arm/km_arm.c create mode 100644 board/keymile/km_arm/kwbimage.cfg create mode 100644 include/configs/km_arm.h create mode 100644 include/configs/suen3.h diff --git a/MAINTAINERS b/MAINTAINERS index d6f78de..0340c19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -413,9 +413,9 @@ Heiko Schocher muas3001 MPC8270 municse MPC5200 sc3 PPC405GP + suen3 ARM926EJS (Kirkwood SoC) uc101 MPC5200 - Peter De Schrijver ML2 PPC4xx diff --git a/MAKEALL b/MAKEALL index a800310..1949985 100755 --- a/MAKEALL +++ b/MAKEALL @@ -587,6 +587,7 @@ LIST_ARM9=" \ spear310 \ spear320 \ spear600 \ + suen3 \ trab \ VCMA9 \ versatile \ diff --git a/Makefile b/Makefile index bd0151f..ce77e10 100644 --- a/Makefile +++ b/Makefile @@ -3060,6 +3060,9 @@ spear320_config : unconfig spear600_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx arm arm926ejs $(@:_config=) spear spear +suen3_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs km_arm keymile kirkwood + SX1_stdout_serial_config \ SX1_config: unconfig @mkdir -p $(obj)include diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index ec27bda..7b4eefd 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -35,6 +35,7 @@ #include #endif +#include "../common/common.h" #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) #include @@ -421,7 +422,6 @@ static int get_scl (void) return ((val & SCL_BIT) == SCL_BIT); } - #endif #if !defined(CONFIG_KMETER1) @@ -500,7 +500,7 @@ void i2c_init_board(void) out_8 (&dev->cr, (I2C_CR_MEN)); #else -#if defined(CONFIG_HARD_I2C) +#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_MACH_SUEN3) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; @@ -578,10 +578,12 @@ int fdt_get_node_and_value (void *blob, } #endif +#if !defined(CONFIG_MACH_SUEN3) int ethernet_present (void) { return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80); } +#endif int board_eth_init (bd_t *bis) { diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile new file mode 100644 index 0000000..fffc6a3 --- /dev/null +++ b/board/keymile/km_arm/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o ../common/common.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/keymile/km_arm/config.mk b/board/keymile/km_arm/config.mk new file mode 100644 index 0000000..b9e81b2 --- /dev/null +++ b/board/keymile/km_arm/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +TEXT_BASE = 0x004000000 + +# Kirkwood Boot Image configuration file +KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c new file mode 100644 index 0000000..53cf474 --- /dev/null +++ b/board/keymile/km_arm/km_arm.c @@ -0,0 +1,324 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Prafulla Wadaskar + * + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/common.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int io_dev; +extern I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf); + +/* Multi-Purpose Pins Functionality configuration */ +u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_PEX_RST_OUTn, +#if defined(CONFIG_SOFT_I2C) + MPP8_GPIO, /* SDA */ + MPP9_GPIO, /* SCL */ +#endif +#if defined(CONFIG_HARD_I2C) + MPP8_TW_SDA, + MPP9_TW_SCK, +#endif + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, /* Reserved */ + MPP13_UART1_TXD, + MPP14_UART1_RXD, + MPP15_GPIO, /* Not used */ + MPP16_GPIO, /* Not used */ + MPP17_GPIO, /* Reserved */ + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, /* CDL1 (input) */ + MPP35_GPIO, /* CDL2 (input) */ + MPP36_GPIO, /* MAIN_IRQ (input) */ + MPP37_GPIO, /* BOARD_LED */ + MPP38_GPIO, /* Piggy3 LED[1] */ + MPP39_GPIO, /* Piggy3 LED[2] */ + MPP40_GPIO, /* Piggy3 LED[3] */ + MPP41_GPIO, /* Piggy3 LED[4] */ + MPP42_GPIO, /* Piggy3 LED[5] */ + MPP43_GPIO, /* Piggy3 LED[6] */ + MPP44_GPIO, /* Piggy3 LED[7] */ + MPP45_GPIO, /* Piggy3 LED[8] */ + MPP46_GPIO, /* Reserved */ + MPP47_GPIO, /* Reserved */ + MPP48_GPIO, /* Reserved */ + MPP49_GPIO, /* SW_INTOUTn */ + 0 +}; + +int ethernet_present(void) +{ + uchar buf; + int ret = 0; + + if (i2c_read(0x10, 2, 1, &buf, 1) != 0) { + printf ("%s: Error reading Boco\n", __FUNCTION__); + return -1; + } + if ((buf & 0x40) == 0x40) { + ret = 1; + } + return ret; +} + +int misc_init_r(void) +{ + I2C_MUX_DEVICE *i2cdev; + char *str; + int mach_type; + + /* add I2C Bus for I/O Expander */ + i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a"); + io_dev = i2cdev->busid; + puts("Piggy:"); + if (ethernet_present() == 0) + puts (" not"); + puts(" present\n"); + + str = getenv("mach_type"); + if (str != NULL) { + mach_type = simple_strtoul(str, NULL, 10); + printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); + gd->bd->bi_arch_number = mach_type; + } + return 0; +} + +int board_init(void) +{ + u32 tmp; + + kirkwood_mpp_conf(kwmpp_config); + + /* + * The FLASH_GPIO_PIN switches between using a + * NAND or a SPI FLASH. Set this pin on start + * to NAND mode. + */ + tmp = readl(KW_GPIO0_BASE); + writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); + tmp = readl(KW_GPIO0_BASE + 4); + writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); + printf("KM: setting NAND mode\n"); + + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_SUEN3; + + /* address of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + +#if defined(CONFIG_SOFT_I2C) + /* init the GPIO for I2C Bitbang driver */ + kw_gpio_set_valid(SUEN3_SDA_PIN, 1); + kw_gpio_set_valid(SUEN3_SCL_PIN, 1); + kw_gpio_direction_output(SUEN3_SDA_PIN, 0); + kw_gpio_direction_output(SUEN3_SCL_PIN, 0); +#endif +#if defined(CONFIG_SYS_EEPROM_WREN) + kw_gpio_set_valid(SUEN3_ENV_WP, 38); + kw_gpio_direction_output(SUEN3_ENV_WP, 1); +#endif + return 0; +} + +#if defined(CONFIG_CMD_SF) +int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u32 tmp; + if (argc < 2) { + cmd_usage(cmdtp); + return 1; + } + + if ((strcmp(argv[1], "off") == 0)) { + printf("SPI FLASH disabled, NAND enabled\n"); + /* Multi-Purpose Pins Functionality configuration */ + kwmpp_config[0] = MPP0_NF_IO2; + kwmpp_config[1] = MPP1_NF_IO3; + kwmpp_config[2] = MPP2_NF_IO4; + kwmpp_config[3] = MPP3_NF_IO5; + + kirkwood_mpp_conf(kwmpp_config); + tmp = readl(KW_GPIO0_BASE); + writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); + } else if ((strcmp(argv[1], "on") == 0)) { + printf("SPI FLASH enabled, NAND disabled\n"); + /* Multi-Purpose Pins Functionality configuration */ + kwmpp_config[0] = MPP0_SPI_SCn; + kwmpp_config[1] = MPP1_SPI_MOSI; + kwmpp_config[2] = MPP2_SPI_SCK; + kwmpp_config[3] = MPP3_SPI_MISO; + + kirkwood_mpp_conf(kwmpp_config); + tmp = readl(KW_GPIO0_BASE); + writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE); + } else { + cmd_usage(cmdtp); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + spitoggle, 2, 0, do_spi_toggle, + "En-/disable SPI FLASH access", + " - Enable (on) or disable (off) SPI FLASH access\n" + ); +#endif + +int dram_init(void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = kw_sdram_bar(i); + gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), + kw_sdram_bs(i)); + } + return 0; +} + +/* Configure and enable MV88E1118 PHY */ +void reset_phy(void) +{ + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* reset the phy */ + miiphy_reset(name, CONFIG_PHY_BASE_ADR); +} + +#if defined(CONFIG_HUSH_INIT_VAR) +int hush_init_var (void) +{ + ivm_read_eeprom (); + return 0; +} +#endif + +#if defined(CONFIG_BOOTCOUNT_LIMIT) +void bootcount_store (ulong a) +{ + volatile ulong *save_addr; + volatile ulong size = 0; + int i; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + size += gd->bd->bi_dram[i].size; + } + save_addr = (ulong*)(size - BOOTCOUNT_ADDR); + writel(a, save_addr); + writel(BOOTCOUNT_MAGIC, &save_addr[1]); +} + +ulong bootcount_load (void) +{ + volatile ulong *save_addr; + volatile ulong size = 0; + int i; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + size += gd->bd->bi_dram[i].size; + } + save_addr = (ulong*)(size - BOOTCOUNT_ADDR); + if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC) + return 0; + else + return readl(save_addr); +} +#endif + +#if defined(CONFIG_SOFT_I2C) +void set_sda (int state) +{ + I2C_ACTIVE; + I2C_SDA(state); +} + +void set_scl (int state) +{ + I2C_SCL(state); +} + +int get_sda (void) +{ + I2C_TRISTATE; + return I2C_READ; +} + +int get_scl (void) +{ + return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0); +} +#endif + +#if defined(CONFIG_SYS_EEPROM_WREN) +int eeprom_write_enable (unsigned dev_addr, int state) +{ + kw_gpio_set_value(SUEN3_ENV_WP, !state); + + return !kw_gpio_get_value(SUEN3_ENV_WP); +} +#endif diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg new file mode 100644 index 0000000..d6edd27 --- /dev/null +++ b/board/keymile/km_arm/kwbimage.cfg @@ -0,0 +1,176 @@ +# +# (C) Copyright 2010 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD10000 0x01111111 # MPP Control 0 Register +# bit 3-0: MPPSel0 1, NF_IO[2] +# bit 7-4: MPPSel1 1, NF_IO[3] +# bit 12-8: MPPSel2 1, NF_IO[4] +# bit 15-12: MPPSel3 1, NF_IO[5] +# bit 19-16: MPPSel4 1, NF_IO[6] +# bit 23-20: MPPSel5 1, NF_IO[7] +# bit 27-24: MPPSel6 1, SYSRST_O +# bit 31-28: MPPSel7 0, GPO[7] + +DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: MPPSel16 0, GPIO[16] +# bit 7-4: MPPSel17 0, GPIO[17] +# bit 12-8: MPPSel18 1, NF_IO[0] +# bit 15-12: MPPSel19 1, NF_IO[1] +# bit 19-16: MPPSel20 0, GPIO[20] +# bit 23-20: MPPSel21 0, GPIO[21] +# bit 27-24: MPPSel22 0, GPIO[22] +# bit 31-28: MPPSel23 0, GPIO[23] + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +DATA 0xFFD20134 0xBBBBBBBB # L2 RAM Timing 0 Register +DATA 0xFFD20138 0x00BBBBBB # L2 RAM Timing 1 Register +DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register + +#Dram initalization +DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register +# bit13-0: 0x400 (DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x36343000 # DDR Controller Control Low + 0x38543000 +# bit 3-0: 0 reserved +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x2302544B # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000032 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000000D # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000642 # DDR Mode +DATA 0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 1, DDR ODT control lsd disabled +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, enabled +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 0 , no sample stage +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00000000 # DDR ODT Control (Low) +# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 00, ODT1 controlled by register +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E90F # CPU ODT Control +# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0 +# bit9-8: 1, ODTEn, never active +# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h new file mode 100644 index 0000000..a928c2c --- /dev/null +++ b/include/configs/km_arm.h @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Prafulla Wadaskar + * + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* for linking errors see http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ + +#ifndef _CONFIG_KM_ARM_H +#define _CONFIG_KM_ARM_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_MARVELL +#define CONFIG_ARM926EJS /* Basic Architecture */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_MACH_SUEN3 /* Machine type */ + +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" +#undef CONFIG_CMD_DTT +#undef CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#undef CONFIG_KIRKWOOD_PCIE_INIT /* Disable PCIE Port0 for kernel */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ + +#define CONFIG_MISC_INIT_R + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /* Console on UART0 */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_BOOTMAPSZ (8 << 20) /* Initial Memmap for Linux */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ + +/* + * Commands configuration + */ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NFS + +/* + * Without NOR FLASH we need this + */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS + +/* + * NAND Flash configuration + */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_NAND_KIRKWOOD +#define CONFIG_SYS_NAND_BASE 0xd8000000 + +#define BOOTFLASH_START 0x0 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ + +/* + * Ethernet Driver configuration + */ +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */ + +/* + * UBI related stuff + */ +#define CONFIG_SYS_USE_UBI + +/* + * I2C related stuff + */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ + +#if defined(CONFIG_HARD_I2C) +#define CONFIG_I2C_KIRKWOOD +#define CONFIG_I2C_KW_REG_BASE KW_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ +#if defined(CONFIG_SOFT_I2C) +#ifndef __ASSEMBLY__ +#include +extern void __set_direction(unsigned pin, int high); +void set_sda (int state); +void set_scl (int state); +int get_sda (void); +int get_scl (void); +#define SUEN3_SDA_PIN 8 +#define SUEN3_SCL_PIN 9 +#define SUEN3_ENV_WP 38 + +#define I2C_ACTIVE __set_direction(SUEN3_SDA_PIN, 0) +#define I2C_TRISTATE __set_direction(SUEN3_SDA_PIN, 1) +#define I2C_READ (kw_gpio_get_value(SUEN3_SDA_PIN) ? 1 : 0) +#define I2C_SDA(bit) kw_gpio_set_value(SUEN3_SDA_PIN, bit); +#define I2C_SCL(bit) kw_gpio_set_value(SUEN3_SCL_PIN, bit); +#endif + +#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ +#define I2C_SOFT_DECLARATIONS + +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +#if defined(CONFIG_SYS_NO_FLASH) +#define CONFIG_KM_UBI_PARTITION_NAME "ubi0" +#undef CONFIG_FLASH_CFI_MTD +#undef CONFIG_JFFS2_CMDLINE +#endif + +#endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/suen3.h b/include/configs/suen3.h new file mode 100644 index 0000000..b2730a3 --- /dev/null +++ b/include/configs/suen3.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Prafulla Wadaskar + * + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html + */ + +#ifndef _CONFIG_SUEN3_H +#define _CONFIG_SUEN3_H + +/* include common defines/options for all arm based Keymile boards */ +#include "km_arm.h" + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nKeymile SUEN3" + +#define CONFIG_HOSTNAME suen3 + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ +#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 +#define CONFIG_ENV_EEPROM_IS_ON_I2C 1 +#define CONFIG_SYS_EEPROM_WREN 1 +#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) +#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0" + +/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#define CONFIG_CMD_SF + +#define CONFIG_SPI_FLASH +#define CONFIG_HARD_SPI +#define CONFIG_KIRKWOOD_SPI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */ + +#define FLASH_GPIO_PIN 0x00010000 + +#define MTDIDS_DEFAULT "nand0=orion_nand" +/* test-only: partitioning needs some tuning, this is just for tests */ +#define MTDPARTS_DEFAULT "mtdparts=" \ + "orion_nand:" \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")" + +#define CONFIG_KM_DEF_ENV_UPDATE \ + "update=" \ + "spi on;sf probe 0;sf erase 0 50000;" \ + "sf write ${u-boot_addr_r} 0 ${filesize};" \ + "spi off\0" + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + "memsize=0x8000000\0" \ + "newenv=setenv addr 0x100000 && " \ + "i2c dev 1; mw.b ${addr} 0 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ + "rootpath=/opt/eldk/arm\0" \ + "EEprom_ivm=pca9544a:70:9\0" \ + "" + +#endif /* _CONFIG_SUEN3_H */ -- cgit v1.1 From cc0b53c8d5d6a3f14f36982552bc3feb8ecb1db5 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 1 Mar 2010 15:58:18 +0100 Subject: arm, suen3: fix compile error, if doing not a local build Signed-off-by: Heiko Schocher --- board/keymile/km_arm/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile index fffc6a3..c5b0be1 100644 --- a/board/keymile/km_arm/Makefile +++ b/board/keymile/km_arm/Makefile @@ -23,6 +23,9 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).a -- cgit v1.1 From 9d69e33d8d0f112fe3a089101d023e87431684d1 Mon Sep 17 00:00:00 2001 From: Vipin Kumar Date: Tue, 2 Mar 2010 10:46:52 +0530 Subject: SPEAr : Supporting new mach ids for spear310 and spear320 Supporting new machine ids for SoCs spear310 and spear320 include/asm-arm/mach-types.h has to be updated before applying this patch for build to work Signed-off-by: Vipin Kumar --- board/spear/spear310/spear310.c | 2 +- board/spear/spear320/spear320.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 756aa56..03dfe16 100755 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -32,7 +32,7 @@ int board_init(void) { - return spear_board_init(MACH_TYPE_SPEAR300); + return spear_board_init(MACH_TYPE_SPEAR310); } /* diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 756aa56..2ba2dbb 100755 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -32,7 +32,7 @@ int board_init(void) { - return spear_board_init(MACH_TYPE_SPEAR300); + return spear_board_init(MACH_TYPE_SPEAR320); } /* -- cgit v1.1 From e4d34492017c95e4041ea0c581e1ab8d1d49381b Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 5 Mar 2010 17:54:37 +0100 Subject: MX51: removed warnings for the mx51evk The patch removes warnings at compile time and provides some cleanup code: - Removed comment on NAND (not yet supported) from lowlevel_init.S - Removed NFMS bit definition from imx-regs.h The bit is only related to MX.25/35 and can lead to confusion - Moved is_soc_rev() to soc specific code (removed from mx51evk.c) Signed-off-by: Stefano Babic --- board/freescale/mx51evk/mx51evk.c | 11 +---------- cpu/arm_cortexa8/mx51/clock.c | 3 ++- cpu/arm_cortexa8/mx51/iomux.c | 1 + cpu/arm_cortexa8/mx51/lowlevel_init.S | 1 - cpu/arm_cortexa8/mx51/soc.c | 7 ++++++- cpu/arm_cortexa8/mx51/speed.c | 1 + include/asm-arm/arch-mx51/clock.h | 16 ++++++++++++++-- include/asm-arm/arch-mx51/imx-regs.h | 21 --------------------- include/asm-arm/arch-mx51/sys_proto.h | 30 ++++++++++++++++++++++++++++++ 9 files changed, 55 insertions(+), 36 deletions(-) create mode 100644 include/asm-arm/arch-mx51/sys_proto.h diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index df0e8ed..af1b0bd 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -48,16 +49,6 @@ u32 get_board_rev(void) return system_rev; } -static inline void set_board_rev(int rev) -{ - system_rev |= (rev & 0xF) << 8; -} - -inline int is_soc_rev(int rev) -{ - return (system_rev & 0xFF) - rev; -} - int dram_init(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; diff --git a/cpu/arm_cortexa8/mx51/clock.c b/cpu/arm_cortexa8/mx51/clock.c index 3c6f0c0..38480ac 100644 --- a/cpu/arm_cortexa8/mx51/clock.c +++ b/cpu/arm_cortexa8/mx51/clock.c @@ -28,6 +28,7 @@ #include #include #include +#include enum pll_clocks { PLL1_CLOCK = 0, @@ -42,7 +43,7 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR, }; -struct mxc_ccm_reg *mxc_ccm = MXC_CCM_BASE; +struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; /* * Calculate the frequency of this pll. diff --git a/cpu/arm_cortexa8/mx51/iomux.c b/cpu/arm_cortexa8/mx51/iomux.c index fc39e8a..62b2954 100644 --- a/cpu/arm_cortexa8/mx51/iomux.c +++ b/cpu/arm_cortexa8/mx51/iomux.c @@ -25,6 +25,7 @@ #include #include #include +#include /* IOMUX register (base) addresses */ enum iomux_reg_addr { diff --git a/cpu/arm_cortexa8/mx51/lowlevel_init.S b/cpu/arm_cortexa8/mx51/lowlevel_init.S index 680a90e..700506e 100644 --- a/cpu/arm_cortexa8/mx51/lowlevel_init.S +++ b/cpu/arm_cortexa8/mx51/lowlevel_init.S @@ -276,7 +276,6 @@ lowlevel_init: init_clock - /* return from mxc_nand_load */ /* r12 saved upper lr*/ mov pc,lr diff --git a/cpu/arm_cortexa8/mx51/soc.c b/cpu/arm_cortexa8/mx51/soc.c index 5e69301..2a139b2 100644 --- a/cpu/arm_cortexa8/mx51/soc.c +++ b/cpu/arm_cortexa8/mx51/soc.c @@ -25,9 +25,14 @@ #include #include +#include #include #include +#ifdef CONFIG_FSL_ESDHC +#include +#endif + u32 get_cpu_rev(void) { int reg; @@ -65,7 +70,7 @@ int print_cpuinfo(void) printf("CPU: Freescale i.MX51 family %d.%dV at %d MHz\n", (cpurev & 0xF0) >> 4, (cpurev & 0x0F) >> 4, - get_mcu_main_clk() / 1000000); + mxc_get_clock(MXC_ARM_CLK) / 1000000); return 0; } #endif diff --git a/cpu/arm_cortexa8/mx51/speed.c b/cpu/arm_cortexa8/mx51/speed.c index 10acbbf..a444def 100644 --- a/cpu/arm_cortexa8/mx51/speed.c +++ b/cpu/arm_cortexa8/mx51/speed.c @@ -26,6 +26,7 @@ #include #include +#include int get_clocks(void) { diff --git a/include/asm-arm/arch-mx51/clock.h b/include/asm-arm/arch-mx51/clock.h index 449a191..1f8a537 100644 --- a/include/asm-arm/arch-mx51/clock.h +++ b/include/asm-arm/arch-mx51/clock.h @@ -23,9 +23,21 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_FEC_CLK, +}; + unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); -ulong imx_get_uartclk(void); -ulong imx_get_fecclk(void); +u32 imx_get_uartclk(void); +u32 imx_get_fecclk(void); +unsigned int mxc_get_clock(enum mxc_clock clk); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/include/asm-arm/arch-mx51/imx-regs.h b/include/asm-arm/arch-mx51/imx-regs.h index 927eda3..3887d3c 100644 --- a/include/asm-arm/arch-mx51/imx-regs.h +++ b/include/asm-arm/arch-mx51/imx-regs.h @@ -209,16 +209,6 @@ #ifndef __ASSEMBLY__ -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_UART_CLK, - MXC_CSPI_CLK, - MXC_FEC_CLK, -}; - struct clkctl { u32 ccr; u32 ccdr; @@ -266,17 +256,6 @@ struct weim { u32 cswcr2; }; -/*! - * NFMS bit in RCSR register for pagesize of nandflash - */ -#define NFMS (*((volatile u32 *)(CCM_BASE_ADDR+0x18))) -#define NFMS_BIT 8 -#define NFMS_NF_DWIDTH 14 -#define NFMS_NF_PG_SZ 8 - -extern unsigned int get_board_rev(void); -extern int is_soc_rev(int rev); - #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MXC_MX51_H__ */ diff --git a/include/asm-arm/arch-mx51/sys_proto.h b/include/asm-arm/arch-mx51/sys_proto.h new file mode 100644 index 0000000..bf500a8 --- /dev/null +++ b/include/asm-arm/arch-mx51/sys_proto.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +u32 get_cpu_rev(void); +#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) + +#endif -- cgit v1.1 From 637833c2d669f9a370706e275e7103454c3c83ec Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Wed, 3 Mar 2010 15:27:37 +0530 Subject: arm: kirkwood: suen3: fixed build warning This patch fixes following build warning Invalid Kwbimage command Type - valid names are: BOOT_FROM, NAND_ECC_MODE, NAND_PAGE_SIZE, SATA_PIO_MODE, DDR_INIT_DELAY, DATA, , spi, nand, sata, pex, uart Signed-off-by: Prafulla Wadaskar --- board/keymile/km_arm/kwbimage.cfg | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg index d6edd27..26d6aa0 100644 --- a/board/keymile/km_arm/kwbimage.cfg +++ b/board/keymile/km_arm/kwbimage.cfg @@ -64,7 +64,6 @@ DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register # bit31-30: 01 DATA 0xFFD01404 0x36343000 # DDR Controller Control Low - 0x38543000 # bit 3-0: 0 reserved # bit 4: 0=addr/cmd in smame cycle # bit 5: 0=clk is driven during self refresh, we don't care for APX @@ -170,7 +169,7 @@ DATA 0xFFD0149C 0x0000E90F # CPU ODT Control # bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write +# bit0=1, enable DDR init upon this register write # End of Header extension DATA 0x0 0x0 -- cgit v1.1 From 7cedb29872069e782f9f97cef4ab1232736e4c85 Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Sun, 14 Feb 2010 12:20:43 +0100 Subject: updates the at91 main_clock calculation * updates the conditional main_clock calculation (if AT91_MAIN_CLOCK defined) to c structure SoC access * add need register flags Signed-off-by: Jens Scharsig --- cpu/arm926ejs/at91/clock.c | 7 ++++--- include/asm-arm/arch-at91/at91_pmc.h | 3 +++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c index 444d42d..b06d760 100644 --- a/cpu/arm926ejs/at91/clock.c +++ b/cpu/arm926ejs/at91/clock.c @@ -157,9 +157,10 @@ int at91_clock_init(unsigned long main_clock) */ if (!main_clock) { do { - tmp = at91_sys_read(AT91_CKGR_MCFR); - } while (!(tmp & AT91_PMC_MAINRDY)); - main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + tmp = readl(&pmc->mcfr); + } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); + tmp &= AT91_PMC_MCFR_MAINF_MASK; + main_clock = tmp * (AT91_SLOW_CLOCK / 16); } #endif main_clk_rate_hz = main_clock; diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index 369b5d7..680fe33 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -71,6 +71,9 @@ typedef struct at91_pmc { #define AT91_PMC_PLLBR_USBDIV_2 0x10000000 #define AT91_PMC_PLLBR_USBDIV_4 0x20000000 +#define AT91_PMC_MCFR_MAINRDY 0x00010000 +#define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF + #define AT91_PMC_MCKR_CSS_SLOW 0x00000000 #define AT91_PMC_MCKR_CSS_MAIN 0x00000001 #define AT91_PMC_MCKR_CSS_PLLA 0x00000002 -- cgit v1.1 From 6258b04e9a41ee60f21547358a58fbcb9087735d Mon Sep 17 00:00:00 2001 From: Daniel Gorsulowski Date: Thu, 11 Feb 2010 14:57:04 +0100 Subject: AT91: Update otc570 board to new SoC access * convert otc570 board to use c stucture SoC access * change gpio access to at91_gpio syntax Signed-off-by: Daniel Gorsulowski --- board/esd/otc570/otc570.c | 180 ++++++++++++++++++++++++---------------------- include/configs/otc570.h | 25 ++++--- 2 files changed, 107 insertions(+), 98 deletions(-) diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c index 3fe28cb..07d9c62 100644 --- a/board/esd/otc570/otc570.c +++ b/board/esd/otc570/otc570.c @@ -28,13 +28,13 @@ #include #include -#include #include #include #include #include +#include +#include #include -#include #include #include #include @@ -58,10 +58,10 @@ int get_hw_rev(void) if (hw_rev >= 0) return hw_rev; - hw_rev = at91_get_gpio_value(AT91_PIN_PB19); - hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1; - hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2; - hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3; + hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19); + hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1; + hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2; + hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3; if (hw_rev == 15) hw_rev = 0; @@ -73,40 +73,44 @@ int get_hw_rev(void) static void otc570_nand_hw_init(void) { unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBI0CSA); - at91_sys_write(AT91_MATRIX_EBI0CSA, - csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_DBW_8 | - AT91_SMC_TDF_(2)); + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif /* CONFIG_CMD_NAND */ #ifdef CONFIG_MACB static void otc570_macb_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); at91_macb_hw_init(); } #endif @@ -119,26 +123,27 @@ static void otc570_macb_hw_init(void) */ static void otc570_ethercat_hw_init(void) { + at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE; + /* Configure SMC EBI1_CS0 for EtherCAT */ - at91_sys_write(AT91_SMC1_SETUP(0), - AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC1_PULSE(0), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) | - AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(9)); - at91_sys_write(AT91_SMC1_CYCLE(0), - AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(6)); + writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), + &smc1->cs[0].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) | + AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9), + &smc1->cs[0].pulse); + writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6), + &smc1->cs[0].cycle); /* * Configure behavior at external wait signal, byte-select mode, 16 bit * data bus width, none data float wait states and TDF optimization */ - at91_sys_write(AT91_SMC1_MODE(0), - AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY | - AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) | - AT91_SMC_TDFMODE); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY | + AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) | + AT91_SMC_MODE_TDF, &smc1->cs[0].mode); /* Configure RDY/BSY */ - at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */ + at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */ } #ifdef CONFIG_LCD @@ -164,43 +169,44 @@ vidinfo_t panel_info = { void lcd_enable(void) { - at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ + at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */ } void lcd_disable(void) { - at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ + at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */ } static void otc570_lcd_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */ - at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ - at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ - at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ - at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ - at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ - at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ - at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ - at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ - at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ - at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ - at91_set_gpio_output(AT91_PIN_PA30, 1); /* PCI */ - - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC); - + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ + at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ + at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ + at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ + at91_set_pio_output(AT91_PIO_PORTA, 30, 1); /* PCI */ + + writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer); gd->fb_base = CONFIG_OTC570_LCD_BASE; } @@ -242,7 +248,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00); #endif return rc; } @@ -290,32 +296,33 @@ u32 get_board_rev(void) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { - char str[64]; + char str[64]; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_set_gpio_output(AT91_PIN_PA29, 1); - at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0); + at91_set_pio_output(AT91_PIO_PORTA, 29, 1); + at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */ + writel(1 << AT91SAM9263_ID_US0, &pmc->pcer); /* Set USART_MODE = 1 (RS485) */ - at91_sys_write((0xFFF8C004 - AT91_BASE_SYS), 1); + writel(1, 0xFFF8C004); printf("USART0: "); if (getenv_r("usart0", str, sizeof(str)) == -1) { printf("No entry - assuming 1-wire\n"); /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */ - at91_set_gpio_output(AT91_PIN_PA29, 0); + at91_set_pio_output(AT91_PIO_PORTA, 29, 0); } else { if (strcmp(str, "1-wire") == 0) { printf("%s\n", str); - at91_set_gpio_output(AT91_PIN_PA29, 0); + at91_set_pio_output(AT91_PIO_PORTA, 29, 0); } else if (strcmp(str, "rs485") == 0) { printf("%s\n", str); - at91_set_gpio_output(AT91_PIN_PA29, 1); + at91_set_pio_output(AT91_PIO_PORTA, 29, 1); } else { printf("Wrong entry - assuming 1-wire "); printf("(valid values are '1-wire' or 'rs485')\n"); - at91_set_gpio_output(AT91_PIN_PA29, 0); + at91_set_pio_output(AT91_PIO_PORTA, 29, 0); } } printf("Display memory address: 0x%08lX\n", gd->fb_base); @@ -326,14 +333,17 @@ int misc_init_r(void) int board_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Peripheral Clock Enable Register */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | - 1 << AT91SAM9263_ID_PIOB | - 1 << AT91SAM9263_ID_PIOCDE | - 1 << AT91SAM9263_ID_TWI | - 1 << AT91SAM9263_ID_SPI0 | - 1 << AT91SAM9263_ID_LCDC | - 1 << AT91SAM9263_ID_UHP); + writel( 1 << AT91SAM9263_ID_PIOA | + 1 << AT91SAM9263_ID_PIOB | + 1 << AT91SAM9263_ID_PIOCDE | + 1 << AT91SAM9263_ID_TWI | + 1 << AT91SAM9263_ID_SPI0 | + 1 << AT91SAM9263_ID_LCDC | + 1 << AT91SAM9263_ID_UHP, + &pmc->pcer); /* arch number of OTC570-Board */ gd->bd->bi_arch_number = MACH_TYPE_OTC570; diff --git a/include/configs/otc570.h b/include/configs/otc570.h index bedaf13..8e27eba 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -55,6 +55,7 @@ /* * Hardware drivers */ +#define CONFIG_AT91_GPIO 1 /* Console output */ #define CONFIG_ATMEL_USART 1 @@ -96,24 +97,22 @@ #ifdef CONFIG_SOFT_I2C #define CONFIG_I2C_CMD_TREE 1 #define CONFIG_I2C_MULTI_BUS 1 -/* Enable peripheral clock and configure data and clock pins for pio */ +/* Configure data and clock pins for pio */ #define I2C_INIT { \ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB | \ - 1 << AT91SAM9263_ID_PIOCDE); \ - at91_set_gpio_output(AT91_PIN_PB4, 0); \ - at91_set_gpio_output(AT91_PIN_PB5, 0); \ + at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \ + at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \ } /* Configure data pin as output */ -#define I2C_ACTIVE at91_set_gpio_output(AT91_PIN_PB4, 0) +#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTB, 4, 0) /* Configure data pin as input */ -#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PB4, 0) +#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTB, 4, 0) /* Read data pin */ -#define I2C_READ at91_get_gpio_value(AT91_PIN_PB4) +#define I2C_READ at91_get_pio_value(AT91_PIO_PORTB, 4) /* Set data pin */ -#define I2C_SDA(bit) at91_set_gpio_value(AT91_PIN_PB4, bit) +#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTB, 4, bit) /* Set clock pin */ -#define I2C_SCL(bit) at91_set_gpio_value(AT91_PIN_PB5, bit) -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTB, 5, bit) +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ #endif /* CONFIG_SOFT_I2C */ #define CONFIG_BOOTDELAY 3 @@ -173,8 +172,8 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif -- cgit v1.1 From bdc6b47a1ae3259ac2b35412940fb3caa0d863e3 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Mon, 8 Mar 2010 10:46:07 +0530 Subject: SPEAr : Adding maintainer name for spear SoCs Signed-off-by: Vipin Kumar --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0340c19..56c597e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -643,6 +643,13 @@ Prakash Kumar cerf250 xscale +Vipin Kumar + + spear300 ARM926EJS (spear300 Soc) + spear310 ARM926EJS (spear310 Soc) + spear320 ARM926EJS (spear320 Soc) + spear600 ARM926EJS (spear600 Soc) + Sergey Lapin afeb9260 ARM926EJS (AT91SAM9260 SoC) -- cgit v1.1 From 6d5ef5335a5eff8f925d4f9bf946757744287d00 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Mon, 8 Mar 2010 16:22:33 +0900 Subject: MAINTAINERS: sort the list of ARM Maintainers by last name Signed-off-by: Minkyu Kang --- MAINTAINERS | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 56c597e..7f40ebd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -618,6 +618,10 @@ Simon Kagstrom openrd_base ARM926EJS (Kirkwood SoC) +Minkyu Kang + + SMDKC100 ARM CORTEX-A8 (S5PC100 SoC) + Nishant Kamat omap1610h2 ARM926EJS @@ -632,13 +636,6 @@ Sergey Kubushyn SONATA ARM926EJS SCHMOOGIE ARM926EJS -Sandeep Paulraj - - davinci_dm355evm ARM926EJS - davinci_dm355leopard ARM926EJS - davinci_dm365evm ARM926EJS - davinci_dm6467evm ARM926EJS - Prakash Kumar cerf250 xscale @@ -682,6 +679,13 @@ Kyungmin Park apollon ARM1136EJS +Sandeep Paulraj + + davinci_dm355evm ARM926EJS + davinci_dm355leopard ARM926EJS + davinci_dm365evm ARM926EJS + davinci_dm6467evm ARM926EJS + Peter Pearse integratorcp All current ARM supplied & supported core modules -see http://www.arm.com/products/DevTools/Hardware_Platforms.html @@ -782,10 +786,6 @@ Alex Z lart SA1100 dnp1110 SA1110 -Minkyu Kang - - SMDKC100 ARM CORTEX-A8 (S5PC100 SoC) - ------------------------------------------------------------------------- Unknown / orphaned boards: -- cgit v1.1 From 0468afff3097c09f7f462591cf0edb8b3519892f Mon Sep 17 00:00:00 2001 From: Naveen Krishna CH Date: Thu, 4 Feb 2010 14:17:38 +0900 Subject: S5PC100: Moves the Macros to a common header file The get_pll_clk(int) API returns the PLL frequency based on the (int) argument which is defined locally in clock.c Moving that #define to common header file (clk.h) would be helpful when using the API from other files. Signed-off-by: Naveen Krishna Ch Signed-off-by: Minkyu Kang --- cpu/arm_cortexa8/s5pc1xx/clock.c | 7 +------ include/asm-arm/arch-s5pc1xx/clk.h | 6 ++++++ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/cpu/arm_cortexa8/s5pc1xx/clock.c index a9e78dd..19619f9 100644 --- a/cpu/arm_cortexa8/s5pc1xx/clock.c +++ b/cpu/arm_cortexa8/s5pc1xx/clock.c @@ -25,12 +25,7 @@ #include #include #include - -#define APLL 0 -#define MPLL 1 -#define EPLL 2 -#define HPLL 3 -#define VPLL 4 +#include #define CLK_M 0 #define CLK_D 1 diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/include/asm-arm/arch-s5pc1xx/clk.h index f1aa44f..3e59abe 100644 --- a/include/asm-arm/arch-s5pc1xx/clk.h +++ b/include/asm-arm/arch-s5pc1xx/clk.h @@ -23,6 +23,12 @@ #ifndef __ASM_ARM_ARCH_CLK_H_ #define __ASM_ARM_ARCH_CLK_H_ +#define APLL 0 +#define MPLL 1 +#define EPLL 2 +#define HPLL 3 +#define VPLL 4 + void s5pc1xx_clock_init(void); extern unsigned long (*get_pll_clk)(int pllreg); -- cgit v1.1 From 803472beb7513a9dac6f105fad4d4d008f2f07c3 Mon Sep 17 00:00:00 2001 From: Joonyoung Shim Date: Mon, 8 Feb 2010 22:00:52 +0900 Subject: s3c64xx: Add ifdef at the S3C64XX only codes The s3c6400.h file is only for S3C64XX cpu and the pheripheral port address(0x70000000 - 0x7fffffff) exists at only S3C64XX cpu, so they should be included by only S3C64XX cpu. Signed-off-by: Joonyoung Shim Signed-off-by: Minkyu Kang --- cpu/arm1176/cpu.c | 2 ++ cpu/arm1176/start.S | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c index 2c0014f..befa0cd 100644 --- a/cpu/arm1176/cpu.c +++ b/cpu/arm1176/cpu.c @@ -33,7 +33,9 @@ #include #include +#ifdef CONFIG_S3C64XX #include +#endif #include static void cache_flush (void); diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S index 68a356d..e2b6c9b 100644 --- a/cpu/arm1176/start.S +++ b/cpu/arm1176/start.S @@ -35,7 +35,9 @@ #ifdef CONFIG_ENABLE_MMU #include #endif +#ifdef CONFIG_S3C64XX #include +#endif #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE @@ -190,10 +192,12 @@ mmu_disable: #endif mmu_disable_phys: +#ifdef CONFIG_S3C64XX /* Peri port setup */ ldr r0, =0x70000000 orr r0, r0, #0x13 mcr p15,0,r0,c15,c2,4 @ 256M (0x70000000 - 0x7fffffff) +#endif /* * Go setup Memory and board specific bits prior to relocation. -- cgit v1.1 From 2c1ad699e53a19964794e97713b7f2f8cdc4f4cb Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Fri, 12 Feb 2010 18:17:52 +0900 Subject: s5pc1xx: support the GPIO interface This patch adds support the GPIO interface Signed-off-by: Minkyu Kang --- cpu/arm_cortexa8/s5pc1xx/Makefile | 1 + cpu/arm_cortexa8/s5pc1xx/gpio.c | 143 ++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-s5pc1xx/gpio.h | 29 ++++++++ 3 files changed, 173 insertions(+) create mode 100644 cpu/arm_cortexa8/s5pc1xx/gpio.c diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile index 4f922e6..7290c2f 100644 --- a/cpu/arm_cortexa8/s5pc1xx/Makefile +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile @@ -33,6 +33,7 @@ SOBJS += reset.o COBJS += clock.o COBJS += cpu_info.o +COBJS += gpio.o COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm_cortexa8/s5pc1xx/gpio.c b/cpu/arm_cortexa8/s5pc1xx/gpio.c new file mode 100644 index 0000000..a97244b --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/gpio.c @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define CON_MASK(x) (0xf << ((x) << 2)) +#define CON_SFR(x, v) ((v) << ((x) << 2)) + +#define DAT_MASK(x) (0x1 << (x)) +#define DAT_SET(x) (0x1 << (x)) + +#define PULL_MASK(x) (0x3 << ((x) << 1)) +#define PULL_MODE(x, v) ((v) << ((x) << 1)) + +#define DRV_MASK(x) (0x3 << ((x) << 1)) +#define DRV_SET(x, m) ((m) << ((x) << 1)) +#define RATE_MASK(x) (0x1 << (x + 16)) +#define RATE_SET(x) (0x1 << (x + 16)) + +void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg) +{ + unsigned int value; + + value = readl(&bank->con); + value &= ~CON_MASK(gpio); + value |= CON_SFR(gpio, cfg); + writel(value, &bank->con); +} + +void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en) +{ + unsigned int value; + + gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); + + value = readl(&bank->dat); + value &= ~DAT_MASK(gpio); + if (en) + value |= DAT_SET(gpio); + writel(value, &bank->dat); +} + +void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio) +{ + gpio_cfg_pin(bank, gpio, GPIO_INPUT); +} + +void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en) +{ + unsigned int value; + + value = readl(&bank->dat); + value &= ~DAT_MASK(gpio); + if (en) + value |= DAT_SET(gpio); + writel(value, &bank->dat); +} + +unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio) +{ + unsigned int value; + + value = readl(&bank->dat); + return !!(value & DAT_MASK(gpio)); +} + +void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->pull); + value &= ~PULL_MASK(gpio); + + switch (mode) { + case GPIO_PULL_DOWN: + case GPIO_PULL_UP: + value |= PULL_MODE(gpio, mode); + break; + default: + return; + } + + writel(value, &bank->pull); +} + +void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->drv); + value &= ~DRV_MASK(gpio); + + switch (mode) { + case GPIO_DRV_1X: + case GPIO_DRV_2X: + case GPIO_DRV_3X: + case GPIO_DRV_4X: + value |= DRV_SET(gpio, mode); + break; + default: + return; + } + + writel(value, &bank->drv); +} + +void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->drv); + value &= ~RATE_MASK(gpio); + + switch (mode) { + case GPIO_DRV_FAST: + case GPIO_DRV_SLOW: + value |= RATE_SET(gpio); + break; + default: + return; + } + + writel(value, &bank->drv); +} diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h index afbc7ea..8e4bb86 100644 --- a/include/asm-arm/arch-s5pc1xx/gpio.h +++ b/include/asm-arm/arch-s5pc1xx/gpio.h @@ -124,6 +124,35 @@ struct s5pc110_gpio { struct s5pc1xx_gpio_bank gpio_h2; struct s5pc1xx_gpio_bank gpio_h3; }; + +/* functions */ +void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg); +void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en); +void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio); +void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en); +unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio); +void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); +void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); +void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); #endif +/* Pin configurations */ +#define GPIO_INPUT 0x0 +#define GPIO_OUTPUT 0x1 +#define GPIO_IRQ 0xf +#define GPIO_FUNC(x) (x) + +/* Pull mode */ +#define GPIO_PULL_NONE 0x0 +#define GPIO_PULL_DOWN 0x1 +#define GPIO_PULL_UP 0x2 + +/* Drive Strength level */ +#define GPIO_DRV_1X 0x0 +#define GPIO_DRV_2X 0x1 +#define GPIO_DRV_3X 0x2 +#define GPIO_DRV_4X 0x3 +#define GPIO_DRV_FAST 0x0 +#define GPIO_DRV_SLOW 0x1 + #endif -- cgit v1.1 From 28937af2321ebd96e5032508fc9048fc150b8f61 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Fri, 12 Feb 2010 18:21:17 +0900 Subject: s5pc1xx: update the README file Because adds support the GPIO Interface, README file is updated. Signed-off-by: Minkyu Kang --- doc/README.s5pc1xx | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/doc/README.s5pc1xx b/doc/README.s5pc1xx index 5a0fe33..ab1f024 100644 --- a/doc/README.s5pc1xx +++ b/doc/README.s5pc1xx @@ -41,7 +41,23 @@ To check SoC: printf("cpu is s5pc110\n"); gpio - not supported yet. + + struct s5pc100_gpio *gpio = (struct s5pc100_gpio*)S5PC100_GPIO_BASE; + + /* GPA[0] pin set to irq */ + gpio_cfg_pin(&gpio->gpio_a, 0, GPIO_IRQ); + + /* GPA[0] pin set to input */ + gpio_direction_input(&gpio->gpio_a, 0); + + /* GPA[0] pin set to output/high */ + gpio_direction_output(&gpio->gpio_a, 0, 1); + + /* GPA[0] value set to low */ + gpio_set_value(&gpio->gpio_a, 0, 0); + + /* get GPA[0] value */ + value = gpio_get_value(&gpio->gpio_a, 0); Links ===== -- cgit v1.1 From fe93100a64e045c14981b2d9129009b085d83f4b Mon Sep 17 00:00:00 2001 From: Naveen Krishna CH Date: Fri, 5 Mar 2010 17:15:13 +0900 Subject: S5PC100: Memory SubSystem Header file, register description(SROMC). Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand, NAND Flash, DDRs. smc.h is a common place for the register description of Memory subsystem of S5PC100. Note: Only SROM related registers are descibed now. Signed-off-by: Naveen Krishna Ch Signed-off-by: Minkyu Kang --- include/asm-arm/arch-s5pc1xx/smc.h | 50 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 include/asm-arm/arch-s5pc1xx/smc.h diff --git a/include/asm-arm/arch-s5pc1xx/smc.h b/include/asm-arm/arch-s5pc1xx/smc.h new file mode 100644 index 0000000..e1a5399 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/smc.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Naveen Krishna Ch + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: This file contains the register description for Memory subsystem + * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. + * + * Only SROMC is defined as of now + */ + +#ifndef __ASM_ARCH_SMC_H_ +#define __ASM_ARCH_SMC_H_ + +#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) +#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ + /* 1-> Byte base address*/ +#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) +#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) + +#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ +#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ +#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ +#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ +#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ +#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ +#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ + +#ifndef __ASSEMBLY__ +struct s5pc1xx_smc { + unsigned int bw; + unsigned int bc[6]; +}; +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_SMC_H_ */ -- cgit v1.1 From a722ca7b9eb77850956c1719ec115d780adda0b4 Mon Sep 17 00:00:00 2001 From: Naveen Krishna CH Date: Fri, 5 Mar 2010 17:15:38 +0900 Subject: S5PC100: Function to configure the SROMC registers. Nand Flash, Ethernet, other features might need to configure the SROMC registers accordingly. The config_sromc() functions helps with this. Signed-off-by: Naveen Krishna Ch Signed-off-by: Minkyu Kang --- cpu/arm_cortexa8/s5pc1xx/Makefile | 1 + cpu/arm_cortexa8/s5pc1xx/sromc.c | 53 ++++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-s5pc1xx/smc.h | 3 +++ 3 files changed, 57 insertions(+) create mode 100644 cpu/arm_cortexa8/s5pc1xx/sromc.c diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile index 7290c2f..01c93fe 100644 --- a/cpu/arm_cortexa8/s5pc1xx/Makefile +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile @@ -34,6 +34,7 @@ SOBJS += reset.o COBJS += clock.o COBJS += cpu_info.o COBJS += gpio.o +COBJS += sromc.o COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c b/cpu/arm_cortexa8/s5pc1xx/sromc.c new file mode 100644 index 0000000..380be81 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * Naveen Krishna Ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the + * band width control and bank control registers + * srom_bank - SROM Bank 0 to 5 + * smc_bw_conf - SMC Band witdh reg configuration value + * smc_bc_conf - SMC Bank Control reg configuration value + */ +void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf) +{ + u32 tmp; + struct s5pc1xx_smc *srom; + + if (cpu_is_s5pc100()) + srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE; + else + srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE; + + /* Configure SMC_BW register to handle proper SROMC bank */ + tmp = srom->bw; + tmp &= ~(0xF << (srom_bank * 4)); + tmp |= smc_bw_conf; + srom->bw = tmp; + + /* Configure SMC_BC register */ + srom->bc[srom_bank] = smc_bc_conf; +} diff --git a/include/asm-arm/arch-s5pc1xx/smc.h b/include/asm-arm/arch-s5pc1xx/smc.h index e1a5399..88f4ffe 100644 --- a/include/asm-arm/arch-s5pc1xx/smc.h +++ b/include/asm-arm/arch-s5pc1xx/smc.h @@ -47,4 +47,7 @@ struct s5pc1xx_smc { }; #endif /* __ASSEMBLY__ */ +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf); + #endif /* __ASM_ARCH_SMC_H_ */ -- cgit v1.1 From 8d9ba7507fc66d83de0fa479e610b6951f4779d5 Mon Sep 17 00:00:00 2001 From: Naveen Krishna CH Date: Fri, 5 Mar 2010 17:16:05 +0900 Subject: SAMSUNG: SMDKC100: Adds ethernet support. Add setup for ethernet on SMDKC100, allowing kernel/ramdisk to be loaded over tftp. The preinit function will configure GPIO (GPK0CON) & SROMC to look for environment in SROM Bank 3. Signed-off-by: Naveen Krishna Ch Signed-off-by: Minkyu Kang --- board/samsung/smdkc100/smdkc100.c | 39 +++++++++++++++++++++++++++++++++++++++ include/configs/smdkc100.h | 12 +++++++++++- 2 files changed, 50 insertions(+), 1 deletion(-) diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 15a1a27..fb466c6 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -23,10 +23,40 @@ */ #include +#include +#include +#include +#include + DECLARE_GLOBAL_DATA_PTR; +/* + * Miscellaneous platform dependent initialisations + */ +static void smc9115_pre_init(void) +{ + u32 smc_bw_conf, smc_bc_conf; + + struct s5pc100_gpio *const gpio = + (struct s5pc100_gpio *)S5PC100_GPIO_BASE; + + /* gpio configuration GPK0CON */ + gpio_cfg_pin(&gpio->gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + + /* Ethernet needs bus width of 16 bits */ + smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); + smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe) + | SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4) + | SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0); + + /* Select and configure the SROMC bank */ + s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); +} + int board_init(void) { + smc9115_pre_init(); + gd->bd->bi_arch_number = MACH_TYPE_SMDKC100; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; @@ -49,3 +79,12 @@ int checkboard(void) return 0; } #endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index a8ba052..09bce6d 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -83,7 +83,6 @@ #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_NAND -#undef CONFIG_CMD_NET #define CONFIG_CMD_CACHE #define CONFIG_CMD_REGINFO @@ -235,4 +234,15 @@ #define CONFIG_DOS_PARTITION 1 +/* + * Ethernet Contoller driver + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X 1 /* we have a SMC9115 on-board */ +#define CONFIG_SMC911X_16_BIT 1 /* SMC911X_16_BIT Mode */ +#define CONFIG_SMC911X_BASE 0x98800300 /* SMC911X Drive Base */ +#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ +#endif /* CONFIG_CMD_NET */ + #endif /* __CONFIG_H */ -- cgit v1.1 From 39ecbfcce0c7bda0fba37e4dfca520927513f4ca Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 9 Mar 2010 22:13:20 +0100 Subject: ep93xx timer: Fix possible overflow in usecs_to_ticks() ep93xx timer: Use 64-bit values in usecs_to_ticks() in order to avoid overflows in intermediate values Signed-off-by: Matthias Kaehlcke --- cpu/arm920t/ep93xx/timer.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c index b1a01a0..bc4ec8f 100644 --- a/cpu/arm920t/ep93xx/timer.c +++ b/cpu/arm920t/ep93xx/timer.c @@ -36,7 +36,7 @@ #define TIMER_CLKSEL (1 << 3) #define TIMER_ENABLE (1 << 7) -#define TIMER_FREQ 508469 +#define TIMER_FREQ 508469 /* ticks / second */ #define TIMER_MAX_VAL 0xFFFFFFFF static struct ep93xx_timer @@ -53,18 +53,10 @@ static inline unsigned long clk_to_systicks(unsigned long long clk_ticks) return (unsigned long)sys_ticks; } -static inline unsigned long usecs_to_ticks(unsigned long usecs) +static inline unsigned long long usecs_to_ticks(unsigned long usecs) { - unsigned long ticks; - - if (usecs >= 1000) { - ticks = usecs / 1000; - ticks *= TIMER_FREQ; - ticks /= 1000; - } else { - ticks = usecs * TIMER_FREQ; - ticks /= (1000 * 1000); - } + unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ; + do_div(ticks, 1000 * 1000); return ticks; } -- cgit v1.1 From dea86bb9aa663d726a6e6c1cf5c464c3ae351da9 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 9 Mar 2010 22:13:33 +0100 Subject: ep93xx timer: Fix resolution of get_ticks() ep93xx timer: Make get_ticks() return a value in CONFIG_SYS_HZ resolution, as announced by get_tbclk() Signed-off-by: Matthias Kaehlcke --- cpu/arm920t/ep93xx/timer.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c index bc4ec8f..31304b7 100644 --- a/cpu/arm920t/ep93xx/timer.c +++ b/cpu/arm920t/ep93xx/timer.c @@ -69,7 +69,7 @@ static inline unsigned long read_timer(void) } /* - * timer without interrupts + * Get the number of ticks (in CONFIG_SYS_HZ resolution) */ unsigned long long get_ticks(void) { @@ -83,12 +83,12 @@ unsigned long long get_ticks(void) timer.last_update = now; - return timer.ticks; + return clk_to_systicks(timer.ticks); } unsigned long get_timer_masked(void) { - return clk_to_systicks(get_ticks()); + return get_ticks(); } unsigned long get_timer(unsigned long base) @@ -109,10 +109,13 @@ void reset_timer(void) void __udelay(unsigned long usec) { - const unsigned long target = get_ticks() + usecs_to_ticks(usec); + /* read the timer and update timer.ticks */ + get_ticks(); - while (get_ticks() < target) - /* noop */; + const unsigned long long target = timer.ticks + usecs_to_ticks(usec); + + while (timer.ticks < target) + get_ticks(); } int timer_init(void) -- cgit v1.1 From 5962bffcb5a064cb58d244f15f08d5d533bcd27b Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 9 Mar 2010 22:13:47 +0100 Subject: ep93xx timer: Rename struct timer_reg pointers ep93xx timer: Renamed pointers to struct timer_regs from name 'timer' to 'timer_regs' in order to avoid confusion with the global variable 'timer' Signed-off-by: Matthias Kaehlcke --- cpu/arm920t/ep93xx/timer.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c index 31304b7..943f193 100644 --- a/cpu/arm920t/ep93xx/timer.c +++ b/cpu/arm920t/ep93xx/timer.c @@ -63,9 +63,9 @@ static inline unsigned long long usecs_to_ticks(unsigned long usecs) static inline unsigned long read_timer(void) { - struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; + struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE; - return TIMER_MAX_VAL - readl(&timer->timer3.value); + return TIMER_MAX_VAL - readl(&timer_regs->timer3.value); } /* @@ -120,17 +120,17 @@ void __udelay(unsigned long usec) int timer_init(void) { - struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; + struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE; /* use timer 3 with 508KHz and free running */ - writel(TIMER_CLKSEL, &timer->timer3.control); + writel(TIMER_CLKSEL, &timer_regs->timer3.control); /* set initial timer value 3 */ - writel(TIMER_MAX_VAL, &timer->timer3.load); + writel(TIMER_MAX_VAL, &timer_regs->timer3.load); /* Enable the timer */ writel(TIMER_ENABLE | TIMER_CLKSEL, - &timer->timer3.control); + &timer_regs->timer3.control); reset_timer_masked(); -- cgit v1.1 From 44de3e8ff7ed48bf96ec6c5e2173187d9c1c61e6 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 9 Mar 2010 22:13:56 +0100 Subject: ep93xx timer: refactoring ep93xx timer: Simplified the timer code by eliminating clk_to_systicks() and performing (almost) all manipulation of the timer structure in read_timer() Signed-off-by: Matthias Kaehlcke --- cpu/arm920t/ep93xx/timer.c | 52 +++++++++++++++++++++------------------------- 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c index 943f193..4a0ce4d 100644 --- a/cpu/arm920t/ep93xx/timer.c +++ b/cpu/arm920t/ep93xx/timer.c @@ -1,8 +1,7 @@ /* * Cirrus Logic EP93xx timer support. * - * Copyright (C) 2009, 2010 - * Matthias Kaehlcke + * Copyright (C) 2009, 2010 Matthias Kaehlcke * * Copyright (C) 2004, 2005 * Cory T. Tusar, Videon Central, Inc., @@ -42,17 +41,9 @@ static struct ep93xx_timer { unsigned long long ticks; - unsigned long last_update; + unsigned long last_read; } timer; -static inline unsigned long clk_to_systicks(unsigned long long clk_ticks) -{ - unsigned long long sys_ticks = (clk_ticks * CONFIG_SYS_HZ); - do_div(sys_ticks, TIMER_FREQ); - - return (unsigned long)sys_ticks; -} - static inline unsigned long long usecs_to_ticks(unsigned long usecs) { unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ; @@ -61,11 +52,18 @@ static inline unsigned long long usecs_to_ticks(unsigned long usecs) return ticks; } -static inline unsigned long read_timer(void) +static inline void read_timer(void) { struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE; + const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value); + + if (now >= timer.last_read) + timer.ticks += now - timer.last_read; + else + /* an overflow occurred */ + timer.ticks += TIMER_MAX_VAL - timer.last_read + now; - return TIMER_MAX_VAL - readl(&timer_regs->timer3.value); + timer.last_read = now; } /* @@ -73,17 +71,14 @@ static inline unsigned long read_timer(void) */ unsigned long long get_ticks(void) { - const unsigned long now = read_timer(); + unsigned long long sys_ticks; - if (now >= timer.last_update) - timer.ticks += now - timer.last_update; - else - /* an overflow occurred */ - timer.ticks += TIMER_MAX_VAL - timer.last_update + now; + read_timer(); - timer.last_update = now; + sys_ticks = timer.ticks * CONFIG_SYS_HZ; + do_div(sys_ticks, TIMER_FREQ); - return clk_to_systicks(timer.ticks); + return sys_ticks; } unsigned long get_timer_masked(void) @@ -98,7 +93,7 @@ unsigned long get_timer(unsigned long base) void reset_timer_masked(void) { - timer.last_update = read_timer(); + read_timer(); timer.ticks = 0; } @@ -109,23 +104,24 @@ void reset_timer(void) void __udelay(unsigned long usec) { - /* read the timer and update timer.ticks */ - get_ticks(); + unsigned long long target; + + read_timer(); - const unsigned long long target = timer.ticks + usecs_to_ticks(usec); + target = timer.ticks + usecs_to_ticks(usec); while (timer.ticks < target) - get_ticks(); + read_timer(); } int timer_init(void) { struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE; - /* use timer 3 with 508KHz and free running */ + /* use timer 3 with 508KHz and free running, not enabled now */ writel(TIMER_CLKSEL, &timer_regs->timer3.control); - /* set initial timer value 3 */ + /* set initial timer value */ writel(TIMER_MAX_VAL, &timer_regs->timer3.load); /* Enable the timer */ -- cgit v1.1