From 17a684449728ce4c9ce79fa9e7e75b86a5f9b41d Mon Sep 17 00:00:00 2001 From: Rupjyoti Sarmah Date: Wed, 7 Jul 2010 18:14:48 +0530 Subject: ppc4xx/Canyonlands added USB board callbacks Functions added to support board callbacks for USB init. This isolates USB manipulations such that it is only touched if USB is used by U-Boot. Signed-off-by: Dave Mitchell Signed-off-by: Rupjyoti Sarmah Signed-off-by: Stefan Roese --- board/amcc/canyonlands/canyonlands.c | 64 +++++++++++++++++++++++++++++++----- include/configs/canyonlands.h | 8 +++++ 2 files changed, 63 insertions(+), 9 deletions(-) diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 23874d2..158f7bb 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -34,7 +34,17 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch DECLARE_GLOBAL_DATA_PTR; -#define CONFIG_SYS_BCSR3_PCIE 0x10 + struct board_bcsr { + u8 board_id; + u8 cpld_rev; + u8 led_user; + u8 board_status; + u8 reset_ctrl; + u8 flash_ctrl; + u8 eth_ctrl; + u8 usb_ctrl; + u8 irq_ctrl; +}; #define BOARD_CANYONLANDS_PCIE 1 #define BOARD_CANYONLANDS_SATA 2 @@ -112,6 +122,9 @@ int board_early_init_f(void) { #if !defined(CONFIG_ARCHES) u32 sdr0_cust0; + struct board_bcsr *bcsr_data = + (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; + #endif /* @@ -172,14 +185,10 @@ int board_early_init_f(void) #if !defined(CONFIG_ARCHES) /* Enable ethernet and take out of reset */ - out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0); + out_8(&bcsr_data->eth_ctrl, 0) ; /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */ - out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0); - - /* Enable USB host & USB-OTG */ - out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0); - + out_8(&bcsr_data->flash_ctrl, 0) ; mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ /* Setup PLB4-AHB bridge based on the system address map */ @@ -201,6 +210,41 @@ int board_early_init_f(void) return 0; } +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) +int usb_board_init(void) +{ + struct board_bcsr *bcsr_data = + (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; + u8 val; + + /* Enable USB host & USB-OTG */ + val = in_8(&bcsr_data->usb_ctrl); + val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); + out_8(&bcsr_data->usb_ctrl, val); + + return 0; +} + +int usb_board_stop(void) +{ + struct board_bcsr *bcsr_data = + (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; + u8 val; + + /* Disable USB host & USB-OTG */ + val = in_8(&bcsr_data->usb_ctrl); + val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); + out_8(&bcsr_data->usb_ctrl, val); + + return 0; +} + +int usb_board_init_fail(void) +{ + return usb_board_stop(); +} +#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */ + #if !defined(CONFIG_ARCHES) static void canyonlands_sata_init(int board_type) { @@ -244,11 +288,13 @@ int get_cpu_num(void) #if !defined(CONFIG_ARCHES) int checkboard(void) { + struct board_bcsr *bcsr_data = + (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; char *s = getenv("serial#"); if (pvr_460ex()) { printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); - if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE) + if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE) gd->board_type = BOARD_CANYONLANDS_PCIE; else gd->board_type = BOARD_CANYONLANDS_SATA; @@ -268,7 +314,7 @@ int checkboard(void) break; } - printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0))); + printf(", Rev. %X", in_8(&bcsr_data->cpld_rev)); if (s != NULL) { puts(", serial# "); diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index ac9b3c5..6fe7639 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -77,6 +77,13 @@ #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 +/* + * BCSR bits as defined in the Canyonlands board user manual. + */ +#define BCSR_USBCTRL_OTG_RST 0x32 +#define BCSR_USBCTRL_HOST_RST 0x01 +#define BCSR_SELECT_PCIE 0x10 + #define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */ /* base address of inbound PCIe window */ @@ -417,6 +424,7 @@ #define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000) #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 +#define CONFIG_SYS_USB_OHCI_BOARD_INIT #endif /* -- cgit v1.1 From 5bf39a96c2b236baf8ef5b7a1e78a18f83152f27 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 19 Jul 2010 14:24:22 +0200 Subject: ppc4xx: T3CORP fixes and updates This patch fixes some problems for the T3CORP board. Here the list of the changes: - Add 600-67 and 677 CPU frequency setting to chip_config command - Define CONFIG_DDR_RFDC_FIXED on t3corp: While using the "normal" auto calibration code, sometimes values for RFDC were picked (>= T3) that resulted in a non-working U-Boot (hang upon relocation, while running from SDRAM). With this optimized RFDC value we can force this register and use the auto-calibration code to setup the remaining calibration registers. - Increase sizes of FPGA chips selects - EBC timing updated OEN=3 for 66 MHz EBC speed - Change ext. IRQ2 setup to level-low active - Enable CONFIG_SYS_CFI_FLASH_STATUS_POLL By defining CONFIG_SYS_CFI_FLASH_STATUS_POLL, DQ7 is polled to detect the chip busy status. This is now used instead of the data toggle method which is used historically by default in the common CFI driver. With this change a problem with not written data is solved on this board, where a 32 byte block of data is still erased instead of filled with the correct content after these commands: => erase 0xfc100000 +0x1000000 .................................................................... done Erased 128 sectors => cp.b 0x100000 0xfc100000 0x1000000 Copy to Flash... done => cmp.b 0x100000 0xfc100000 0x1000000 byte at 0x00d0d6c0 (0x00) != byte at 0xfcd0d6c0 (0xff) Total of 12637888 bytes were the same Signed-off-by: Stefan Roese --- board/t3corp/chip_config.c | 16 +++++++++++++++- board/t3corp/init.S | 8 +++++--- board/t3corp/t3corp.c | 2 +- include/configs/t3corp.h | 27 +++++++++++++-------------- 4 files changed, 34 insertions(+), 19 deletions(-) diff --git a/board/t3corp/chip_config.c b/board/t3corp/chip_config.c index c00bf16..98ab49f 100644 --- a/board/t3corp/chip_config.c +++ b/board/t3corp/chip_config.c @@ -27,13 +27,27 @@ struct ppc4xx_config ppc4xx_config_val[] = { { - "600", "CPU: 600 PLB: 200 OPB: 100 EBC: 100", + "600-67", "CPU: 600 PLB: 200 OPB: 67 EBC: 67", + { + 0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0, + 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + } + }, + { + "600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100", { 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 } }, { + "667", "CPU: 667 PLB: 166 OPB: 83 EBC: 83", + { + 0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0, + 0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + } + }, + { "800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100", { 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, diff --git a/board/t3corp/init.S b/board/t3corp/init.S index 4a4217f..ecd35ff 100644 --- a/board/t3corp/init.S +++ b/board/t3corp/init.S @@ -81,11 +81,13 @@ tlbtab: tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG) /* TLB-entry for FPGA(s) */ - tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_1M, CONFIG_SYS_FPGA1_BASE, 4, + tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_1M, CONFIG_SYS_FPGA2_BASE, 4, + tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M, + CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG) + tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_1M, CONFIG_SYS_FPGA3_BASE, 4, + tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4, AC_RW | SA_IG) /* TLB-entry for OCM */ diff --git a/board/t3corp/t3corp.c b/board/t3corp/t3corp.c index 8ffa321..ddf5897 100644 --- a/board/t3corp/t3corp.c +++ b/board/t3corp/t3corp.c @@ -45,7 +45,7 @@ int board_early_init_f(void) mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC1ER, 0x00000000); /* disable all */ mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1PR, 0x7fffffff); /* per ref-board manual */ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 0ecc5b1..7b88601 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -74,8 +74,8 @@ #define CONFIG_SYS_FLASH_SIZE (64 << 20) #define CONFIG_SYS_FPGA1_BASE 0xe0000000 -#define CONFIG_SYS_FPGA2_BASE 0xe0100000 -#define CONFIG_SYS_FPGA3_BASE 0xe0200000 +#define CONFIG_SYS_FPGA2_BASE 0xe2000000 +#define CONFIG_SYS_FPGA3_BASE 0xe4000000 #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 @@ -84,14 +84,12 @@ (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \ | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) -#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ +#define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */ #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ -#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */ - /* * Initial RAM & stack pointer (placed in OCM) */ @@ -121,6 +119,7 @@ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ @@ -144,10 +143,13 @@ /* * DDR2 SDRAM */ +#define CONFIG_SYS_MBYTES_SDRAM 256 +#define CONFIG_DDR_ECC #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ #undef CONFIG_PPC4xx_DDR_METHOD_A +#define CONFIG_DDR_RFDC_FIXED 0x000001D7 /* optimal value */ /* DDR1/2 SDRAM Device Control Register Data Values */ /* Memory Queue */ @@ -162,9 +164,6 @@ #define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 #define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000 -#define CONFIG_DDR_ECC -#define CONFIG_SYS_MBYTES_SDRAM 256 - #define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK /* DDR1/2 SDRAM Device Control Register Data Values */ @@ -417,7 +416,7 @@ #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(5) | \ EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_OEN_ENCODE(3) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ @@ -426,7 +425,7 @@ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \ - EBC_BXCR_BS_1MB | \ + EBC_BXCR_BS_32MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_32BIT) @@ -434,7 +433,7 @@ #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(5) | \ EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_OEN_ENCODE(3) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ @@ -443,7 +442,7 @@ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) #define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \ - EBC_BXCR_BS_1MB | \ + EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_32BIT) @@ -451,7 +450,7 @@ #define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(5) | \ EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_OEN_ENCODE(3) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ @@ -460,7 +459,7 @@ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) #define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \ - EBC_BXCR_BS_1MB | \ + EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_32BIT) -- cgit v1.1 From eab9800182a0ff5ee2a9d7055a91dd9360ed681f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 20 Jul 2010 07:06:03 +0200 Subject: ppc4xx: Add CONFIG_DDR_RFDC_FIXED to allow board specific RFDC values Using this define, a board can define an opimized RFDC value and use the auto calibration code to "tune" the remaining DDR2 controller calibration register. Signed-off-by: Stefan Roese --- arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 0f69ef9..2fee995 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -767,6 +767,13 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal) debug("\n\n"); +#if defined(CONFIG_DDR_RFDC_FIXED) + mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED); + size = 512; + rffd_average = CONFIG_DDR_RFDC_FIXED & SDRAM_RFDC_RFFD_MASK; + mfsdram(SDRAM_RDCC, rdcc); /* record this value */ + cal->rdcc = rdcc; +#else /* CONFIG_DDR_RFDC_FIXED */ in_window = 0; rdcc = 0; @@ -830,6 +837,7 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal) rffd_average = SDRAM_RFDC_RFFD_MAX; mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average)); +#endif /* CONFIG_DDR_RFDC_FIXED */ rffd = rffd_average; in_window = 0; @@ -1211,10 +1219,14 @@ u32 DQS_autocalibration(void) debug("*** best_result: read value SDRAM_RQDC 0x%08x\n", rqdc_reg); +#if defined(CONFIG_DDR_RFDC_FIXED) + mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED); +#else /* CONFIG_DDR_RFDC_FIXED */ mfsdram(SDRAM_RFDC, rfdc_reg); rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK); mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd)); +#endif /* CONFIG_DDR_RFDC_FIXED */ mfsdram(SDRAM_RFDC, rfdc_reg); debug("*** best_result: read value SDRAM_RFDC 0x%08x\n", -- cgit v1.1 From 897d6abc50e95fb57fa6952c27deae5776ba08cc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 21 Jul 2010 11:08:16 +0200 Subject: ppc4xx: Only define DDR2 registers for the correct PowerPC variants Make sure that some SDRAM/DDR2 registers are only defined for the PPC variants really implementing those registers. Signed-off-by: Stefan Roese --- arch/powerpc/include/asm/ppc4xx-sdram.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index d9506e2..42eac45 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -363,6 +363,7 @@ /* * Memory controller registers */ +#ifdef CONFIG_405EX #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -371,11 +372,10 @@ #define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ -#ifndef CONFIG_405EX -#define SDRAM_MCSTAT 0x14 /* memory controller status */ -#else #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#endif +#else /* CONFIG_405EX */ +#define SDRAM_MCSTAT 0x14 /* memory controller status */ +#endif /* CONFIG_405EX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ -- cgit v1.1 From b995d7cb2c1e47305cd7feb2513ed37d30f8edd3 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 21 Jul 2010 11:08:27 +0200 Subject: ppc4xx: DDR/ECC: Use correct macros to clear error status Use the correct macro instead of the hardcoded 0x4c to clear the ECC status in the 440/460 DDR(2) error status register after ECC initialization. Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants (440GX) use a different registers to clear this error status. Use the correct ones. Signed-off-by: Stefan Roese --- arch/powerpc/cpu/ppc4xx/ecc.c | 21 ++++++++++++++++++++- arch/powerpc/include/asm/ppc4xx-sdram.h | 2 ++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/ppc4xx/ecc.c b/arch/powerpc/cpu/ppc4xx/ecc.c index f105605..49f28d9 100644 --- a/arch/powerpc/cpu/ppc4xx/ecc.c +++ b/arch/powerpc/cpu/ppc4xx/ecc.c @@ -130,7 +130,26 @@ static void program_ecc_addr(unsigned long start_address, /* clear ECC error repoting registers */ mtsdram(SDRAM_ECCES, 0xffffffff); - mtdcr(0x4c, 0xffffffff); +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) + /* + * IBM DDR(1) core (440GX): + * Clear Mx bits in SDRAM0_BESR0/1 + */ + mtsdram(SDRAM0_BESR0, 0xffffffff); + mtsdram(SDRAM0_BESR1, 0xffffffff); +#elif defined(CONFIG_440) + /* + * 440/460 DDR2 core: + * Clear EMID (Error PLB Master ID) in MQ0_ESL + */ + mtdcr(SDRAM_ERRSTATLL, 0xfff00000); +#else + /* + * 405EX(r) DDR2 core: + * Clear M0ID (Error PLB Master ID) in SDRAM_BESR + */ + mtsdram(SDRAM_BESR, 0xf0000000); +#endif mtsdram(SDRAM_MCOPT1, (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP); diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index 42eac45..4ec1ef8 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -63,6 +63,8 @@ #define SDRAM_CFG0 0x20 /* memory controller options 0 */ #define SDRAM_CFG1 0x21 /* memory controller options 1 */ +#define SDRAM0_BESR0 0x0000 /* bus error status reg 0 */ +#define SDRAM0_BESR1 0x0008 /* bus error status reg 1 */ #define SDRAM0_BEAR 0x0010 /* bus error address reg */ #define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */ #define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */ -- cgit v1.1 From 58eb869ffc45856658648e24a88d47fdd3768b53 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 21 Jul 2010 19:06:10 +0200 Subject: ppc4xx: Add "ecctest" command to test/simulate ECC errors This patch adds the "ecctest" command to test and simulate ECC errors (single bit and/or double bit) while running from SDRAM. Currently only the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT). This is done by copying and calling functions, modifying the SDRAM controller operation mode, in internal SRAM/OCM. For correctable ECC errors (single bit) only the status will be printed since the DDR2 controller doesn't provide the faulting address: => ecctest 1000000 1 Using address 01000000 for 1 bit ECC error injection ECC: Correctable error Uncorrectable ECC errors (double bit) will also display the faulting address: => ecctest 1000000 2 Using address 01000000 for 2 bit ECC error injection ECC: Uncorrectable error at 0x0001000000 To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST in the board config header. Tested on katmai and t3corp. Signed-off-by: Stefan Roese --- arch/powerpc/cpu/ppc4xx/Makefile | 3 + arch/powerpc/cpu/ppc4xx/cmd_ecctest.c | 284 ++++++++++++++++++++++++++++++++++ 2 files changed, 287 insertions(+) create mode 100644 arch/powerpc/cpu/ppc4xx/cmd_ecctest.c diff --git a/arch/powerpc/cpu/ppc4xx/Makefile b/arch/powerpc/cpu/ppc4xx/Makefile index 88d53fb..c9c1a33 100644 --- a/arch/powerpc/cpu/ppc4xx/Makefile +++ b/arch/powerpc/cpu/ppc4xx/Makefile @@ -51,6 +51,9 @@ COBJS += cpu_init.o COBJS += denali_data_eye.o COBJS += denali_spd_ddr2.o COBJS += ecc.o +ifdef CONFIG_CMD_ECCTEST +COBJS += cmd_ecctest.o +endif COBJS += fdt.o COBJS += interrupts.o COBJS += iop480_uart.o diff --git a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c new file mode 100644 index 0000000..b4eac40 --- /dev/null +++ b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c @@ -0,0 +1,284 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \ + defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) +#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) + +#if defined(CONFIG_405EX) +/* + * Currently only 405EX uses 16bit data bus width as an alternative + * option to 32bit data width (SDRAM0_MCOPT1_WDTH) + */ +#define SDRAM_DATA_ALT_WIDTH 2 +#else +#define SDRAM_DATA_ALT_WIDTH 8 +#endif + +#if defined(CONFIG_SYS_OCM_BASE) +#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_OCM_BASE +#endif + +#if defined(CONFIG_SYS_ISRAM_BASE) +#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_ISRAM_BASE +#endif + +#if !defined(CONFIG_FUNC_ISRAM_ADDR) +#error "No internal SRAM/OCM provided!" +#endif + +#define force_inline inline __attribute__ ((always_inline)) + +static inline void machine_check_disable(void) +{ + mtmsr(mfmsr() & ~MSR_ME); +} + +static inline void machine_check_enable(void) +{ + mtmsr(mfmsr() | MSR_ME); +} + +/* + * These helper functions need to be inlined, since they + * are called from the functions running from internal SRAM. + * SDRAM operation is forbidden at that time, so calling + * functions in SDRAM has to be avoided. + */ +static force_inline void wait_ddr_idle(void) +{ + u32 val; + + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT); +} + +static force_inline void recalibrate_ddr(void) +{ + u32 val; + + /* + * Rewrite RQDC & RFDC to calibrate again. If this is not + * done, the SDRAM controller is working correctly after + * changing the MCOPT1_MCHK bits. + */ + mfsdram(SDRAM_RQDC, val); + mtsdram(SDRAM_RQDC, val); + mfsdram(SDRAM_RFDC, val); + mtsdram(SDRAM_RFDC, val); +} + +static force_inline void set_mcopt1_mchk(u32 bits) +{ + u32 val; + + wait_ddr_idle(); + mfsdram(SDRAM_MCOPT1, val); + mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | bits); + recalibrate_ddr(); +} + +/* + * The next 2 functions are copied to internal SRAM/OCM and run + * there. No function calls allowed here. No SDRAM acitivity should + * be done here. + */ +static void inject_ecc_error(void *ptr, int par) +{ + u32 val; + + /* + * Taken from PPC460EX/EXr/GT users manual (Rev 1.21) + * 22.2.17.13 ECC Diagnostics + * + * Items 1 ... 5 are already done by now, running from RAM + * with ECC enabled + */ + + out_be32(ptr, 0x00000000); + val = in_be32(ptr); + + /* 6. Set memory controller to no error checking */ + set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_NON); + + /* 7. Modify one or two bits for error simulation */ + if (par == 1) + out_be32(ptr, in_be32(ptr) ^ 0x00000001); + else + out_be32(ptr, in_be32(ptr) ^ 0x00000003); + + /* 8. Wait for SDRAM idle */ + val = in_be32(ptr); + set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP); + + /* Wait for SDRAM idle */ + wait_ddr_idle(); + + /* Continue with 9. in calling function... */ +} + +static void rewrite_ecc_parity(void *ptr, int par) +{ + u32 current_address = (u32)ptr; + u32 end_address; + u32 address_increment; + u32 mcopt1; + u32 val; + + /* + * Fill ECC parity byte again. Otherwise further accesses to + * the failure address will result in exceptions. + */ + + /* Wait for SDRAM idle */ + val = in_be32(0x00000000); + set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_GEN); + + /* ECC bit set method for non-cached memory */ + mfsdram(SDRAM_MCOPT1, mcopt1); + if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32) + address_increment = 4; + else + address_increment = SDRAM_DATA_ALT_WIDTH; + end_address = current_address + CONFIG_SYS_CACHELINE_SIZE; + + while (current_address < end_address) { + *((unsigned long *)current_address) = 0; + current_address += address_increment; + } + + set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP); + + /* Wait for SDRAM idle */ + wait_ddr_idle(); +} + +static int do_ecctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u32 old_val; + u32 val; + u32 *ptr; + void (*sram_func)(u32 *, int); + int error; + + if (argc < 3) { + cmd_usage(cmdtp); + return 1; + } + + ptr = (u32 *)simple_strtoul(argv[1], NULL, 16); + error = simple_strtoul(argv[2], NULL, 16); + if ((error < 1) || (error > 2)) { + cmd_usage(cmdtp); + return 1; + } + + printf("Using address %p for %d bit ECC error injection\n", + ptr, error); + + /* + * Save value to restore it later on + */ + old_val = in_be32(ptr); + + /* + * Copy ECC injection function into internal SRAM/OCM + */ + sram_func = (void *)CONFIG_FUNC_ISRAM_ADDR; + memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, inject_ecc_error, 0x10000); + + /* + * Disable interrupts and exceptions before calling this + * function in internal SRAM/OCM + */ + disable_interrupts(); + machine_check_disable(); + eieio(); + + /* + * Jump to ECC simulation function in internal SRAM/OCM + */ + (*sram_func)(ptr, error); + + /* 10. Read the corresponding address */ + val = in_be32(ptr); + + /* + * Read and print ECC status register/info: + * The faulting address is only known upon uncorrectable ECC + * errors. + */ + mfsdram(SDRAM_ECCES, val); + if (val & SDRAM_ECCES_CE) + printf("ECC: Correctable error\n"); + if (val & SDRAM_ECCES_UE) { + printf("ECC: Uncorrectable error at 0x%02x%08x\n", + mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL)); + } + + /* + * Clear pending interrupts/exceptions + */ + mtsdram(SDRAM_ECCES, 0xffffffff); + mtdcr(SDRAM_ERRSTATLL, 0xff000000); + set_mcsr(get_mcsr()); + + /* Now enable interrupts and exceptions again */ + eieio(); + machine_check_enable(); + enable_interrupts(); + + /* + * The ECC parity byte need to be re-written for the + * corresponding address. Otherwise future accesses to it + * will result in exceptions. + * + * Jump to ECC parity generation function + */ + memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, rewrite_ecc_parity, 0x10000); + (*sram_func)(ptr, 0); + + /* + * Restore value in corresponding address + */ + out_be32(ptr, old_val); + + return 0; +} + +U_BOOT_CMD( + ecctest, 3, 0, do_ecctest, + "Test ECC by single and double error bit injection", + "address 1/2" +); + +#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ +#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */ -- cgit v1.1 From be24ef6e8ee48602f453bf16c7b7b708fac0eb2f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 21 Jul 2010 19:06:26 +0200 Subject: ppc4xx: Add ECC status info to machine-check exception for IBM DDR2 core Signed-off-by: Stefan Roese --- arch/powerpc/cpu/ppc4xx/traps.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/powerpc/cpu/ppc4xx/traps.c b/arch/powerpc/cpu/ppc4xx/traps.c index 1616772..b5562ad 100644 --- a/arch/powerpc/cpu/ppc4xx/traps.c +++ b/arch/powerpc/cpu/ppc4xx/traps.c @@ -209,6 +209,22 @@ MachineCheckException(struct pt_regs *regs) /* Clear MCSR */ mtspr(SPRN_MCSR, val); } + +#if defined(CONFIG_DDR_ECC) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) + /* + * Read and print ECC status register/info: + * The faulting address is only known upon uncorrectable ECC + * errors. + */ + mfsdram(SDRAM_ECCES, val); + if (val & SDRAM_ECCES_CE) + printf("ECC: Correctable error\n"); + if (val & SDRAM_ECCES_UE) { + printf("ECC: Uncorrectable error at 0x%02x%08x\n", + mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL)); + } +#endif /* CONFIG_DDR_ECC ... */ + #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) mfsdram(DDR0_00, val) ; printf("DDR0: DDR0_00 %lx\n", val); -- cgit v1.1 From e37228602592b347a7741f0d2d12755295517584 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 22 Jul 2010 19:06:14 +0200 Subject: ppc4xx: Enable "ecctest" command on katmai Signed-off-by: Stefan Roese --- include/configs/katmai.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/katmai.h b/include/configs/katmai.h index fb8ccae..76e9a76 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -202,6 +202,7 @@ */ #define CONFIG_CMD_CHIP_CONFIG #define CONFIG_CMD_DATE +#define CONFIG_CMD_ECCTEST #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_PCI -- cgit v1.1 From 1ffcb86ce06a252ff6f4620691eb347c8ab47b61 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 22 Jul 2010 19:06:27 +0200 Subject: ppc4xx: Enable "ecctest" command on t3corp Signed-off-by: Stefan Roese --- include/configs/t3corp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 7b88601..b38886b 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -359,6 +359,7 @@ * Commands additional to the ones defined in amcc-common.h */ #define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_ECCTEST #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM -- cgit v1.1