From d0b0dcaa220549999d6ea74cf87487846c186a0f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 1 Apr 2010 14:37:24 +0200 Subject: i2c: Move PPC4xx I2C driver into drivers/i2c directory This patch moves the PPC4xx specific I2C device driver into the I2C drivers directory. All 4xx config headers are updated to include this driver. Signed-off-by: Stefan Roese --- cpu/ppc4xx/Makefile | 1 - cpu/ppc4xx/i2c.c | 439 --------------------------------------- drivers/i2c/Makefile | 1 + drivers/i2c/ppc4xx_i2c.c | 439 +++++++++++++++++++++++++++++++++++++++ include/configs/ASH405.h | 1 + include/configs/CANBT.h | 1 + include/configs/CMS700.h | 1 + include/configs/CPCI2DP.h | 1 + include/configs/CPCI405.h | 1 + include/configs/CPCI4052.h | 1 + include/configs/CPCI405AB.h | 1 + include/configs/CPCI405DT.h | 1 + include/configs/CPCIISER4.h | 1 + include/configs/CRAYL1.h | 1 + include/configs/DP405.h | 1 + include/configs/DU405.h | 1 + include/configs/DU440.h | 1 + include/configs/ERIC.h | 1 + include/configs/G2000.h | 1 + include/configs/HH405.h | 1 + include/configs/HUB405.h | 1 + include/configs/JSE.h | 1 + include/configs/KAREF.h | 1 + include/configs/METROBOX.h | 1 + include/configs/MIP405.h | 1 + include/configs/OCRTC.h | 1 + include/configs/ORSG.h | 1 + include/configs/PCI405.h | 1 + include/configs/PIP405.h | 1 + include/configs/PLU405.h | 1 + include/configs/PMC405.h | 1 + include/configs/PMC405DE.h | 1 + include/configs/PMC440.h | 1 + include/configs/PPChameleonEVB.h | 1 + include/configs/VOH405.h | 1 + include/configs/VOM405.h | 1 + include/configs/W7OLMC.h | 1 + include/configs/W7OLMG.h | 1 + include/configs/WUH405.h | 1 + include/configs/XPEDITE1000.h | 1 + include/configs/alpr.h | 1 + include/configs/amcc-common.h | 1 + include/configs/csb272.h | 1 + include/configs/csb472.h | 1 + include/configs/korat.h | 1 + include/configs/lwmon5.h | 1 + include/configs/netstal-common.h | 1 + include/configs/p3p440.h | 1 + include/configs/pcs440ep.h | 1 + include/configs/quad100hd.h | 1 + include/configs/sbc405.h | 1 + include/configs/sc3.h | 1 + include/configs/zeus.h | 1 + 53 files changed, 489 insertions(+), 440 deletions(-) delete mode 100644 cpu/ppc4xx/i2c.c create mode 100644 drivers/i2c/ppc4xx_i2c.c diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 365f966..88d53fb 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -52,7 +52,6 @@ COBJS += denali_data_eye.o COBJS += denali_spd_ddr2.o COBJS += ecc.o COBJS += fdt.o -COBJS += i2c.o COBJS += interrupts.o COBJS += iop480_uart.o ifdef CONFIG_CMD_REGINFO diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c deleted file mode 100644 index 9b86187..0000000 --- a/cpu/ppc4xx/i2c.c +++ /dev/null @@ -1,439 +0,0 @@ -/* - * (C) Copyright 2007-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * based on work by Anne Sophie Harnois - * - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include <4xx_i2c.h> -#include -#include - -#ifdef CONFIG_HARD_I2C - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_I2C_MULTI_BUS) -/* - * Initialize the bus pointer to whatever one the SPD EEPROM is on. - * Default is bus 0. This is necessary because the DDR initialization - * runs from ROM, and we can't switch buses because we can't modify - * the global variables. - */ -#ifndef CONFIG_SYS_SPD_BUS_NUM -#define CONFIG_SYS_SPD_BUS_NUM 0 -#endif -static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = - CONFIG_SYS_SPD_BUS_NUM; -#endif /* CONFIG_I2C_MULTI_BUS */ - -static void _i2c_bus_reset(void) -{ - struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; - int i; - u8 dc; - - /* Reset status register */ - /* write 1 in SCMP and IRQA to clear these fields */ - out_8(&i2c->sts, 0x0A); - - /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ - out_8(&i2c->extsts, 0x8F); - - /* Place chip in the reset state */ - out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST); - - /* Check if bus is free */ - dc = in_8(&i2c->directcntl); - if (!DIRCTNL_FREE(dc)){ - /* Try to set bus free state */ - out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC); - - /* Wait until we regain bus control */ - for (i = 0; i < 100; ++i) { - dc = in_8(&i2c->directcntl); - if (DIRCTNL_FREE(dc)) - break; - - /* Toggle SCL line */ - dc ^= IIC_DIRCNTL_SCC; - out_8(&i2c->directcntl, dc); - udelay(10); - dc ^= IIC_DIRCNTL_SCC; - out_8(&i2c->directcntl, dc); - } - } - - /* Remove reset */ - out_8(&i2c->xtcntlss, 0); -} - -void i2c_init(int speed, int slaveaddr) -{ - struct ppc4xx_i2c *i2c; - int val, divisor; - int bus; - -#ifdef CONFIG_SYS_I2C_INIT_BOARD - /* - * Call board specific i2c bus reset routine before accessing the - * environment, which might be in a chip on that bus. For details - * about this problem see doc/I2C_Edge_Conditions. - */ - i2c_init_board(); -#endif - - for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) { - I2C_SET_BUS(bus); - - /* Set i2c pointer after calling I2C_SET_BUS() */ - i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; - - /* Handle possible failed I2C state */ - /* FIXME: put this into i2c_init_board()? */ - _i2c_bus_reset(); - - /* clear lo master address */ - out_8(&i2c->lmadr, 0); - - /* clear hi master address */ - out_8(&i2c->hmadr, 0); - - /* clear lo slave address */ - out_8(&i2c->lsadr, 0); - - /* clear hi slave address */ - out_8(&i2c->hsadr, 0); - - /* Clock divide Register */ - /* set divisor according to freq_opb */ - divisor = (get_OPB_freq() - 1) / 10000000; - if (divisor == 0) - divisor = 1; - out_8(&i2c->clkdiv, divisor); - - /* no interrupts */ - out_8(&i2c->intrmsk, 0); - - /* clear transfer count */ - out_8(&i2c->xfrcnt, 0); - - /* clear extended control & stat */ - /* write 1 in SRC SRS SWC SWS to clear these fields */ - out_8(&i2c->xtcntlss, 0xF0); - - /* Mode Control Register - Flush Slave/Master data buffer */ - out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); - - val = in_8(&i2c->mdcntl); - - /* Ignore General Call, slave transfers are ignored, - * disable interrupts, exit unknown bus state, enable hold - * SCL 100kHz normaly or FastMode for 400kHz and above - */ - - val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL; - if (speed >= 400000) - val |= IIC_MDCNTL_FSM; - out_8(&i2c->mdcntl, val); - - /* clear control reg */ - out_8(&i2c->cntl, 0x00); - } - - /* set to SPD bus as default bus upon powerup */ - I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); -} - -/* - * This code tries to use the features of the 405GP i2c - * controller. It will transfer up to 4 bytes in one pass - * on the loop. It only does out_8((u8 *)lbz) to the buffer when it - * is possible to do out16(lhz) transfers. - * - * cmd_type is 0 for write 1 for read. - * - * addr_len can take any value from 0-255, it is only limited - * by the char, we could make it larger if needed. If it is - * 0 we skip the address write cycle. - * - * Typical case is a Write of an addr followd by a Read. The - * IBM FAQ does not cover this. On the last byte of the write - * we don't set the creg CHT bit, and on the first bytes of the - * read we set the RPST bit. - * - * It does not support address only transfers, there must be - * a data part. If you want to write the address yourself, put - * it in the data pointer. - * - * It does not support transfer to/from address 0. - * - * It does not check XFRCNT. - */ -static int i2c_transfer(unsigned char cmd_type, - unsigned char chip, - unsigned char addr[], - unsigned char addr_len, - unsigned char data[], - unsigned short data_len) -{ - struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; - u8 *ptr; - int reading; - int tran, cnt; - int result; - int status; - int i; - u8 creg; - - if (data == 0 || data_len == 0) { - /* Don't support data transfer of no length or to address 0 */ - printf( "i2c_transfer: bad call\n" ); - return IIC_NOK; - } - if (addr && addr_len) { - ptr = addr; - cnt = addr_len; - reading = 0; - } else { - ptr = data; - cnt = data_len; - reading = cmd_type; - } - - /* Clear Stop Complete Bit */ - out_8(&i2c->sts, IIC_STS_SCMP); - - /* Check init */ - i = 10; - do { - /* Get status */ - status = in_8(&i2c->sts); - i--; - } while ((status & IIC_STS_PT) && (i > 0)); - - if (status & IIC_STS_PT) { - result = IIC_NOK_TOUT; - return(result); - } - - /* flush the Master/Slave Databuffers */ - out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) | - IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB); - - /* need to wait 4 OPB clocks? code below should take that long */ - - /* 7-bit adressing */ - out_8(&i2c->hmadr, 0); - out_8(&i2c->lmadr, chip); - - tran = 0; - result = IIC_OK; - creg = 0; - - while (tran != cnt && (result == IIC_OK)) { - int bc,j; - - /* - * Control register = - * Normal transfer, 7-bits adressing, Transfer up to - * bc bytes, Normal start, Transfer is a sequence of transfers - */ - creg |= IIC_CNTL_PT; - - bc = (cnt - tran) > 4 ? 4 : cnt - tran; - creg |= (bc - 1) << 4; - /* if the real cmd type is write continue trans */ - if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt)) - creg |= IIC_CNTL_CHT; - - if (reading) { - creg |= IIC_CNTL_READ; - } else { - for(j = 0; j < bc; j++) { - /* Set buffer */ - out_8(&i2c->mdbuf, ptr[tran + j]); - } - } - out_8(&i2c->cntl, creg); - - /* - * Transfer is in progress - * we have to wait for upto 5 bytes of data - * 1 byte chip address+r/w bit then bc bytes - * of data. - * udelay(10) is 1 bit time at 100khz - * Doubled for slop. 20 is too small. - */ - i = 2 * 5 * 8; - do { - /* Get status */ - status = in_8(&i2c->sts); - udelay(10); - i--; - } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && - (i > 0)); - - if (status & IIC_STS_ERR) { - result = IIC_NOK; - status = in_8(&i2c->extsts); - /* Lost arbitration? */ - if (status & IIC_EXTSTS_LA) - result = IIC_NOK_LA; - /* Incomplete transfer? */ - if (status & IIC_EXTSTS_ICT) - result = IIC_NOK_ICT; - /* Transfer aborted? */ - if (status & IIC_EXTSTS_XFRA) - result = IIC_NOK_XFRA; - } else if ( status & IIC_STS_PT) { - result = IIC_NOK_TOUT; - } - - /* Command is reading => get buffer */ - if ((reading) && (result == IIC_OK)) { - /* Are there data in buffer */ - if (status & IIC_STS_MDBS) { - /* - * even if we have data we have to wait 4OPB - * clocks for it to hit the front of the FIFO, - * after that we can just read. We should check - * XFCNT here and if the FIFO is full there is - * no need to wait. - */ - udelay(1); - for (j = 0; j < bc; j++) - ptr[tran + j] = in_8(&i2c->mdbuf); - } else - result = IIC_NOK_DATA; - } - creg = 0; - tran += bc; - if (ptr == addr && tran == cnt) { - ptr = data; - cnt = data_len; - tran = 0; - reading = cmd_type; - if (reading) - creg = IIC_CNTL_RPST; - } - } - return result; -} - -int i2c_probe(uchar chip) -{ - uchar buf[1]; - - buf[0] = 0; - - /* - * What is needed is to send the chip address and verify that the - * address was ed (i.e. there was a chip at that address which - * drove the data line low). - */ - return (i2c_transfer(1, chip << 1, 0, 0, buf, 1) != 0); -} - -static int ppc4xx_i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, - int len, int read) -{ - uchar xaddr[4]; - int ret; - - if (alen > 4) { - printf("I2C: addr len %d not supported\n", alen); - return 1; - } - - if (alen > 0) { - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - } - - -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - if (alen > 0) - chip |= ((addr >> (alen * 8)) & - CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); -#endif - if ((ret = i2c_transfer(read, chip << 1, &xaddr[4 - alen], alen, - buffer, len)) != 0) { - if (gd->have_console) { - printf("I2C %s: failed %d\n", - read ? "read" : "write", ret); - } - - return 1; - } - - return 0; -} - -int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 1); -} - -int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 0); -} - -#if defined(CONFIG_I2C_MULTI_BUS) -/* - * Functions for multiple I2C bus handling - */ -unsigned int i2c_get_bus_num(void) -{ - return i2c_bus_num; -} - -int i2c_set_bus_num(unsigned int bus) -{ - if (bus >= CONFIG_SYS_MAX_I2C_BUS) - return -1; - - i2c_bus_num = bus; - - return 0; -} -#endif /* CONFIG_I2C_MULTI_BUS */ -#endif /* CONFIG_HARD_I2C */ diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 29bda85..d2c2515 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o +COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o diff --git a/drivers/i2c/ppc4xx_i2c.c b/drivers/i2c/ppc4xx_i2c.c new file mode 100644 index 0000000..9b86187 --- /dev/null +++ b/drivers/i2c/ppc4xx_i2c.c @@ -0,0 +1,439 @@ +/* + * (C) Copyright 2007-2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * based on work by Anne Sophie Harnois + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include <4xx_i2c.h> +#include +#include + +#ifdef CONFIG_HARD_I2C + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_I2C_MULTI_BUS) +/* + * Initialize the bus pointer to whatever one the SPD EEPROM is on. + * Default is bus 0. This is necessary because the DDR initialization + * runs from ROM, and we can't switch buses because we can't modify + * the global variables. + */ +#ifndef CONFIG_SYS_SPD_BUS_NUM +#define CONFIG_SYS_SPD_BUS_NUM 0 +#endif +static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = + CONFIG_SYS_SPD_BUS_NUM; +#endif /* CONFIG_I2C_MULTI_BUS */ + +static void _i2c_bus_reset(void) +{ + struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; + int i; + u8 dc; + + /* Reset status register */ + /* write 1 in SCMP and IRQA to clear these fields */ + out_8(&i2c->sts, 0x0A); + + /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ + out_8(&i2c->extsts, 0x8F); + + /* Place chip in the reset state */ + out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST); + + /* Check if bus is free */ + dc = in_8(&i2c->directcntl); + if (!DIRCTNL_FREE(dc)){ + /* Try to set bus free state */ + out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC); + + /* Wait until we regain bus control */ + for (i = 0; i < 100; ++i) { + dc = in_8(&i2c->directcntl); + if (DIRCTNL_FREE(dc)) + break; + + /* Toggle SCL line */ + dc ^= IIC_DIRCNTL_SCC; + out_8(&i2c->directcntl, dc); + udelay(10); + dc ^= IIC_DIRCNTL_SCC; + out_8(&i2c->directcntl, dc); + } + } + + /* Remove reset */ + out_8(&i2c->xtcntlss, 0); +} + +void i2c_init(int speed, int slaveaddr) +{ + struct ppc4xx_i2c *i2c; + int val, divisor; + int bus; + +#ifdef CONFIG_SYS_I2C_INIT_BOARD + /* + * Call board specific i2c bus reset routine before accessing the + * environment, which might be in a chip on that bus. For details + * about this problem see doc/I2C_Edge_Conditions. + */ + i2c_init_board(); +#endif + + for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) { + I2C_SET_BUS(bus); + + /* Set i2c pointer after calling I2C_SET_BUS() */ + i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; + + /* Handle possible failed I2C state */ + /* FIXME: put this into i2c_init_board()? */ + _i2c_bus_reset(); + + /* clear lo master address */ + out_8(&i2c->lmadr, 0); + + /* clear hi master address */ + out_8(&i2c->hmadr, 0); + + /* clear lo slave address */ + out_8(&i2c->lsadr, 0); + + /* clear hi slave address */ + out_8(&i2c->hsadr, 0); + + /* Clock divide Register */ + /* set divisor according to freq_opb */ + divisor = (get_OPB_freq() - 1) / 10000000; + if (divisor == 0) + divisor = 1; + out_8(&i2c->clkdiv, divisor); + + /* no interrupts */ + out_8(&i2c->intrmsk, 0); + + /* clear transfer count */ + out_8(&i2c->xfrcnt, 0); + + /* clear extended control & stat */ + /* write 1 in SRC SRS SWC SWS to clear these fields */ + out_8(&i2c->xtcntlss, 0xF0); + + /* Mode Control Register + Flush Slave/Master data buffer */ + out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); + + val = in_8(&i2c->mdcntl); + + /* Ignore General Call, slave transfers are ignored, + * disable interrupts, exit unknown bus state, enable hold + * SCL 100kHz normaly or FastMode for 400kHz and above + */ + + val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL; + if (speed >= 400000) + val |= IIC_MDCNTL_FSM; + out_8(&i2c->mdcntl, val); + + /* clear control reg */ + out_8(&i2c->cntl, 0x00); + } + + /* set to SPD bus as default bus upon powerup */ + I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); +} + +/* + * This code tries to use the features of the 405GP i2c + * controller. It will transfer up to 4 bytes in one pass + * on the loop. It only does out_8((u8 *)lbz) to the buffer when it + * is possible to do out16(lhz) transfers. + * + * cmd_type is 0 for write 1 for read. + * + * addr_len can take any value from 0-255, it is only limited + * by the char, we could make it larger if needed. If it is + * 0 we skip the address write cycle. + * + * Typical case is a Write of an addr followd by a Read. The + * IBM FAQ does not cover this. On the last byte of the write + * we don't set the creg CHT bit, and on the first bytes of the + * read we set the RPST bit. + * + * It does not support address only transfers, there must be + * a data part. If you want to write the address yourself, put + * it in the data pointer. + * + * It does not support transfer to/from address 0. + * + * It does not check XFRCNT. + */ +static int i2c_transfer(unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], + unsigned short data_len) +{ + struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; + u8 *ptr; + int reading; + int tran, cnt; + int result; + int status; + int i; + u8 creg; + + if (data == 0 || data_len == 0) { + /* Don't support data transfer of no length or to address 0 */ + printf( "i2c_transfer: bad call\n" ); + return IIC_NOK; + } + if (addr && addr_len) { + ptr = addr; + cnt = addr_len; + reading = 0; + } else { + ptr = data; + cnt = data_len; + reading = cmd_type; + } + + /* Clear Stop Complete Bit */ + out_8(&i2c->sts, IIC_STS_SCMP); + + /* Check init */ + i = 10; + do { + /* Get status */ + status = in_8(&i2c->sts); + i--; + } while ((status & IIC_STS_PT) && (i > 0)); + + if (status & IIC_STS_PT) { + result = IIC_NOK_TOUT; + return(result); + } + + /* flush the Master/Slave Databuffers */ + out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) | + IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB); + + /* need to wait 4 OPB clocks? code below should take that long */ + + /* 7-bit adressing */ + out_8(&i2c->hmadr, 0); + out_8(&i2c->lmadr, chip); + + tran = 0; + result = IIC_OK; + creg = 0; + + while (tran != cnt && (result == IIC_OK)) { + int bc,j; + + /* + * Control register = + * Normal transfer, 7-bits adressing, Transfer up to + * bc bytes, Normal start, Transfer is a sequence of transfers + */ + creg |= IIC_CNTL_PT; + + bc = (cnt - tran) > 4 ? 4 : cnt - tran; + creg |= (bc - 1) << 4; + /* if the real cmd type is write continue trans */ + if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt)) + creg |= IIC_CNTL_CHT; + + if (reading) { + creg |= IIC_CNTL_READ; + } else { + for(j = 0; j < bc; j++) { + /* Set buffer */ + out_8(&i2c->mdbuf, ptr[tran + j]); + } + } + out_8(&i2c->cntl, creg); + + /* + * Transfer is in progress + * we have to wait for upto 5 bytes of data + * 1 byte chip address+r/w bit then bc bytes + * of data. + * udelay(10) is 1 bit time at 100khz + * Doubled for slop. 20 is too small. + */ + i = 2 * 5 * 8; + do { + /* Get status */ + status = in_8(&i2c->sts); + udelay(10); + i--; + } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && + (i > 0)); + + if (status & IIC_STS_ERR) { + result = IIC_NOK; + status = in_8(&i2c->extsts); + /* Lost arbitration? */ + if (status & IIC_EXTSTS_LA) + result = IIC_NOK_LA; + /* Incomplete transfer? */ + if (status & IIC_EXTSTS_ICT) + result = IIC_NOK_ICT; + /* Transfer aborted? */ + if (status & IIC_EXTSTS_XFRA) + result = IIC_NOK_XFRA; + } else if ( status & IIC_STS_PT) { + result = IIC_NOK_TOUT; + } + + /* Command is reading => get buffer */ + if ((reading) && (result == IIC_OK)) { + /* Are there data in buffer */ + if (status & IIC_STS_MDBS) { + /* + * even if we have data we have to wait 4OPB + * clocks for it to hit the front of the FIFO, + * after that we can just read. We should check + * XFCNT here and if the FIFO is full there is + * no need to wait. + */ + udelay(1); + for (j = 0; j < bc; j++) + ptr[tran + j] = in_8(&i2c->mdbuf); + } else + result = IIC_NOK_DATA; + } + creg = 0; + tran += bc; + if (ptr == addr && tran == cnt) { + ptr = data; + cnt = data_len; + tran = 0; + reading = cmd_type; + if (reading) + creg = IIC_CNTL_RPST; + } + } + return result; +} + +int i2c_probe(uchar chip) +{ + uchar buf[1]; + + buf[0] = 0; + + /* + * What is needed is to send the chip address and verify that the + * address was ed (i.e. there was a chip at that address which + * drove the data line low). + */ + return (i2c_transfer(1, chip << 1, 0, 0, buf, 1) != 0); +} + +static int ppc4xx_i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, + int len, int read) +{ + uchar xaddr[4]; + int ret; + + if (alen > 4) { + printf("I2C: addr len %d not supported\n", alen); + return 1; + } + + if (alen > 0) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + + +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if (alen > 0) + chip |= ((addr >> (alen * 8)) & + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); +#endif + if ((ret = i2c_transfer(read, chip << 1, &xaddr[4 - alen], alen, + buffer, len)) != 0) { + if (gd->have_console) { + printf("I2C %s: failed %d\n", + read ? "read" : "write", ret); + } + + return 1; + } + + return 0; +} + +int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 1); +} + +int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 0); +} + +#if defined(CONFIG_I2C_MULTI_BUS) +/* + * Functions for multiple I2C bus handling + */ +unsigned int i2c_get_bus_num(void) +{ + return i2c_bus_num; +} + +int i2c_set_bus_num(unsigned int bus) +{ + if (bus >= CONFIG_SYS_MAX_I2C_BUS) + return -1; + + i2c_bus_num = bus; + + return 0; +} +#endif /* CONFIG_I2C_MULTI_BUS */ +#endif /* CONFIG_HARD_I2C */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 5cb0f1e..4cb8052 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -244,6 +244,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index e3e6e75..cdba81d 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -173,6 +173,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index ae8494d..2b6786b 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -224,6 +224,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 5c88c47..9221211 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -207,6 +207,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index d131aea..3e7020d 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -256,6 +256,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 07c4e35..d3000f6 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -283,6 +283,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index c78552b..d376344 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -259,6 +259,7 @@ * I2C EEPROM (CAT24WC32) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 59e0778..07acab0 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -278,6 +278,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index b2679e5..5b50bcf 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -189,6 +189,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 96bf161..9ab30ec 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -65,6 +65,7 @@ #define CONFIG_ETHADDR 00:40:a6:80:14:5 */ #define CONFIG_HARD_I2C 1 /* hardware support for i2c */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SDRAM_BANK0 1 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 49ecb6f..4423f2a 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -174,6 +174,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DU405.h b/include/configs/DU405.h index cfb3023..8f1fc78 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -212,6 +212,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 65dc235..830466f 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -169,6 +169,7 @@ */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_I2C_MULTI_BUS 1 diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 023f33e..e07f9a1 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -54,6 +54,7 @@ #endif /* total size of a X1240 is 2048 bytes */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/G2000.h b/include/configs/G2000.h index 6819c3e..d2883eb 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -295,6 +295,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 9233523..01e0bc6 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -331,6 +331,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #if 0 /* test-only */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #else diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index ea502d4..8c6d5ed 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -244,6 +244,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 80c70e4..98f5661 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -217,6 +217,7 @@ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 4b67c94..49a7378 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -132,6 +132,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C hardware support */ #undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 518173a..e7429dd 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -194,6 +194,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C hardware support */ #undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 7ac9342..7e6484e 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -97,6 +97,7 @@ ***************************************************************/ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 860ec52..55471af 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -210,6 +210,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index b2e2d41..1424713 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -208,6 +208,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 4e39799..0d443ea 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -204,6 +204,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 962b29e..3e57c0b 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -86,6 +86,7 @@ * The Atmel EEPROM uses 16Bit addressing. ***************************************************************/ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 3d59454..f917eb5 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -278,6 +278,7 @@ * I2C EEPROM (24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 87ea7b6..00a12fb 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -235,6 +235,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 7198632..2c048dd 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -215,6 +215,7 @@ * I2C EEPROM (24W16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 89799af..c2fb56c 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -226,6 +226,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 8e9d928..44f03dc 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -414,6 +414,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 38a1d0d..9c91fcc 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -277,6 +277,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 4717869..871e4c3 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -203,6 +203,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index c017915..f06bfe5 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -273,6 +273,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 1d4ad13..be8c9f8 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -280,6 +280,7 @@ * I2C EEPROM (ATMEL 24C04N) */ #define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 5c281a1..be9ac62 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -241,6 +241,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/XPEDITE1000.h b/include/configs/XPEDITE1000.h index 658e947..cf39aea 100644 --- a/include/configs/XPEDITE1000.h +++ b/include/configs/XPEDITE1000.h @@ -141,6 +141,7 @@ extern void out32(unsigned int, unsigned long); * I2C */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7f #define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 0fed9ad..f2392f6 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -118,6 +118,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 8cd97b8..13a941e 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -40,6 +40,7 @@ * I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* diff --git a/include/configs/csb272.h b/include/configs/csb272.h index aed6f50..9ded330 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -171,6 +171,7 @@ * */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 24b961f..71eb083 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -170,6 +170,7 @@ * */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ diff --git a/include/configs/korat.h b/include/configs/korat.h index 026dd08..f95df68 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -153,6 +153,7 @@ */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 011dd5c..6461124 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -258,6 +258,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h index 4bed7ae..cb7efe7 100644 --- a/include/configs/netstal-common.h +++ b/include/configs/netstal-common.h @@ -42,6 +42,7 @@ * I2C */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 729ca6a..d6b9207 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -92,6 +92,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 000ae5c..1f744b8 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -138,6 +138,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index b08dcd4..403837e 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -150,6 +150,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index 242f42f..429b11c 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -166,6 +166,7 @@ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/sc3.h b/include/configs/sc3.h index a5eca39..d00f248 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -251,6 +251,7 @@ */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define I2C_INIT #define I2C_ACTIVE 0 diff --git a/include/configs/zeus.h b/include/configs/zeus.h index 1a77c71..3b2aede 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -167,6 +167,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F -- cgit v1.1