From 7bc8768039948e50cc149bea2ec214bde3245c4a Mon Sep 17 00:00:00 2001 From: trix Date: Sat, 10 Apr 2010 12:46:49 -0500 Subject: ARM Update mach-types Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 85b3cce880a19e78286570d5fd004cc3cac06f57 Signed-off-by: Tom Rix --- arch/arm/include/asm/mach-types.h | 986 +++++++++++++++++++++++++++++++++++++- 1 file changed, 974 insertions(+), 12 deletions(-) diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 4622557..b33e97b 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -2659,7 +2659,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_AQUILA 2676 #define MACH_TYPE_SPARK_SLS_HW2 2677 #define MACH_TYPE_ESATA_SHEEVAPLUG 2678 -#define MACH_TYPE_SURF7X30 2679 +#define MACH_TYPE_MSM7X30_SURF 2679 #define MACH_TYPE_MICRO2440 2680 #define MACH_TYPE_AM2440 2681 #define MACH_TYPE_TQ2440 2682 @@ -2693,12 +2693,86 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_QSD8X50_FFA 2710 #define MACH_TYPE_QSD8X50A_SURF 2711 #define MACH_TYPE_QSD8X50A_FFA 2712 -#define MACH_TYPE_XGCP10 2713 +#define MACH_TYPE_ADX_XGCP10 2713 #define MACH_TYPE_MCGWUMTS2A 2714 #define MACH_TYPE_MOBIKT 2715 #define MACH_TYPE_MX53_EVK 2716 #define MACH_TYPE_IGEP0030 2717 #define MACH_TYPE_AXELL_H40_H50_CTRL 2718 +#define MACH_TYPE_DTCOMMOD 2719 +#define MACH_TYPE_GOULD 2720 +#define MACH_TYPE_SIBERIA 2721 +#define MACH_TYPE_SBC3530 2722 +#define MACH_TYPE_QARM 2723 +#define MACH_TYPE_MIPS 2724 +#define MACH_TYPE_MX27GRB 2725 +#define MACH_TYPE_SBC8100 2726 +#define MACH_TYPE_SAARB 2727 +#define MACH_TYPE_OMAP3MINI 2728 +#define MACH_TYPE_CNMBOOK7SE 2729 +#define MACH_TYPE_CATAN 2730 +#define MACH_TYPE_HARMONY 2731 +#define MACH_TYPE_TONGA 2732 +#define MACH_TYPE_CYBOOK_ORIZON 2733 +#define MACH_TYPE_HTCRHODIUMCDMA 2734 +#define MACH_TYPE_EPC_G45 2735 +#define MACH_TYPE_EPC_LPC3250 2736 +#define MACH_TYPE_MXC91341EVB 2737 +#define MACH_TYPE_RTW1000 2738 +#define MACH_TYPE_BOBCAT 2739 +#define MACH_TYPE_TRIZEPS6 2740 +#define MACH_TYPE_MSM7X30_FLUID 2741 +#define MACH_TYPE_NEDAP9263 2742 +#define MACH_TYPE_NETGEAR_MS2110 2743 +#define MACH_TYPE_BMX 2744 +#define MACH_TYPE_NETSTREAM 2745 +#define MACH_TYPE_VPNEXT_RCU 2746 +#define MACH_TYPE_VPNEXT_MPU 2747 +#define MACH_TYPE_BCMRING_TABLET_V1 2748 +#define MACH_TYPE_SGARM10 2749 +#define MACH_TYPE_CM_T3517 2750 +#define MACH_TYPE_OMAP3_CPS 2751 +#define MACH_TYPE_AXAR1500_RECEIVER 2752 +#define MACH_TYPE_WBD222 2753 +#define MACH_TYPE_MT65XX 2754 +#define MACH_TYPE_MSM8X60_SURF 2755 +#define MACH_TYPE_MSM8X60_SIM 2756 +#define MACH_TYPE_VMC300 2757 +#define MACH_TYPE_TCC8000_SDK 2758 +#define MACH_TYPE_NANOS 2759 +#define MACH_TYPE_STAMP9G10 2760 +#define MACH_TYPE_STAMP9G45 2761 +#define MACH_TYPE_H6053 2762 +#define MACH_TYPE_SMINT01 2763 +#define MACH_TYPE_PRTLVT2 2764 +#define MACH_TYPE_AP420 2765 +#define MACH_TYPE_HTCSHIFT 2766 +#define MACH_TYPE_DAVINCI_DM365_FC 2767 +#define MACH_TYPE_MSM8X55_SURF 2768 +#define MACH_TYPE_MSM8X55_FFA 2769 +#define MACH_TYPE_ESL_VAMANA 2770 +#define MACH_TYPE_SBC35 2771 +#define MACH_TYPE_MPX6446 2772 +#define MACH_TYPE_OREO_CONTROLLER 2773 +#define MACH_TYPE_KOPIN_MODELS 2774 +#define MACH_TYPE_TTC_VISION2 2775 +#define MACH_TYPE_CNS3420VB 2776 +#define MACH_TYPE_LPC2 2777 +#define MACH_TYPE_OLYMPUS 2778 +#define MACH_TYPE_VORTEX 2779 +#define MACH_TYPE_S5PC200 2780 +#define MACH_TYPE_ECUCORE_9263 2781 +#define MACH_TYPE_SMDKC200 2782 +#define MACH_TYPE_EMSISO_SX27 2783 +#define MACH_TYPE_APX_SOM9G45_EK 2784 +#define MACH_TYPE_SONGSHAN 2785 +#define MACH_TYPE_TIANSHAN 2786 +#define MACH_TYPE_VPX500 2787 +#define MACH_TYPE_AM3517SAM 2788 +#define MACH_TYPE_SKAT91_SIM508 2789 +#define MACH_TYPE_SKAT91_S3E 2790 +#define MACH_TYPE_OMAP4_PANDA 2791 +#define MACH_TYPE_DF7220 2792 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -18343,9 +18417,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_HYNET_INE # endif -# define machine_is_hynet_ine() (machine_arch_type == MACH_TYPE_HYNET_INE) +# define machine_is_argonst_foundation() (machine_arch_type == MACH_TYPE_HYNET_INE) #else -# define machine_is_hynet_ine() (0) +# define machine_is_argonst_foundation() (0) #endif #ifdef CONFIG_MACH_HYNET_APP @@ -30211,9 +30285,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_OREO # endif -# define machine_is_oreo() (machine_arch_type == MACH_TYPE_OREO) +# define machine_is_oreo_camera() (machine_arch_type == MACH_TYPE_OREO) #else -# define machine_is_oreo() (0) +# define machine_is_oreo_camera() (0) #endif #ifdef CONFIG_MACH_SMDK6442 @@ -34464,14 +34538,14 @@ extern unsigned int __machine_arch_type; # define machine_is_sheeva_esata() (0) #endif -#ifdef CONFIG_MACH_SURF7X30 +#ifdef CONFIG_MACH_MSM7X30_SURF # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_SURF7X30 +# define machine_arch_type MACH_TYPE_MSM7X30_SURF # endif -# define machine_is_msm7x30_surf() (machine_arch_type == MACH_TYPE_SURF7X30) +# define machine_is_msm7x30_surf() (machine_arch_type == MACH_TYPE_MSM7X30_SURF) #else # define machine_is_msm7x30_surf() (0) #endif @@ -34872,14 +34946,14 @@ extern unsigned int __machine_arch_type; # define machine_is_qsd8x50a_ffa() (0) #endif -#ifdef CONFIG_MACH_XGCP10 +#ifdef CONFIG_MACH_ADX_XGCP10 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_XGCP10 +# define machine_arch_type MACH_TYPE_ADX_XGCP10 # endif -# define machine_is_adx_xgcp10() (machine_arch_type == MACH_TYPE_XGCP10) +# define machine_is_adx_xgcp10() (machine_arch_type == MACH_TYPE_ADX_XGCP10) #else # define machine_is_adx_xgcp10() (0) #endif @@ -34944,6 +35018,894 @@ extern unsigned int __machine_arch_type; # define machine_is_axell_h40_h50_ctrl() (0) #endif +#ifdef CONFIG_MACH_DTCOMMOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DTCOMMOD +# endif +# define machine_is_dtcommod() (machine_arch_type == MACH_TYPE_DTCOMMOD) +#else +# define machine_is_dtcommod() (0) +#endif + +#ifdef CONFIG_MACH_GOULD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GOULD +# endif +# define machine_is_gould() (machine_arch_type == MACH_TYPE_GOULD) +#else +# define machine_is_gould() (0) +#endif + +#ifdef CONFIG_MACH_SIBERIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIBERIA +# endif +# define machine_is_siberia() (machine_arch_type == MACH_TYPE_SIBERIA) +#else +# define machine_is_siberia() (0) +#endif + +#ifdef CONFIG_MACH_SBC3530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC3530 +# endif +# define machine_is_sbc3530() (machine_arch_type == MACH_TYPE_SBC3530) +#else +# define machine_is_sbc3530() (0) +#endif + +#ifdef CONFIG_MACH_QARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QARM +# endif +# define machine_is_qarm() (machine_arch_type == MACH_TYPE_QARM) +#else +# define machine_is_qarm() (0) +#endif + +#ifdef CONFIG_MACH_MIPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIPS +# endif +# define machine_is_mips() (machine_arch_type == MACH_TYPE_MIPS) +#else +# define machine_is_mips() (0) +#endif + +#ifdef CONFIG_MACH_MX27GRB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27GRB +# endif +# define machine_is_mx27grb() (machine_arch_type == MACH_TYPE_MX27GRB) +#else +# define machine_is_mx27grb() (0) +#endif + +#ifdef CONFIG_MACH_SBC8100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC8100 +# endif +# define machine_is_sbc8100() (machine_arch_type == MACH_TYPE_SBC8100) +#else +# define machine_is_sbc8100() (0) +#endif + +#ifdef CONFIG_MACH_SAARB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAARB +# endif +# define machine_is_saarb() (machine_arch_type == MACH_TYPE_SAARB) +#else +# define machine_is_saarb() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3MINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3MINI +# endif +# define machine_is_omap3mini() (machine_arch_type == MACH_TYPE_OMAP3MINI) +#else +# define machine_is_omap3mini() (0) +#endif + +#ifdef CONFIG_MACH_CNMBOOK7SE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CNMBOOK7SE +# endif +# define machine_is_cnmbook7se() (machine_arch_type == MACH_TYPE_CNMBOOK7SE) +#else +# define machine_is_cnmbook7se() (0) +#endif + +#ifdef CONFIG_MACH_CATAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATAN +# endif +# define machine_is_catan() (machine_arch_type == MACH_TYPE_CATAN) +#else +# define machine_is_catan() (0) +#endif + +#ifdef CONFIG_MACH_HARMONY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HARMONY +# endif +# define machine_is_harmony() (machine_arch_type == MACH_TYPE_HARMONY) +#else +# define machine_is_harmony() (0) +#endif + +#ifdef CONFIG_MACH_TONGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TONGA +# endif +# define machine_is_tonga() (machine_arch_type == MACH_TYPE_TONGA) +#else +# define machine_is_tonga() (0) +#endif + +#ifdef CONFIG_MACH_CYBOOK_ORIZON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBOOK_ORIZON +# endif +# define machine_is_cybook_orizon() (machine_arch_type == MACH_TYPE_CYBOOK_ORIZON) +#else +# define machine_is_cybook_orizon() (0) +#endif + +#ifdef CONFIG_MACH_HTCRHODIUMCDMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRHODIUMCDMA +# endif +# define machine_is_htcrhodiumcdma() (machine_arch_type == MACH_TYPE_HTCRHODIUMCDMA) +#else +# define machine_is_htcrhodiumcdma() (0) +#endif + +#ifdef CONFIG_MACH_EPC_G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPC_G45 +# endif +# define machine_is_epc_g45() (machine_arch_type == MACH_TYPE_EPC_G45) +#else +# define machine_is_epc_g45() (0) +#endif + +#ifdef CONFIG_MACH_EPC_LPC3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPC_LPC3250 +# endif +# define machine_is_epc_lpc3250() (machine_arch_type == MACH_TYPE_EPC_LPC3250) +#else +# define machine_is_epc_lpc3250() (0) +#endif + +#ifdef CONFIG_MACH_MXC91341EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC91341EVB +# endif +# define machine_is_mxc91341evb() (machine_arch_type == MACH_TYPE_MXC91341EVB) +#else +# define machine_is_mxc91341evb() (0) +#endif + +#ifdef CONFIG_MACH_RTW1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RTW1000 +# endif +# define machine_is_rtw1000() (machine_arch_type == MACH_TYPE_RTW1000) +#else +# define machine_is_rtw1000() (0) +#endif + +#ifdef CONFIG_MACH_BOBCAT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BOBCAT +# endif +# define machine_is_bobcat() (machine_arch_type == MACH_TYPE_BOBCAT) +#else +# define machine_is_bobcat() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS6 +# endif +# define machine_is_trizeps6() (machine_arch_type == MACH_TYPE_TRIZEPS6) +#else +# define machine_is_trizeps6() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X30_FLUID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X30_FLUID +# endif +# define machine_is_msm7x30_fluid() (machine_arch_type == MACH_TYPE_MSM7X30_FLUID) +#else +# define machine_is_msm7x30_fluid() (0) +#endif + +#ifdef CONFIG_MACH_NEDAP9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEDAP9263 +# endif +# define machine_is_nedap9263() (machine_arch_type == MACH_TYPE_NEDAP9263) +#else +# define machine_is_nedap9263() (0) +#endif + +#ifdef CONFIG_MACH_NETGEAR_MS2110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETGEAR_MS2110 +# endif +# define machine_is_netgear_ms2110() (machine_arch_type == MACH_TYPE_NETGEAR_MS2110) +#else +# define machine_is_netgear_ms2110() (0) +#endif + +#ifdef CONFIG_MACH_BMX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BMX +# endif +# define machine_is_bmx() (machine_arch_type == MACH_TYPE_BMX) +#else +# define machine_is_bmx() (0) +#endif + +#ifdef CONFIG_MACH_NETSTREAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSTREAM +# endif +# define machine_is_netstream() (machine_arch_type == MACH_TYPE_NETSTREAM) +#else +# define machine_is_netstream() (0) +#endif + +#ifdef CONFIG_MACH_VPNEXT_RCU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPNEXT_RCU +# endif +# define machine_is_vpnext_rcu() (machine_arch_type == MACH_TYPE_VPNEXT_RCU) +#else +# define machine_is_vpnext_rcu() (0) +#endif + +#ifdef CONFIG_MACH_VPNEXT_MPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPNEXT_MPU +# endif +# define machine_is_vpnext_mpu() (machine_arch_type == MACH_TYPE_VPNEXT_MPU) +#else +# define machine_is_vpnext_mpu() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_TABLET_V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_TABLET_V1 +# endif +# define machine_is_bcmring_tablet_v1() (machine_arch_type == MACH_TYPE_BCMRING_TABLET_V1) +#else +# define machine_is_bcmring_tablet_v1() (0) +#endif + +#ifdef CONFIG_MACH_SGARM10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGARM10 +# endif +# define machine_is_sgarm10() (machine_arch_type == MACH_TYPE_SGARM10) +#else +# define machine_is_sgarm10() (0) +#endif + +#ifdef CONFIG_MACH_CM_T3517 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_T3517 +# endif +# define machine_is_cm_t3517() (machine_arch_type == MACH_TYPE_CM_T3517) +#else +# define machine_is_cm_t3517() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_CPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_CPS +# endif +# define machine_is_omap3_cps() (machine_arch_type == MACH_TYPE_OMAP3_CPS) +#else +# define machine_is_omap3_cps() (0) +#endif + +#ifdef CONFIG_MACH_AXAR1500_RECEIVER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXAR1500_RECEIVER +# endif +# define machine_is_axar1500_receiver() (machine_arch_type == MACH_TYPE_AXAR1500_RECEIVER) +#else +# define machine_is_axar1500_receiver() (0) +#endif + +#ifdef CONFIG_MACH_WBD222 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WBD222 +# endif +# define machine_is_wbd222() (machine_arch_type == MACH_TYPE_WBD222) +#else +# define machine_is_wbd222() (0) +#endif + +#ifdef CONFIG_MACH_MT65XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MT65XX +# endif +# define machine_is_mt65xx() (machine_arch_type == MACH_TYPE_MT65XX) +#else +# define machine_is_mt65xx() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_SURF +# endif +# define machine_is_msm8x60_surf() (machine_arch_type == MACH_TYPE_MSM8X60_SURF) +#else +# define machine_is_msm8x60_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_SIM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_SIM +# endif +# define machine_is_msm8x60_sim() (machine_arch_type == MACH_TYPE_MSM8X60_SIM) +#else +# define machine_is_msm8x60_sim() (0) +#endif + +#ifdef CONFIG_MACH_VMC300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMC300 +# endif +# define machine_is_vmc300() (machine_arch_type == MACH_TYPE_VMC300) +#else +# define machine_is_vmc300() (0) +#endif + +#ifdef CONFIG_MACH_TCC8000_SDK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TCC8000_SDK +# endif +# define machine_is_tcc8000_sdk() (machine_arch_type == MACH_TYPE_TCC8000_SDK) +#else +# define machine_is_tcc8000_sdk() (0) +#endif + +#ifdef CONFIG_MACH_NANOS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NANOS +# endif +# define machine_is_nanos() (machine_arch_type == MACH_TYPE_NANOS) +#else +# define machine_is_nanos() (0) +#endif + +#ifdef CONFIG_MACH_STAMP9G10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAMP9G10 +# endif +# define machine_is_stamp9g10() (machine_arch_type == MACH_TYPE_STAMP9G10) +#else +# define machine_is_stamp9g10() (0) +#endif + +#ifdef CONFIG_MACH_STAMP9G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAMP9G45 +# endif +# define machine_is_stamp9g45() (machine_arch_type == MACH_TYPE_STAMP9G45) +#else +# define machine_is_stamp9g45() (0) +#endif + +#ifdef CONFIG_MACH_H6053 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H6053 +# endif +# define machine_is_h6053() (machine_arch_type == MACH_TYPE_H6053) +#else +# define machine_is_h6053() (0) +#endif + +#ifdef CONFIG_MACH_SMINT01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMINT01 +# endif +# define machine_is_smint01() (machine_arch_type == MACH_TYPE_SMINT01) +#else +# define machine_is_smint01() (0) +#endif + +#ifdef CONFIG_MACH_PRTLVT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRTLVT2 +# endif +# define machine_is_prtlvt2() (machine_arch_type == MACH_TYPE_PRTLVT2) +#else +# define machine_is_prtlvt2() (0) +#endif + +#ifdef CONFIG_MACH_AP420 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AP420 +# endif +# define machine_is_ap420() (machine_arch_type == MACH_TYPE_AP420) +#else +# define machine_is_ap420() (0) +#endif + +#ifdef CONFIG_MACH_HTCSHIFT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCSHIFT +# endif +# define machine_is_htcclio() (machine_arch_type == MACH_TYPE_HTCSHIFT) +#else +# define machine_is_htcclio() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM365_FC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM365_FC +# endif +# define machine_is_davinci_dm365_fc() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_FC) +#else +# define machine_is_davinci_dm365_fc() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_SURF +# endif +# define machine_is_msm8x55_surf() (machine_arch_type == MACH_TYPE_MSM8X55_SURF) +#else +# define machine_is_msm8x55_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_FFA +# endif +# define machine_is_msm8x55_ffa() (machine_arch_type == MACH_TYPE_MSM8X55_FFA) +#else +# define machine_is_msm8x55_ffa() (0) +#endif + +#ifdef CONFIG_MACH_ESL_VAMANA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_VAMANA +# endif +# define machine_is_esl_vamana() (machine_arch_type == MACH_TYPE_ESL_VAMANA) +#else +# define machine_is_esl_vamana() (0) +#endif + +#ifdef CONFIG_MACH_SBC35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC35 +# endif +# define machine_is_sbc35() (machine_arch_type == MACH_TYPE_SBC35) +#else +# define machine_is_sbc35() (0) +#endif + +#ifdef CONFIG_MACH_MPX6446 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPX6446 +# endif +# define machine_is_mpx6446() (machine_arch_type == MACH_TYPE_MPX6446) +#else +# define machine_is_mpx6446() (0) +#endif + +#ifdef CONFIG_MACH_OREO_CONTROLLER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OREO_CONTROLLER +# endif +# define machine_is_oreo_controller() (machine_arch_type == MACH_TYPE_OREO_CONTROLLER) +#else +# define machine_is_oreo_controller() (0) +#endif + +#ifdef CONFIG_MACH_KOPIN_MODELS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KOPIN_MODELS +# endif +# define machine_is_kopin_models() (machine_arch_type == MACH_TYPE_KOPIN_MODELS) +#else +# define machine_is_kopin_models() (0) +#endif + +#ifdef CONFIG_MACH_TTC_VISION2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TTC_VISION2 +# endif +# define machine_is_ttc_vision2() (machine_arch_type == MACH_TYPE_TTC_VISION2) +#else +# define machine_is_ttc_vision2() (0) +#endif + +#ifdef CONFIG_MACH_CNS3420VB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CNS3420VB +# endif +# define machine_is_cns3420vb() (machine_arch_type == MACH_TYPE_CNS3420VB) +#else +# define machine_is_cns3420vb() (0) +#endif + +#ifdef CONFIG_MACH_LPC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC2 +# endif +# define machine_is_lpc2() (machine_arch_type == MACH_TYPE_LPC2) +#else +# define machine_is_lpc2() (0) +#endif + +#ifdef CONFIG_MACH_OLYMPUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OLYMPUS +# endif +# define machine_is_olympus() (machine_arch_type == MACH_TYPE_OLYMPUS) +#else +# define machine_is_olympus() (0) +#endif + +#ifdef CONFIG_MACH_VORTEX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VORTEX +# endif +# define machine_is_vortex() (machine_arch_type == MACH_TYPE_VORTEX) +#else +# define machine_is_vortex() (0) +#endif + +#ifdef CONFIG_MACH_S5PC200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5PC200 +# endif +# define machine_is_s5pc200() (machine_arch_type == MACH_TYPE_S5PC200) +#else +# define machine_is_s5pc200() (0) +#endif + +#ifdef CONFIG_MACH_ECUCORE_9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECUCORE_9263 +# endif +# define machine_is_ecucore_9263() (machine_arch_type == MACH_TYPE_ECUCORE_9263) +#else +# define machine_is_ecucore_9263() (0) +#endif + +#ifdef CONFIG_MACH_SMDKC200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKC200 +# endif +# define machine_is_smdkc200() (machine_arch_type == MACH_TYPE_SMDKC200) +#else +# define machine_is_smdkc200() (0) +#endif + +#ifdef CONFIG_MACH_EMSISO_SX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMSISO_SX27 +# endif +# define machine_is_emsiso_sx27() (machine_arch_type == MACH_TYPE_EMSISO_SX27) +#else +# define machine_is_emsiso_sx27() (0) +#endif + +#ifdef CONFIG_MACH_APX_SOM9G45_EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APX_SOM9G45_EK +# endif +# define machine_is_apx_som9g45_ek() (machine_arch_type == MACH_TYPE_APX_SOM9G45_EK) +#else +# define machine_is_apx_som9g45_ek() (0) +#endif + +#ifdef CONFIG_MACH_SONGSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SONGSHAN +# endif +# define machine_is_songshan() (machine_arch_type == MACH_TYPE_SONGSHAN) +#else +# define machine_is_songshan() (0) +#endif + +#ifdef CONFIG_MACH_TIANSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIANSHAN +# endif +# define machine_is_tianshan() (machine_arch_type == MACH_TYPE_TIANSHAN) +#else +# define machine_is_tianshan() (0) +#endif + +#ifdef CONFIG_MACH_VPX500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPX500 +# endif +# define machine_is_vpx500() (machine_arch_type == MACH_TYPE_VPX500) +#else +# define machine_is_vpx500() (0) +#endif + +#ifdef CONFIG_MACH_AM3517SAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AM3517SAM +# endif +# define machine_is_am3517sam() (machine_arch_type == MACH_TYPE_AM3517SAM) +#else +# define machine_is_am3517sam() (0) +#endif + +#ifdef CONFIG_MACH_SKAT91_SIM508 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKAT91_SIM508 +# endif +# define machine_is_skat91_sim508() (machine_arch_type == MACH_TYPE_SKAT91_SIM508) +#else +# define machine_is_skat91_sim508() (0) +#endif + +#ifdef CONFIG_MACH_SKAT91_S3E +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKAT91_S3E +# endif +# define machine_is_skat91_s3e() (machine_arch_type == MACH_TYPE_SKAT91_S3E) +#else +# define machine_is_skat91_s3e() (0) +#endif + +#ifdef CONFIG_MACH_OMAP4_PANDA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP4_PANDA +# endif +# define machine_is_omap4_panda() (machine_arch_type == MACH_TYPE_OMAP4_PANDA) +#else +# define machine_is_omap4_panda() (0) +#endif + +#ifdef CONFIG_MACH_DF7220 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DF7220 +# endif +# define machine_is_df7220() (machine_arch_type == MACH_TYPE_DF7220) +#else +# define machine_is_df7220() (0) +#endif + /* * These have not yet been registered */ -- cgit v1.1 From e3150c77617c7d452420e6c87769b79b6671b12d Mon Sep 17 00:00:00 2001 From: Asen Dimov Date: Tue, 6 Apr 2010 16:18:04 +0300 Subject: pm9261 converted to at91 soc access Signed-off-by: Asen Dimov --- board/ronetix/pm9261/led.c | 18 ++--- board/ronetix/pm9261/pm9261.c | 152 ++++++++++++++++++++++++------------------ include/configs/pm9261.h | 68 +++++++++---------- 3 files changed, 130 insertions(+), 108 deletions(-) diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c index 396c3e7..ff21ce6 100644 --- a/board/ronetix/pm9261/led.c +++ b/board/ronetix/pm9261/led.c @@ -26,19 +26,21 @@ #include #include #include -#include +#include #include void coloured_LED_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + writel(1 << AT91SAM9261_ID_PIOC, &pmc->pcer); - at91_set_gpio_output(CONFIG_RED_LED, 1); - at91_set_gpio_output(CONFIG_GREEN_LED, 1); - at91_set_gpio_output(CONFIG_YELLOW_LED, 1); + at91_set_pio_output(CONFIG_RED_LED, 1); + at91_set_pio_output(CONFIG_GREEN_LED, 1); + at91_set_pio_output(CONFIG_YELLOW_LED, 1); - at91_set_gpio_value(CONFIG_RED_LED, 0); - at91_set_gpio_value(CONFIG_GREEN_LED, 1); - at91_set_gpio_value(CONFIG_YELLOW_LED, 1); + at91_set_pio_value(CONFIG_RED_LED, 0); + at91_set_pio_value(CONFIG_GREEN_LED, 1); + at91_set_pio_value(CONFIG_YELLOW_LED, 1); } diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 8662339..53d8c48 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -27,13 +27,14 @@ #include #include #include -#include #include #include #include #include +#include +#include #include -#include +#include #include #include #include @@ -55,39 +56,48 @@ DECLARE_GLOBAL_DATA_PTR; static void pm9261_nand_hw_init(void) { unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + + writel(1 << AT91SAM9261_ID_PIOA | + 1 << AT91SAM9261_ID_PIOC, + &pmc->pcer); /* Configure RDY/BSY */ - at91_set_gpio_input(AT91_PIN_PA16, 1); + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(AT91_PIN_PC14, 1); + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); - at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ - at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */ } #endif @@ -95,23 +105,30 @@ static void pm9261_nand_hw_init(void) #ifdef CONFIG_DRIVER_DM9000 static void pm9261_dm9000_hw_init(void) { + at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Configure SMC CS2 for DM9000 */ - at91_sys_write(AT91_SMC_SETUP(2), - AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(2), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | - AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); - at91_sys_write(AT91_SMC_CYCLE(2), - AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); - at91_sys_write(AT91_SMC_MODE(2), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | - AT91_SMC_TDF_(1)); + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8), + &smc->cs[2].pulse); + + writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16), + &smc->cs[2].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[2].mode); /* Configure Interrupt pin as input, no pull-up */ - at91_set_gpio_input(AT91_PIN_PA24, 0); + writel(1 << AT91SAM9261_ID_PIOA, &pmc->pcer); + at91_set_pio_input(AT91_PIO_PORTA, 24, 0); } #endif @@ -135,40 +152,42 @@ vidinfo_t panel_info = { void lcd_enable(void) { - at91_set_gpio_value(AT91_PIN_PA22, 0); /* power up */ + at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */ } void lcd_disable(void) { - at91_set_gpio_value(AT91_PIN_PA22, 1); /* power down */ + at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */ } static void pm9261_lcd_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ - at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ - at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ - at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ - at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ - at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ - at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ - at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ - at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ - at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ - - at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */ + at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */ + at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */ + at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */ + at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */ + at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */ + at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */ + at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */ + at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */ + + writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */ gd->fb_base = AT91SAM9261_SRAM_BASE; } @@ -222,11 +241,14 @@ void lcd_show_board_info(void) int board_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Enable Ctrlc */ console_init_f(); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + writel(1 << AT91SAM9261_ID_PIOA | + 1 << AT91SAM9261_ID_PIOC, + &pmc->pcer); /* arch number of PM9261-Board */ gd->bd->bi_arch_number = MACH_TYPE_PM9261; diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 47bb8c0..b245761 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -28,8 +28,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY - /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" @@ -51,26 +49,26 @@ /* clocks */ /* CKGR_MOR - enable main osc. */ #define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ + (AT91_PMC_MOR_MOSCEN | \ (255 << 8)) /* Main Oscillator Start-up Time */ #define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ + (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_PLLXR_OUT(3) | \ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) + (AT91_PMC_MCKR_CSS_SLOW | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2 | \ + AT91_PMC_MCKR_PLLADIV_1) /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) + (AT91_PMC_MCKR_CSS_PLLA | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2 | \ + AT91_PMC_MCKR_PLLADIV_1) /* define PDC[31:16] as DATA[31:16] */ #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 @@ -79,7 +77,7 @@ /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ #define CONFIG_SYS_MATRIX_EBICSA_VAL \ - (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC) + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ @@ -122,32 +120,32 @@ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) #define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) #define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) #define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | \ + AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ #define CONFIG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) + AT91_RSTC_CR_PROCRST | \ + AT91_RSTC_MR_ERSTL(1) | \ + AT91_RSTC_MR_ERSTL(2)) /* Disable Watchdog */ #define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xfff) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xfff)) #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 @@ -180,9 +178,9 @@ /* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PC12 -#define CONFIG_GREEN_LED AT91_PIN_PC13 -#define CONFIG_YELLOW_LED AT91_PIN_PC15 +#define CONFIG_RED_LED AT91_PIO_PORTC, 12 +#define CONFIG_GREEN_LED AT91_PIO_PORTC, 13 +#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 15 #define CONFIG_BOOTDELAY 3 @@ -236,8 +234,8 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) /* our CLE is AD21 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 16 /* NOR flash */ #define CONFIG_SYS_FLASH_CFI 1 -- cgit v1.1 From dc8cab87459d682fc272444044592d20243da2f0 Mon Sep 17 00:00:00 2001 From: Asen Dimov Date: Tue, 6 Apr 2010 16:17:34 +0300 Subject: pm9261: remove CONFIG_CMD_AUTOSCRIPT Signed-off-by: Asen Dimov --- include/configs/pm9261.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index b245761..a0b00e9 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -198,7 +198,6 @@ #include #undef CONFIG_CMD_BDI #undef CONFIG_CMD_IMI -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS -- cgit v1.1 From 47eb08a97eb166e93d0495848b0c7582a0639fbc Mon Sep 17 00:00:00 2001 From: Alexander Holler Date: Mon, 29 Mar 2010 21:39:43 +0200 Subject: at91: add defines for RTT and GPBR Signed-off-by: Alexander Holler --- arch/arm/include/asm/arch-at91/at91sam9260.h | 2 ++ arch/arm/include/asm/arch-at91/at91sam9261.h | 2 ++ arch/arm/include/asm/arch-at91/at91sam9263.h | 3 +++ 3 files changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h index a60a081..ec04318 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260.h @@ -56,8 +56,10 @@ #define AT91_PIO_BASE 0xfffff400 #define AT91_PMC_BASE 0xfffffc00 #define AT91_RSTC_BASE 0xfffffd00 +#define AT91_RTT_BASE 0xfffffd20 #define AT91_PIT_BASE 0xfffffd30 #define AT91_WDT_BASE 0xfffffd40 +#define AT91_GPR_BASE 0xfffffd50 #ifdef CONFIG_AT91_LEGACY diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h index 2952292..7ca0283 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261.h +++ b/arch/arm/include/asm/arch-at91/at91sam9261.h @@ -49,8 +49,10 @@ #define AT91_PIO_BASE 0xfffff400 #define AT91_PMC_BASE 0xfffffc00 #define AT91_RSTC_BASE 0xfffffd00 +#define AT91_RTT_BASE 0xfffffd20 #define AT91_PIT_BASE 0xfffffd30 #define AT91_WDT_BASE 0xfffffd40 +#define AT91_GPBR_BASE 0xfffffd50 #ifdef CONFIG_AT91_LEGACY diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h index c177bd0..4ada1ce 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263.h +++ b/arch/arm/include/asm/arch-at91/at91sam9263.h @@ -61,8 +61,11 @@ #define AT91_PIO_BASE 0xfffff200 #define AT91_PMC_BASE 0xfffffc00 #define AT91_RSTC_BASE 0xfffffd00 +#define AT91_RTT0_BASE 0xfffffd20 #define AT91_PIT_BASE 0xfffffd30 #define AT91_WDT_BASE 0xfffffd40 +#define AT91_RTT1_BASE 0xfffffd50 +#define AT91_GPBR_BASE 0xfffffd60 #ifdef CONFIG_AT91_LEGACY -- cgit v1.1 From da0f2af279563ddc75eff304ad5389f7f0e79381 Mon Sep 17 00:00:00 2001 From: Asen Dimov Date: Wed, 7 Apr 2010 12:33:11 +0300 Subject: pm9263: remove CONFIG_CMD_AUTOSCRIPT Signed-off-by: Asen Dimov --- include/configs/pm9263.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 807dba8..f854f38 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -215,7 +215,6 @@ #include #undef CONFIG_CMD_BDI #undef CONFIG_CMD_IMI -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS -- cgit v1.1 From 46a3b5c8df939f5547bcd3684030072c94d06bd8 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Wed, 24 Mar 2010 16:59:30 +0900 Subject: SAMSUNG: serial: modify name from s5pc1xx to s5p Because of other s5p series SoC will use these serial functions, modify function's name and structure's name. Signed-off-by: Minkyu Kang --- arch/arm/include/asm/arch-s5pc1xx/uart.h | 2 +- common/serial.c | 16 +-- drivers/serial/Makefile | 2 +- drivers/serial/serial_s5p.c | 206 +++++++++++++++++++++++++++++++ drivers/serial/serial_s5pc1xx.c | 206 ------------------------------- include/serial.h | 8 +- 6 files changed, 220 insertions(+), 220 deletions(-) create mode 100644 drivers/serial/serial_s5p.c delete mode 100644 drivers/serial/serial_s5pc1xx.c diff --git a/arch/arm/include/asm/arch-s5pc1xx/uart.h b/arch/arm/include/asm/arch-s5pc1xx/uart.h index 140dbdc..2d7ad7e 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/uart.h +++ b/arch/arm/include/asm/arch-s5pc1xx/uart.h @@ -24,7 +24,7 @@ #define __ASM_ARCH_UART_H_ #ifndef __ASSEMBLY__ -struct s5pc1xx_uart { +struct s5p_uart { unsigned int ulcon; unsigned int ucon; unsigned int ufcon; diff --git a/common/serial.c b/common/serial.c index 754e329..0682faa 100644 --- a/common/serial.c +++ b/common/serial.c @@ -79,13 +79,13 @@ struct serial_device *__default_serial_console (void) #endif #elif defined(CONFIG_S5PC1XX) #if defined(CONFIG_SERIAL0) - return &s5pc1xx_serial0_device; + return &s5p_serial0_device; #elif defined(CONFIG_SERIAL1) - return &s5pc1xx_serial1_device; + return &s5p_serial1_device; #elif defined(CONFIG_SERIAL2) - return &s5pc1xx_serial2_device; + return &s5p_serial2_device; #elif defined(CONFIG_SERIAL3) - return &s5pc1xx_serial3_device; + return &s5p_serial3_device; #else #error "CONFIG_SERIAL? missing." #endif @@ -162,10 +162,10 @@ void serial_initialize (void) serial_register(&s3c24xx_serial2_device); #endif #if defined(CONFIG_S5PC1XX) - serial_register(&s5pc1xx_serial0_device); - serial_register(&s5pc1xx_serial1_device); - serial_register(&s5pc1xx_serial2_device); - serial_register(&s5pc1xx_serial3_device); + serial_register(&s5p_serial0_device); + serial_register(&s5p_serial1_device); + serial_register(&s5p_serial2_device); + serial_register(&s5p_serial3_device); #endif #if defined(CONFIG_MPC512X) #if defined(CONFIG_SYS_PSC1) diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index d2b4820..c731bfb 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -36,7 +36,7 @@ COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o COBJS-$(CONFIG_SYS_NS16550) += ns16550.o COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o -COBJS-$(CONFIG_S5PC1XX) += serial_s5pc1xx.o +COBJS-$(CONFIG_S5PC1XX) += serial_s5p.o COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c new file mode 100644 index 0000000..9747db3 --- /dev/null +++ b/drivers/serial/serial_s5p.c @@ -0,0 +1,206 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang + * Heungjun Kim + * + * based on drivers/serial/s3c64xx.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include + +static inline struct s5p_uart *s5p_get_base_uart(int dev_index) +{ + u32 offset = dev_index * sizeof(struct s5p_uart); + + if (cpu_is_s5pc100()) + return (struct s5p_uart *)(S5PC100_UART_BASE + offset); + else + return (struct s5p_uart *)(S5PC110_UART_BASE + offset); +} + +/* + * The coefficient, used to calculate the baudrate on S5P UARTs is + * calculated as + * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT + * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1, + * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants: + */ +static const int udivslot[] = { + 0, + 0x0080, + 0x0808, + 0x0888, + 0x2222, + 0x4924, + 0x4a52, + 0x54aa, + 0x5555, + 0xd555, + 0xd5d5, + 0xddd5, + 0xdddd, + 0xdfdd, + 0xdfdf, + 0xffdf, +}; + +void serial_setbrg_dev(const int dev_index) +{ + DECLARE_GLOBAL_DATA_PTR; + struct s5p_uart *const uart = s5p_get_base_uart(dev_index); + u32 pclk = get_pclk(); + u32 baudrate = gd->baudrate; + u32 val; + + val = pclk / baudrate; + + writel(val / 16 - 1, &uart->ubrdiv); + writew(udivslot[val % 16], &uart->udivslot); +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +int serial_init_dev(const int dev_index) +{ + struct s5p_uart *const uart = s5p_get_base_uart(dev_index); + + /* reset and enable FIFOs, set triggers to the maximum */ + writel(0, &uart->ufcon); + writel(0, &uart->umcon); + /* 8N1 */ + writel(0x3, &uart->ulcon); + /* No interrupts, no DMA, pure polling */ + writel(0x245, &uart->ucon); + + serial_setbrg_dev(dev_index); + + return 0; +} + +static int serial_err_check(const int dev_index, int op) +{ + struct s5p_uart *const uart = s5p_get_base_uart(dev_index); + unsigned int mask; + + /* + * UERSTAT + * Break Detect [3] + * Frame Err [2] : receive operation + * Parity Err [1] : receive operation + * Overrun Err [0] : receive operation + */ + if (op) + mask = 0x8; + else + mask = 0xf; + + return readl(&uart->uerstat) & mask; +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc_dev(const int dev_index) +{ + struct s5p_uart *const uart = s5p_get_base_uart(dev_index); + + /* wait for character to arrive */ + while (!(readl(&uart->utrstat) & 0x1)) { + if (serial_err_check(dev_index, 0)) + return 0; + } + + return (int)(readl(&uart->urxh) & 0xff); +} + +/* + * Output a single byte to the serial port. + */ +void serial_putc_dev(const char c, const int dev_index) +{ + struct s5p_uart *const uart = s5p_get_base_uart(dev_index); + + /* wait for room in the tx FIFO */ + while (!(readl(&uart->utrstat) & 0x2)) { + if (serial_err_check(dev_index, 1)) + return; + } + + writel(c, &uart->utxh); + + /* If \n, also do \r */ + if (c == '\n') + serial_putc('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc_dev(const int dev_index) +{ + struct s5p_uart *const uart = s5p_get_base_uart(dev_index); + + return (int)(readl(&uart->utrstat) & 0x1); +} + +void serial_puts_dev(const char *s, const int dev_index) +{ + while (*s) + serial_putc_dev(*s++, dev_index); +} + +/* Multi serial device functions */ +#define DECLARE_S5P_SERIAL_FUNCTIONS(port) \ +int s5p_serial##port##_init(void) { return serial_init_dev(port); } \ +void s5p_serial##port##_setbrg(void) { serial_setbrg_dev(port); } \ +int s5p_serial##port##_getc(void) { return serial_getc_dev(port); } \ +int s5p_serial##port##_tstc(void) { return serial_tstc_dev(port); } \ +void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \ +void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); } + +#define INIT_S5P_SERIAL_STRUCTURE(port, name, bus) { \ + name, \ + bus, \ + s5p_serial##port##_init, \ + NULL, \ + s5p_serial##port##_setbrg, \ + s5p_serial##port##_getc, \ + s5p_serial##port##_tstc, \ + s5p_serial##port##_putc, \ + s5p_serial##port##_puts, } + +DECLARE_S5P_SERIAL_FUNCTIONS(0); +struct serial_device s5p_serial0_device = + INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0", "S5PUART0"); +DECLARE_S5P_SERIAL_FUNCTIONS(1); +struct serial_device s5p_serial1_device = + INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1", "S5PUART1"); +DECLARE_S5P_SERIAL_FUNCTIONS(2); +struct serial_device s5p_serial2_device = + INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2", "S5PUART2"); +DECLARE_S5P_SERIAL_FUNCTIONS(3); +struct serial_device s5p_serial3_device = + INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3", "S5PUART3"); diff --git a/drivers/serial/serial_s5pc1xx.c b/drivers/serial/serial_s5pc1xx.c deleted file mode 100644 index 8da0c86..0000000 --- a/drivers/serial/serial_s5pc1xx.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang - * Heungjun Kim - * - * based on drivers/serial/s3c64xx.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include -#include -#include -#include - -static inline struct s5pc1xx_uart *s5pc1xx_get_base_uart(int dev_index) -{ - u32 offset = dev_index * sizeof(struct s5pc1xx_uart); - - if (cpu_is_s5pc100()) - return (struct s5pc1xx_uart *)(S5PC100_UART_BASE + offset); - else - return (struct s5pc1xx_uart *)(S5PC110_UART_BASE + offset); -} - -/* - * The coefficient, used to calculate the baudrate on S5PC1XX UARTs is - * calculated as - * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT - * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1, - * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants: - */ -static const int udivslot[] = { - 0, - 0x0080, - 0x0808, - 0x0888, - 0x2222, - 0x4924, - 0x4a52, - 0x54aa, - 0x5555, - 0xd555, - 0xd5d5, - 0xddd5, - 0xdddd, - 0xdfdd, - 0xdfdf, - 0xffdf, -}; - -void serial_setbrg_dev(const int dev_index) -{ - DECLARE_GLOBAL_DATA_PTR; - struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); - u32 pclk = get_pclk(); - u32 baudrate = gd->baudrate; - u32 val; - - val = pclk / baudrate; - - writel(val / 16 - 1, &uart->ubrdiv); - writew(udivslot[val % 16], &uart->udivslot); -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - */ -int serial_init_dev(const int dev_index) -{ - struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); - - /* reset and enable FIFOs, set triggers to the maximum */ - writel(0, &uart->ufcon); - writel(0, &uart->umcon); - /* 8N1 */ - writel(0x3, &uart->ulcon); - /* No interrupts, no DMA, pure polling */ - writel(0x245, &uart->ucon); - - serial_setbrg_dev(dev_index); - - return 0; -} - -static int serial_err_check(const int dev_index, int op) -{ - struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); - unsigned int mask; - - /* - * UERSTAT - * Break Detect [3] - * Frame Err [2] : receive operation - * Parity Err [1] : receive operation - * Overrun Err [0] : receive operation - */ - if (op) - mask = 0x8; - else - mask = 0xf; - - return readl(&uart->uerstat) & mask; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc_dev(const int dev_index) -{ - struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); - - /* wait for character to arrive */ - while (!(readl(&uart->utrstat) & 0x1)) { - if (serial_err_check(dev_index, 0)) - return 0; - } - - return (int)(readl(&uart->urxh) & 0xff); -} - -/* - * Output a single byte to the serial port. - */ -void serial_putc_dev(const char c, const int dev_index) -{ - struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); - - /* wait for room in the tx FIFO */ - while (!(readl(&uart->utrstat) & 0x2)) { - if (serial_err_check(dev_index, 1)) - return; - } - - writel(c, &uart->utxh); - - /* If \n, also do \r */ - if (c == '\n') - serial_putc('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int serial_tstc_dev(const int dev_index) -{ - struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); - - return (int)(readl(&uart->utrstat) & 0x1); -} - -void serial_puts_dev(const char *s, const int dev_index) -{ - while (*s) - serial_putc_dev(*s++, dev_index); -} - -/* Multi serial device functions */ -#define DECLARE_S5P_SERIAL_FUNCTIONS(port) \ -int s5p_serial##port##_init(void) { return serial_init_dev(port); } \ -void s5p_serial##port##_setbrg(void) { serial_setbrg_dev(port); } \ -int s5p_serial##port##_getc(void) { return serial_getc_dev(port); } \ -int s5p_serial##port##_tstc(void) { return serial_tstc_dev(port); } \ -void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \ -void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); } - -#define INIT_S5P_SERIAL_STRUCTURE(port, name, bus) { \ - name, \ - bus, \ - s5p_serial##port##_init, \ - NULL, \ - s5p_serial##port##_setbrg, \ - s5p_serial##port##_getc, \ - s5p_serial##port##_tstc, \ - s5p_serial##port##_putc, \ - s5p_serial##port##_puts, } - -DECLARE_S5P_SERIAL_FUNCTIONS(0); -struct serial_device s5pc1xx_serial0_device = - INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0", "S5PUART0"); -DECLARE_S5P_SERIAL_FUNCTIONS(1); -struct serial_device s5pc1xx_serial1_device = - INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1", "S5PUART1"); -DECLARE_S5P_SERIAL_FUNCTIONS(2); -struct serial_device s5pc1xx_serial2_device = - INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2", "S5PUART2"); -DECLARE_S5P_SERIAL_FUNCTIONS(3); -struct serial_device s5pc1xx_serial3_device = - INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3", "S5PUART3"); diff --git a/include/serial.h b/include/serial.h index 6423fba..111edbe 100644 --- a/include/serial.h +++ b/include/serial.h @@ -52,10 +52,10 @@ extern struct serial_device s3c24xx_serial2_device; #endif #if defined(CONFIG_S5PC1XX) -extern struct serial_device s5pc1xx_serial0_device; -extern struct serial_device s5pc1xx_serial1_device; -extern struct serial_device s5pc1xx_serial2_device; -extern struct serial_device s5pc1xx_serial3_device; +extern struct serial_device s5p_serial0_device; +extern struct serial_device s5p_serial1_device; +extern struct serial_device s5p_serial2_device; +extern struct serial_device s5p_serial3_device; #endif #if defined(CONFIG_OMAP3_ZOOM2) -- cgit v1.1 From 3bb6b037e8557fd3c0f3b3d9840c8b5996651dcb Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Wed, 24 Mar 2010 15:31:06 +0900 Subject: SAMSUNG: make s5p common gpio functions Because of s5pc1xx gpio is same as s5p seires SoC, move gpio functions to drvier/gpio/ and modify structure's name from s5pc1xx_ to s5p_. Signed-off-by: Minkyu Kang --- arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile | 1 - arch/arm/cpu/arm_cortexa8/s5pc1xx/gpio.c | 143 --------------------- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 192 ++++++++++++++--------------- drivers/gpio/Makefile | 1 + drivers/gpio/s5p_gpio.c | 143 +++++++++++++++++++++ 5 files changed, 240 insertions(+), 240 deletions(-) delete mode 100644 arch/arm/cpu/arm_cortexa8/s5pc1xx/gpio.c create mode 100644 drivers/gpio/s5p_gpio.c diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile b/arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile index 01c93fe..3785593 100644 --- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile +++ b/arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile @@ -33,7 +33,6 @@ SOBJS += reset.o COBJS += clock.o COBJS += cpu_info.o -COBJS += gpio.o COBJS += sromc.o COBJS += timer.o diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/gpio.c b/arch/arm/cpu/arm_cortexa8/s5pc1xx/gpio.c deleted file mode 100644 index a97244b..0000000 --- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/gpio.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define CON_MASK(x) (0xf << ((x) << 2)) -#define CON_SFR(x, v) ((v) << ((x) << 2)) - -#define DAT_MASK(x) (0x1 << (x)) -#define DAT_SET(x) (0x1 << (x)) - -#define PULL_MASK(x) (0x3 << ((x) << 1)) -#define PULL_MODE(x, v) ((v) << ((x) << 1)) - -#define DRV_MASK(x) (0x3 << ((x) << 1)) -#define DRV_SET(x, m) ((m) << ((x) << 1)) -#define RATE_MASK(x) (0x1 << (x + 16)) -#define RATE_SET(x) (0x1 << (x + 16)) - -void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg) -{ - unsigned int value; - - value = readl(&bank->con); - value &= ~CON_MASK(gpio); - value |= CON_SFR(gpio, cfg); - writel(value, &bank->con); -} - -void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en) -{ - unsigned int value; - - gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); - - value = readl(&bank->dat); - value &= ~DAT_MASK(gpio); - if (en) - value |= DAT_SET(gpio); - writel(value, &bank->dat); -} - -void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio) -{ - gpio_cfg_pin(bank, gpio, GPIO_INPUT); -} - -void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en) -{ - unsigned int value; - - value = readl(&bank->dat); - value &= ~DAT_MASK(gpio); - if (en) - value |= DAT_SET(gpio); - writel(value, &bank->dat); -} - -unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio) -{ - unsigned int value; - - value = readl(&bank->dat); - return !!(value & DAT_MASK(gpio)); -} - -void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) -{ - unsigned int value; - - value = readl(&bank->pull); - value &= ~PULL_MASK(gpio); - - switch (mode) { - case GPIO_PULL_DOWN: - case GPIO_PULL_UP: - value |= PULL_MODE(gpio, mode); - break; - default: - return; - } - - writel(value, &bank->pull); -} - -void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) -{ - unsigned int value; - - value = readl(&bank->drv); - value &= ~DRV_MASK(gpio); - - switch (mode) { - case GPIO_DRV_1X: - case GPIO_DRV_2X: - case GPIO_DRV_3X: - case GPIO_DRV_4X: - value |= DRV_SET(gpio, mode); - break; - default: - return; - } - - writel(value, &bank->drv); -} - -void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) -{ - unsigned int value; - - value = readl(&bank->drv); - value &= ~RATE_MASK(gpio); - - switch (mode) { - case GPIO_DRV_FAST: - case GPIO_DRV_SLOW: - value |= RATE_SET(gpio); - break; - default: - return; - } - - writel(value, &bank->drv); -} diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index 8e4bb86..9a7faed 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -22,7 +22,7 @@ #define __ASM_ARCH_GPIO_H #ifndef __ASSEMBLY__ -struct s5pc1xx_gpio_bank { +struct s5p_gpio_bank { unsigned int con; unsigned int dat; unsigned int pull; @@ -33,107 +33,107 @@ struct s5pc1xx_gpio_bank { }; struct s5pc100_gpio { - struct s5pc1xx_gpio_bank gpio_a0; - struct s5pc1xx_gpio_bank gpio_a1; - struct s5pc1xx_gpio_bank gpio_b; - struct s5pc1xx_gpio_bank gpio_c; - struct s5pc1xx_gpio_bank gpio_d; - struct s5pc1xx_gpio_bank gpio_e0; - struct s5pc1xx_gpio_bank gpio_e1; - struct s5pc1xx_gpio_bank gpio_f0; - struct s5pc1xx_gpio_bank gpio_f1; - struct s5pc1xx_gpio_bank gpio_f2; - struct s5pc1xx_gpio_bank gpio_f3; - struct s5pc1xx_gpio_bank gpio_g0; - struct s5pc1xx_gpio_bank gpio_g1; - struct s5pc1xx_gpio_bank gpio_g2; - struct s5pc1xx_gpio_bank gpio_g3; - struct s5pc1xx_gpio_bank gpio_i; - struct s5pc1xx_gpio_bank gpio_j0; - struct s5pc1xx_gpio_bank gpio_j1; - struct s5pc1xx_gpio_bank gpio_j2; - struct s5pc1xx_gpio_bank gpio_j3; - struct s5pc1xx_gpio_bank gpio_j4; - struct s5pc1xx_gpio_bank gpio_k0; - struct s5pc1xx_gpio_bank gpio_k1; - struct s5pc1xx_gpio_bank gpio_k2; - struct s5pc1xx_gpio_bank gpio_k3; - struct s5pc1xx_gpio_bank gpio_l0; - struct s5pc1xx_gpio_bank gpio_l1; - struct s5pc1xx_gpio_bank gpio_l2; - struct s5pc1xx_gpio_bank gpio_l3; - struct s5pc1xx_gpio_bank gpio_l4; - struct s5pc1xx_gpio_bank gpio_h0; - struct s5pc1xx_gpio_bank gpio_h1; - struct s5pc1xx_gpio_bank gpio_h2; - struct s5pc1xx_gpio_bank gpio_h3; + struct s5p_gpio_bank gpio_a0; + struct s5p_gpio_bank gpio_a1; + struct s5p_gpio_bank gpio_b; + struct s5p_gpio_bank gpio_c; + struct s5p_gpio_bank gpio_d; + struct s5p_gpio_bank gpio_e0; + struct s5p_gpio_bank gpio_e1; + struct s5p_gpio_bank gpio_f0; + struct s5p_gpio_bank gpio_f1; + struct s5p_gpio_bank gpio_f2; + struct s5p_gpio_bank gpio_f3; + struct s5p_gpio_bank gpio_g0; + struct s5p_gpio_bank gpio_g1; + struct s5p_gpio_bank gpio_g2; + struct s5p_gpio_bank gpio_g3; + struct s5p_gpio_bank gpio_i; + struct s5p_gpio_bank gpio_j0; + struct s5p_gpio_bank gpio_j1; + struct s5p_gpio_bank gpio_j2; + struct s5p_gpio_bank gpio_j3; + struct s5p_gpio_bank gpio_j4; + struct s5p_gpio_bank gpio_k0; + struct s5p_gpio_bank gpio_k1; + struct s5p_gpio_bank gpio_k2; + struct s5p_gpio_bank gpio_k3; + struct s5p_gpio_bank gpio_l0; + struct s5p_gpio_bank gpio_l1; + struct s5p_gpio_bank gpio_l2; + struct s5p_gpio_bank gpio_l3; + struct s5p_gpio_bank gpio_l4; + struct s5p_gpio_bank gpio_h0; + struct s5p_gpio_bank gpio_h1; + struct s5p_gpio_bank gpio_h2; + struct s5p_gpio_bank gpio_h3; }; struct s5pc110_gpio { - struct s5pc1xx_gpio_bank gpio_a0; - struct s5pc1xx_gpio_bank gpio_a1; - struct s5pc1xx_gpio_bank gpio_b; - struct s5pc1xx_gpio_bank gpio_c0; - struct s5pc1xx_gpio_bank gpio_c1; - struct s5pc1xx_gpio_bank gpio_d0; - struct s5pc1xx_gpio_bank gpio_d1; - struct s5pc1xx_gpio_bank gpio_e0; - struct s5pc1xx_gpio_bank gpio_e1; - struct s5pc1xx_gpio_bank gpio_f0; - struct s5pc1xx_gpio_bank gpio_f1; - struct s5pc1xx_gpio_bank gpio_f2; - struct s5pc1xx_gpio_bank gpio_f3; - struct s5pc1xx_gpio_bank gpio_g0; - struct s5pc1xx_gpio_bank gpio_g1; - struct s5pc1xx_gpio_bank gpio_g2; - struct s5pc1xx_gpio_bank gpio_g3; - struct s5pc1xx_gpio_bank gpio_i; - struct s5pc1xx_gpio_bank gpio_j0; - struct s5pc1xx_gpio_bank gpio_j1; - struct s5pc1xx_gpio_bank gpio_j2; - struct s5pc1xx_gpio_bank gpio_j3; - struct s5pc1xx_gpio_bank gpio_j4; - struct s5pc1xx_gpio_bank gpio_mp0_1; - struct s5pc1xx_gpio_bank gpio_mp0_2; - struct s5pc1xx_gpio_bank gpio_mp0_3; - struct s5pc1xx_gpio_bank gpio_mp0_4; - struct s5pc1xx_gpio_bank gpio_mp0_5; - struct s5pc1xx_gpio_bank gpio_mp0_6; - struct s5pc1xx_gpio_bank gpio_mp0_7; - struct s5pc1xx_gpio_bank gpio_mp1_0; - struct s5pc1xx_gpio_bank gpio_mp1_1; - struct s5pc1xx_gpio_bank gpio_mp1_2; - struct s5pc1xx_gpio_bank gpio_mp1_3; - struct s5pc1xx_gpio_bank gpio_mp1_4; - struct s5pc1xx_gpio_bank gpio_mp1_5; - struct s5pc1xx_gpio_bank gpio_mp1_6; - struct s5pc1xx_gpio_bank gpio_mp1_7; - struct s5pc1xx_gpio_bank gpio_mp1_8; - struct s5pc1xx_gpio_bank gpio_mp2_0; - struct s5pc1xx_gpio_bank gpio_mp2_1; - struct s5pc1xx_gpio_bank gpio_mp2_2; - struct s5pc1xx_gpio_bank gpio_mp2_3; - struct s5pc1xx_gpio_bank gpio_mp2_4; - struct s5pc1xx_gpio_bank gpio_mp2_5; - struct s5pc1xx_gpio_bank gpio_mp2_6; - struct s5pc1xx_gpio_bank gpio_mp2_7; - struct s5pc1xx_gpio_bank gpio_mp2_8; - struct s5pc1xx_gpio_bank res1[48]; - struct s5pc1xx_gpio_bank gpio_h0; - struct s5pc1xx_gpio_bank gpio_h1; - struct s5pc1xx_gpio_bank gpio_h2; - struct s5pc1xx_gpio_bank gpio_h3; + struct s5p_gpio_bank gpio_a0; + struct s5p_gpio_bank gpio_a1; + struct s5p_gpio_bank gpio_b; + struct s5p_gpio_bank gpio_c0; + struct s5p_gpio_bank gpio_c1; + struct s5p_gpio_bank gpio_d0; + struct s5p_gpio_bank gpio_d1; + struct s5p_gpio_bank gpio_e0; + struct s5p_gpio_bank gpio_e1; + struct s5p_gpio_bank gpio_f0; + struct s5p_gpio_bank gpio_f1; + struct s5p_gpio_bank gpio_f2; + struct s5p_gpio_bank gpio_f3; + struct s5p_gpio_bank gpio_g0; + struct s5p_gpio_bank gpio_g1; + struct s5p_gpio_bank gpio_g2; + struct s5p_gpio_bank gpio_g3; + struct s5p_gpio_bank gpio_i; + struct s5p_gpio_bank gpio_j0; + struct s5p_gpio_bank gpio_j1; + struct s5p_gpio_bank gpio_j2; + struct s5p_gpio_bank gpio_j3; + struct s5p_gpio_bank gpio_j4; + struct s5p_gpio_bank gpio_mp0_1; + struct s5p_gpio_bank gpio_mp0_2; + struct s5p_gpio_bank gpio_mp0_3; + struct s5p_gpio_bank gpio_mp0_4; + struct s5p_gpio_bank gpio_mp0_5; + struct s5p_gpio_bank gpio_mp0_6; + struct s5p_gpio_bank gpio_mp0_7; + struct s5p_gpio_bank gpio_mp1_0; + struct s5p_gpio_bank gpio_mp1_1; + struct s5p_gpio_bank gpio_mp1_2; + struct s5p_gpio_bank gpio_mp1_3; + struct s5p_gpio_bank gpio_mp1_4; + struct s5p_gpio_bank gpio_mp1_5; + struct s5p_gpio_bank gpio_mp1_6; + struct s5p_gpio_bank gpio_mp1_7; + struct s5p_gpio_bank gpio_mp1_8; + struct s5p_gpio_bank gpio_mp2_0; + struct s5p_gpio_bank gpio_mp2_1; + struct s5p_gpio_bank gpio_mp2_2; + struct s5p_gpio_bank gpio_mp2_3; + struct s5p_gpio_bank gpio_mp2_4; + struct s5p_gpio_bank gpio_mp2_5; + struct s5p_gpio_bank gpio_mp2_6; + struct s5p_gpio_bank gpio_mp2_7; + struct s5p_gpio_bank gpio_mp2_8; + struct s5p_gpio_bank res1[48]; + struct s5p_gpio_bank gpio_h0; + struct s5p_gpio_bank gpio_h1; + struct s5p_gpio_bank gpio_h2; + struct s5p_gpio_bank gpio_h3; }; /* functions */ -void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg); -void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en); -void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio); -void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en); -unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio); -void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); -void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); -void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); +void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); +void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); +void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); +void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); +unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio); +void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); +void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); +void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); #endif /* Pin configurations */ diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d966082..528ca2e 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o +COBJS-$(CONFIG_S5PC1XX) += s5p_gpio.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c new file mode 100644 index 0000000..0439477 --- /dev/null +++ b/drivers/gpio/s5p_gpio.c @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define CON_MASK(x) (0xf << ((x) << 2)) +#define CON_SFR(x, v) ((v) << ((x) << 2)) + +#define DAT_MASK(x) (0x1 << (x)) +#define DAT_SET(x) (0x1 << (x)) + +#define PULL_MASK(x) (0x3 << ((x) << 1)) +#define PULL_MODE(x, v) ((v) << ((x) << 1)) + +#define DRV_MASK(x) (0x3 << ((x) << 1)) +#define DRV_SET(x, m) ((m) << ((x) << 1)) +#define RATE_MASK(x) (0x1 << (x + 16)) +#define RATE_SET(x) (0x1 << (x + 16)) + +void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) +{ + unsigned int value; + + value = readl(&bank->con); + value &= ~CON_MASK(gpio); + value |= CON_SFR(gpio, cfg); + writel(value, &bank->con); +} + +void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en) +{ + unsigned int value; + + gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); + + value = readl(&bank->dat); + value &= ~DAT_MASK(gpio); + if (en) + value |= DAT_SET(gpio); + writel(value, &bank->dat); +} + +void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio) +{ + gpio_cfg_pin(bank, gpio, GPIO_INPUT); +} + +void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) +{ + unsigned int value; + + value = readl(&bank->dat); + value &= ~DAT_MASK(gpio); + if (en) + value |= DAT_SET(gpio); + writel(value, &bank->dat); +} + +unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio) +{ + unsigned int value; + + value = readl(&bank->dat); + return !!(value & DAT_MASK(gpio)); +} + +void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->pull); + value &= ~PULL_MASK(gpio); + + switch (mode) { + case GPIO_PULL_DOWN: + case GPIO_PULL_UP: + value |= PULL_MODE(gpio, mode); + break; + default: + return; + } + + writel(value, &bank->pull); +} + +void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->drv); + value &= ~DRV_MASK(gpio); + + switch (mode) { + case GPIO_DRV_1X: + case GPIO_DRV_2X: + case GPIO_DRV_3X: + case GPIO_DRV_4X: + value |= DRV_SET(gpio, mode); + break; + default: + return; + } + + writel(value, &bank->drv); +} + +void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->drv); + value &= ~RATE_MASK(gpio); + + switch (mode) { + case GPIO_DRV_FAST: + case GPIO_DRV_SLOW: + value |= RATE_SET(gpio); + break; + default: + return; + } + + writel(value, &bank->drv); +} -- cgit v1.1 From 1e65c2beb5805f975cd5d0ab7d853040a716d51b Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 4 Mar 2010 08:12:05 +0100 Subject: arm, mx27: add support for SDHC1 pin init Signed-off-by: Heiko Schocher --- arch/arm/cpu/arm926ejs/mx27/generic.c | 17 +++++++++++++++++ arch/arm/include/asm/arch-mx27/imx-regs.h | 1 + 2 files changed, 18 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c index 30cf544..ae2ce58 100644 --- a/arch/arm/cpu/arm926ejs/mx27/generic.c +++ b/arch/arm/cpu/arm926ejs/mx27/generic.c @@ -316,6 +316,23 @@ void mx27_fec_init_pins(void) #endif /* CONFIG_FEC_MXC */ #ifdef CONFIG_MXC_MMC +void mx27_sd1_init_pins(void) +{ + int i; + unsigned int mode[] = { + PE18_PF_SD1_D0, + PE19_PF_SD1_D1, + PE20_PF_SD1_D2, + PE21_PF_SD1_D3, + PE22_PF_SD1_CMD, + PE23_PF_SD1_CLK, + }; + + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + +} + void mx27_sd2_init_pins(void) { int i; diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index d36a6da..6ecddaa 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -37,6 +37,7 @@ extern void mx27_fec_init_pins(void); #endif /* CONFIG_FEC_MXC */ #ifdef CONFIG_MXC_MMC +extern void mx27_sd1_init_pins(void); extern void mx27_sd2_init_pins(void); #endif /* CONFIG_MXC_MMC */ -- cgit v1.1 From bbe310922f4d0b12c8aba97b45ed979db9c0ec9a Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 5 Mar 2010 07:36:33 +0100 Subject: arm, i.mx27: add support for magnesium board from projectiondesign This patch adds support for the magnesium board from projectiondesign. This board uses i.MX27 SoC and has 8MB NOR flash, 128MB NAND flash, FEC ethernet controller integrated into i.MX27. As this port is based on the imx27lite port, common config options are collected in include/configs/imx27lite-common.h Signed-off-by: Heiko Schocher --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 1 + board/logicpd/imx27lite/imx27lite.c | 18 ++- include/configs/imx27lite-common.h | 237 ++++++++++++++++++++++++++++++++++++ include/configs/imx27lite.h | 200 +----------------------------- include/configs/magnesium.h | 71 +++++++++++ 7 files changed, 335 insertions(+), 197 deletions(-) create mode 100644 include/configs/imx27lite-common.h create mode 100644 include/configs/magnesium.h diff --git a/MAINTAINERS b/MAINTAINERS index a5d5835..4e6d735 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -738,6 +738,10 @@ Jens Scharsig eb_cpux9k2 ARM920T (AT91RM9200 SoC) +Heiko Schocher + + magnesium i.MX27 + Robert Schwebel csb226 xscale diff --git a/MAKEALL b/MAKEALL index 34bc4a1..e2bba1c 100755 --- a/MAKEALL +++ b/MAKEALL @@ -569,6 +569,7 @@ LIST_ARM9=" \ edb9315a \ imx27lite \ lpd7a400 \ + magnesium \ mv88f6281gtw_ge \ mx1ads \ mx1fs2 \ diff --git a/Makefile b/Makefile index 25e3b8c..9213ec2 100644 --- a/Makefile +++ b/Makefile @@ -2940,6 +2940,7 @@ davinci_dm365evm_config : unconfig davinci_dm6467evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci +magnesium_config \ imx27lite_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27 diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c index 63375d5..4427415 100644 --- a/board/logicpd/imx27lite/imx27lite.c +++ b/board/logicpd/imx27lite/imx27lite.c @@ -29,6 +29,10 @@ DECLARE_GLOBAL_DATA_PTR; int board_init (void) { struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE; +#if defined(CONFIG_SYS_NAND_LARGEPAGE) + struct system_control_regs *sc_regs = + (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; +#endif gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; @@ -43,9 +47,20 @@ int board_init (void) ®s->port[PORTC].dr); #endif #ifdef CONFIG_MXC_MMC +#if defined(CONFIG_MAGNESIUM) + mx27_sd1_init_pins(); +#else mx27_sd2_init_pins(); #endif +#endif +#if defined(CONFIG_SYS_NAND_LARGEPAGE) + /* + * set in FMCR NF_FMS Bit(5) to 1 + * (NAND Flash with 2 Kbyte page size) + */ + writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr); +#endif return 0; } @@ -68,6 +83,7 @@ int dram_init (void) int checkboard(void) { - printf("LogicPD imx27lite\n"); + puts ("Board: "); + puts(CONFIG_BOARDNAME); return 0; } diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h new file mode 100644 index 0000000..1da8602 --- /dev/null +++ b/include/configs/imx27lite-common.h @@ -0,0 +1,237 @@ +/* + * Copyright (C) 2010 Heiko Schocher + * + * based on: + * Copyright (C) 2009 Ilya Yanok + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMX27LITE_COMMON_CONFIG_H +#define __IMX27LITE_COMMON_CONFIG_H + +/* + * SoC Configuration + */ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_MX27 +#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Lowlevel configuration + */ +#define SDRAM_ESDCFG_REGISTER_VAL(cas) \ + (ESDCFG_TRC(10) | \ + ESDCFG_TRCD(3) | \ + ESDCFG_TCAS(cas) | \ + ESDCFG_TRRD(1) | \ + ESDCFG_TRAS(5) | \ + ESDCFG_TWR | \ + ESDCFG_TMRD(2) | \ + ESDCFG_TRP(2) | \ + ESDCFG_TXP(3)) + +#define SDRAM_ESDCTL_REGISTER_VAL \ + (ESDCTL_PRCT(0) | \ + ESDCTL_BL | \ + ESDCTL_PWDT(0) | \ + ESDCTL_SREFR(3) | \ + ESDCTL_DSIZ_32 | \ + ESDCTL_COL10 | \ + ESDCTL_ROW13 | \ + ESDCTL_SDE) + +#define SDRAM_ALL_VAL 0xf00 + +#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ +#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 + +#define MPCTL0_VAL 0x1ef15d5 + +#define SPCTL0_VAL 0x043a1c09 + +#define CSCR_VAL 0x33f08107 + +#define PCDR0_VAL 0x120470c3 +#define PCDR1_VAL 0x03030303 +#define PCCR0_VAL 0xffffffff +#define PCCR1_VAL 0xfffffffc + +#define AIPI1_PSR0_VAL 0x20040304 +#define AIPI1_PSR1_VAL 0xdffbfcfb +#define AIPI2_PSR0_VAL 0x07ffc200 +#define AIPI2_PSR1_VAL 0xffffffff + +/* + * Memory Info + */ +/* malloc() len */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) +/* reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +/* memtest start address */ +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */ +#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ + +/* + * Serial Driver info + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX27_UART1 +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Flash & Environment + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +/* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* Use hardware sector protection */ +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +/* CS2 Base address */ +#define PHYS_FLASH_1 0xc0000000 +/* Flash Base for U-Boot */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ + CONFIG_SYS_FLASH_SECT_SZ) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* + * Ethernet + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x1f +#define CONFIG_MII +#define CONFIG_NET_MULTI + +/* + * MTD + */ +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_MTD_DEVICE + +/* + * NAND + */ +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0xd8000000 +#define CONFIG_JFFS2_NAND +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +/* + * SD/MMC + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MXC_MMC +#define CONFIG_DOS_PARTITION + +/* + * MTD partitions + */ +#define CONFIG_CMD_MTDPARTS + +/* + * U-Boot general configuration + */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Print buffer sz */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +/* + * U-Boot commands + */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttymxc0,${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "kernel_addr_r=a0800000\0" \ + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "rootpath=/opt/eldk-4.2-arm/arm\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm\0" \ + "bootcmd=run net_nfs\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};cp.b ${fileaddr} " \ + xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + +#endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h index ee749ec..72f6e80 100644 --- a/include/configs/imx27lite.h +++ b/include/configs/imx27lite.h @@ -20,158 +20,31 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* include common defines/options for all imx27lite related boards */ +#include "imx27lite-common.h" /* * SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_MX27 #define CONFIG_IMX27LITE -#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Lowlevel configuration - */ -#define SDRAM_ESDCFG_REGISTER_VAL(cas) \ - (ESDCFG_TRC(10) | \ - ESDCFG_TRCD(3) | \ - ESDCFG_TCAS(cas) | \ - ESDCFG_TRRD(1) | \ - ESDCFG_TRAS(5) | \ - ESDCFG_TWR | \ - ESDCFG_TMRD(2) | \ - ESDCFG_TRP(2) | \ - ESDCFG_TXP(3)) - -#define SDRAM_ESDCTL_REGISTER_VAL \ - (ESDCTL_PRCT(0) | \ - ESDCTL_BL | \ - ESDCTL_PWDT(0) | \ - ESDCTL_SREFR(3) | \ - ESDCTL_DSIZ_32 | \ - ESDCTL_COL10 | \ - ESDCTL_ROW13 | \ - ESDCTL_SDE) - -#define SDRAM_ALL_VAL 0xf00 - -#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ -#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 - -#define MPCTL0_VAL 0x1ef15d5 - -#define SPCTL0_VAL 0x043a1c09 - -#define CSCR_VAL 0x33f08107 - -#define PCDR0_VAL 0x120470c3 -#define PCDR1_VAL 0x03030303 -#define PCCR0_VAL 0xffffffff -#define PCCR1_VAL 0xfffffffc - -#define AIPI1_PSR0_VAL 0x20040304 -#define AIPI1_PSR1_VAL 0xdffbfcfb -#define AIPI2_PSR0_VAL 0x07ffc200 -#define AIPI2_PSR1_VAL 0xffffffff - -/* - * Memory Info - */ -/* malloc() len */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) -/* reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 -/* memtest start address */ -#define CONFIG_SYS_MEMTEST_START 0xA0000000 -#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */ -#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ - -/* - * Serial Driver info - */ -#define CONFIG_MXC_UART -#define CONFIG_SYS_MX27_UART1 -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_HOSTNAME imx27 +#define CONFIG_BOARDNAME "LogicPD imx27lite\n" /* * Flash & Environment */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -/* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -/* Use hardware sector protection */ -#define CONFIG_SYS_FLASH_PROTECTION 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */ -/* end of flash */ #define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000) -/* CS2 Base address */ -#define PHYS_FLASH_1 0xc0000000 -/* Flash Base for U-Boot */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -/* Flash size 2MB */ #define PHYS_FLASH_SIZE 0x200000 -#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ - CONFIG_SYS_FLASH_SECT_SZ) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ #define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Ethernet - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f -#define CONFIG_MII -#define CONFIG_NET_MULTI - -/* - * MTD - */ -#define CONFIG_FLASH_CFI_MTD -#define CONFIG_MTD_DEVICE - -/* - * NAND - */ -#define CONFIG_NAND_MXC -#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0xd8000000 -#define CONFIG_JFFS2_NAND -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ /* * SD/MMC */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_MXC_MMC #define CONFIG_MXC_MCI_REGS_BASE 0x10014000 -#define CONFIG_DOS_PARTITION /* * MTD partitions */ -#define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0" #define MTDPARTS_DEFAULT \ "mtdparts=" \ @@ -186,69 +59,4 @@ "22m(rootfs)," \ "-(userfs)" -/* - * U-Boot general configuration - */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Print buffer sz */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP - -/* - * U-Boot commands - */ -#include -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define xstr(s) str(s) -#define str(s) #s - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "u-boot=imx27/u-boot.bin\0" \ - "kernel_addr_r=a0800000\0" \ - "hostname=imx27\0" \ - "bootfile=imx27/uImage\0" \ - "rootpath=/opt/eldk-4.2-arm/arm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm\0" \ - "bootcmd=run net_nfs\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};cp.b ${fileaddr} " \ - xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - #endif /* __CONFIG_H */ diff --git a/include/configs/magnesium.h b/include/configs/magnesium.h new file mode 100644 index 0000000..4fb7744 --- /dev/null +++ b/include/configs/magnesium.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2010 Heiko Schocher + * + * based on: + * Copyright (C) 2009 Ilya Yanok + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* include common defines/options for all imx27lite related boards */ +#include "imx27lite-common.h" + +/* + * SoC Configuration + */ +#define CONFIG_MAGNESIUM +#define CONFIG_HOSTNAME magnesium +#define CONFIG_BOARDNAME "Projectiondesign magnesium\n" + +/* + * Flash & Environment + */ +#define CONFIG_SYS_FLASH_SECT_SZ 0x8000 /* 64KB sect size */ +#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x40000) +#define PHYS_FLASH_SIZE 0x800000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* Env sector Size */ + +/* + * NAND + */ +#define CONFIG_SYS_NAND_LARGEPAGE + +/* + * SD/MMC + */ +#define CONFIG_MXC_MCI_REGS_BASE 0x10013000 + +/* + * MTD partitions + */ +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0" +#define MTDPARTS_DEFAULT \ + "mtdparts=" \ + "physmap-flash.0:" \ + "256k(U-Boot)," \ + "7680k(user)," \ + "128k(env1)," \ + "128k(env2);" \ + "mxc_nand.0:" \ + "128k(IPL-SPL)," \ + "4m(kernel)," \ + "22m(rootfs)," \ + "-(userfs)" + +#endif /* __CONFIG_H */ -- cgit v1.1 From 272017853339f5b9685f9488bdaf5405812d12a4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 31 Mar 2010 06:32:56 -0700 Subject: MX51EVK: Remove CPLD related code There is no CPLD on MX51EVK board, so remove CPLD related function. Signed-off-by: Fabio Estevam --- board/freescale/mx51evk/mx51evk.c | 67 --------------------------------------- board/freescale/mx51evk/mx51evk.h | 1 - 2 files changed, 68 deletions(-) diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 8754563..f0b7abc 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -72,72 +72,6 @@ static void setup_iomux_uart(void) mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); } -static void setup_expio(void) -{ - u32 reg; - struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; - struct clkctl *pclkctl = (struct clkctl *)CCM_BASE_ADDR; - - /* CS5 setup */ - mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0); - writel(0x00410089, &pweim[5].csgcr1); - writel(0x00000002, &pweim[5].csgcr2); - - /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ - writel(0x32260000, &pweim[5].csrcr1); - - /* APR = 0 */ - writel(0x00000000, &pweim[5].csrcr2); - - /* - * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, - * WCSA=0, WCSN=0 - */ - writel(0x72080F00, &pweim[5].cswcr1); - - mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR + - IO_BOARD_OFFSET); - if ((readw(&mx51_io_board->id1) == 0xAAAA) && - (readw(&mx51_io_board->id2) == 0x5555)) { - if (is_soc_rev(CHIP_REV_2_0) < 0) { - reg = readl(&pclkctl->cbcdr); - reg = (reg & (~0x70000)) | 0x30000; - writel(reg, &pclkctl->cbcdr); - /* make sure divider effective */ - while (readl(&pclkctl->cdhipr) != 0) - ; - writel(0x0, &pclkctl->ccdr); - } - } else { - /* CS1 */ - writel(0x00410089, &pweim[1].csgcr1); - writel(0x00000002, &pweim[1].csgcr2); - /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ - writel(0x32260000, &pweim[1].csrcr1); - /* APR=0 */ - writel(0x00000000, &pweim[1].csrcr2); - /* - * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, - * WEN=0, WCSA=0, WCSN=0 - */ - writel(0x72080F00, &pweim[1].cswcr1); - mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR + - IO_BOARD_OFFSET); - } - - /* Reset interrupt status reg */ - writew(0x1F, &(mx51_io_board->int_rest)); - writew(0x00, &(mx51_io_board->int_rest)); - writew(0xFFFF, &(mx51_io_board->int_mask)); - - /* Reset the XUART and Ethernet controllers */ - reg = readw(&(mx51_io_board->sw_reset)); - reg |= 0x9; - writew(reg, &(mx51_io_board->sw_reset)); - reg &= ~0x9; - writew(reg, &(mx51_io_board->sw_reset)); -} - static void setup_iomux_fec(void) { /*FEC_MDIO*/ @@ -349,7 +283,6 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; setup_iomux_uart(); - setup_expio(); setup_iomux_fec(); return 0; } diff --git a/board/freescale/mx51evk/mx51evk.h b/board/freescale/mx51evk/mx51evk.h index 524cdcc..2854e71 100644 --- a/board/freescale/mx51evk/mx51evk.h +++ b/board/freescale/mx51evk/mx51evk.h @@ -47,5 +47,4 @@ struct io_board_ctrl { }; #endif -#define IO_BOARD_OFFSET (0x20000) #endif -- cgit v1.1 From 5e1fe88fe3df2555a8a0cba7d2ffaf2b03041dfb Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 28 Mar 2010 13:43:26 +0200 Subject: Moved board specific values in config file The lowlevel_init file contained some hard-coded values to setup the RAM. These board related values are moved into the board configuration file. Signed-off-by: Stefano Babic --- arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S | 5 ++++- include/configs/mx51evk.h | 3 +++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S b/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S index 31af9e2..783c81f 100644 --- a/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S +++ b/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S @@ -158,6 +158,7 @@ /* Switch peripheral to PLL 3 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x000010C0 + orr r1,r1,#CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR] @@ -171,6 +172,7 @@ ldr r1, =0x19239145 str r1, [r0, #CLKCTL_CBCDR] ldr r1, =0x000020C0 + orr r1,r1,#CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] mov r3, #DP_OP_216 @@ -201,9 +203,10 @@ /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ ldr r1, =0x000020C2 + orr r1,r1,#CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ - ldr r1, =0x59E35100 + ldr r1, =CONFIG_SYS_CLKTL_CBCDR str r1, [r0, #CLKCTL_CBCDR] /* Restore the default values in the Gate registers */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 903fe6d..3626df7 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -160,6 +160,9 @@ #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define CONFIG_SYS_DDR_CLKSEL 0 +#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 + /*----------------------------------------------------------------------- * FLASH and environment organization */ -- cgit v1.1 From 16b76705d36ac137fa9231cedfe1355561639e47 Mon Sep 17 00:00:00 2001 From: Siddarth Gore <[gores@marvell.com]> Date: Thu, 18 Mar 2010 20:25:40 +0530 Subject: Marvell GuruPlug Board Support GuruPlug Standard: 1 Gb Ethernet, 2 USB 2.0 GuruPlug Plus: 2 Gb Ethernet, 2 USB 2.0, 1 eSATA, 1 uSD slot References: http://www.globalscaletechnologies.com/t-guruplugdetails.aspx http://plugcomputer.org This patch is for GuruPlug Plus, but it supports Standard version as well. Signed-off-by: Siddarth Gore --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/Marvell/guruplug/Makefile | 51 ++++++++++ board/Marvell/guruplug/config.mk | 27 +++++ board/Marvell/guruplug/guruplug.c | 167 ++++++++++++++++++++++++++++++ board/Marvell/guruplug/guruplug.h | 39 +++++++ board/Marvell/guruplug/kwbimage.cfg | 162 +++++++++++++++++++++++++++++ include/configs/guruplug.h | 198 ++++++++++++++++++++++++++++++++++++ 9 files changed, 652 insertions(+) create mode 100644 board/Marvell/guruplug/Makefile create mode 100644 board/Marvell/guruplug/config.mk create mode 100644 board/Marvell/guruplug/guruplug.c create mode 100644 board/Marvell/guruplug/guruplug.h create mode 100644 board/Marvell/guruplug/kwbimage.cfg create mode 100644 include/configs/guruplug.h diff --git a/MAINTAINERS b/MAINTAINERS index 4e6d735..7f688c3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -194,6 +194,10 @@ Niklaus Giger MCU25 PPC405GPr HCU5 PPC440EPx +Siddarth Gore + + guruplug ARM926EJS (Kirkwood SoC) + Frank Gottschling MHPC MPC8xx diff --git a/MAKEALL b/MAKEALL index e2bba1c..326bde0 100755 --- a/MAKEALL +++ b/MAKEALL @@ -567,6 +567,7 @@ LIST_ARM9=" \ edb9312 \ edb9315 \ edb9315a \ + guruplug \ imx27lite \ lpd7a400 \ magnesium \ diff --git a/Makefile b/Makefile index 9213ec2..e49def3 100644 --- a/Makefile +++ b/Makefile @@ -2940,6 +2940,9 @@ davinci_dm365evm_config : unconfig davinci_dm6467evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci +guruplug_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood + magnesium_config \ imx27lite_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27 diff --git a/board/Marvell/guruplug/Makefile b/board/Marvell/guruplug/Makefile new file mode 100644 index 0000000..99748a7 --- /dev/null +++ b/board/Marvell/guruplug/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Siddarth Gore +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := guruplug.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/Marvell/guruplug/config.mk b/board/Marvell/guruplug/config.mk new file mode 100644 index 0000000..caa26b6 --- /dev/null +++ b/board/Marvell/guruplug/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Siddarth Gore +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +TEXT_BASE = 0x00600000 + +KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c new file mode 100644 index 0000000..ba47ca1 --- /dev/null +++ b/board/Marvell/guruplug/guruplug.c @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Siddarth Gore + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "guruplug.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(GURUPLUG_OE_VAL_LOW, + GURUPLUG_OE_VAL_HIGH, + GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* GPIO_RST */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GE1_8, + MPP29_GE1_9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GE1_14, + MPP35_GE1_15, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_TDM_SPI_SCK, + MPP41_TDM_SPI_MISO, + MPP42_TDM_SPI_MOSI, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, /* M_RLED */ + MPP47_GPIO, /* M_GLED */ + MPP48_GPIO, /* B_RLED */ + MPP49_GPIO, /* B_GLED */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +int dram_init(void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = kw_sdram_bar(i); + gd->bd->bi_dram[i].size = kw_sdram_bs(i); + } + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void mv_phy_88e1121_init(char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®); + reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg); + miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0); + + /* reset the phy */ + if (miiphy_read (name, devadr, PHY_BMCR, ®) != 0) { + printf("Err..(%s) PHY status read failed\n", __FUNCTION__); + return; + } + if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) { + printf("Err..(%s) PHY reset failed\n", __FUNCTION__); + return; + } + + printf("88E1121 Initialized on %s\n", name); +} + +void reset_phy(void) +{ + /* configure and initialize both PHY's */ + mv_phy_88e1121_init("egiga0"); + mv_phy_88e1121_init("egiga1"); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/guruplug/guruplug.h b/board/Marvell/guruplug/guruplug.h new file mode 100644 index 0000000..5bc16b4 --- /dev/null +++ b/board/Marvell/guruplug/guruplug.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Siddarth Gore + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __GURUPLUG_H +#define __GURUPLUG_H + +#define GURUPLUG_OE_LOW (~(0)) +#define GURUPLUG_OE_HIGH (~(0)) +#define GURUPLUG_OE_VAL_LOW 0 +#define GURUPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */ + +/* PHY related */ +#define MV88E1121_MAC_CTRL2_REG 21 +#define MV88E1121_PGADR_REG 22 +#define MV88E1121_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1121_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __GURUPLUG_H */ diff --git a/board/Marvell/guruplug/kwbimage.cfg b/board/Marvell/guruplug/kwbimage.cfg new file mode 100644 index 0000000..2afd927 --- /dev/null +++ b/board/Marvell/guruplug/kwbimage.cfg @@ -0,0 +1,162 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Siddarth Gore +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0/1 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b9b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x000000cc # DDR Address Control +# bit1-0: 01, Cs0width=x8 +# bit3-2: 10, Cs0size=1Gb +# bit5-4: 01, Cs1width=x8 +# bit7-6: 10, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h new file mode 100644 index 0000000..2fbc6ad --- /dev/null +++ b/include/configs/guruplug.h @@ -0,0 +1,198 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Siddarth Gore + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_GURUPLUG_H +#define _CONFIG_GURUPLUG_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nMarvell-GuruPlug" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_GURUPLUG /* Machine type */ + +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ + +/* + * CLKs configurations + */ +#define CONFIG_SYS_HZ 1000 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200,230400, 460800, 921600 } +/* auto boot */ +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_KIRKWOOD +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ +#define NAND_ALLOW_ERASE_ALL 1 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0x40000 +#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \ + "${x_bootcmd_ethernet}; setenv ethact egiga1; " \ + "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "bootm 0x6400000;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "x_bootcmd_ethernet=ping 192.168.2.1\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootcmd_kernel=nand read.e 0x6400000 0x100000 0x400000\0" \ + "x_bootargs=console=ttyS0,115200\0" \ + "x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required configurations + */ +#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ +#define CONFIG_SYS_MEMTEST_END 0x1fffffff /*(_512M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_CMD_MII +#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */ +#define CONFIG_PHY_BASE_ADR 0 +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv88e1121 PHY */ +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +#define CONFIG_SYS_ALT_MEMTEST + +#endif /* _CONFIG_GURUPLUG_H */ -- cgit v1.1 From 5414fec85ff558af8823d4391f03977288871fe4 Mon Sep 17 00:00:00 2001 From: Frans Meulenbroeks <[fransmeulenbroeks@gmail.com]> Date: Tue, 6 Apr 2010 18:26:19 +0530 Subject: configs/sheevaplug: added a few additional commands This patch includes a few additional commands in the sheevaplug version of u-boot: - support for LONGHELP so you can get help messages - auto completion and command editing - ubi and mii support - ext2 filesystem (convenient if you have an ext2 from which you want to boot) - jffs2 and ubifs filesystems (if you want to use these in NAND) This also makes it more similar to openrd client. Side effect of this patch is that the code now needs 3 sectors i.s.o. 2 so an existing env is overwritten Signed-off-by: Frans Meulenbroeks --- include/configs/sheevaplug.h | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index fc401a8..e9edc44 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -85,6 +85,7 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ + /* * Commands configuration */ @@ -93,7 +94,7 @@ #define CONFIG_CMD_AUTOSCRIPT #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV -#define CONFIG_CMD_FAT +#define CONFIG_CMD_MII #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB @@ -123,8 +124,8 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */ +#define CONFIG_ENV_ADDR 0x60000 +#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ /* * Default environment variables @@ -145,14 +146,16 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1 MiB for malloc() */ /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* * Other required minimal configurations */ -#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ @@ -192,4 +195,18 @@ #define CONFIG_SUPPORT_VFAT #endif /* CONFIG_CMD_USB */ +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + #endif /* _CONFIG_SHEEVAPLUG_H */ -- cgit v1.1 From 1c9d91aca649f17762bae2c0e38f5101d62ed0b5 Mon Sep 17 00:00:00 2001 From: Frans Meulenbroeks <[fransmeulenbroeks@gmail.com]> Date: Tue, 6 Apr 2010 19:06:11 +0530 Subject: configs/openrd_base.h: reordered macros moved CONFIG_CMD_FAT to filesystem section swapped CONFIG_CMD_NAND and CONFIG_CMD_MII so they are alpha correct Signed-off-by: Frans Meulenbroeks --- include/configs/openrd_base.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h index 88f27ba..d2f4502 100644 --- a/include/configs/openrd_base.h +++ b/include/configs/openrd_base.h @@ -99,9 +99,8 @@ #define CONFIG_CMD_AUTOSCRIPT #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NAND #define CONFIG_CMD_MII +#define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB @@ -208,6 +207,7 @@ /* * File system */ +#define CONFIG_CMD_FAT #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS #define CONFIG_RBTREE -- cgit v1.1 From 34196b0a8bd7ab6d472e2e6f6c90b73e915a1fae Mon Sep 17 00:00:00 2001 From: John Rigby Date: Wed, 7 Apr 2010 23:30:09 -0600 Subject: MX25 print arm clock instead of mpllclk on boot Replace call to imx_get_mpllclk with imx_get_armclk to show frequency of ARM core instead of mpll internal bus in print_cpuinfo. Signed-off-by: John Rigby CC: Stefano Babic --- arch/arm/cpu/arm926ejs/mx25/generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 694841d..b80a389 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -111,7 +111,7 @@ int print_cpuinfo (void) char buf[32]; printf ("CPU: Freescale i.MX25 at %s MHz\n\n", - strmhz (buf, imx_get_mpllclk ())); + strmhz (buf, imx_get_armclk ())); return 0; } #endif -- cgit v1.1 From f581e3a2157fbd736e7dd2378465ae242fba545c Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 13 Apr 2010 12:38:22 +0200 Subject: mkimage: correct spelling error in imximage Signed-off-by: Stefano Babic --- tools/imximage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/imximage.c b/tools/imximage.c index df2d8c4..39f89c2 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -36,7 +36,7 @@ * Supported commands for configuration file */ static table_entry_t imximage_cmds[] = { - {CMD_BOOT_FROM, "BOOT_FROM", "boot comand", }, + {CMD_BOOT_FROM, "BOOT_FROM", "boot command", }, {CMD_DATA, "DATA", "Reg Write Data", }, {-1, "", "", }, }; -- cgit v1.1 From dfe83352cb58c55dfdbd5b535cb335526cb1c581 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 13 Apr 2010 12:38:43 +0200 Subject: mx51evk: correct list of possible BOOT_FROM values Signed-off-by: Stefano Babic --- board/freescale/mx51evk/imximage.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg index db09913..a875e8f 100644 --- a/board/freescale/mx51evk/imximage.cfg +++ b/board/freescale/mx51evk/imximage.cfg @@ -26,7 +26,7 @@ # The syntax is taken as close as possible with the kwbimage # Boot Device : one of -# spi_flash, nand, onenand, sd_card +# spi, sd (the board has no nand neither onenand) BOOT_FROM spi -- cgit v1.1 From 7d27cd08b4c1adfd58c54aaa8b8c8f4eeb3c7021 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 13 Apr 2010 12:07:00 +0200 Subject: MX31: add accessor function to get a gpio The patch adds an accessor function to get the value of a gpio. Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx31/mx31.h | 5 +++++ drivers/gpio/mx31_gpio.c | 15 +++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/include/asm/arch-mx31/mx31.h b/arch/arm/include/asm/arch-mx31/mx31.h index 3cc4b35..f702d26 100644 --- a/arch/arm/include/asm/arch-mx31/mx31.h +++ b/arch/arm/include/asm/arch-mx31/mx31.h @@ -37,12 +37,17 @@ enum mx31_gpio_direction { extern int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction); extern void mx31_gpio_set(unsigned int gpio, unsigned int value); +extern int mx31_gpio_get(unsigned int gpio); #else static inline int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction) { return 1; } +static inline int mx31_gpio_get(unsigned int gpio) +{ + return 1; +} static inline void mx31_gpio_set(unsigned int gpio, unsigned int value) { } diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c index 737aafa..b07f038 100644 --- a/drivers/gpio/mx31_gpio.c +++ b/drivers/gpio/mx31_gpio.c @@ -71,3 +71,18 @@ void mx31_gpio_set(unsigned int gpio, unsigned int value) l &= ~(1 << gpio); __REG(gpio_ports[port] + GPIO_DR) = l; } + +int mx31_gpio_get(unsigned int gpio) +{ + unsigned int port = gpio >> 5; + u32 l; + + if (port >= ARRAY_SIZE(gpio_ports)) + return -1; + + gpio &= 0x1f; + + l = (__REG(gpio_ports[port] + GPIO_DR) >> gpio) & 0x01; + + return l; +} -- cgit v1.1 From efb9591069ee276f7fa27a821240c7511f72fe65 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 29 Mar 2010 15:56:10 +0200 Subject: MX31: add pin definitions for NAND controller Add pin definitions ralted to the NAND controller to be used to set up the pin multiplexer. Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx31/mx31-regs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/mx31-regs.h index 6f6e9a4..c59255e 100644 --- a/arch/arm/include/asm/arch-mx31/mx31-regs.h +++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h @@ -207,6 +207,15 @@ struct clock_control_regs { #define MUX_CTL_CSPI1_SS0 0x8e #define MUX_CTL_CSPI1_SS1 0x8f +#define MUX_CTL_NFC_WP 0xD0 +#define MUX_CTL_NFC_CE 0xD1 +#define MUX_CTL_NFC_RB 0xD2 +#define MUX_CTL_NFC_WE 0xD4 +#define MUX_CTL_NFC_RE 0xD5 +#define MUX_CTL_NFC_ALE 0xD6 +#define MUX_CTL_NFC_CLE 0xD7 + + /* * Helper macros for the MUX_[contact name]__[pin function] macros */ -- cgit v1.1 From 45997e0a86ee8d8abec6d791a241cb20011fe0e3 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 29 Mar 2010 16:43:39 +0200 Subject: MX31: Add support for NAND to QONG board The NAND device is connected to the FPGA of the QONG board and not to the NFC controller. For this reason, the FPGA must be set and initialized before accessing to the NAND itself. Signed-off-by: Stefano Babic --- board/davedenx/qong/qong.c | 93 +++++++++++++++++++++++++++++++---------- board/davedenx/qong/qong_fpga.h | 4 +- include/configs/qong.h | 27 ++++++++++++ 3 files changed, 101 insertions(+), 23 deletions(-) diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index b801150..e73d26b 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "qong_fpga.h" DECLARE_GLOBAL_DATA_PTR; @@ -38,6 +39,15 @@ int dram_init (void) return 0; } +static void qong_fpga_reset(void) +{ + mx31_gpio_set(QONG_FPGA_RST_PIN, 0); + udelay(30); + mx31_gpio_set(QONG_FPGA_RST_PIN, 1); + + udelay(300); +} + int board_init (void) { /* Chip selects */ @@ -101,6 +111,15 @@ int board_init (void) mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO)); mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO)); + + /* FPGA reset Pin */ + /* rstn = 0 */ + mx31_gpio_set(QONG_FPGA_RST_PIN, 0); + mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT); + + /* set interrupt pin as input */ + mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN); + #endif /* setup pins for UART1 */ @@ -127,32 +146,11 @@ int misc_init_r (void) #ifdef CONFIG_QONG_FPGA u32 tmp; - /* FPGA reset */ - /* rstn = 0 */ - tmp = __REG(GPIO2_BASE + GPIO_DR); - tmp &= (~(1 << QONG_FPGA_RST_PIN)); - __REG(GPIO2_BASE + GPIO_DR) = tmp; - /* set the GPIO as output */ - tmp = __REG(GPIO2_BASE + GPIO_GDIR); - tmp |= (1 << QONG_FPGA_RST_PIN); - __REG(GPIO2_BASE + GPIO_GDIR) = tmp; - /* wait */ - udelay(30); - /* rstn = 1 */ - tmp = __REG(GPIO2_BASE + GPIO_DR); - tmp |= (1 << QONG_FPGA_RST_PIN); - __REG(GPIO2_BASE + GPIO_DR) = tmp; - /* set interrupt pin as input */ - __REG(GPIO2_BASE + GPIO_GDIR) = tmp | (1 << QONG_FPGA_IRQ_PIN); - /* wait while the FPGA starts */ - udelay(300); - tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION; printf("FPGA: "); printf("version register = %u.%u.%u\n", (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF); #endif - return 0; } @@ -164,3 +162,56 @@ int board_eth_init(bd_t *bis) return 0; #endif } + +#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT) +static void board_nand_setup(void) +{ + + /* CS3: NAND 8-bit */ + __REG(CSCR_U(3)) = 0x00004f00; + __REG(CSCR_L(3)) = 0x20013b31; + __REG(CSCR_A(3)) = 0x00020800; + __REG(IOMUXC_GPR) |= 1 << 13; + + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO)); + + /* Make sure to reset the fpga else you cannot access NAND */ + qong_fpga_reset(); + + /* Enable NAND flash */ + mx31_gpio_set(15, 1); + mx31_gpio_set(14, 1); + mx31_gpio_direction(15, MX31_GPIO_DIRECTION_OUT); + mx31_gpio_direction(16, MX31_GPIO_DIRECTION_IN); + mx31_gpio_direction(14, MX31_GPIO_DIRECTION_IN); + mx31_gpio_set(15, 0); + +} + +int qong_nand_rdy(void *chip) +{ + udelay(1); + return mx31_gpio_get(16); +} + +void qong_nand_select_chip(struct mtd_info *mtd, int chip) +{ + if (chip >= 0) + mx31_gpio_set(15, 0); + else + mx31_gpio_set(15, 1); + +} + +void qong_nand_plat_init(void *chip) +{ + struct nand_chip *nand = (struct nand_chip *)chip; + nand->chip_delay = 20; + nand->select_chip = qong_nand_select_chip; + nand->options &= ~NAND_BUSWIDTH_16; + board_nand_setup(); +} + +#endif diff --git a/board/davedenx/qong/qong_fpga.h b/board/davedenx/qong/qong_fpga.h index e8042b1..4e11f5a 100644 --- a/board/davedenx/qong/qong_fpga.h +++ b/board/davedenx/qong/qong_fpga.h @@ -33,8 +33,8 @@ #define QONG_FPGA_TMS_PIN 25 #define QONG_FPGA_TDI_PIN 8 #define QONG_FPGA_TDO_PIN 7 -#define QONG_FPGA_RST_PIN 16 -#define QONG_FPGA_IRQ_PIN 8 +#define QONG_FPGA_RST_PIN 48 +#define QONG_FPGA_IRQ_PIN 40 #endif #endif /* QONG_FPGA_H */ diff --git a/include/configs/qong.h b/include/configs/qong.h index e41ea91..669b586 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -52,6 +52,8 @@ #define CONFIG_MXC_UART 1 #define CONFIG_SYS_MX31_UART1 1 +#define CONFIG_MX31_GPIO + /* FPGA */ #define CONFIG_QONG_FPGA 1 #define CONFIG_FPGA_BASE (CS1_BASE) @@ -96,6 +98,7 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NAND /* * You can compile in a MAC address and your custom net settings by using @@ -188,6 +191,30 @@ #define PHYS_SDRAM_1 CSD0_BASE #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ +/* + * NAND driver + */ + +#ifndef __ASSEMBLY__ +extern void qong_nand_plat_init(void *chip); +extern int qong_nand_rdy(void *chip); +#endif +#define CONFIG_NAND_PLAT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CS3_BASE +#define NAND_PLAT_INIT() qong_nand_plat_init(nand) + +#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24)) +#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23)) +#define QONG_NAND_WRITE(addr, cmd) \ + do { \ + __REG8(addr) = cmd; \ + } while (0) + +#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd) +#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd) +#define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip)) + /*----------------------------------------------------------------------- * FLASH and environment organization */ -- cgit v1.1 From eab40f819ddd50eef465619db1386c053b59a95b Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 31 Mar 2010 10:27:47 +0200 Subject: MX31: Support 128MB RAM on QONG module The QONG module can be downsized and delivered with 128MB instead of 256MB. The patch adds run time support for the two different memory configurations. Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx31/mx31-regs.h | 6 ++ board/davedenx/qong/lowlevel_init.S | 130 +++++++++++++++++++++-------- 2 files changed, 103 insertions(+), 33 deletions(-) diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/mx31-regs.h index c59255e..d72585c 100644 --- a/arch/arm/include/asm/arch-mx31/mx31-regs.h +++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h @@ -303,4 +303,10 @@ struct clock_control_regs { */ #define NFC_BASE_ADDR 0xB8000000 +/* + * Internal RAM (16KB) + */ +#define IRAM_BASE_ADDR 0x1FFFC000 +#define IRAM_SIZE (16 * 1024) + #endif /* __ASM_ARCH_MX31_REGS_H */ diff --git a/board/davedenx/qong/lowlevel_init.S b/board/davedenx/qong/lowlevel_init.S index 198dd76..80bed92 100644 --- a/board/davedenx/qong/lowlevel_init.S +++ b/board/davedenx/qong/lowlevel_init.S @@ -42,6 +42,27 @@ bcs 1b .endm +.macro SETUP_RAM cfg, ctl + /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ + REG 0xB8001010, 0x00000004 + ldr r3, =\cfg + ldr r2, =WEIM_ESDCFG0 + str r3, [r2] + REG 0xB8001000, 0x92100000 + REG 0x80000f00, 0x12344321 + REG 0xB8001000, 0xa2100000 + REG 0x80000000, 0x12344321 + REG 0x80000000, 0x12344321 + REG 0xB8001000, 0xb2100000 + REG8 0x80000033, 0xda + REG8 0x81000000, 0xff + ldr r3, =\ctl + ldr r2, =WEIM_ESDCTL0 + str r3, [r2] + REG 0x80000000, 0xDEADBEEF + REG 0xB8001010, 0x0000000c + +.endm /* RedBoot: To support 133MHz DDR */ .macro init_drive_strength /* @@ -130,43 +151,86 @@ lowlevel_init: /* Default: 1, 4, 12, 1 */ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) - /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ - REG 0xB8001010, 0x00000004 - REG 0xB8001004, ((3 << 21) | /* tXP */ \ - (0 << 20) | /* tWTR */ \ - (2 << 18) | /* tRP */ \ - (1 << 16) | /* tMRD */ \ - (0 << 15) | /* tWR */ \ - (5 << 12) | /* tRAS */ \ - (1 << 10) | /* tRRD */ \ - (3 << 8) | /* tCAS */ \ - (2 << 4) | /* tRCD */ \ - (7 << 0) /* tRC */ ) - REG 0xB8001000, 0x92100000 - REG 0x80000f00, 0x12344321 - REG 0xB8001000, 0xa2100000 - REG 0x80000000, 0x12344321 - REG 0x80000000, 0x12344321 - REG 0xB8001000, 0xb2100000 - REG8 0x80000033, 0xda - REG8 0x81000000, 0xff - REG 0xB8001000, ((1 << 31) | \ - (0 << 28) | \ - (0 << 27) | \ - (3 << 24) | /* 14 rows */ \ - (2 << 20) | /* 10 cols */ \ - (2 << 16) | \ - (4 << 13) | /* 3.91us (64ms/16384) */ \ - (0 << 10) | \ - (0 << 8) | \ - (1 << 7) | \ - (0 << 0)) - REG 0x80000000, 0xDEADBEEF - REG 0xB8001010, 0x0000000c +check_ddr_module: +/* Set stackpointer in internal RAM to call get_ram_size */ + ldr sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16) + stmfd sp!, {r0-r11, ip, lr} + mov ip, lr /* save link reg across call */ + + ldr r0,=0x08000000 + SETUP_RAM ESDCFG0_256MB, ESDCTL0_256MB + ldr r0,=0x80000000 + ldr r1,=0x10000000 + bl get_ram_size + ldr r1,=0x10000000 + cmp r0,r1 + beq restore_regs + SETUP_RAM ESDCFG0_128MB, ESDCTL0_128MB + ldr r0,=0x80000000 + ldr r1,=0x08000000 + bl get_ram_size + ldr r1,=0x08000000 + cmp r0,r1 + beq restore_regs + +restore_regs: + ldmfd sp!, {r0-r11, ip, lr} + mov lr, ip /* restore link reg */ mov pc, lr + MPCTL_PARAM_399: .word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0)) UPCTL_PARAM_240: .word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0)) + + .equ ESDCFG0_128MB, \ + (0 << 21) + /* tXP */ \ + (1 << 20) + /* tWTR */ \ + (2 << 18) + /* tRP */ \ + (1 << 16) + /* tMRD */ \ + (0 << 15) + /* tWR */ \ + (5 << 12) + /* tRAS */ \ + (1 << 10) + /* tRRD */ \ + (3 << 8) + /* tCAS */ \ + (2 << 4) + /* tRCD */ \ + (0x0F << 0) /* tRC */ + + .equ ESDCTL0_128MB, \ + (1 << 31) + /* enable */ \ + (0 << 28) + /* mode */ \ + (0 << 27) + /* supervisor protect */ \ + (2 << 24) + /* 13 rows */ \ + (2 << 20) + /* 10 cols */ \ + (2 << 16) + /* 32 bit */ \ + (3 << 13) + /* 7.81us (64ms/8192) */ \ + (0 << 10) + /* power down timer */ \ + (0 << 8) + /* full page */ \ + (1 << 7) + /* burst length */ \ + (0 << 0) /* precharge timer */ + + .equ ESDCFG0_256MB, \ + (3 << 21) + /* tXP */ \ + (0 << 20) + /* tWTR */ \ + (2 << 18) + /* tRP */ \ + (1 << 16) + /* tMRD */ \ + (0 << 15) + /* tWR */ \ + (5 << 12) + /* tRAS */ \ + (1 << 10) + /* tRRD */ \ + (3 << 8) + /* tCAS */ \ + (2 << 4) + /* tRCD */ \ + (7 << 0) /* tRC */ + + .equ ESDCTL0_256MB, \ + (1 << 31) + \ + (0 << 28) + \ + (0 << 27) + \ + (3 << 24) + /* 14 rows */ \ + (2 << 20) + /* 10 cols */ \ + (2 << 16) + \ + (4 << 13) + /* 3.91us (64ms/16384) */ \ + (0 << 10) + \ + (0 << 8) + \ + (1 << 7) + \ + (0 << 0) -- cgit v1.1 From c9d944d35e7904229c5333e761bce9d4324971f8 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 8 Apr 2010 17:23:52 +0200 Subject: MX31: Add UBI support to QONG module The UBI/UBIFS support is added to the QONG module. Signed-off-by: Stefano Babic --- include/configs/qong.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/include/configs/qong.h b/include/configs/qong.h index 669b586..baf8481 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -41,7 +41,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128 @@ -97,7 +97,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NET #define CONFIG_CMD_MII -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NAND /* @@ -229,7 +228,7 @@ extern int qong_nand_rdy(void *chip); #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) /* Address and size of Redundant Environment Sector */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) @@ -248,9 +247,15 @@ extern int qong_nand_rdy(void *chip); #define CONFIG_SYS_FLASH_PROTECTION 1 /* - * JFFS2 partitions + * Filesystem */ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_PARTITIONS #define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=physmap-flash.0" -- cgit v1.1 From eeb50ce193453951529015f50e5c1ccd7b55aad2 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 13 Apr 2010 12:19:06 +0200 Subject: MX31: Removed erroneous board name from QONG QONG is a module that can be installed on several boards, not only on the QONG-EVB manufactured by Dave srl. Signed-off-by: Stefano Babic --- board/davedenx/qong/qong.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index e73d26b..eb9218e 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -137,7 +137,7 @@ int board_init (void) int checkboard (void) { - printf("Board: DAVE/DENX QongEVB-LITE\n"); + printf("Board: DAVE/DENX Qong\n"); return 0; } -- cgit v1.1 From d6b91e30d32871eb20b6227519fd2f3a6ea073fd Mon Sep 17 00:00:00 2001 From: Asen Dimov Date: Mon, 19 Apr 2010 14:17:22 +0300 Subject: at91: define matrix registers bit fields Signed-off-by: Asen Dimov --- arch/arm/include/asm/arch-at91/at91_matrix.h | 138 +++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm/include/asm/arch-at91/at91_matrix.h b/arch/arm/include/asm/arch-at91/at91_matrix.h index 981ec20..f99b1d4 100644 --- a/arch/arm/include/asm/arch-at91/at91_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91_matrix.h @@ -113,4 +113,142 @@ typedef struct at91_matrix { #define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008 +#if defined CONFIG_AT91SAM9261 +/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_MCFG_RCB0 (1 << 0) +/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_MCFG_RCB1 (1 << 1) +#endif + +/* Undefined Length Burst Type */ +#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ + defined(CONFIG_AT91SAM9G45) +#define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000 +#define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001 +#define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002 +#define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003 +#define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004 +#endif +#if defined(CONFIG_AT91SAM9G45) +#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005 +#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006 +#define AT91_MATRIX_MCFG_ULBT_128 0x00000007 +#endif + +/* Default Master Type */ +#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000 +#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000 +#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000 + +/* Fixed Index of Default Master */ +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) +#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18) +#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260) +#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18) +#endif + +/* Maximum Number of Allowed Cycles for a Burst */ +#if defined(CONFIG_AT91SAM9G45) +#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0) +#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ + defined(CONFIG_AT91SAM9263) +#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0) +#endif + +/* Arbitration Type */ +#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) +#define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000 +#define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000 +#endif + +/* Master Remap Control Register */ +#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ + defined(CONFIG_AT91SAM9G45) +/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_MRCR_RCB0 (1 << 0) +/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_MRCR_RCB1 (1 << 1) +#endif +#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) +#define AT91_MATRIX_MRCR_RCB2 0x00000004 +#define AT91_MATRIX_MRCR_RCB3 0x00000008 +#define AT91_MATRIX_MRCR_RCB4 0x00000010 +#define AT91_MATRIX_MRCR_RCB5 0x00000020 +#define AT91_MATRIX_MRCR_RCB6 0x00000040 +#define AT91_MATRIX_MRCR_RCB7 0x00000080 +#define AT91_MATRIX_MRCR_RCB8 0x00000100 +#endif +#if defined(CONFIG_AT91SAM9G45) +#define AT91_MATRIX_MRCR_RCB9 0x00000200 +#define AT91_MATRIX_MRCR_RCB10 0x00000400 +#define AT91_MATRIX_MRCR_RCB11 0x00000800 +#endif + +/* TCM Configuration Register */ +#if defined(CONFIG_AT91SAM9G45) +/* Size of ITCM enabled memory block */ +#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 +#define AT91_MATRIX_TCMR_ITCM_32 0x00000040 +/* Size of DTCM enabled memory block */ +#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 +#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 +#define AT91_MATRIX_TCMR_DTCM_64 0x00000070 +/* Wait state TCM register */ +#define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000 +#define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800 +#endif +#if defined(CONFIG_AT91SAM9263) +/* Size of ITCM enabled memory block */ +#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 +#define AT91_MATRIX_TCMR_ITCM_16 0x00000005 +#define AT91_MATRIX_TCMR_ITCM_32 0x00000006 +/* Size of DTCM enabled memory block */ +#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 +#define AT91_MATRIX_TCMR_DTCM_16 0x00000050 +#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 +#endif +#if defined(CONFIG_AT91SAM9261) +/* Size of ITCM enabled memory block */ +#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 +#define AT91_MATRIX_TCMR_ITCM_16 0x00000005 +#define AT91_MATRIX_TCMR_ITCM_32 0x00000006 +#define AT91_MATRIX_TCMR_ITCM_64 0x00000007 +/* Size of DTCM enabled memory block */ +#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 +#define AT91_MATRIX_TCMR_DTCM_16 0x00000050 +#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 +#define AT91_MATRIX_TCMR_DTCM_64 0x00000070 +#endif + +#if defined(CONFIG_AT91SAM9G45) +/* Video Mode Configuration Register */ +#define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000 +#define AT91C_MATRIX_VDEC_SEL_ON 0x00000001 +/* Write Protect Mode Register */ +#define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000 +#define AT91_MATRIX_WPMR_WP_WPEN 0x00000001 +#define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */ +/* Write Protect Status Register */ +#define AT91_MATRIX_WPSR_NO_WPV 0x00000000 +#define AT91_MATRIX_WPSR_WPV 0x00000001 +#define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */ +#endif + +/* USB Pad Pull-Up Control Register */ +#if defined(CONFIG_AT91SAM9261) +#define AT91_MATRIX_USBPUCR_PUON 0x40000000 +#endif + +#define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/ +#define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/ +#define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/ +#define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/ +#define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/ +#define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/ +#define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/ +#define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/ +#define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */ +#define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */ +#define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */ + #endif -- cgit v1.1 From 20d98c2cea3398ad93beccd4727a371f41514086 Mon Sep 17 00:00:00 2001 From: Asen Dimov Date: Mon, 19 Apr 2010 14:18:43 +0300 Subject: pm9263 converted to at91 soc access Signed-off-by: Asen Dimov --- board/ronetix/pm9263/led.c | 15 ++-- board/ronetix/pm9263/pm9263.c | 195 ++++++++++++++++++++++-------------------- include/configs/pm9263.h | 87 ++++++++++--------- 3 files changed, 152 insertions(+), 145 deletions(-) diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c index fe1a1d2..4e585a4 100644 --- a/board/ronetix/pm9263/led.c +++ b/board/ronetix/pm9263/led.c @@ -26,18 +26,19 @@ #include #include #include -#include +#include #include void coloured_LED_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB | - 1 << AT91SAM9263_ID_PIOCDE); + writel(1 << AT91SAM9263_ID_PIOB, &pmc->pcer); - at91_set_gpio_output(CONFIG_RED_LED, 1); - at91_set_gpio_output(CONFIG_GREEN_LED, 1); + at91_set_pio_output(CONFIG_RED_LED, 1); + at91_set_pio_output(CONFIG_GREEN_LED, 1); - at91_set_gpio_value(CONFIG_RED_LED, 0); - at91_set_gpio_value(CONFIG_GREEN_LED, 1); + at91_set_pio_value(CONFIG_RED_LED, 0); + at91_set_pio_value(CONFIG_GREEN_LED, 1); } diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 23ea154..c7835de 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -27,13 +27,13 @@ #include #include #include -#include #include #include #include #include +#include +#include #include -#include #include #include #include @@ -55,52 +55,59 @@ DECLARE_GLOBAL_DATA_PTR; static void pm9263_nand_hw_init(void) { unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBI0CSA); - at91_sys_write(AT91_MATRIX_EBI0CSA, - csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(1) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(1)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif #ifdef CONFIG_MACB static void pm9263_macb_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + /* * PB27 enables the 50MHz oscillator for Ethernet PHY * 1 - enable * 0 - disable */ - at91_set_gpio_output(AT91_PIN_PB27, 1); - at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ + at91_set_pio_output(AT91_PIO_PORTB, 27, 1); + at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); /* * Disable pull-up on: @@ -110,19 +117,15 @@ static void pm9263_macb_hw_init(void) * * PHY has internal pull-down */ - writel(pin_to_mask(AT91_PIN_PC25), - pin_to_controller(AT91_PIN_PC0) + PIO_PUDR); - writel(pin_to_mask(AT91_PIN_PE25) | - pin_to_mask(AT91_PIN_PE26), - pin_to_controller(AT91_PIN_PE0) + PIO_PUDR); + at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0); + at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0); + at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0); /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PC25), - pin_to_controller(AT91_PIN_PC0) + PIO_PUER); - writel(pin_to_mask(AT91_PIN_PE25) | - pin_to_mask(AT91_PIN_PE26), - pin_to_controller(AT91_PIN_PE0) + PIO_PUER); + at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1); + at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1); + at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1); at91_macb_hw_init(); } @@ -148,17 +151,17 @@ vidinfo_t panel_info = { void lcd_enable(void) { - at91_set_gpio_value(AT91_PIN_PA22, 1); /* power up */ + at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */ } void lcd_disable(void) { - at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */ + at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ } #ifdef CONFIG_LCD_IN_PSRAM -#define PSRAM_CRE_PIN AT91_PIN_PB29 +#define PSRAM_CRE_PIN AT91_PIO_PORTB, 29 #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2) /* Initialize the PSRAM memory */ @@ -166,31 +169,34 @@ static int pm9263_lcd_hw_psram_init(void) { volatile uint16_t x; unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC1_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; /* Enable CS3 3.3v, no pull-ups */ - csa = at91_sys_read(AT91_MATRIX_EBI1CSA); - at91_sys_write(AT91_MATRIX_EBI1CSA, - csa | AT91_MATRIX_EBI1_DBPUC | - AT91_MATRIX_EBI1_VDDIOMSEL_3_3V); + csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC | + AT91_MATRIX_CSA_VDDIOMSEL_3_3V; + + writel(csa, &matrix->csa[1]); /* Configure SMC1 CS0 for PSRAM - 16-bit */ - at91_sys_write(AT91_SMC1_SETUP(0), - AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC1_PULSE(0), - AT91_SMC_NWEPULSE_(7) | AT91_SMC_NCS_WRPULSE_(7) | - AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(7)); - at91_sys_write(AT91_SMC1_CYCLE(0), - AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8)); - at91_sys_write(AT91_SMC1_MODE(0), - AT91_SMC_DBW_16 | - AT91_SMC_PMEN | - AT91_SMC_PS_32); + writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[0].setup); + + writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7), + &smc->cs[0].pulse); + + writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), + &smc->cs[0].cycle); + + writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32, + &smc->cs[0].mode); /* setup PB29 as output */ - at91_set_gpio_output(PSRAM_CRE_PIN, 1); + at91_set_pio_output(PSRAM_CRE_PIN, 1); - at91_set_gpio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */ + at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */ /* PSRAM: write BCR */ x = readw(PSRAM_CTRL_REG); @@ -216,7 +222,7 @@ static int pm9263_lcd_hw_psram_init(void) /* test if the chip is MT45W2M16B */ if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) { /* try with CRE=1 (MT45W2M16A) */ - at91_set_gpio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */ + at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */ /* write RCR of the PSRAM */ x = readw(PSRAM_CTRL_REG); @@ -229,17 +235,14 @@ static int pm9263_lcd_hw_psram_init(void) writew(0x1234, PHYS_PSRAM); writew(0x5678, PHYS_PSRAM+2); if ((readw(PHYS_PSRAM) != 0x1234) - || (readw(PHYS_PSRAM + 2) != 0x5678)) + || (readw(PHYS_PSRAM + 2) != 0x5678)) return 1; } /* Bus matrix */ - at91_sys_write( AT91_MATRIX_PRAS5, AT91_MATRIX_M5PR ); - at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY | - (AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) | - AT91_MATRIX_DEFMSTR_TYPE_FIXED | - (AT91_MATRIX_SLOT_CYCLE & (0xFF << 0))); + writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a); + writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]); return 0; } @@ -247,35 +250,37 @@ static int pm9263_lcd_hw_psram_init(void) static void pm9263_lcd_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */ - at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ - at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ - at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ - at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ - at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ - at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ - at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ - at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ - at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ - at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ - - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC); + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ + at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ + at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ + at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ + + writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer); /* Power Control */ - at91_set_gpio_output(AT91_PIN_PA22, 1); - at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */ + at91_set_pio_output(AT91_PIO_PORTA, 22, 1); + at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ #ifdef CONFIG_LCD_IN_PSRAM /* initialize te PSRAM */ @@ -337,13 +342,15 @@ void lcd_show_board_info(void) int board_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Enable Ctrlc */ console_init_f(); - at91_sys_write(AT91_PMC_PCER, - (1 << AT91SAM9263_ID_PIOA) | - (1 << AT91SAM9263_ID_PIOCDE) | - (1 << AT91SAM9263_ID_PIOB)); + writel((1 << AT91SAM9263_ID_PIOA) | + (1 << AT91SAM9263_ID_PIOCDE) | + (1 << AT91SAM9263_ID_PIOB), + &pmc->pcer); /* arch number of AT91SAM9263EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_PM9263; @@ -394,7 +401,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x01); + rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01); #endif return rc; } diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index f854f38..9735e6a 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -28,8 +28,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY - /* ARM asynchronous clock */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -49,41 +47,37 @@ /* clocks */ #define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ + (AT91_PMC_MOR_MOSCEN | \ (255 << 8)) /* Main Oscillator Start-up Time */ #define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ - AT91_PMC_PLLCOUNT | /* PLL Counter */ \ + (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_PLLXR_OUT(3) | \ + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ (2 << 28) | /* PLL Clock Frequency Range */ \ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) #if (MAIN_PLL_DIV == 2) /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) + (AT91_PMC_MCKR_CSS_SLOW | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) + (AT91_PMC_MCKR_CSS_PLLA | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) #else /* PCK/4 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91RM9200_PMC_MDIV_3 | \ - AT91_PMC_PDIV_1) + (AT91_PMC_MCKR_CSS_SLOW | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_4) /* PCK/4 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91RM9200_PMC_MDIV_3 | \ - AT91_PMC_PDIV_1) + (AT91_PMC_MCKR_CSS_PLLA | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_4) #endif /* define PDC[31:16] as DATA[31:16] */ #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 @@ -91,8 +85,8 @@ #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ - (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \ - AT91_MATRIX_EBI0_CS1A_SDRAMC) + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ + AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ @@ -135,32 +129,32 @@ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) #define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) #define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) #define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | \ + AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ #define CONFIG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) + AT91_RSTC_CR_PROCRST | \ + AT91_RSTC_MR_ERSTL(1) | \ + AT91_RSTC_MR_ERSTL(2)) /* Disable Watchdog */ #define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xfff) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xfff)) #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 @@ -196,8 +190,8 @@ /* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */ -#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */ +#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* this is the power led */ +#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* this is the user1 led */ #define CONFIG_BOOTDELAY 3 @@ -258,8 +252,8 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 30 #endif @@ -273,6 +267,11 @@ /* PSRAM */ #define PHYS_PSRAM 0x70000000 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ +/* Slave EBI1, PSRAM connected */ +#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ + AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ + AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ + AT91_MATRIX_SCFG_SLOT_CYCLE(255)) /* Ethernet */ #define CONFIG_MACB 1 -- cgit v1.1