From 7ea7f689cab5bf715255e22c31aeefb23259afe5 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 4 Jun 2013 11:00:57 +0200 Subject: arm, am33xx: move uart soft reset code to common place move uart soft reset code to common place and call this function from board code, instead of copy and paste this code for every board. Signed-off-by: Heiko Schocher Cc: Matt Porter Cc: Lars Poeschel Cc: Tom Rini Cc: Enric Balletbo i Serra Acked-by: Tom Rini [trini: Fix igep0033 build, remove 'regval' on pcm051] Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/board.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + board/isee/igep0033/board.c | 24 +----------------------- board/phytec/pcm051/board.c | 23 +---------------------- board/ti/am335x/board.c | 23 +---------------------- board/ti/ti814x/evm.c | 19 +------------------ 6 files changed, 27 insertions(+), 85 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index d3b3612..b935a29 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -166,4 +166,26 @@ void rtc32k_enable(void) /* Enable the RTC 32K OSC by setting bits 3 and 6. */ writel((1 << 3) | (1 << 6), &rtc->osc); } + +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +void uart_soft_reset(void) +{ + struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; + u32 regval; + + regval = readl(&uart_base->uartsyscfg); + regval |= UART_RESET; + writel(regval, &uart_base->uartsyscfg); + while ((readl(&uart_base->uartsyssts) & + UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) + ; + + /* Disable smart idle */ + regval = readl(&uart_base->uartsyscfg); + regval |= UART_SMART_IDLE_EN; + writel(regval, &uart_base->uartsyscfg); +} #endif diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index cbbb54e..307ac28 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -44,4 +44,5 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, void omap_nand_switch_ecc(uint32_t, uint32_t); void rtc32k_enable(void); +void uart_soft_reset(void); #endif diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 3e9e25f..ea3bea5 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -36,21 +36,13 @@ DECLARE_GLOBAL_DATA_PTR; static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -#ifdef CONFIG_SPL_BUILD -static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; -#endif /* MII mode defines */ #define RMII_MODE_ENABLE 0x4D static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -/* UART Defines */ #ifdef CONFIG_SPL_BUILD -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) - static const struct ddr_data ddr3_data = { .datardsratio0 = K4B2G1646EBIH9_RD_DQS, .datawdsratio0 = K4B2G1646EBIH9_WR_DQS, @@ -115,23 +107,9 @@ void s_init(void) /* Enable RTC32K clock */ rtc32k_enable(); - /* UART softreset */ - u32 regval; - enable_uart0_pin_mux(); - regval = readl(&uart_base->uartsyscfg); - regval |= UART_RESET; - writel(regval, &uart_base->uartsyscfg); - while ((readl(&uart_base->uartsyssts) & - UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) - ; - - /* Disable smart idle */ - regval = readl(&uart_base->uartsyscfg); - regval |= UART_SMART_IDLE_EN; - writel(regval, &uart_base->uartsyscfg); - + uart_soft_reset(); gd = &gdata; preloader_console_init(); diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 281f699..0cca8d7 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -39,9 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -#ifdef CONFIG_SPL_BUILD -static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; -#endif /* MII mode defines */ #define MII_MODE_ENABLE 0x0 @@ -50,11 +47,7 @@ static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -/* UART defines */ #ifdef CONFIG_SPL_BUILD -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) /* DDR RAM defines */ #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ @@ -125,22 +118,8 @@ void s_init(void) /* Enable RTC32K clock */ rtc32k_enable(); - /* UART softreset */ - u32 regval; - enable_uart0_pin_mux(); - - regval = readl(&uart_base->uartsyscfg); - regval |= UART_RESET; - writel(regval, &uart_base->uartsyscfg); - while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK) - != UART_CLK_RUNNING_MASK) - ; - - /* Disable smart idle */ - regval = readl(&uart_base->uartsyscfg); - regval |= UART_SMART_IDLE_EN; - writel(regval, &uart_base->uartsyscfg); + uart_soft_reset(); gd = &gdata; diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 75f129e..fb98df0 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -38,9 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -#ifdef CONFIG_SPL_BUILD -static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; -#endif /* MII mode defines */ #define MII_MODE_ENABLE 0x0 @@ -126,12 +123,7 @@ static int read_eeprom(void) return 0; } -/* UART Defines */ #ifdef CONFIG_SPL_BUILD -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) - static const struct ddr_data ddr2_data = { .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | (MT47H128M16RT25E_RD_DQS<<20) | @@ -314,9 +306,6 @@ void s_init(void) /* Enable RTC32K clock */ rtc32k_enable(); - /* UART softreset */ - u32 regVal; - #ifdef CONFIG_SERIAL1 enable_uart0_pin_mux(); #endif /* CONFIG_SERIAL1 */ @@ -336,17 +325,7 @@ void s_init(void) enable_uart5_pin_mux(); #endif /* CONFIG_SERIAL6 */ - regVal = readl(&uart_base->uartsyscfg); - regVal |= UART_RESET; - writel(regVal, &uart_base->uartsyscfg); - while ((readl(&uart_base->uartsyssts) & - UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) - ; - - /* Disable smart idle */ - regVal = readl(&uart_base->uartsyscfg); - regVal |= UART_SMART_IDLE_EN; - writel(regVal, &uart_base->uartsyscfg); + uart_soft_reset(); gd = &gdata; diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 38a6ced..6ad3dd8 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -37,33 +37,16 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; #endif static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* UART Defines */ #ifdef CONFIG_SPL_BUILD -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) - static void uart_enable(void) { - u32 regVal; - /* UART softreset */ - regVal = readl(&uart_base->uartsyscfg); - regVal |= UART_RESET; - writel(regVal, &uart_base->uartsyscfg); - while ((readl(&uart_base->uartsyssts) & - UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) - ; - - /* Disable smart idle */ - regVal = readl(&uart_base->uartsyscfg); - regVal |= UART_SMART_IDLE_EN; - writel(regVal, &uart_base->uartsyscfg); + uart_soft_reset(); } static void wdt_disable(void) -- cgit v1.1