From 6f3c7d808a73c0e5a46a24d9abfd8799719aeb95 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 30 Dec 2011 11:31:24 +0800 Subject: ENGR00171091 [MX6]Remove workaround for reset issue The root cause is the L1 I-cache need invalidation, now we don't need this workaround, so remove it. Signed-off-by: Anson Huang --- cpu/arm_cortexa8/mx6/generic.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c index 44f1a43..73fee40 100644 --- a/cpu/arm_cortexa8/mx6/generic.c +++ b/cpu/arm_cortexa8/mx6/generic.c @@ -948,31 +948,6 @@ int cpu_eth_init(bd_t *bis) int arch_cpu_init(void) { int val; -#ifndef CONFIG_MFG - unsigned int reg; - - /* Check the flag of SNVS_LPGPR[0], SRC register will not reset - when we do a wdog reset, so we keep flag in SNVS_LPGPR[0], - when we finish this workaround, we will clear it */ - reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR_OFFSET); - /* If flagg is not set */ - if (!(reg & 0x1)) { - /* Set flag in SNVS_LPGPR[0] */ - writel(readl(SNVS_BASE_ADDR + SNVS_LPGPR_OFFSET) | 0x1, - SNVS_BASE_ADDR + SNVS_LPGPR_OFFSET); - /* Set wdog to timeout in 0.5 second */ - writew(0x34, WDOG1_BASE_ADDR); - /* Disable CORE LDO */ - writel(0x0, ANATOP_BASE_ADDR + HW_ANADIG_REG_CORE); - /* Wait for wdog timeout */ - while (1) - ; - } else { - /* Clear flag */ - writel(readl(SNVS_BASE_ADDR + SNVS_LPGPR_OFFSET) & (~0x1), - SNVS_BASE_ADDR + SNVS_LPGPR_OFFSET); - } -#endif icache_enable(); dcache_enable(); -- cgit v1.1