From fc0c2b6fc929f1d4038c4f0de1b631170b8f397c Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 1 Dec 2010 10:35:31 -0500 Subject: 8xxx/ddr: add support to only compute the ddr sdram size This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in case that the DDR SDRAM is initialized in the 2nd stage uboot and should not be intialized again in the final stage uboot. Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 10 +++++++++- arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 8 +++++--- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 31 ++++++++++++++++++++++++++----- 3 files changed, 40 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 3fec100..8fdafdb 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1176,7 +1176,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_params, - unsigned int dbw_cap_adj) + unsigned int dbw_cap_adj, + unsigned int size_only) { unsigned int i; unsigned int cas_latency; @@ -1394,6 +1395,13 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, printf("CS%d is disabled.\n", i); } + /* + * In the case we only need to compute the ddr sdram size, we only need + * to set csn registers, so return from here. + */ + if (size_only) + return 0; + set_ddr_eor(ddr, popts); #if !defined(CONFIG_FSL_DDR1) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index 98acb8d..35b60a0 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -55,7 +55,8 @@ typedef struct { #define STEP_ALL 0xFFF extern unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step); +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only); extern const char * step_to_string(unsigned int step); @@ -64,7 +65,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_parameters, - unsigned int dbw_capacity_adjust); + unsigned int dbw_capacity_adjust, + unsigned int size_only); extern unsigned int compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index e3888ff..bb96d66 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -233,7 +233,8 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, } unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step) +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only) { unsigned int i, j; unsigned int all_controllers_memctl_interleaving = 0; @@ -338,7 +339,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step) &pinfo->memctl_opts[i], &ddr_reg[i], &timing_params[i], pinfo->dimm_params[i], - dbw_capacity_adjust[i]); + dbw_capacity_adjust[i], + size_only); } default: @@ -405,7 +407,7 @@ phys_size_t fsl_ddr_sdram(void) memset(&info, 0, sizeof(fsl_ddr_info_t)); /* Compute it once normally. */ - total_memory = fsl_ddr_compute(&info, STEP_GET_SPD); + total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); /* Check for memory controller interleaving. */ memctl_interleaved = 0; @@ -430,7 +432,8 @@ phys_size_t fsl_ddr_sdram(void) info.memctl_opts[i].memctl_interleaving = 0; debug("Recomputing with memctl_interleaving off.\n"); total_memory = fsl_ddr_compute(&info, - STEP_ASSIGN_ADDRESSES); + STEP_ASSIGN_ADDRESSES, + 0); } } @@ -478,3 +481,21 @@ phys_size_t fsl_ddr_sdram(void) return total_memory; } + +/* + * fsl_ddr_sdram_size() - This function only returns the size of the total + * memory without setting ddr control registers. + */ +phys_size_t +fsl_ddr_sdram_size(void) +{ + fsl_ddr_info_t info; + unsigned long long total_memory = 0; + + memset(&info, 0 , sizeof(fsl_ddr_info_t)); + + /* Compute it once normally. */ + total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); + + return total_memory; +} -- cgit v1.1 From 7a577fda2243cc55b7b942310259f7d1341f0011 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 12 Jan 2011 02:48:53 -0600 Subject: powerpc/85xx: Move RESET_VECTOR_ADDRESS into config.h Rather than defining it config.mk we can set it in config.h and remove config.mk from several boards that don't need it. We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for config.h to set. Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk --- arch/powerpc/cpu/mpc85xx/u-boot.lds | 8 ++++++-- board/freescale/corenet_ds/config.mk | 27 --------------------------- board/freescale/mpc8536ds/config.mk | 14 +------------- board/freescale/mpc8572ds/config.mk | 4 +--- board/freescale/p1022ds/config.mk | 10 ---------- board/freescale/p1_p2_rdb/config.mk | 14 +------------- board/freescale/p2020ds/config.mk | 26 -------------------------- include/configs/MPC8536DS.h | 6 ++++++ include/configs/MPC8572DS.h | 4 ++++ include/configs/P1022DS.h | 4 ++++ include/configs/P1_P2_RDB.h | 6 ++++++ include/configs/P2020DS.h | 4 ++++ include/configs/corenet_ds.h | 4 ++++ 13 files changed, 37 insertions(+), 94 deletions(-) delete mode 100644 board/freescale/corenet_ds/config.mk delete mode 100644 board/freescale/p1022ds/config.mk delete mode 100644 board/freescale/p2020ds/config.mk diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 67d7763..506c7f2 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2009, 2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -20,7 +20,11 @@ * MA 02111-1307 USA */ -#ifndef RESET_VECTOR_ADDRESS +#include "config.h" /* CONFIG_BOARDDIR */ + +#ifdef CONFIG_RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS +#else #define RESET_VECTOR_ADDRESS 0xfffffffc #endif diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk deleted file mode 100644 index 15bbf20..0000000 --- a/board/freescale/corenet_ds/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright 2007-2009 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# P4080DS board -# - -RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk index b7deb4a..228d8c0 100644 --- a/board/freescale/mpc8536ds/config.mk +++ b/board/freescale/mpc8536ds/config.mk @@ -1,5 +1,5 @@ # -# Copyright 2008 Freescale Semiconductor. +# Copyright 2008, 2011 Freescale Semiconductor. # # See file CREDITS for list of people who contributed to this # project. @@ -28,15 +28,3 @@ ifeq ($(CONFIG_NAND), y) LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds endif endif - -ifeq ($(CONFIG_SDCARD), y) -RESET_VECTOR_ADDRESS = 0xf8fffffc -endif - -ifeq ($(CONFIG_SPIFLASH), y) -RESET_VECTOR_ADDRESS = 0xf8fffffc -endif - -ifndef RESET_VECTOR_ADDRESS -RESET_VECTOR_ADDRESS = 0xeffffffc -endif diff --git a/board/freescale/mpc8572ds/config.mk b/board/freescale/mpc8572ds/config.mk index 7fd6412..9fd30f9 100644 --- a/board/freescale/mpc8572ds/config.mk +++ b/board/freescale/mpc8572ds/config.mk @@ -1,5 +1,5 @@ # -# Copyright 2007-2008,2010 Freescale Semiconductor, Inc. +# Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. # # See file CREDITS for list of people who contributed to this # project. @@ -28,5 +28,3 @@ ifeq ($(CONFIG_NAND), y) LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds endif endif - -RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/freescale/p1022ds/config.mk b/board/freescale/p1022ds/config.mk deleted file mode 100644 index a953fdd..0000000 --- a/board/freescale/p1022ds/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright 2010 Freescale Semiconductor, Inc. -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License as published by the Free -# Software Foundation; either version 2 of the License, or (at your option) -# any later version. -# - -RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk index eececaa..0769804 100644 --- a/board/freescale/p1_p2_rdb/config.mk +++ b/board/freescale/p1_p2_rdb/config.mk @@ -1,5 +1,5 @@ # -# Copyright 2009 Freescale Semiconductor, Inc. +# Copyright 2009, 2011 Freescale Semiconductor, Inc. # # See file CREDITS for list of people who contributed to this # project. @@ -29,15 +29,3 @@ ifeq ($(CONFIG_NAND), y) LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds endif endif - -ifeq ($(CONFIG_SDCARD), y) -RESET_VECTOR_ADDRESS = 0xf8fffffc -endif - -ifeq ($(CONFIG_SPIFLASH), y) -RESET_VECTOR_ADDRESS = 0xf8fffffc -endif - -ifndef RESET_VECTOR_ADDRESS -RESET_VECTOR_ADDRESS = 0xeffffffc -endif diff --git a/board/freescale/p2020ds/config.mk b/board/freescale/p2020ds/config.mk deleted file mode 100644 index f5c07e5..0000000 --- a/board/freescale/p2020ds/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright 2007-2009 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# p2020ds board -# -RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index d1ae35d..11ee650 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -47,17 +47,23 @@ #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #ifndef CONFIG_SYS_MONITOR_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index ea15831..e6b60cf 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -48,6 +48,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #ifndef CONFIG_SYS_MONITOR_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 2b8fc7d..f310768 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -26,6 +26,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 80b0b40..d18d2f6 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -57,17 +57,23 @@ #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #ifndef CONFIG_SYS_MONITOR_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index b6e3260..b32a997 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -45,6 +45,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 23bbd42..fa05baa 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -41,6 +41,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ -- cgit v1.1 From 17028be23887ea6d467e63e115c49b516ae58746 Mon Sep 17 00:00:00 2001 From: Prabhakar Date: Tue, 18 Jan 2011 09:03:59 +0530 Subject: Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha --- arch/powerpc/include/asm/immap_85xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index b96dec7..93a9e6c 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2309,7 +2309,7 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_CPM_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET) #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ -- cgit v1.1 From b8cdd014629133c554b81df0447c748d10960583 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Thu, 13 Jan 2011 21:39:27 +0530 Subject: powerpc/85xx: Add Support for Freescale P1010 Processor Key Features include of the P1010: * e500v2 core frequency operation of 500 to 800 MHz * Power consumption less than 5.0 W at 800 MHz core speed * Dual SATA 3 Gbps controllers with integrated PHY * Dual PCI Express controllers * Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs) * TCP/IP acceleration and classification capabilities * IEEE 1588 support * Lossless flow control * RGMII, SGMII * DDR3 with support for a 32-bit data interface (40 bits including ECC), up to 800 MHz data rate 32/16-bit DDR3 memory controller * Dedicated security engine featuring trusted boot * TDM interface * Dual controller area networks (FlexCAN) controller * SD/MMC card controller supporting booting from Flash cards * USB 2.0 host and device controller with an on-chip, high-speed PHY * Integrated Flash controller (IFC) * Power Management Controller (PMC) * Four-channel, general-purpose DMA controller * I2C controller * Serial peripheral interface (SPI) controller with master and slave support * System timers including a periodic interrupt timer, real-time clock, software watchdog timer, and four general-purpose timers * Dual DUARTs Signed-off-by: Poonam Aggrwal Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/cpu.c | 4 +++- arch/powerpc/include/asm/config.h | 8 +++++--- arch/powerpc/include/asm/processor.h | 2 ++ drivers/misc/fsl_law.c | 3 ++- 5 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index af7bc09..e1261cf 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -50,6 +50,7 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_MPC8569) += ddr-gen3.o +COBJS-$(CONFIG_P1010) += ddr-gen3.o COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1012) += ddr-gen3.o COBJS-$(CONFIG_P1013) += ddr-gen3.o diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 5b30fbd..d1aa9e7 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains @@ -64,6 +64,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8569, 8569_E, 1), CPU_TYPE_ENTRY(8572, 8572, 2), CPU_TYPE_ENTRY(8572, 8572_E, 2), + CPU_TYPE_ENTRY(P1010, P1010, 1), + CPU_TYPE_ENTRY(P1010, P1010_E, 1), CPU_TYPE_ENTRY(P1011, P1011, 1), CPU_TYPE_ENTRY(P1011, P1011_E, 1), CPU_TYPE_ENTRY(P1012, P1012, 1), diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 76dedeb..e142459 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -69,14 +69,16 @@ /* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ #if defined(CONFIG_TSEC_ENET) && \ - (defined(CONFIG_P1020) || defined(CONFIG_P1011)) + (defined(CONFIG_P1010) || \ + defined(CONFIG_P1020) || defined(CONFIG_P1011)) #define CONFIG_TSECV2 #endif /* * SEC (crypto unit) major compatible version determination */ -#if defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_FSL_CORENET) || \ + defined(CONFIG_P1010) #define CONFIG_SYS_FSL_SEC_COMPAT 4 #elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx) #define CONFIG_SYS_FSL_SEC_COMPAT 2 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 71fafa3..6b43dc5 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1038,6 +1038,8 @@ #define SVR_8569_E 0x808800 #define SVR_8572 0x80E000 #define SVR_8572_E 0x80E800 +#define SVR_P1010 0x80F100 +#define SVR_P1010_E 0x80F900 #define SVR_P1011 0x80E500 #define SVR_P1011_E 0x80ED00 #define SVR_P1012 0x80E501 diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 6589076..6476231 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610) #define FSL_HW_NUM_LAWS 10 #elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \ + defined(CONFIG_P1010) || \ defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ defined(CONFIG_P1012) || defined(CONFIG_P1021) || \ defined(CONFIG_P1013) || defined(CONFIG_P1022) || \ -- cgit v1.1 From b5debec5b57bb8b876c49d2f56cd168dc0adf755 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Thu, 13 Jan 2011 21:40:05 +0530 Subject: powerpc/85xx: Add Support for Freescale P1014 Processor The P1014 is similar to the P1010 processor with the following differences: - 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC) - no eCAN interface. (P1010 has 2 eCAN interfaces) - Two SGMII interface (P1010 has 3 SGMII) - No secure boot Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++ arch/powerpc/include/asm/config.h | 4 ++-- arch/powerpc/include/asm/processor.h | 2 ++ drivers/misc/fsl_law.c | 2 +- 5 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index e1261cf..3f118db 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -54,6 +54,7 @@ COBJS-$(CONFIG_P1010) += ddr-gen3.o COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1012) += ddr-gen3.o COBJS-$(CONFIG_P1013) += ddr-gen3.o +COBJS-$(CONFIG_P1014) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P1021) += ddr-gen3.o COBJS-$(CONFIG_P1022) += ddr-gen3.o diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index d1aa9e7..94051de 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -71,6 +71,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P1012, P1012, 1), CPU_TYPE_ENTRY(P1012, P1012_E, 1), CPU_TYPE_ENTRY(P1013, P1013, 1), + CPU_TYPE_ENTRY(P1014, P1014_E, 1), + CPU_TYPE_ENTRY(P1014, P1014, 1), CPU_TYPE_ENTRY(P1013, P1013_E, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), CPU_TYPE_ENTRY(P1020, P1020_E, 2), diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index e142459..1328b9d 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -69,7 +69,7 @@ /* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ #if defined(CONFIG_TSEC_ENET) && \ - (defined(CONFIG_P1010) || \ + (defined(CONFIG_P1010) || defined(CONFIG_P1014) || \ defined(CONFIG_P1020) || defined(CONFIG_P1011)) #define CONFIG_TSECV2 #endif @@ -78,7 +78,7 @@ * SEC (crypto unit) major compatible version determination */ #if defined(CONFIG_FSL_CORENET) || \ - defined(CONFIG_P1010) + defined(CONFIG_P1010) || defined(CONFIG_P1014) #define CONFIG_SYS_FSL_SEC_COMPAT 4 #elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx) #define CONFIG_SYS_FSL_SEC_COMPAT 2 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 6b43dc5..646e0db 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1046,6 +1046,8 @@ #define SVR_P1012_E 0x80ED01 #define SVR_P1013 0x80E700 #define SVR_P1013_E 0x80EF00 +#define SVR_P1014 0x80F101 +#define SVR_P1014_E 0x80F901 #define SVR_P1020 0x80E400 #define SVR_P1020_E 0x80EC00 #define SVR_P1021 0x80E401 diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 6476231..a30d851 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610) #define FSL_HW_NUM_LAWS 10 #elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \ - defined(CONFIG_P1010) || \ + defined(CONFIG_P1010) || defined(CONFIG_P1014) || \ defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ defined(CONFIG_P1012) || defined(CONFIG_P1021) || \ defined(CONFIG_P1013) || defined(CONFIG_P1022) || \ -- cgit v1.1 From d5d2cd4331414127327c8c8fcdb6a31b915f4ae3 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sun, 4 Jul 2010 13:07:08 -0500 Subject: powerpc/p3041: Add various p3041 specific information Add P3041 SoC specific information: * SERDES Table * LIODN setup * Portal configuration Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 2 + arch/powerpc/cpu/mpc85xx/p3041_ids.c | 105 ++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/p3041_serdes.c | 151 ++++++++++++++++++++++++++++++++ 3 files changed, 258 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/p3041_ids.c create mode 100644 arch/powerpc/cpu/mpc85xx/p3041_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 3f118db..7069749 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -72,6 +72,7 @@ COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_FSL_CORENET) += portals.o # various SoC specific assignments +COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_QE) += qe_io.o @@ -93,6 +94,7 @@ COBJS-$(CONFIG_P1021) += p1021_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o +COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS = $(COBJS-y) diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c new file mode 100644 index 0000000..febbee9 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -0,0 +1,105 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO( 1, 2, 1, 0), + SET_QP_INFO( 3, 4, 2, 1), + SET_QP_INFO( 5, 6, 3, 2), + SET_QP_INFO( 7, 8, 4, 3), + SET_QP_INFO( 9, 10, 5, 4), + SET_QP_INFO( 0, 0, 0, 5), + SET_QP_INFO( 0, 0, 0, 6), + SET_QP_INFO( 0, 0, 0, 7), + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ +}; + +struct liodn_id_table liodn_tbl[] = { + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), + + SET_SDHC_LIODN(1, 64), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 125), + SET_USB_LIODN(2, "fsl-usb2-dr", 126), + + SET_SATA_LIODN(1, 127), + SET_SATA_LIODN(2, 128), + + SET_PCI_LIODN(1, 193), + SET_PCI_LIODN(2, 194), + SET_PCI_LIODN(3, 195), + SET_PCI_LIODN(4, 196), + + SET_DMA_LIODN(1, 197), + SET_DMA_LIODN(2, 198), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +}; + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 10), + SET_FMAN_RX_1G_LIODN(1, 1, 11), + SET_FMAN_RX_1G_LIODN(1, 2, 12), + SET_FMAN_RX_1G_LIODN(1, 3, 13), + SET_FMAN_RX_1G_LIODN(1, 4, 14), + SET_FMAN_RX_10G_LIODN(1, 0, 15), +}; +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 129, 130), + SET_SEC_JR_LIODN_ENTRY(1, 131, 132), + SET_SEC_JR_LIODN_ENTRY(2, 133, 134), + SET_SEC_JR_LIODN_ENTRY(3, 135, 136), + SET_SEC_RTIC_LIODN_ENTRY(a, 154), + SET_SEC_RTIC_LIODN_ENTRY(b, 155), + SET_SEC_RTIC_LIODN_ENTRY(c, 156), + SET_SEC_RTIC_LIODN_ENTRY(d, 157), + SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), + SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), +}; + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), +#endif +}; + +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c new file mode 100644 index 0000000..fba9ff2 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c @@ -0,0 +1,151 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, }, + [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, }, + [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1, + SRIO1, }, + [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, + SATA1, SATA2, }, + [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, }, + [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, }, + [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, + [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, }, + [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(u32 prtcl) { + int i; + + if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} -- cgit v1.1 From 1eda59ff6bcd09ce4bfbe7af9898951b0c66f303 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 8 Jul 2010 05:24:44 -0500 Subject: powerpc/p5020: Add various p5020 specific information Add P5020 SoC specific information: * SERDES Table * LIODN setup * Portal configuration Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 2 + arch/powerpc/cpu/mpc85xx/p5020_ids.c | 105 ++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/p5020_serdes.c | 151 ++++++++++++++++++++++++++++++++ 3 files changed, 258 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/p5020_ids.c create mode 100644 arch/powerpc/cpu/mpc85xx/p5020_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 7069749..b7f51e7 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -74,6 +74,7 @@ COBJS-$(CONFIG_FSL_CORENET) += portals.o # various SoC specific assignments COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o +COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o @@ -96,6 +97,7 @@ COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o +COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o COBJS = $(COBJS-y) COBJS += cpu.o diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c new file mode 100644 index 0000000..febbee9 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -0,0 +1,105 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO( 1, 2, 1, 0), + SET_QP_INFO( 3, 4, 2, 1), + SET_QP_INFO( 5, 6, 3, 2), + SET_QP_INFO( 7, 8, 4, 3), + SET_QP_INFO( 9, 10, 5, 4), + SET_QP_INFO( 0, 0, 0, 5), + SET_QP_INFO( 0, 0, 0, 6), + SET_QP_INFO( 0, 0, 0, 7), + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ +}; + +struct liodn_id_table liodn_tbl[] = { + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), + + SET_SDHC_LIODN(1, 64), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 125), + SET_USB_LIODN(2, "fsl-usb2-dr", 126), + + SET_SATA_LIODN(1, 127), + SET_SATA_LIODN(2, 128), + + SET_PCI_LIODN(1, 193), + SET_PCI_LIODN(2, 194), + SET_PCI_LIODN(3, 195), + SET_PCI_LIODN(4, 196), + + SET_DMA_LIODN(1, 197), + SET_DMA_LIODN(2, 198), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +}; + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 10), + SET_FMAN_RX_1G_LIODN(1, 1, 11), + SET_FMAN_RX_1G_LIODN(1, 2, 12), + SET_FMAN_RX_1G_LIODN(1, 3, 13), + SET_FMAN_RX_1G_LIODN(1, 4, 14), + SET_FMAN_RX_10G_LIODN(1, 0, 15), +}; +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 129, 130), + SET_SEC_JR_LIODN_ENTRY(1, 131, 132), + SET_SEC_JR_LIODN_ENTRY(2, 133, 134), + SET_SEC_JR_LIODN_ENTRY(3, 135, 136), + SET_SEC_RTIC_LIODN_ENTRY(a, 154), + SET_SEC_RTIC_LIODN_ENTRY(b, 155), + SET_SEC_RTIC_LIODN_ENTRY(c, 156), + SET_SEC_RTIC_LIODN_ENTRY(d, 157), + SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), + SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), +}; + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), +#endif +}; + +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/p5020_serdes.c b/arch/powerpc/cpu/mpc85xx/p5020_serdes.c new file mode 100644 index 0000000..fba9ff2 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p5020_serdes.c @@ -0,0 +1,151 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, }, + [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, }, + [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1, + SRIO1, }, + [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, + SATA1, SATA2, }, + [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, }, + [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, }, + [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, + [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, }, + [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(u32 prtcl) { + int i; + + if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} -- cgit v1.1 From f193e3da9817dc4892bc25967954d98838f84386 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 1 Jun 2010 10:29:11 -0500 Subject: powerpc/p2040: Add various p2040 specific information Add P2040 SoC specific information: * SERDES Table * Added p2040 to cpu_type_list and SVR list * Added number of LAWs for p2040 * Set CONFIG_MAX_CPUS to 4 for p2040 Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/p2040_serdes.c | 66 +++++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xxx/cpu.c | 2 + arch/powerpc/include/asm/config.h | 2 + arch/powerpc/include/asm/processor.h | 2 + drivers/misc/fsl_law.c | 4 +- 5 files changed, 74 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/p2040_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c new file mode 100644 index 0000000..a96eff4 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c @@ -0,0 +1,66 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, + [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, + [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1, + SATA2, NONE, NONE, NONE, NONE, }, + [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3, + PCIE3, NONE, NONE, NONE, NONE, }, + [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, + SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, + [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, + NONE, NONE, NONE, }, + [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, + NONE, NONE, NONE, }, + [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, + SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, + NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, + [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA, + SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, }, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 94051de..4335fb4 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -84,6 +84,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), CPU_TYPE_ENTRY(P2020, P2020_E, 2), + CPU_TYPE_ENTRY(P2040, P2040, 4), + CPU_TYPE_ENTRY(P2040, P2040_E, 4), CPU_TYPE_ENTRY(P3041, P3041, 4), CPU_TYPE_ENTRY(P3041, P3041_E, 4), CPU_TYPE_ENTRY(P4040, P4040, 4), diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 1328b9d..1b9c47b 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -47,6 +47,8 @@ defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ defined(CONFIG_P2020) || defined(CONFIG_MPC8641) #define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_PPC_P2040) +#define CONFIG_MAX_CPUS 4 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 #elif defined(CONFIG_PPC_P4080) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 646e0db..fcee1a2 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1058,6 +1058,8 @@ #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 #define SVR_P2020_E 0x80EA00 +#define SVR_P2040 0x821000 +#define SVR_P2040_E 0x821800 #define SVR_P3041 0x821103 #define SVR_P3041_E 0x821903 #define SVR_P4040 0x820100 diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index a30d851..76f4688 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -44,8 +44,8 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_P1013) || defined(CONFIG_P1022) || \ defined(CONFIG_P2010) || defined(CONFIG_P2020) #define FSL_HW_NUM_LAWS 12 -#elif defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P4080) || \ - defined(CONFIG_PPC_P5020) +#elif defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P3041) || \ + defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P5020) #define FSL_HW_NUM_LAWS 32 #else #error FSL_HW_NUM_LAWS not defined for this platform -- cgit v1.1 From dd50af2515ad39fa2f6c09ab621f69fef4f5fceb Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sun, 9 Jan 2011 11:37:00 -0600 Subject: powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR init There are several users of the hwconfig APIs (8xxx DDR) before we have the environment properly setup. This causes issues because of the numerous ways the environment might be accessed because of the non-volatile memory it might be stored in. Additionally the access might be so early that memory isn't even properly setup for us. Towards resolving these issues we provide versions of all the hwconfig APIs that can be passed in a buffer to parse and leave it to the caller to determine how to allocate and populate the buffer. We use the _f naming convention for these new APIs even though they are perfectly useable after relocation and the environment being ready. We also now warn if the non-f APIs are called before the environment is ready to allow users to address the issues. Finally, we convert the 8xxx DDR code to utilize the new APIs to hopefully address the issue once and for all. We have the 8xxx DDR code create a buffer on the stack and populate it via getenv_f(). Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk --- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 78 ++++++++++++++++++++++-------- common/hwconfig.c | 86 +++++++++++++++++----------------- include/hwconfig.h | 68 ++++++++++++++++++++------- 3 files changed, 154 insertions(+), 78 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index c641e85..0e7097b 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -13,6 +13,14 @@ #include "ddr.h" +/* + * Use our own stack based buffer before relocation to allow accessing longer + * hwconfig strings that might be in the environment before we've relocated. + * This is pretty fragile on both the use of stack and if the buffer is big + * enough. However we will get a warning from getenv_f for the later. + */ +#define HWCONFIG_BUFFER_SIZE 128 + /* Board-specific functions defined in each board's ddr.c */ extern void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, @@ -24,6 +32,15 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, unsigned int ctrl_num) { unsigned int i; + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + + /* + * Extract hwconfig from environment since we have not properly setup + * the environment but need it for ddr config params + */ + if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + buf = buffer; /* Chip select options. */ @@ -221,7 +238,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * should be a subset of the requested configuration. */ #if (CONFIG_NUM_DDR_CONTROLLERS > 1) - if (hwconfig_sub("fsl_ddr", "ctlr_intlv")) { + if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) { if (pdimm[0].n_ranks == 0) { printf("There is no rank on CS0 for controller %d. Because only" " rank on CS0 and ranks chip-select interleaved with CS0" @@ -234,19 +251,25 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * test null first. if CONFIG_HWCONFIG is not defined * hwconfig_arg_cmp returns non-zero */ - if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "null")) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", + "null", buf)) { popts->memctl_interleaving = 0; debug("memory controller interleaving disabled.\n"); - } else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "cacheline")) + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "cacheline", buf)) popts->memctl_interleaving_mode = FSL_DDR_CACHE_LINE_INTERLEAVING; - else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "page")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", + "page", buf)) popts->memctl_interleaving_mode = FSL_DDR_PAGE_INTERLEAVING; - else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "bank")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", + "bank", buf)) popts->memctl_interleaving_mode = FSL_DDR_BANK_INTERLEAVING; - else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "superbank")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", + "superbank", buf)) popts->memctl_interleaving_mode = FSL_DDR_SUPERBANK_INTERLEAVING; else { @@ -256,19 +279,24 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } } #endif - if ((hwconfig_sub("fsl_ddr", "bank_intlv")) && + if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { /* test null first. if CONFIG_HWCONFIG is not defined, - * hwconfig_arg_cmp returns non-zero */ - if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "null")) + * hwconfig_subarg_cmp_f returns non-zero */ + if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "null", buf)) debug("bank interleaving disabled.\n"); - else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "cs0_cs1", buf)) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; - else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs2_cs3")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "cs2_cs3", buf)) popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; - else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_and_cs2_cs3")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "cs0_cs1_and_cs2_cs3", buf)) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; - else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_cs2_cs3")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "cs0_cs1_cs2_cs3", buf)) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; else printf("hwconfig has unrecognized parameter for bank_intlv.\n"); @@ -342,10 +370,11 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } } - if (hwconfig_sub("fsl_ddr", "addr_hash")) { - if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "null")) + if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf)) popts->addr_hash = 0; - else if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "true")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", + "true", buf)) popts->addr_hash = 1; } @@ -393,11 +422,22 @@ int fsl_use_spd(void) int use_spd = 0; #ifdef CONFIG_DDR_SPD + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + + /* + * Extract hwconfig from environment since we have not properly setup + * the environment but need it for ddr config params + */ + if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + buf = buffer; + /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ - if (hwconfig_sub("fsl_ddr", "sdram")) { - if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd")) + if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf)) use_spd = 1; - else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", + "fixed", buf)) use_spd = 0; else use_spd = 1; diff --git a/common/hwconfig.c b/common/hwconfig.c index 193863a..5150748 100644 --- a/common/hwconfig.c +++ b/common/hwconfig.c @@ -2,6 +2,7 @@ * An inteface for configuring a hardware via u-boot environment. * * Copyright (c) 2009 MontaVista Software, Inc. + * Copyright 2011 Freescale Semiconductor, Inc. * * Author: Anton Vorontsov * @@ -71,25 +72,19 @@ next: const char cpu_hwconfig[] __attribute__((weak)) = ""; const char board_hwconfig[] __attribute__((weak)) = ""; -#define HWCONFIG_PRE_RELOC_BUF_SIZE 128 - -static const char *__hwconfig(const char *opt, size_t *arglen) +static const char *__hwconfig(const char *opt, size_t *arglen, + const char *env_hwconfig) { - const char *env_hwconfig = NULL, *ret; - char buf[HWCONFIG_PRE_RELOC_BUF_SIZE]; + const char *ret; - if (gd->flags & GD_FLG_ENV_READY) { + /* if we are passed a buffer use it, otherwise try the environment */ + if (!env_hwconfig) { + if (!(gd->flags & GD_FLG_ENV_READY)) { + printf("WARNING: Calling __hwconfig without a buffer " + "and before environment is ready\n"); + return NULL; + } env_hwconfig = getenv("hwconfig"); - } else { - /* - * Use our own on stack based buffer before relocation to allow - * accessing longer hwconfig strings that might be in the - * environment before we've relocated. This is pretty fragile - * on both the use of stack and if the buffer is big enough. - * However we will get a warning from getenv_f for the later. - */ - if ((getenv_f("hwconfig", buf, sizeof(buf))) > 0) - env_hwconfig = buf; } if (env_hwconfig) { @@ -109,8 +104,9 @@ static const char *__hwconfig(const char *opt, size_t *arglen) } /* - * hwconfig - query if a particular hwconfig option is specified + * hwconfig_f - query if a particular hwconfig option is specified * @opt: a string representing an option + * @buf: if non-NULL use this buffer to parse, otherwise try env * * This call can be used to find out whether U-Boot should configure * a particular hardware option. @@ -127,34 +123,36 @@ static const char *__hwconfig(const char *opt, size_t *arglen) * that the board file only calls things that are actually used, so * hwconfig() will always return true result. */ -int hwconfig(const char *opt) +int hwconfig_f(const char *opt, char *buf) { - return !!__hwconfig(opt, NULL); + return !!__hwconfig(opt, NULL, buf); } /* - * hwconfig_arg - get hwconfig option's argument + * hwconfig_arg_f - get hwconfig option's argument * @opt: a string representing an option * @arglen: a pointer to an allocated size_t variable + * @buf: if non-NULL use this buffer to parse, otherwise try env * - * Unlike hwconfig() function, this function returns a pointer to the + * Unlike hwconfig_f() function, this function returns a pointer to the * start of the hwconfig arguments, if option is not found or it has * no specified arguments, the function returns NULL pointer. * * If CONFIG_HWCONFIG is undefined, the function returns "", and * arglen is set to 0. */ -const char *hwconfig_arg(const char *opt, size_t *arglen) +const char *hwconfig_arg_f(const char *opt, size_t *arglen, char *buf) { - return __hwconfig(opt, arglen); + return __hwconfig(opt, arglen, buf); } /* - * hwconfig_arg_cmp - compare hwconfig option's argument + * hwconfig_arg_cmp_f - compare hwconfig option's argument * @opt: a string representing an option * @arg: a string for comparing an option's argument + * @buf: if non-NULL use this buffer to parse, otherwise try env * - * This call is similar to hwconfig_arg, but instead of returning + * This call is similar to hwconfig_arg_f, but instead of returning * hwconfig argument and its length, it is comparing it to @arg. * * Returns non-zero value if @arg matches, 0 otherwise. @@ -162,12 +160,12 @@ const char *hwconfig_arg(const char *opt, size_t *arglen) * If CONFIG_HWCONFIG is undefined, the function returns a non-zero * value, i.e. the argument matches. */ -int hwconfig_arg_cmp(const char *opt, const char *arg) +int hwconfig_arg_cmp_f(const char *opt, const char *arg, char *buf) { const char *argstr; size_t arglen; - argstr = hwconfig_arg(opt, &arglen); + argstr = hwconfig_arg_f(opt, &arglen, buf); if (!argstr || arglen != strlen(arg)) return 0; @@ -175,63 +173,67 @@ int hwconfig_arg_cmp(const char *opt, const char *arg) } /* - * hwconfig_sub - query if a particular hwconfig sub-option is specified + * hwconfig_sub_f - query if a particular hwconfig sub-option is specified * @opt: a string representing an option * @subopt: a string representing a sub-option + * @buf: if non-NULL use this buffer to parse, otherwise try env * - * This call is similar to hwconfig(), except that it takes additional + * This call is similar to hwconfig_f(), except that it takes additional * argument @subopt. In this example: * "dr_usb:mode=peripheral" * "dr_usb" is an option, "mode" is a sub-option, and "peripheral" is its * argument. */ -int hwconfig_sub(const char *opt, const char *subopt) +int hwconfig_sub_f(const char *opt, const char *subopt, char *buf) { size_t arglen; const char *arg; - arg = __hwconfig(opt, &arglen); + arg = __hwconfig(opt, &arglen, buf); if (!arg) return 0; return !!hwconfig_parse(arg, arglen, subopt, ",;", '=', NULL); } /* - * hwconfig_subarg - get hwconfig sub-option's argument + * hwconfig_subarg_f - get hwconfig sub-option's argument * @opt: a string representing an option * @subopt: a string representing a sub-option * @subarglen: a pointer to an allocated size_t variable + * @buf: if non-NULL use this buffer to parse, otherwise try env * - * This call is similar to hwconfig_arg(), except that it takes an additional - * argument @subopt, and so works with sub-options. + * This call is similar to hwconfig_arg_f(), except that it takes an + * additional argument @subopt, and so works with sub-options. */ -const char *hwconfig_subarg(const char *opt, const char *subopt, - size_t *subarglen) +const char *hwconfig_subarg_f(const char *opt, const char *subopt, + size_t *subarglen, char *buf) { size_t arglen; const char *arg; - arg = __hwconfig(opt, &arglen); + arg = __hwconfig(opt, &arglen, buf); if (!arg) return NULL; return hwconfig_parse(arg, arglen, subopt, ",;", '=', subarglen); } /* - * hwconfig_arg_cmp - compare hwconfig sub-option's argument + * hwconfig_arg_cmp_f - compare hwconfig sub-option's argument * @opt: a string representing an option * @subopt: a string representing a sub-option * @subarg: a string for comparing an sub-option's argument + * @buf: if non-NULL use this buffer to parse, otherwise try env * - * This call is similar to hwconfig_arg_cmp, except that it takes an additional - * argument @subopt, and so works with sub-options. + * This call is similar to hwconfig_arg_cmp_f, except that it takes an + * additional argument @subopt, and so works with sub-options. */ -int hwconfig_subarg_cmp(const char *opt, const char *subopt, const char *subarg) +int hwconfig_subarg_cmp_f(const char *opt, const char *subopt, + const char *subarg, char *buf) { const char *argstr; size_t arglen; - argstr = hwconfig_subarg(opt, subopt, &arglen); + argstr = hwconfig_subarg_f(opt, subopt, &arglen, buf); if (!argstr || arglen != strlen(subarg)) return 0; diff --git a/include/hwconfig.h b/include/hwconfig.h index d517f78..a037ed8 100644 --- a/include/hwconfig.h +++ b/include/hwconfig.h @@ -2,6 +2,7 @@ * An inteface for configuring a hardware via u-boot environment. * * Copyright (c) 2009 MontaVista Software, Inc. + * Copyright 2011 Freescale Semiconductor, Inc. * * Author: Anton Vorontsov * @@ -19,51 +20,84 @@ #ifdef CONFIG_HWCONFIG -extern int hwconfig(const char *opt); -extern const char *hwconfig_arg(const char *opt, size_t *arglen); -extern int hwconfig_arg_cmp(const char *opt, const char *arg); -extern int hwconfig_sub(const char *opt, const char *subopt); -extern const char *hwconfig_subarg(const char *opt, const char *subopt, - size_t *subarglen); -extern int hwconfig_subarg_cmp(const char *opt, const char *subopt, - const char *subarg); - +extern int hwconfig_f(const char *opt, char *buf); +extern const char *hwconfig_arg_f(const char *opt, size_t *arglen, char *buf); +extern int hwconfig_arg_cmp_f(const char *opt, const char *arg, char *buf); +extern int hwconfig_sub_f(const char *opt, const char *subopt, char *buf); +extern const char *hwconfig_subarg_f(const char *opt, const char *subopt, + size_t *subarglen, char *buf); +extern int hwconfig_subarg_cmp_f(const char *opt, const char *subopt, + const char *subarg, char *buf); #else -static inline int hwconfig(const char *opt) +static inline int hwconfig_f(const char *opt, char *buf) { return -ENOSYS; } -static inline const char *hwconfig_arg(const char *opt, size_t *arglen) +static inline const char *hwconfig_arg_f(const char *opt, size_t *arglen, + char *buf) { *arglen = 0; return ""; } -static inline int hwconfig_arg_cmp(const char *opt, const char *arg) +static inline int hwconfig_arg_cmp_f(const char *opt, const char *arg, + char *buf) { return -ENOSYS; } -static inline int hwconfig_sub(const char *opt, const char *subopt) +static inline int hwconfig_sub_f(const char *opt, const char *subopt, char *buf) { return -ENOSYS; } -static inline const char *hwconfig_subarg(const char *opt, const char *subopt, - size_t *subarglen) +static inline const char *hwconfig_subarg_f(const char *opt, const char *subopt, + size_t *subarglen, char *buf) { *subarglen = 0; return ""; } -static inline int hwconfig_subarg_cmp(const char *opt, const char *subopt, - const char *subarg) +static inline int hwconfig_subarg_cmp_f(const char *opt, const char *subopt, + const char *subarg, char *buf) { return -ENOSYS; } #endif /* CONFIG_HWCONFIG */ +static inline int hwconfig(const char *opt) +{ + return hwconfig_f(opt, NULL); +} + +static inline const char *hwconfig_arg(const char *opt, size_t *arglen) +{ + return hwconfig_arg_f(opt, arglen, NULL); +} + +static inline int hwconfig_arg_cmp(const char *opt, const char *arg) +{ + return hwconfig_arg_cmp_f(opt, arg, NULL); +} + +static inline int hwconfig_sub(const char *opt, const char *subopt) +{ + return hwconfig_sub_f(opt, subopt, NULL); +} + +static inline const char *hwconfig_subarg(const char *opt, const char *subopt, + size_t *subarglen) +{ + return hwconfig_subarg_f(opt, subopt, subarglen, NULL); +} + +static inline int hwconfig_subarg_cmp(const char *opt, const char *subopt, + const char *subarg) +{ + return hwconfig_subarg_cmp_f(opt, subopt, subarg, NULL); +} + #endif /* _HWCONFIG_H */ -- cgit v1.1 From 243be8e296c53343eb21a6224f5329ff94778a4f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 19 Jan 2011 03:05:26 -0600 Subject: powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headers Add new headers that capture common defines for a given SoC/processor rather than duplicating that information in board config.h and random other places. Eventually this should be handled by Kconfig & defconfigs Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk --- arch/powerpc/include/asm/config.h | 41 ++----- arch/powerpc/include/asm/config_mpc85xx.h | 187 ++++++++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc86xx.h | 38 ++++++ drivers/misc/fsl_law.c | 22 +--- include/configs/P4080DS.h | 16 --- include/configs/corenet_ds.h | 2 - 6 files changed, 236 insertions(+), 70 deletions(-) create mode 100644 arch/powerpc/include/asm/config_mpc85xx.h create mode 100644 arch/powerpc/include/asm/config_mpc86xx.h diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 1b9c47b..2b6b233 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -21,6 +21,14 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#ifdef CONFIG_MPC85xx +#include +#endif + +#ifdef CONFIG_MPC86xx +#include +#endif + #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH #define CONFIG_SYS_BOOT_GET_CMDLINE @@ -43,19 +51,7 @@ #endif #endif -#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ - defined(CONFIG_P2020) || defined(CONFIG_MPC8641) -#define CONFIG_MAX_CPUS 2 -#elif defined(CONFIG_PPC_P2040) -#define CONFIG_MAX_CPUS 4 -#elif defined(CONFIG_PPC_P3041) -#define CONFIG_MAX_CPUS 4 -#elif defined(CONFIG_PPC_P4080) -#define CONFIG_MAX_CPUS 8 -#elif defined(CONFIG_PPC_P5020) -#define CONFIG_MAX_CPUS 2 -#else +#ifndef CONFIG_MAX_CPUS #define CONFIG_MAX_CPUS 1 #endif @@ -69,30 +65,13 @@ #endif #endif -/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ -#if defined(CONFIG_TSEC_ENET) && \ - (defined(CONFIG_P1010) || defined(CONFIG_P1014) || \ - defined(CONFIG_P1020) || defined(CONFIG_P1011)) -#define CONFIG_TSECV2 -#endif - /* * SEC (crypto unit) major compatible version determination */ -#if defined(CONFIG_FSL_CORENET) || \ - defined(CONFIG_P1010) || defined(CONFIG_P1014) -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx) +#if defined(CONFIG_MPC83xx) #define CONFIG_SYS_FSL_SEC_COMPAT 2 #endif -/* Number of TLB CAM entries we have on FSL Book-E chips */ -#if defined(CONFIG_E500MC) -#define CONFIG_SYS_NUM_TLBCAMS 64 -#elif defined(CONFIG_E500) -#define CONFIG_SYS_NUM_TLBCAMS 16 -#endif - /* Since so many PPC SOCs have a semi-common LBC, define this here */ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ defined(CONFIG_MPC83xx) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h new file mode 100644 index 0000000..8ba6c7e --- /dev/null +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -0,0 +1,187 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_MPC85xx_CONFIG_H_ +#define _ASM_MPC85xx_CONFIG_H_ + +/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ + +/* Number of TLB CAM entries we have on FSL Book-E chips */ +#if defined(CONFIG_E500MC) +#define CONFIG_SYS_NUM_TLBCAMS 64 +#elif defined(CONFIG_E500) +#define CONFIG_SYS_NUM_TLBCAMS 16 +#endif + +#if defined(CONFIG_MPC8536) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8540) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 8 + +#elif defined(CONFIG_MPC8541) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8544) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8548) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8555) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8560) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 8 + +#elif defined(CONFIG_MPC8568) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8569) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8572) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P1010) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#elif defined(CONFIG_P1011) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P1012) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P1013) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P1014) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#elif defined(CONFIG_P1020) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P1021) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P1022) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P2010) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P2020) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_PPC_P2040) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#elif defined(CONFIG_PPC_P3041) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#elif defined(CONFIG_PPC_P4040) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#elif defined(CONFIG_PPC_P4080) +#define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 2 +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM2_DTSEC 4 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_ERRATUM_CPC_A002 +#define CONFIG_SYS_FSL_ERRATUM_CPC_A003 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC136 +#define CONFIG_SYS_P4080_ERRATUM_CPU22 +#define CONFIG_SYS_P4080_ERRATUM_SERDES8 + +#elif defined(CONFIG_PPC_P5010) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#elif defined(CONFIG_PPC_P5020) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#else +#error Processor type not defined for this platform +#endif + +#endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h new file mode 100644 index 0000000..c5c1ef4 --- /dev/null +++ b/arch/powerpc/include/asm/config_mpc86xx.h @@ -0,0 +1,38 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_MPC86xx_CONFIG_H_ +#define _ASM_MPC86xx_CONFIG_H_ + +/* SoC specific defines for Freescale MPC86xx processors */ + +#if defined(CONFIG_MPC8610) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 10 + +#elif defined(CONFIG_MPC8641) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 10 + +#else +#error Processor type not defined for this platform +#endif + +#endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 76f4688..63c08bf 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -29,27 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; -/* number of LAWs in the hw implementation */ -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) -#define FSL_HW_NUM_LAWS 8 -#elif defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \ - defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569) || \ - defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610) -#define FSL_HW_NUM_LAWS 10 -#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \ - defined(CONFIG_P1010) || defined(CONFIG_P1014) || \ - defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ - defined(CONFIG_P1012) || defined(CONFIG_P1021) || \ - defined(CONFIG_P1013) || defined(CONFIG_P1022) || \ - defined(CONFIG_P2010) || defined(CONFIG_P2020) -#define FSL_HW_NUM_LAWS 12 -#elif defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P3041) || \ - defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P5020) -#define FSL_HW_NUM_LAWS 32 -#else -#error FSL_HW_NUM_LAWS not defined for this platform -#endif +#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS #ifdef CONFIG_FSL_CORENET #define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR) diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 5c818c9..49f7c53 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -26,23 +26,7 @@ #define CONFIG_P4080DS #define CONFIG_PHYS_64BIT #define CONFIG_PPC_P4080 -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM2_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC136 - -#define CONFIG_SYS_P4080_ERRATUM_CPU22 -#define CONFIG_SYS_FSL_ERRATUM_CPC_A002 -#define CONFIG_SYS_FSL_ERRATUM_CPC_A003 -#define CONFIG_SYS_P4080_ERRATUM_SERDES8 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 - #include "corenet_ds.h" diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index fa05baa..5e9de90 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -446,13 +446,11 @@ #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 -#if (CONFIG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 -#endif #define CONFIG_SYS_TBIPA_VALUE 8 #define CONFIG_MII /* MII PHY management */ -- cgit v1.1 From dd12768974358e9f03147c3bffc54b619308f318 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Jan 2011 12:02:56 +0000 Subject: mpc8xxx: Display RDIMM if detected Print a message when a RDIMM is detected. Signed-off-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index 029e566..a58e5a9 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -98,7 +98,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, unsigned int tDQSQ_max_ps = 0; unsigned int tQHS_ps = 0; - unsigned int temp1, temp2, temp3; + unsigned int temp1, temp2; unsigned int additive_latency = 0; #if !defined(CONFIG_FSL_DDR3) const unsigned int mclk_ps = get_memory_clk_period_ps(); @@ -215,18 +215,14 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, } outpdimm->all_DIMMs_registered = 0; + outpdimm->all_DIMMs_unbuffered = 0; if (temp1 && !temp2) { outpdimm->all_DIMMs_registered = 1; - } - - outpdimm->all_DIMMs_unbuffered = 0; - if (!temp1 && temp2) { + printf("Detected RDIMM(s)\n"); + } else if (!temp1 && temp2) { outpdimm->all_DIMMs_unbuffered = 1; - } - - /* CHECKME: */ - if (!outpdimm->all_DIMMs_registered - && !outpdimm->all_DIMMs_unbuffered) { + printf("Detected UDIMM(s)\n"); + } else { printf("ERROR: Mix of registered buffered and unbuffered " "DIMMs detected!\n"); } @@ -237,7 +233,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, outpdimm->rcw[j] = dimm_params[0].rcw[j]; for (i = 1; i < number_of_dimms; i++) if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) { - temp3 = 1; + temp1 = 1; break; } } -- cgit v1.1 From 47df8f03f4cae5cec1f42856916a3dd0d0460dc1 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Jan 2011 12:02:57 +0000 Subject: mpc8xxx: Enable ECC on/off control in hwconfig Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file, ECC can be turned on/off by this switch. If this switch is omitted, it is ON by default. Updated hwconfig calls to use local buffer. Syntax is hwconfig=fsl_ddr:ecc=on Signed-off-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 9 ++++++--- doc/README.fsl-ddr | 7 +++++++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 0e7097b..55dff43 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -98,10 +98,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, /* Operational Mode Paramters */ /* Pick ECC modes */ -#ifdef CONFIG_DDR_ECC - popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */ -#else popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */ +#ifdef CONFIG_DDR_ECC + if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf)) + popts->ECC_mode = 1; + } else + popts->ECC_mode = 1; #endif popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 1657ef6..9e3c539 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -78,6 +78,13 @@ If the DDR controller supports address hashing, it can be enabled by hwconfig. Syntax is: hwconfig=fsl_ddr:addr_hash=true +Memory controller ECC on/off +============================ +If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC, +ECC can be turned on/off by hwconfig. + +Syntax is +hwconfig=fsl_ddr:ecc=off Memory testing options for mpc85xx ================================== -- cgit v1.1 From 8ed20f2c178aa44c8e1a35703579fd63350e9f42 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Jan 2011 12:02:58 +0000 Subject: corenet_ds: Enable ECC for corenet_ds ECC can be turned on/off by hwconfig without recompiling. So enable it by default. Signed-off-by: York Sun Signed-off-by: Kumar Gala --- include/configs/corenet_ds.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 5e9de90..bff212e 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -80,7 +80,7 @@ #define CONFIG_BACKSIDE_L2_CACHE #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ -/*#define CONFIG_DDR_ECC*/ +#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -- cgit v1.1 From d2a9568c57f0aa02f097911d3811e002a1eec1b8 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Jan 2011 12:02:59 +0000 Subject: mpc85xx: Adding more registers and options This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 12 +++++++++--- arch/powerpc/include/asm/fsl_ddr_sdram.h | 12 ++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 21 ++------------------- board/tqc/tqm85xx/sdram.c | 8 ++++---- 4 files changed, 27 insertions(+), 26 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index e46dcb7..4e768d3 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -9,6 +9,7 @@ #include #include #include +#include #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL @@ -79,6 +80,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); + out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); + out_be32(&ddr->err_disable, regs->err_disable); + out_be32(&ddr->err_int_en, regs->err_int_en); + for (i = 0; i < 32; i++) + out_be32(&ddr->debug[i], regs->debug[i]); /* Set, but do not enable the memory */ temp_sdram_cfg = regs->ddr_sdram_cfg; @@ -93,8 +100,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) && in_be32(&ddr->sdram_cfg) & 0x80000) { /* set DEBUG_1[31] */ - u32 temp = in_be32(&ddr->debug_1); - out_be32(&ddr->debug_1, temp | 1); + setbits_be32(&ddr->debug[0], 1); } #endif diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 3de2113..04aeb40 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -120,6 +120,11 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; unsigned int ddr_eor; + unsigned int ddr_cdr1; + unsigned int ddr_cdr2; + unsigned int err_disable; + unsigned int err_int_en; + unsigned int debug[32]; } fsl_ddr_cfg_regs_t; typedef struct memctl_options_partial_s { @@ -175,6 +180,7 @@ typedef struct memctl_options_s { /* mirrior DIMMs for DDR3 */ unsigned int mirrored_dimm; unsigned int quad_rank_present; + unsigned int ap_en; /* address parity enable for RDIMM */ /* Global Timing Parameters */ unsigned int cas_latency_override; @@ -210,6 +216,12 @@ typedef struct memctl_options_s { unsigned int zq_en; /* Write leveling */ unsigned int wrlvl_en; + /* RCW override for RDIMM */ + unsigned int rcw_override; + unsigned int rcw_1; + unsigned int rcw_2; + /* control register 1 */ + unsigned int ddr_cdr1; } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 93a9e6c..6bd83ba 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -222,25 +222,8 @@ typedef struct ccsr_ddr { u32 capture_ext_address; /* Error Extended Addr Capture */ u32 err_sbe; /* Single-Bit ECC Error Management */ u8 res11[164]; - u32 debug_1; - u32 debug_2; - u32 debug_3; - u32 debug_4; - u32 debug_5; - u32 debug_6; - u32 debug_7; - u32 debug_8; - u32 debug_9; - u32 debug_10; - u32 debug_11; - u32 debug_12; - u32 debug_13; - u32 debug_14; - u32 debug_15; - u32 debug_16; - u32 debug_17; - u32 debug_18; - u8 res12[184]; + u32 debug[32]; /* debug_1 to debug_32 */ + u8 res12[128]; } ccsr_ddr_t; #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */ diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index b2d3185..39a9e21 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -240,7 +240,7 @@ static phys_size_t sdram_setup(int casl) * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data * training */ - ddr->debug_3 |= 0x00000400; + ddr->debug[2] |= 0x00000400; /* * 5. Wait 200 micro-seconds @@ -282,18 +282,18 @@ static phys_size_t sdram_setup(int casl) /* * 8. Clear D3[21] to re-enable data training */ - ddr->debug_3 &= ~0x00000400; + ddr->debug[2] &= ~0x00000400; /* * 9. Set D2(21) to force data training to run */ - ddr->debug_2 |= 0x00000400; + ddr->debug[1] |= 0x00000400; /* * 10. Poll on D2[21] until it is cleared by hardware */ asm ("sync;isync;msync"); - while (ddr->debug_2 & 0x00000400) + while (ddr->debug[1] & 0x00000400) asm ("eieio"); /* -- cgit v1.1 From e1fd16b6f5e80d932c73f5a36141adfb35126e83 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Jan 2011 12:03:00 +0000 Subject: mpc85xx: Enable unique mode registers and dynamic ODT for DDR3 Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 6 + arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 252 ++++++++++++++++++++----- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 308 ++++++++++++++++++++++++++++++- arch/powerpc/include/asm/fsl_ddr_sdram.h | 18 ++ doc/README.fsl-ddr | 67 ++++++- 5 files changed, 596 insertions(+), 55 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index 4e768d3..9bc36f3 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -66,6 +66,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); + out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); + out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); + out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); + out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); + out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); out_be32(&ddr->sdram_data_init, regs->ddr_data_init); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 8fdafdb..2271071 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free @@ -18,7 +18,28 @@ #include "ddr.h" -extern unsigned int picos_to_mclk(unsigned int picos); +#ifdef CONFIG_MPC85xx + #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR +#elif defined(CONFIG_MPC86xx) + #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR +#else + #error "Undefined _DDR_ADDR" +#endif + +u32 fsl_ddr_get_version(void) +{ + ccsr_ddr_t *ddr; + u32 ver_major_minor_errata; + + ddr = (void *)_DDR_ADDR; + ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8; + ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8; + + return ver_major_minor_errata; +} + +unsigned int picos_to_mclk(unsigned int picos); + /* * Determine Rtt value. * @@ -187,7 +208,8 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) * Avoid writing for DDR I. The new PQ38 DDR controller * dreams up non-zero default values to be backwards compatible. */ -static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) +static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) { unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ @@ -204,7 +226,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) /* Mode register set cycle time (tMRD). */ unsigned char tmrd_mclk; -#if defined(CONFIG_FSL_DDR3) +#ifdef CONFIG_FSL_DDR3 /* * (tXARD and tXARDS). Empirical? * The DDR3 spec has not tXARD, @@ -214,13 +236,21 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) * tAXPD=1, need design to confirm. */ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ - act_pd_exit_mclk = picos_to_mclk(tXP); - /* Mode register MR0[A12] is '1' - fast exit */ - pre_pd_exit_mclk = act_pd_exit_mclk; - taxpd_mclk = 1; tmrd_mclk = 4; /* set the turnaround time */ trwt_mclk = 1; + + if (popts->dynamic_power == 0) { /* powerdown is not used */ + act_pd_exit_mclk = 1; + pre_pd_exit_mclk = 1; + taxpd_mclk = 1; + } else { + /* act_pd_exit_mclk = tXARD, see above */ + act_pd_exit_mclk = picos_to_mclk(tXP); + /* Mode register MR0[A12] is '1' - fast exit */ + pre_pd_exit_mclk = act_pd_exit_mclk; + taxpd_mclk = 1; + } #else /* CONFIG_FSL_DDR2 */ /* * (tXARD and tXARDS). Empirical? @@ -450,28 +480,34 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, /* DDR SDRAM Register Control Word */ static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, const common_timing_params_t *common_dimm) { if (common_dimm->all_DIMMs_registered && !common_dimm->all_DIMMs_unbuffered) { - ddr->ddr_sdram_rcw_1 = - common_dimm->rcw[0] << 28 | \ - common_dimm->rcw[1] << 24 | \ - common_dimm->rcw[2] << 20 | \ - common_dimm->rcw[3] << 16 | \ - common_dimm->rcw[4] << 12 | \ - common_dimm->rcw[5] << 8 | \ - common_dimm->rcw[6] << 4 | \ - common_dimm->rcw[7]; - ddr->ddr_sdram_rcw_2 = - common_dimm->rcw[8] << 28 | \ - common_dimm->rcw[9] << 24 | \ - common_dimm->rcw[10] << 20 | \ - common_dimm->rcw[11] << 16 | \ - common_dimm->rcw[12] << 12 | \ - common_dimm->rcw[13] << 8 | \ - common_dimm->rcw[14] << 4 | \ - common_dimm->rcw[15]; + if (popts->rcw_override) { + ddr->ddr_sdram_rcw_1 = popts->rcw_1; + ddr->ddr_sdram_rcw_2 = popts->rcw_2; + } else { + ddr->ddr_sdram_rcw_1 = + common_dimm->rcw[0] << 28 | \ + common_dimm->rcw[1] << 24 | \ + common_dimm->rcw[2] << 20 | \ + common_dimm->rcw[3] << 16 | \ + common_dimm->rcw[4] << 12 | \ + common_dimm->rcw[5] << 8 | \ + common_dimm->rcw[6] << 4 | \ + common_dimm->rcw[7]; + ddr->ddr_sdram_rcw_2 = + common_dimm->rcw[8] << 28 | \ + common_dimm->rcw[9] << 24 | \ + common_dimm->rcw[10] << 20 | \ + common_dimm->rcw[11] << 16 | \ + common_dimm->rcw[12] << 12 | \ + common_dimm->rcw[13] << 8 | \ + common_dimm->rcw[14] << 4 | \ + common_dimm->rcw[15]; + } debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); } @@ -509,8 +545,14 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, ecc_en = 0; } - rd_en = (common_dimm->all_DIMMs_registered - && !common_dimm->all_DIMMs_unbuffered); + if (common_dimm->all_DIMMs_registered + && !common_dimm->all_DIMMs_unbuffered) { + rd_en = 1; + twoT_en = 0; + } else { + rd_en = 0; + twoT_en = popts->twoT_en; + } sdram_type = CONFIG_FSL_SDRAM_TYPE; @@ -530,7 +572,6 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, } threeT_en = popts->threeT_en; - twoT_en = popts->twoT_en; ba_intlv_ctl = popts->ba_intlv_ctl; hse = popts->half_strength_driver_enable; @@ -558,7 +599,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) + const memctl_options_t *popts, + const unsigned int unq_mrs_en) { unsigned int frc_sr = 0; /* Force self refresh */ unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ @@ -598,11 +640,17 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, obc_cfg = 0; #endif - ap_en = 0; /* Make this configurable? */ + if (popts->registered_dimm_en) { + rcw_en = 1; + ap_en = popts->ap_en; + } else { + rcw_en = 0; + ap_en = 0; + } #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* Use the DDR controller to auto initialize memory. */ - d_init = 1; + d_init = popts->ECC_init_using_memctl; ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); #else @@ -613,7 +661,6 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_FSL_DDR3) md_en = popts->mirrored_dimm; #endif - rcw_en = popts->registered_dimm_en; qd_en = popts->quad_rank_present ? 1 : 0; ddr->ddr_sdram_cfg_2 = (0 | ((frc_sr & 0x1) << 31) @@ -623,6 +670,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((odt_cfg & 0x3) << 21) | ((num_pr & 0xf) << 12) | (qd_en << 9) + | (unq_mrs_en << 8) | ((obc_cfg & 0x1) << 6) | ((ap_en & 0x1) << 5) | ((d_init & 0x1) << 4) @@ -634,10 +682,12 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) + const memctl_options_t *popts, + const unsigned int unq_mrs_en) { unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ + int i; #if defined(CONFIG_FSL_DDR3) unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ @@ -648,7 +698,8 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, if (popts->rtt_override) rtt_wr = popts->rtt_wr_override_value; - + else + rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; esdmode2 = (0 | ((rtt_wr & 0x3) << 9) | ((srt & 0x1) << 7) @@ -661,6 +712,46 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, | ((esdmode3 & 0xFFFF) << 0) ); debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); + +#ifdef CONFIG_FSL_DDR3 + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < 4; i++) { + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + else + rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; + + esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ + esdmode2 |= (rtt_wr & 0x3) << 9; + switch (i) { + case 1: + ddr->ddr_sdram_mode_4 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_6 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_8 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", + ddr->ddr_sdram_mode_4); + debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", + ddr->ddr_sdram_mode_6); + debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", + ddr->ddr_sdram_mode_8); + } +#endif } /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ @@ -689,7 +780,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, - unsigned int additive_latency) + unsigned int additive_latency, + const unsigned int unq_mrs_en) { unsigned short esdmode; /* Extended SDRAM mode */ unsigned short sdmode; /* SDRAM mode */ @@ -700,7 +792,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, unsigned int rtt; unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ unsigned int al = 0; /* Posted CAS# additive latency (AL) */ - unsigned int dic = 1; /* Output driver impedance, 34ohm */ + unsigned int dic = 0; /* Output driver impedance, 40ohm */ unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), 1=Disable (Test/Debug) */ @@ -717,16 +809,21 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, unsigned int wr_mclk; const unsigned int mclk_ps = get_memory_clk_period_ps(); + int i; - rtt = fsl_ddr_get_rtt(); if (popts->rtt_override) rtt = popts->rtt_override_value; + else + rtt = popts->cs_local_opts[0].odt_rtt_norm; if (additive_latency == (cas_latency - 1)) al = 1; if (additive_latency == (cas_latency - 2)) al = 2; + if (popts->quad_rank_present) + dic = 1; /* output driver impedance 240/7 ohm */ + /* * The esdmode value will also be used for writing * MR1 during write leveling for DDR3, although the @@ -812,6 +909,48 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, ); debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); + + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < 4; i++) { + if (popts->rtt_override) + rtt = popts->rtt_override_value; + else + rtt = popts->cs_local_opts[i].odt_rtt_norm; + + esdmode &= 0xFDBB; /* clear bit 9,6,2 */ + esdmode |= (0 + | ((rtt & 0x4) << 7) /* rtt field is split */ + | ((rtt & 0x2) << 5) /* rtt field is split */ + | ((rtt & 0x1) << 2) /* rtt field is split */ + ); + switch (i) { + case 1: + ddr->ddr_sdram_mode_3 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_5 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_7 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", + ddr->ddr_sdram_mode_3); + debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", + ddr->ddr_sdram_mode_5); + debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", + ddr->ddr_sdram_mode_5); + } } #else /* !CONFIG_FSL_DDR3 */ @@ -821,7 +960,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, - unsigned int additive_latency) + unsigned int additive_latency, + const unsigned int unq_mrs_en) { unsigned short esdmode; /* Extended SDRAM mode */ unsigned short sdmode; /* SDRAM mode */ @@ -1024,7 +1164,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ -static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) +static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) { unsigned int rodt_on = 0; /* Read to ODT on */ unsigned int rodt_off = 0; /* Read to ODT off */ @@ -1032,7 +1172,8 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) unsigned int wodt_off = 0; /* Write to ODT off */ #if defined(CONFIG_FSL_DDR3) - rodt_on = 2; /* 2 clocks */ + /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */ + rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1; rodt_off = 4; /* 4 clocks */ wodt_on = 1; /* 1 clocks */ wodt_off = 4; /* 4 clocks */ @@ -1068,6 +1209,7 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) | ((zqoper & 0xF) << 16) | ((zqcs & 0xF) << 8) ); + debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); } /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ @@ -1113,7 +1255,8 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, /* * Write leveling start time * The value use for the DQS_ADJUST for the first sample - * when write leveling is enabled. + * when write leveling is enabled. It probably needs to be + * overriden per platform. */ wrlvl_start = 0x8; /* @@ -1135,6 +1278,7 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, | ((wrlvl_wlr & 0x7) << 8) | ((wrlvl_start & 0x1F) << 0) ); + debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); } /* DDR Self Refresh Counter (DDR_SR_CNTR) */ @@ -1152,6 +1296,12 @@ static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) } } +static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) +{ + ddr->ddr_cdr1 = popts->ddr_cdr1; + debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); +} + unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) { @@ -1185,6 +1335,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, unsigned int sr_it; unsigned int zq_en; unsigned int wrlvl_en; + unsigned int ip_rev = 0; + unsigned int unq_mrs_en = 0; int cs_en = 1; memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); @@ -1405,7 +1557,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_eor(ddr, popts); #if !defined(CONFIG_FSL_DDR1) - set_timing_cfg_0(ddr); + set_timing_cfg_0(ddr, popts); #endif set_timing_cfg_3(ddr, common_dimm, cas_latency); @@ -1413,26 +1565,30 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_timing_cfg_2(ddr, popts, common_dimm, cas_latency, additive_latency); + set_ddr_cdr1(ddr, popts); set_ddr_sdram_cfg(ddr, popts, common_dimm); + ip_rev = fsl_ddr_get_version(); + if (ip_rev > 0x40400) + unq_mrs_en = 1; - set_ddr_sdram_cfg_2(ddr, popts); + set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); set_ddr_sdram_mode(ddr, popts, common_dimm, - cas_latency, additive_latency); - set_ddr_sdram_mode_2(ddr, popts); + cas_latency, additive_latency, unq_mrs_en); + set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en); set_ddr_sdram_interval(ddr, popts, common_dimm); set_ddr_data_init(ddr); set_ddr_sdram_clk_cntl(ddr, popts); set_ddr_init_addr(ddr); set_ddr_init_ext_addr(ddr); set_timing_cfg_4(ddr, popts); - set_timing_cfg_5(ddr); + set_timing_cfg_5(ddr, cas_latency); set_ddr_zq_cntl(ddr, zq_en); set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); set_ddr_sr_cntr(ddr, sr_it); - set_ddr_sdram_rcw(ddr, common_dimm); + set_ddr_sdram_rcw(ddr, popts, common_dimm); return check_fsl_memctl_config_regs(ddr); } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 55dff43..6ccc3b0 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -26,6 +26,243 @@ extern void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num); +typedef struct { + unsigned int odt_rd_cfg; + unsigned int odt_wr_cfg; + unsigned int odt_rtt_norm; + unsigned int odt_rtt_wr; +} dynamic_odt_t; + +static const dynamic_odt_t single_Q[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS_AND_OTHER_DIMM, + DDR3_RTT_20_OHM, + DDR3_RTT_120_OHM + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, /* tied high */ + DDR3_RTT_OFF, + DDR3_RTT_120_OHM + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS_AND_OTHER_DIMM, + DDR3_RTT_20_OHM, + DDR3_RTT_120_OHM + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, /* tied high */ + DDR3_RTT_OFF, + DDR3_RTT_120_OHM + } +}; + +static const dynamic_odt_t single_D[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR3_RTT_OFF, + DDR3_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const dynamic_odt_t single_S[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, +}; + +static const dynamic_odt_t dual_DD[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR3_RTT_30_OHM, + DDR3_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR3_RTT_30_OHM, + DDR3_RTT_OFF + } +}; + +static const dynamic_odt_t dual_DS[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR3_RTT_30_OHM, + DDR3_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR3_RTT_20_OHM, + DDR3_RTT_120_OHM + }, + {0, 0, 0, 0} +}; +static const dynamic_odt_t dual_SD[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR3_RTT_20_OHM, + DDR3_RTT_120_OHM + }, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR3_RTT_20_OHM, + DDR3_RTT_OFF + } +}; + +static const dynamic_odt_t dual_SS[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR3_RTT_30_OHM, + DDR3_RTT_120_OHM + }, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR3_RTT_30_OHM, + DDR3_RTT_120_OHM + }, + {0, 0, 0, 0} +}; + +static const dynamic_odt_t dual_D0[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR3_RTT_OFF, + DDR3_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const dynamic_odt_t dual_0D[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR3_RTT_OFF, + DDR3_RTT_OFF + } +}; + +static const dynamic_odt_t dual_S0[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0} + +}; + +static const dynamic_odt_t dual_0S[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + {0, 0, 0, 0} + +}; + +static const dynamic_odt_t odt_unknown[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + } +}; + unsigned int populate_memctl_options(int all_DIMMs_registered, memctl_options_t *popts, dimm_params_t *pdimm, @@ -34,6 +271,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, unsigned int i; char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; + const dynamic_odt_t *pdodt = odt_unknown; /* * Extract hwconfig from environment since we have not properly setup @@ -43,15 +281,70 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, buf = buffer; /* Chip select options. */ + if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { + switch (pdimm[0].n_ranks) { + case 1: + pdodt = single_S; + break; + case 2: + pdodt = single_D; + break; + case 4: + pdodt = single_Q; + break; + } + } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { + switch (pdimm[0].n_ranks) { + case 2: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_DD; + break; + case 1: + pdodt = dual_DS; + break; + case 0: + pdodt = dual_D0; + break; + } + break; + case 1: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_SD; + break; + case 1: + pdodt = dual_SS; + break; + case 0: + pdodt = dual_S0; + break; + } + break; + case 0: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_0D; + break; + case 1: + pdodt = dual_0S; + break; + } + break; + } + } /* Pick chip-select local options. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */ - - /* only for single CS? */ - popts->cs_local_opts[i].odt_rd_cfg = 0; - - popts->cs_local_opts[i].odt_wr_cfg = 1; +#if defined(CONFIG_FSL_DDR3) + popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg; + popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg; + popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm; + popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr; +#else + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; +#endif popts->cs_local_opts[i].auto_precharge = 0; } @@ -179,6 +472,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->twoT_en = 0; popts->threeT_en = 0; + /* for RDIMM, address parity enable */ + popts->ap_en = 1; + /* * BSTTOPRE precharge interval * diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 04aeb40..989c915 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -24,6 +24,7 @@ #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ #define DDR_BL8 8 /* burst length 8 */ +#define DDR3_RTT_OFF 0 #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ @@ -50,6 +51,15 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #endif #endif /* #if defined(CONFIG_FSL_DDR1) */ +#define FSL_DDR_ODT_NEVER 0x0 +#define FSL_DDR_ODT_CS 0x1 +#define FSL_DDR_ODT_ALL_OTHER_CS 0x2 +#define FSL_DDR_ODT_OTHER_DIMM 0x3 +#define FSL_DDR_ODT_ALL 0x4 +#define FSL_DDR_ODT_SAME_DIMM 0x5 +#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 +#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 + /* define bank(chip select) interleaving mode */ #define FSL_DDR_CS0_CS1 0x40 #define FSL_DDR_CS2_CS3 0x20 @@ -106,6 +116,12 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int ddr_sdram_cfg_2; unsigned int ddr_sdram_mode; unsigned int ddr_sdram_mode_2; + unsigned int ddr_sdram_mode_3; + unsigned int ddr_sdram_mode_4; + unsigned int ddr_sdram_mode_5; + unsigned int ddr_sdram_mode_6; + unsigned int ddr_sdram_mode_7; + unsigned int ddr_sdram_mode_8; unsigned int ddr_sdram_md_cntl; unsigned int ddr_sdram_interval; unsigned int ddr_data_init; @@ -156,6 +172,8 @@ typedef struct memctl_options_s { unsigned int auto_precharge; unsigned int odt_rd_cfg; unsigned int odt_wr_cfg; + unsigned int odt_rtt_norm; + unsigned int odt_rtt_wr; } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; /* Special configurations for chip select */ diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 9e3c539..a7ba193 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -104,4 +104,69 @@ Combination of hwconfig Hwconfig can be combined with multiple parameters, for example, on a supported platform -hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3 +hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on + +Table for dynamic ODT for DDR3 +============================== +For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may +be needed, depending on the configuration. The numbers in the following tables are +in Ohms. + +* denotes dynamic ODT + +Two slots system ++-----------------------+----------+---------------+-----------------------------+-----------------------------+ +| Configuration | |DRAM controller| Slot 1 | Slot 2 | ++-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+ +| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 | ++ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+ +| | | | | | Write | Read | Write | Read | Write | Read | Write | Read | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 | +| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | | +| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 | +|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | | +|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +|Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ + +Single slot system ++-------------+------------+---------------+-----------------------------+-----------------------------+ +| | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 | +|Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read | ++-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off | +| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off | +| Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off | +| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off | ++-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | R1 | off | 75 | 40 | off | off | off | +| Dual Rank |------------+-------+-------+-------+------+-------+------+ +| | R2 | off | 75 | 40 | off | off | off | ++-------------+------------+-------+-------+-------+------+-------+------+ +| Single Rank | R1 | off | 75 | 40 | off | ++-------------+------------+-------+-------+-------+------+ + +Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf + http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf -- cgit v1.1 From fa8d23c0ee5c66d5cda902ac6ea5b1dfc68d9712 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Jan 2011 12:03:01 +0000 Subject: mpc85xx: Implement workaround for erratum DDR-A003 Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM. Also adding polling after enabling DDR controller to ensure completion. Signed-off-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 ++ arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 81 ++++++++++++++++++++++++++++++- arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/fsl_ddr_sdram.h | 19 ++++++++ 4 files changed, 103 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 7dfa596..0cc8b1e 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -68,6 +68,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001 puts("Work-around for Erratum ELBC-A001 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 + puts("Work-around for Erratum DDR-A003 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index 9bc36f3..fa7e09f 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -97,6 +97,82 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, temp_sdram_cfg = regs->ddr_sdram_cfg; temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); out_be32(&ddr->sdram_cfg, temp_sdram_cfg); +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 + if (regs->ddr_sdram_rcw_2 & 0x00f00000) { + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); + out_be32(&ddr->debug[2], 0x00000400); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); + out_be32(&ddr->mtcr, 0); + out_be32(&ddr->debug[12], 0x00000015); + out_be32(&ddr->debug[21], 0x24000000); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); + + asm volatile("sync;isync"); + while (!(in_be32(&ddr->debug[1]) & 0x2)) + ; + + switch (regs->ddr_sdram_rcw_2 & 0x00f00000) { + case 0x00000000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); + break; + case 0x00100000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x0a)); + break; + case 0x00200000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x12)); + break; + case 0x00300000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x1a)); + break; + default: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); + printf("Unsupported RC10\n"); + break; + } + + while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) + ; + udelay(6); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->debug[2], 0x0); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->debug[12], 0x0); + out_be32(&ddr->debug[21], 0x0); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); + + } +#endif /* * For 8572 DDR1 erratum - DDR controller may enter illegal state * when operatiing in 32-bit bus mode with 4-beat bursts, @@ -120,8 +196,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, asm volatile("sync;isync"); /* Let the controller go */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg); + temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + asm volatile("sync;isync"); + while (!(in_be32(&ddr->debug[1]) & 0x2)) + ; /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ while (in_be32(&ddr->sdram_cfg_2) & 0x10) { diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8ba6c7e..5792f2f 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -163,6 +163,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 989c915..e6f0d32 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -101,6 +101,25 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define WR_DATA_DELAY_SHIFT 10 #endif +/* DDR_MD_CNTL */ +#define MD_CNTL_MD_EN 0x80000000 +#define MD_CNTL_CS_SEL_CS0 0x00000000 +#define MD_CNTL_CS_SEL_CS1 0x10000000 +#define MD_CNTL_CS_SEL_CS2 0x20000000 +#define MD_CNTL_CS_SEL_CS3 0x30000000 +#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 +#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 +#define MD_CNTL_MD_SEL_MR 0x00000000 +#define MD_CNTL_MD_SEL_EMR 0x01000000 +#define MD_CNTL_MD_SEL_EMR2 0x02000000 +#define MD_CNTL_MD_SEL_EMR3 0x03000000 +#define MD_CNTL_SET_REF 0x00800000 +#define MD_CNTL_SET_PRE 0x00400000 +#define MD_CNTL_CKE_CNTL_LOW 0x00100000 +#define MD_CNTL_CKE_CNTL_HIGH 0x00200000 +#define MD_CNTL_WRCW 0x00080000 +#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) + /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { struct { -- cgit v1.1 From 6b06d7dc071a41e7c9d34447a18acdf53c6bdc4f Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Jan 2011 12:03:02 +0000 Subject: corenet_ds: Extend board specific parameters Extend board specific parameters to include cpo, write leveling override Extend write leveling sample to 0xf Adding rcw overrid for quad-rank RDIMMs Signed-off-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/fsl_ddr_sdram.h | 3 + board/freescale/corenet_ds/ddr.c | 159 ++++++++++++++++--------------- 2 files changed, 84 insertions(+), 78 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index e6f0d32..852e5c3 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -120,6 +120,9 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define MD_CNTL_WRCW 0x00080000 #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) +/* DDR_CDR1 */ +#define DDR_CDR1_DHC_EN 0x80000000 + /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { struct { diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 85b6c78..6660b01 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -56,12 +56,14 @@ phys_size_t fixed_sdram(void) strmhz(buf, sysinfo.freqDDRBus)); ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); #if (CONFIG_NUM_DDR_CONTROLLERS == 2) memcpy(&ddr_cfg_regs, fixed_ddr_parm_1[i].ddr_settings, sizeof(ddr_cfg_regs)); + ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1); #endif @@ -143,6 +145,7 @@ typedef struct { u32 datarate_mhz_high; u32 n_ranks; u32 clk_adjust; + u32 wrlvl_start; u32 cpo; u32 write_data_delay; u32 force_2T; @@ -162,57 +165,61 @@ typedef struct { /* XXX: Single rank at 800 MHz is OK. */ const board_specific_parameters_t board_specific_parameters[][30] = { { - /* memory controller 0 */ - /* lo| hi| num| clk| cpo|wrdata|2T */ - /* mhz| mhz|ranks|adjst| | delay| */ - { 0, 333, 4, 6, 7, 3, 0}, - {334, 400, 4, 6, 9, 3, 0}, - {401, 549, 4, 6, 11, 3, 0}, - {550, 680, 4, 1, 10, 5, 0}, - {681, 850, 4, 1, 12, 5, 0}, - {851, 1050, 4, 1, 12, 5, 0}, - {1051, 1250, 4, 1, 15, 4, 0}, - {1251, 1350, 4, 1, 15, 4, 0}, - { 0, 333, 2, 6, 7, 3, 0}, - {334, 400, 2, 6, 9, 3, 0}, - {401, 549, 2, 6, 11, 3, 0}, - {550, 680, 2, 1, 10, 5, 0}, - {681, 850, 2, 1, 12, 5, 0}, - {851, 1050, 2, 1, 12, 5, 0}, - {1051, 1250, 2, 1, 15, 4, 0}, - {1251, 1350, 2, 1, 15, 4, 0}, - { 0, 333, 1, 6, 7, 3, 0}, - {334, 400, 1, 6, 9, 3, 0}, - {401, 549, 1, 6, 11, 3, 0}, - {550, 680, 1, 1, 10, 5, 0}, - {681, 850, 1, 1, 12, 5, 0} + /* + * memory controller 0 + * lo| hi| num| clk| wrlvl | cpo |wrdata|2T + * mhz| mhz|ranks|adjst| start | delay| + */ + { 0, 333, 4, 5, 7, 0xff, 2, 0}, + {334, 400, 4, 5, 7, 0xff, 2, 0}, + {401, 549, 4, 5, 7, 0xff, 2, 0}, + {550, 680, 4, 5, 7, 0xff, 2, 0}, + {681, 850, 4, 5, 7, 0xff, 2, 0}, + {851, 1050, 4, 5, 7, 0xff, 2, 0}, + {1051, 1250, 4, 5, 8, 0xff, 2, 0}, + {1251, 1350, 4, 5, 9, 0xff, 2, 0}, + { 0, 333, 2, 5, 7, 0xff, 2, 0}, + {334, 400, 2, 5, 7, 0xff, 2, 0}, + {401, 549, 2, 5, 7, 0xff, 2, 0}, + {550, 680, 2, 5, 7, 0xff, 2, 0}, + {681, 850, 2, 5, 7, 0xff, 2, 0}, + {851, 1050, 2, 5, 7, 0xff, 2, 0}, + {1051, 1250, 2, 5, 7, 0xff, 2, 0}, + {1251, 1350, 2, 5, 7, 0xff, 2, 0}, + { 0, 333, 1, 5, 7, 0xff, 2, 0}, + {334, 400, 1, 5, 7, 0xff, 2, 0}, + {401, 549, 1, 5, 7, 0xff, 2, 0}, + {550, 680, 1, 5, 7, 0xff, 2, 0}, + {681, 850, 1, 5, 7, 0xff, 2, 0} }, { - /* memory controller 1 */ - /* lo| hi| num| clk| cpo|wrdata|2T */ - /* mhz| mhz|ranks|adjst| | delay| */ - { 0, 333, 4, 6, 7, 3, 0}, - {334, 400, 4, 6, 9, 3, 0}, - {401, 549, 4, 6, 11, 3, 0}, - {550, 680, 4, 1, 10, 5, 0}, - {681, 850, 4, 1, 12, 5, 0}, - {851, 1050, 4, 1, 12, 5, 0}, - {1051, 1250, 4, 1, 15, 4, 0}, - {1251, 1350, 4, 1, 15, 4, 0}, - { 0, 333, 2, 6, 7, 3, 0}, - {334, 400, 2, 6, 9, 3, 0}, - {401, 549, 2, 6, 11, 3, 0}, - {550, 680, 2, 1, 11, 6, 0}, - {681, 850, 2, 1, 13, 6, 0}, - {851, 1050, 2, 1, 13, 6, 0}, - {1051, 1250, 2, 1, 15, 4, 0}, - {1251, 1350, 2, 1, 15, 4, 0}, - { 0, 333, 1, 6, 7, 3, 0}, - {334, 400, 1, 6, 9, 3, 0}, - {401, 549, 1, 6, 11, 3, 0}, - {550, 680, 1, 1, 11, 6, 0}, - {681, 850, 1, 1, 13, 6, 0} + /* + * memory controller 1 + * lo| hi| num| clk| wrlvl | cpo |wrdata|2T + * mhz| mhz|ranks|adjst| start | delay| + */ + { 0, 333, 4, 5, 7, 0xff, 2, 0}, + {334, 400, 4, 5, 7, 0xff, 2, 0}, + {401, 549, 4, 5, 7, 0xff, 2, 0}, + {550, 680, 4, 5, 7, 0xff, 2, 0}, + {681, 850, 4, 5, 7, 0xff, 2, 0}, + {851, 1050, 4, 5, 7, 0xff, 2, 0}, + {1051, 1250, 4, 5, 8, 0xff, 2, 0}, + {1251, 1350, 4, 5, 9, 0xff, 2, 0}, + { 0, 333, 2, 5, 7, 0xff, 2, 0}, + {334, 400, 2, 5, 7, 0xff, 2, 0}, + {401, 549, 2, 5, 7, 0xff, 2, 0}, + {550, 680, 2, 5, 7, 0xff, 2, 0}, + {681, 850, 2, 5, 7, 0xff, 2, 0}, + {851, 1050, 2, 5, 7, 0xff, 2, 0}, + {1051, 1250, 2, 5, 7, 0xff, 2, 0}, + {1251, 1350, 2, 5, 7, 0xff, 2, 0}, + { 0, 333, 1, 5, 7, 0xff, 2, 0}, + {334, 400, 1, 5, 7, 0xff, 2, 0}, + {401, 549, 1, 5, 7, 0xff, 2, 0}, + {550, 680, 1, 5, 7, 0xff, 2, 0}, + {681, 850, 1, 5, 7, 0xff, 2, 0} } }; @@ -227,37 +234,18 @@ void fsl_ddr_board_options(memctl_options_t *popts, u32 i; ulong ddr_freq; - /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in - * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If - * there are two dimms in the controller, set odt_rd_cfg to 3 and - * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. - */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i&1) { /* odd CS */ - popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 1; - } else { /* even CS */ - if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { - popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 1; - } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { - popts->cs_local_opts[i].odt_rd_cfg = 3; - popts->cs_local_opts[i].odt_wr_cfg = 3; - } - } - } - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; for (i = 0; i < num_params; i++) { if (ddr_freq >= pbsp->datarate_mhz_low && - ddr_freq <= pbsp->datarate_mhz_high && - pdimm->n_ranks == pbsp->n_ranks) { - popts->cpo_override = 0xff; /* force auto CPO calibration */ - popts->write_data_delay = 2; - popts->clk_adjust = 5; /* Force value to be 5/8 clock cycle */ + ddr_freq <= pbsp->datarate_mhz_high && + pdimm[0].n_ranks == pbsp->n_ranks) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; popts->twoT_en = pbsp->force_2T; } pbsp++; @@ -272,17 +260,32 @@ void fsl_ddr_board_options(memctl_options_t *popts, * Write leveling override */ popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xa; - popts->wrlvl_start = 0x7; + popts->wrlvl_sample = 0xf; + /* * Rtt and Rtt_WR override */ - popts->rtt_override = 1; - popts->rtt_override_value = DDR3_RTT_120_OHM; - popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ + popts->rtt_override = 0; /* Enable ZQ calibration */ popts->zq_en = 1; + + /* DHC_EN =1, ODT = 60 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN; + + /* override SPD values. rcw_2 should vary at differnt speed */ + if (pdimm[0].n_ranks == 4) { + popts->rcw_override = 1; + popts->rcw_1 = 0x000a5a00; + if (ddr_freq <= 800) + popts->rcw_2 = 0x00000000; + else if (ddr_freq <= 1066) + popts->rcw_2 = 0x00100000; + else if (ddr_freq <= 1333) + popts->rcw_2 = 0x00200000; + else + popts->rcw_2 = 0x00300000; + } } phys_size_t initdram(int board_type) -- cgit v1.1 From 768d5b2bafd702c711d79b67ad0a289d22938c40 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Jan 2011 14:10:28 -0800 Subject: powerpc/p4080: Fix warning in serdes code from early use of hwconfig Hwconfig is called before relocating. Use the new hwconfig APIs. Signed-off-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 5bcf91a..7fc00d8 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -33,6 +33,8 @@ static u32 serdes_prtcl_map; +#define HWCONFIG_BUFFER_SIZE 128 + #ifdef DEBUG static const char *serdes_prtcl_str[] = { [NONE] = "NA", @@ -277,6 +279,15 @@ void fsl_serdes_init(void) const char *srds_lpd_arg; size_t arglen; #endif + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + + /* + * Extract hwconfig from environment since we have not properly setup + * the environment but need it for ddr config params + */ + if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + buf = buffer; /* Is serdes enabled at all? */ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) @@ -295,8 +306,8 @@ void fsl_serdes_init(void) if (!IS_SVR_REV(get_svr(), 1, 0)) for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); - srds_lpd_arg = hwconfig_subarg("serdes", srds_lpd_opt, - &arglen); + srds_lpd_arg = hwconfig_subarg_f("serdes", srds_lpd_opt, + &arglen, buf); if (srds_lpd_arg) srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg, NULL, 0); -- cgit v1.1 From b7070904327d10eb789ccafa4622659ffaa6645c Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Wed, 19 Jan 2011 10:52:04 +0530 Subject: ppc/85xx: Fix compile err when PCI disabled on P1_P2_RDB u-boot cannot be compiled after disabling CONFIG_PCI. Place PCI related codes under #ifdef CONFIG_PCI Signed-off-by: Prabhakar Kushwaha Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/p1_p2_rdb.c | 4 +++- board/freescale/p1_p2_rdb/tlb.c | 4 +++- include/configs/P1_P2_RDB.h | 13 ++++++++----- 3 files changed, 14 insertions(+), 7 deletions(-) diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 440fcb9..0780942 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -222,7 +222,9 @@ void ft_board_setup(void *blob, bd_t *bd) base = getenv_bootm_low(); size = getenv_bootm_size(); +#if defined(CONFIG_PCI) ft_pci_board_setup(blob); +#endif /* #if defined(CONFIG_PCI) */ fdt_fixup_memory(blob, (u64)base, (u64)size); } diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index 93d0bf7..b85c268 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -58,6 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_16M, 1), +#if defined(CONFIG_PCI) /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -68,6 +69,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), +#endif /* #if defined(CONFIG_PCI) */ /* *I*G - NAND */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index d18d2f6..bf34740 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -83,17 +83,23 @@ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ + #define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#if defined(CONFIG_PCI) #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#endif /* #if defined(CONFIG_PCI) */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_PCI) #define CONFIG_E1000 1 /* E1000 pci Ethernet card*/ +#endif + #ifndef __ASSEMBLY__ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif @@ -364,6 +370,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#if defined(CONFIG_PCI) #define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 @@ -385,8 +392,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#if defined(CONFIG_PCI) -#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 @@ -405,11 +410,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_PCI */ -#if defined(CONFIG_TSEC_ENET) -#ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 -#endif +#if defined(CONFIG_TSEC_ENET) #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_TSEC1 1 -- cgit v1.1 From beba93ed05d8cea795bad895b6cc1490004fc242 Mon Sep 17 00:00:00 2001 From: Dipen Dudhat Date: Wed, 19 Jan 2011 12:46:27 +0530 Subject: powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBC Future SoC (like the P1010) replace the LBC controller with the new IFC (Integrated Flash Controller) so ensure we properly protect code that is related to the LBC. Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu.c | 9 ++++++++- arch/powerpc/cpu/mpc85xx/speed.c | 6 +++++- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 4ef9be1..1aad2ba 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2007-2010 Freescale Semiconductor, Inc. + * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. * (C) Copyright 2002, 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -166,12 +166,14 @@ int checkcpu (void) } #endif +#if defined(CONFIG_FSL_LBC) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } +#endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); @@ -284,7 +286,10 @@ void mpc85xx_reginfo(void) { print_tlbcam(); print_laws(); +#if defined(CONFIG_FSL_LBC) print_lbc_regs(); +#endif + } /* Common ddr init for non-corenet fsl 85xx platforms */ @@ -330,8 +335,10 @@ phys_size_t initdram(int board_type) ddr_enable_ecc(dram_size); #endif +#if defined(CONFIG_FSL_LBC) /* Some boards also have sdram on the lbc */ lbc_sdram_init(); +#endif puts("DDR: "); return dram_size; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index dd4c6b3..f2aa8d0 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) @@ -131,7 +131,9 @@ void get_sys_info (sys_info_t * sysInfo) #else uint plat_ratio,e500_ratio,half_freqSystemBus; +#if defined(CONFIG_FSL_LBC) uint lcrr_div; +#endif int i; #ifdef CONFIG_QE u32 qe_ratio; @@ -168,6 +170,7 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; #endif +#if defined(CONFIG_FSL_LBC) #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; @@ -193,6 +196,7 @@ void get_sys_info (sys_info_t * sysInfo) /* In case anyone cares what the unknown value is */ sysInfo->freqLocalBus = lcrr_div; } +#endif } -- cgit v1.1 From 92966835e96af324fed574815036e481be807d04 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 20 Jan 2011 01:53:15 -0600 Subject: powerpc/8xxx: Fix compile warning when build for a DDR1 or DDR2 board ctrl_regs.c: In function 'set_ddr_sdram_mode_2': ctrl_regs.c:690:6: warning: unused variable 'i' 'i' is only used by DDR3 code. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 2271071..c3e1d76 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -687,9 +687,9 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, { unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ - int i; #if defined(CONFIG_FSL_DDR3) + int i; unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ unsigned int srt = 0; /* self-refresh temerature, normal range */ unsigned int asr = 0; /* auto self-refresh disable */ -- cgit v1.1