From a0117a5e416629932becf079589f5e1859eab90a Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 26 May 2015 19:53:41 +0200 Subject: imx: drop warning: unused variable 'max_freq' max_freq in print_cpuinfo is used only with imx6. Signed-off-by: Stefano Babic --- arch/arm/imx-common/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 275befd..a78e0ed 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -145,11 +145,12 @@ const char *get_imx_type(u32 imxtype) int print_cpuinfo(void) { - u32 cpurev, max_freq; + u32 cpurev; #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL) struct udevice *thermal_dev; int cpu_tmp, minc, maxc, ret; + u32 max_freq; #endif cpurev = get_cpu_rev(); -- cgit v1.1 From 8649b405c5e53314598c6e50a0e72f2eb481ce37 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 28 May 2015 12:00:05 +0200 Subject: Revert "imx: drop warning: unused variable 'max_freq'" This reverts commit a0117a5e416629932becf079589f5e1859eab90a. Signed-off-by: Stefano Babic --- arch/arm/imx-common/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index a78e0ed..275befd 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -145,12 +145,11 @@ const char *get_imx_type(u32 imxtype) int print_cpuinfo(void) { - u32 cpurev; + u32 cpurev, max_freq; #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL) struct udevice *thermal_dev; int cpu_tmp, minc, maxc, ret; - u32 max_freq; #endif cpurev = get_cpu_rev(); -- cgit v1.1 From 378b02d7edea56a53cfd51700e0c63c3ee126bbc Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 8 May 2015 15:17:10 -0700 Subject: pci: imx: display message if no pcie link If CONFIG_PCI_SCAN_SHOW enabled then lets print a message of no link was detected. Signed-off-by: Tim Harvey --- drivers/pci/pcie_imx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index fd7e4d4..ca485ba 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -588,7 +588,9 @@ static int imx_pcie_link_up(void) udelay(10); count++; if (count >= 2000) { - debug("phy link never came up\n"); +#ifdef CONFIG_PCI_SCAN_SHOW + puts("PCI: pcie phy link never came up\n"); +#endif debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0), readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1)); -- cgit v1.1 From 825adb991ab081a50a92e50cc54a1f42b7277c94 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 27 May 2015 01:11:44 -0300 Subject: warp: Adjust CONFIG_SYS_DFU_DATA_BUF_SIZE Adjust CONFIG_SYS_DFU_DATA_BUF_SIZE in order to avoid the following error when running the dfu command: => dfu 0 mmc 0 dfu_get_buf: Could not memalign 0x2000000 bytes Signed-off-by: Fabio Estevam --- include/configs/warp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/warp.h b/include/configs/warp.h index 2673948..f0a912b 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -94,7 +94,7 @@ #define CONFIG_CMD_DFU #define CONFIG_DFU_FUNCTION #define CONFIG_DFU_MMC -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v1.1 From b459803335c2375ea776e68a1382f6d923278736 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 27 May 2015 01:11:45 -0300 Subject: warp: Fix CONFIG_SYS_FSL_ESDHC_ADDR Warp uses eMMC connected to esdhc2 port, so fix CONFIG_SYS_FSL_ESDHC_ADDR to reflect that. Signed-off-by: Fabio Estevam --- include/configs/warp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/warp.h b/include/configs/warp.h index f0a912b..a67254e 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -25,7 +25,7 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #define CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE -- cgit v1.1 From e6434d7eca14fc3b1bde9beac5eb8df6db1bf929 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 27 May 2015 01:11:46 -0300 Subject: warp: Enable CONFIG_SUPPORT_EMMC_BOOT CONFIG_SUPPORT_EMMC_BOOT is important to enable the boot partition via 'mmc partconf 0 1 1 0' command, for example. Signed-off-by: Fabio Estevam --- include/configs/warp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/warp.h b/include/configs/warp.h index a67254e..5463c40 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -28,6 +28,7 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #define CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE +#define CONFIG_SUPPORT_EMMC_BOOT /* Command definition */ #undef CONFIG_CMD_NET -- cgit v1.1 From fdf71898d943505412daa6f9dd37f86fd7e70c6c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 27 May 2015 01:11:47 -0300 Subject: warp: Add fuse command support Select the fuse command support. Signed-off-by: Fabio Estevam --- include/configs/warp.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/warp.h b/include/configs/warp.h index 5463c40..296ea83 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -98,6 +98,10 @@ #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M #define DFU_DEFAULT_POLL_TIMEOUT 300 +/* Fuses */ +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ -- cgit v1.1 From 68006aeb6d62343238578c6ea767907d63346aad Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 27 May 2015 01:11:48 -0300 Subject: warp: Fix the 'saveenv' command After the mx6 config consolidation, 'save' command is no longer recognized. Pass the full command name 'saveenv' instead. Signed-off-by: Fabio Estevam --- board/warp/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/warp/README b/board/warp/README index db3100e..22f9055 100644 --- a/board/warp/README +++ b/board/warp/README @@ -34,7 +34,7 @@ Then U-boot should start and its messages will appear in the console program. Use the default environment variables: => env default -f -a -=> save +=> saveenv Run the DFU command: => dfu 0 mmc 0 -- cgit v1.1 From 7bbc5ff732bcf8d2aa935249ce4b7c28a701ca51 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Thu, 21 May 2015 11:20:17 +0000 Subject: mxs: Do not disable bo detection when DC-DC is already enabled In case the DC-DC is already enabled mxs_enable_4p2_dcdc_input() returns without reenabling brown out detection. So fix this issue by moving the return before brown out deactivation. Signed-off-by: Stefan Wahren Reviewed-by: Marek Vasut --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index c342217..42f3df2 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -332,6 +332,11 @@ static void mxs_enable_4p2_dcdc_input(int xfer) debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling"); + if (xfer && (readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ENABLE_DCDC)) { + return; + } + prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) & POWER_5VCTRL_PWDN_5VBRNOUT; prev_5v_droop = readl(&power_regs->hw_power_ctrl) & @@ -343,11 +348,6 @@ static void mxs_enable_4p2_dcdc_input(int xfer) clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); - if (xfer && (readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_ENABLE_DCDC)) { - return; - } - /* * Recording orignal values that will be modified temporarlily * to handle a chip bug. See chip errata for CQ ENGR00115837 -- cgit v1.1 From 9a83a8154590ebfbdbe32579b97c501ca240a706 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 26 May 2015 11:04:54 -0700 Subject: imx: ventana: various board-specific GPIO config updates - Added iomux for CAN_STBY and RS484_TEN (GW52xx/GW53xx/GW54xx/GW551x) - Moved iomux of USBHUB_RST# out of board_ehci_hcd_init so that it is done regardless of USB being initialized in bootloader - Added usb_sel iomux/hwconfig for GW552x - Fixed mezzanine DIO for GW54xx - Fixed PANLEDR# for GW54xx - Fixed dio iomux/hwconfig for GW552x - Fixed dio iomux for GW551x - removed redundant #define Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/common.c | 56 +++++++++++++++++++++++---------- board/gateworks/gw_ventana/common.h | 6 +--- board/gateworks/gw_ventana/gw_ventana.c | 14 ++++----- 3 files changed, 46 insertions(+), 30 deletions(-) diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 5fa5d6a..d406c83 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -191,7 +191,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), /* MX6_LOCLED# */ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* GPS_SHDN */ @@ -204,11 +205,17 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), /* PCI_RST# (GW522x) */ IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* USB_HUBRST# */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ @@ -227,36 +234,46 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), /* PCI_RST# */ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* MX6_LOCLED# */ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* USB_HUBRST# */ + IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG), /* MIPI_DIO */ IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), /* RS485_EN */ IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), /* DIOI2C_DIS# */ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), /* PCI_RST# */ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), /* VID_EN */ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw551x_gpio_pads[] = { + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), /* PANLED# */ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* PCI_RST# */ @@ -266,6 +283,10 @@ static iomux_v3_cfg_t const gw551x_gpio_pads[] = { }; static iomux_v3_cfg_t const gw552x_gpio_pads[] = { + /* USBOTG_SEL */ + IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), + /* USB_HUBRST# */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ @@ -522,12 +543,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, .dio_cfg = { { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, IMX_GPIO_NR(1, 19), { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, @@ -539,12 +554,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 3 }, - { - { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, - IMX_GPIO_NR(1, 18), - { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, - 4 - }, }, .num_gpios = 2, .leds = { @@ -560,6 +569,12 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, .dio_cfg = { { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, IMX_GPIO_NR(1, 19), { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, @@ -571,6 +586,12 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 3 }, + { + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, }, .num_gpios = 4, .leds = { @@ -579,6 +600,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { IMX_GPIO_NR(4, 15), }, .pcie_rst = IMX_GPIO_NR(1, 29), + .usb_sel = IMX_GPIO_NR(1, 7), .wdis = IMX_GPIO_NR(7, 12), }, }; @@ -712,7 +734,7 @@ void setup_board_gpio(int board, struct ventana_board_info *info) * Configure DIO pinmux/padctl registers * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions */ - for (i = 0; i < 4; i++) { + for (i = 0; i < gpio_cfg[board].num_gpios; i++) { struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; iomux_v3_cfg_t ctrl = DIO_PAD_CFG; unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index b7c0e96..28f5816 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -34,10 +34,6 @@ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) - #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) @@ -46,7 +42,7 @@ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) -#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION) +#define DIO_PAD_CFG (MUX_PAD_CTRL(IRQ_PAD_CTRL) | MUX_MODE_SION) #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 22f3b38..ae3cc84 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -157,20 +157,18 @@ static iomux_v3_cfg_t const usb_pads[] = { int board_ehci_hcd_init(int port) { - struct ventana_board_info *info = &ventana_info; int gpio; SETUP_IOMUX_PADS(usb_pads); - /* Reset USB HUB (present on GW54xx/GW53xx) */ - switch (info->model[3]) { - case '3': /* GW53xx */ - case '5': /* GW552x */ - SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG); + /* Reset USB HUB */ + switch (board_type) { + case GW53xx: + case GW552x: gpio = (IMX_GPIO_NR(1, 9)); break; - case '4': /* GW54xx */ - SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG); + case GW54proto: + case GW54xx: gpio = (IMX_GPIO_NR(1, 16)); break; default: -- cgit v1.1 From 40c746758c4b9fabf07fbfa3b4ed9e907b4c8fd5 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 26 May 2015 11:04:55 -0700 Subject: imx: ventana: make model env var automatic and non-overridable We want to model env var to always reflect what was in the EEPROM. There is no point in allowing a user to override this. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index ae3cc84..e3737d1 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -685,8 +685,7 @@ int misc_init_r(void) memset(str, 0, sizeof(str)); for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) str[i] = tolower(info->model[i]); - if (!getenv("model")) - setenv("model", str); + setenv("model", str); if (!getenv("fdt_file")) { sprintf(fdt, "%s-%s.dtb", cputype, str); setenv("fdt_file", fdt); @@ -827,10 +826,6 @@ int ft_board_setup(void *blob, bd_t *bd) printf(" Set display timings for %s...\n", display); } - if (!model) { - puts("invalid board info: Leaving FDT fully enabled\n"); - return 0; - } printf(" Adjusting FDT per EEPROM for %s...\n", model); /* board serial number */ -- cgit v1.1 From 80d1a3ee72ad6b88b871f745343becd07a546bef Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 26 May 2015 11:04:56 -0700 Subject: imx: ventana: make fdt_file1 and fdt_file2 automatic and non-overridable The fdt_file1 and fdt_file2 vars provide fallbacks for the fdt file loading script. There is no need to allow the user to override these as if they want to specify the fdt, they should do so in the first attempt which is the fdt_file var. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index e3737d1..221069f 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -695,18 +695,14 @@ int misc_init_r(void) *p++ = 0; setenv("model_base", str); - if (!getenv("fdt_file1")) { - sprintf(fdt, "%s-%s.dtb", cputype, str); - setenv("fdt_file1", fdt); - } + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file1", fdt); if (board_type != GW551x && board_type != GW552x) str[4] = 'x'; str[5] = 'x'; str[6] = 0; - if (!getenv("fdt_file2")) { - sprintf(fdt, "%s-%s.dtb", cputype, str); - setenv("fdt_file2", fdt); - } + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file2", fdt); } /* initialize env from EEPROM */ -- cgit v1.1 From fdead4be6ad29cce17b57e78a0f7e8a488aeba80 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 26 May 2015 11:04:57 -0700 Subject: imx: ventana: hang if board model could not be determined If the EEPROM could not be read or is corrupt we always want to hang. Note that an error message will have been displayed by read_eeprom in this case. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana_spl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 9f5d2b1..d4418e5 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -515,10 +515,8 @@ void board_init_f(ulong dummy) setup_iomux_gpio(board_model, &ventana_info); /* provide some some default: 32bit 128MB */ - if (GW_UNKNOWN == board_model) { - ventana_info.sdram_width = 2; - ventana_info.sdram_size = 3; - } + if (GW_UNKNOWN == board_model) + hang(); /* configure MMDC for SDRAM width/size and per-model calibration */ spl_dram_init(8 << ventana_info.sdram_width, -- cgit v1.1 From c2fd3f57040d4d8e858f0449afe46416cfad95da Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 26 May 2015 11:04:58 -0700 Subject: imx: ventana: skip mtdparts fixup if no flash This avoids an error message on NAND-less boards. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 221069f..3b7c82b 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -811,9 +811,11 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } - /* Update partition nodes using info from mtdparts env var */ - puts(" Updating MTD partitions...\n"); - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + if (test_bit(EECONFIG_NAND, info->config)) { + /* Update partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + } /* Update display timings from display env var */ if (display) { -- cgit v1.1 From da2103c79ec95820bdbf7f1100a34bc501ebf7a4 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 12 May 2015 10:55:39 +0200 Subject: arm: mx6: tqma6: fix spelling error in condition Signed-off-by: Markus Niebel --- include/configs/tqma6_mba6.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index 88c0067..2f52598 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013, 2014 Markus Niebel + * Copyright (C) 2013 - 2015 Markus Niebel * * Configuration settings for the TQ Systems TQMa6 module. * @@ -11,7 +11,7 @@ #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) #define CONFIG_DEFAULT_FDT_FILE "imx6dl-mba6x.dtb" -#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q) +#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) #define CONFIG_DEFAULT_FDT_FILE "imx6q-mba6x.dtb" #endif -- cgit v1.1 From c0c5341e732b0c52190b2fd85bb6b94c5879dfd9 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 12 May 2015 10:55:40 +0200 Subject: arm: mx6: tqma6: use default CONFIG_SYS_PBSIZE this removes a config entry and uses the default value defined in config_fallbacks.h. This implements the same behaviour as a patch series for other i.MX6 boards from Freescale Signed-off-by: Markus Niebel --- include/configs/tqma6.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 4c93c9b..a091184 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -369,10 +369,6 @@ "panicboot=echo No boot device !!! reset\0" \ TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_STACKSIZE (128u * SZ_1K) /* Physical Memory Map */ -- cgit v1.1 From 9a8804a85e37d774419ee6452a90cc6e57d925f3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 21 May 2015 19:24:05 -0300 Subject: wandboard: Add board revision detection support There are two revisions of wandboard: version B1 and C1. Add the revision detection support, so that the correct dtb file can be automatically loaded. Based on the patch from Richard Hu . Signed-off-by: Fabio Estevam Reviewed-by: Stefano Babic Tested-By: Vagrant Cascadian --- board/wandboard/wandboard.c | 26 +++++++++++++++++++++++++- include/configs/wandboard.h | 8 ++++++-- 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 90625ab..0af63d2 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -50,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR; #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) +#define REV_DETECTION IMX_GPIO_NR(2, 28) int dram_init(void) { @@ -105,6 +106,10 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; +static iomux_v3_cfg_t const rev_detection_pad[] = { + IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + static void setup_iomux_uart(void) { SETUP_IOMUX_PADS(uart1_pads); @@ -393,6 +398,17 @@ static const struct boot_mode board_boot_modes[] = { }; #endif +static bool is_revc1(void) +{ + SETUP_IOMUX_PADS(rev_detection_pad); + gpio_direction_input(REV_DETECTION); + + if (gpio_get_value(REV_DETECTION)) + return true; + else + return false; +} + int board_late_init(void) { #ifdef CONFIG_CMD_BMODE @@ -404,6 +420,11 @@ int board_late_init(void) setenv("board_rev", "MX6Q"); else setenv("board_rev", "MX6DL"); + + if (is_revc1()) + setenv("board_name", "C1"); + else + setenv("board_name", "B1"); #endif return 0; } @@ -424,7 +445,10 @@ int board_init(void) int checkboard(void) { - puts("Board: Wandboard\n"); + if (is_revc1()) + puts("Board: Wandboard rev C1\n"); + else + puts("Board: Wandboard rev B1\n"); return 0; } diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 69590ad..0cc0f03 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -194,10 +194,14 @@ "bootz; " \ "fi;\0" \ "findfdt="\ - "if test $board_rev = MX6Q ; then " \ + "if test $board_name = C1 && test $board_rev = MX6Q ; then " \ "setenv fdtfile imx6q-wandboard.dtb; fi; " \ - "if test $board_rev = MX6DL ; then " \ + "if test $board_name = C1 && test $board_rev = MX6DL ; then " \ "setenv fdtfile imx6dl-wandboard.dtb; fi; " \ + "if test $board_name = B1 && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-wandboard-revb1.dtb; fi; " \ + "if test $board_name = B1 && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-wandboard-revb1.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine dtb to use; fi; \0" \ -- cgit v1.1 From cd6ddc48134297497d226209a4e6ea72b71c87c5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 28 May 2015 12:33:34 -0300 Subject: mx6_common: Fix LOADADDR and SYS_TEXT_BASE for MX6SL and MX6SX Commit 8183058188cd2d942 ("imx6: centralise common boot options in mx6_common.h") broke boot on mx6sl and mx6sx by assuming that all mx6 SoCs use the same LOADADDR/SYS_TEXT_BASE range, which is not correct. DDR on mx6sx/mx6sl starts at 0x80000000. Adjust LOADADDR/SYS_TEXT_BASE to the proper values for mx6sx/mx6sl, so that these SoCs can boot again. Also, TQMA6 requires a custom CONFIG_SYS_TEXT_BASE value, so move its setting prior to the inclusion of mx6_common.h. Signed-off-by: Fabio Estevam --- include/configs/mx6_common.h | 10 +++++++++- include/configs/tqma6.h | 14 +++++++------- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 233c6d2..50370e1 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -53,11 +53,19 @@ #define CONFIG_REVISION_TAG /* Boot options */ +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL)) +#define CONFIG_LOADADDR 0x82000000 +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x87800000 +#endif +#else #define CONFIG_LOADADDR 0x12000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x17800000 #endif +#endif +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #ifndef CONFIG_BOOTDELAY #define CONFIG_BOOTDELAY 3 #endif diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index a091184..e46c580 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -22,6 +22,13 @@ /* #endif */ +/* place code in last 4 MiB of RAM */ +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#define CONFIG_SYS_TEXT_BASE 0x2fc00000 +#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) +#define CONFIG_SYS_TEXT_BASE 0x4fc00000 +#endif + #include "mx6_common.h" #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) @@ -118,13 +125,6 @@ #define CONFIG_CMD_ITEST #define CONFIG_CMD_SETEXPR -/* place code in last 4 MiB of RAM */ -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) -#define CONFIG_SYS_TEXT_BASE 0x2fc00000 -#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) -#define CONFIG_SYS_TEXT_BASE 0x4fc00000 -#endif - #define CONFIG_ENV_SIZE (SZ_8K) /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) -- cgit v1.1 From ae89bb0d363eba33074106309c81c02f84b91ef8 Mon Sep 17 00:00:00 2001 From: Bhuvanchandra DV Date: Mon, 1 Jun 2015 18:37:15 +0530 Subject: dm: gpio: uclass: Add flag to control sequence numbering Like SPI and I2C few GPIO controllers also have multiple chip instances. This patch adds the flag 'DM_UC_FLAG_SEQ_ALIAS' in gpio_uclass driver to control device sequence numbering. By defalut the dev->r_seq for gpio_uclass will alwalys returns -1, which leads the gpio driver probe failure when using the driver with device trees. Signed-off-by: Bhuvanchandra DV --- drivers/gpio/gpio-uclass.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 530bb3e..bf982b9 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -757,6 +757,7 @@ static int gpio_pre_remove(struct udevice *dev) UCLASS_DRIVER(gpio) = { .id = UCLASS_GPIO, .name = "gpio", + .flags = DM_UC_FLAG_SEQ_ALIAS, .post_probe = gpio_post_probe, .pre_remove = gpio_pre_remove, .per_device_auto_alloc_size = sizeof(struct gpio_dev_priv), -- cgit v1.1 From d348a943e77ed72dd809cecf03365552545382b2 Mon Sep 17 00:00:00 2001 From: Bhuvanchandra DV Date: Mon, 1 Jun 2015 18:37:16 +0530 Subject: dm: gpio: vf610: Add GPIO driver support Add GPIO driver support to Freescale VF610 Signed-off-by: Bhuvanchandra DV --- arch/arm/imx-common/iomux-v3.c | 26 +++++ arch/arm/include/asm/arch-vf610/gpio.h | 29 +++++ arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + arch/arm/include/asm/imx-common/iomux-v3.h | 6 + drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/vybrid_gpio.c | 169 +++++++++++++++++++++++++++++ 7 files changed, 243 insertions(+) create mode 100644 arch/arm/include/asm/arch-vf610/gpio.h create mode 100644 drivers/gpio/vybrid_gpio.c diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index e88e6e2..7fb23dd 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -92,3 +92,29 @@ void imx_iomux_set_gpr_register(int group, int start_bit, reg |= (value << start_bit); writel(reg, base + group * 4); } + +#ifdef CONFIG_IOMUX_SHARE_CONF_REG +void imx_iomux_gpio_set_direction(unsigned int gpio, + unsigned int direction) +{ + u32 reg; + /* + * Only on Vybrid the input/output buffer enable flags + * are part of the shared mux/conf register. + */ + reg = readl(base + (gpio << 2)); + + if (direction) + reg |= 0x2; + else + reg &= ~0x2; + + writel(reg, base + (gpio << 2)); +} + +void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state) +{ + *gpio_state = readl(base + (gpio << 2)) & + ((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE); +} +#endif diff --git a/arch/arm/include/asm/arch-vf610/gpio.h b/arch/arm/include/asm/arch-vf610/gpio.h new file mode 100644 index 0000000..622b8f0 --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/gpio.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2015 + * Bhuvanchandra DV, Toradex, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_VF610_GPIO_H +#define __ASM_ARCH_VF610_GPIO_H + +#define VYBRID_GPIO_COUNT 32 +#define VF610_GPIO_DIRECTION_IN 0x0 +#define VF610_GPIO_DIRECTION_OUT 0x1 + +/* GPIO registers */ +struct vybrid_gpio_regs { + u32 gpio_pdor; + u32 gpio_psor; + u32 gpio_pcor; + u32 gpio_ptor; + u32 gpio_pdir; +}; + +struct vybrid_gpio_platdata { + unsigned int chip; + u32 base; + const char *port_name; +}; +#endif /* __ASM_ARCH_VF610_GPIO_H */ diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 2021981..7df3b1e 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -81,6 +81,11 @@ #define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000) #define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000) #define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) +#define GPIO0_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF000) +#define GPIO1_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF040) +#define GPIO2_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF080) +#define GPIO3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF0C0) +#define GPIO4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF100) /* AIPS 1 */ #define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000) diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index e0a49be..2581019 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -187,6 +187,12 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, */ void imx_iomux_set_gpr_register(int group, int start_bit, int num_bits, int value); +#ifdef CONFIG_IOMUX_SHARE_CONF_REG +void imx_iomux_gpio_set_direction(unsigned int gpio, + unsigned int direction); +void imx_iomux_gpio_get_function(unsigned int gpio, + u32 *gpio_state); +#endif /* macros for declaring and using pinmux array */ #if defined(CONFIG_MX6QDL) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 0840a30..0c43777 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -35,3 +35,10 @@ config SANDBOX_GPIO_COUNT are specified using the device tree. But you can also have a number of 'anonymous' GPIOs that do not belong to any device or bank. Select a suitable value depending on your needs. + +config VYBRID_GPIO + bool "Vybrid GPIO driver" + depends on DM + default n + help + Say yes here to support Vybrid vf610 GPIOs. diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index ba9efe8..5864850 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o +obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o diff --git a/drivers/gpio/vybrid_gpio.c b/drivers/gpio/vybrid_gpio.c new file mode 100644 index 0000000..6eaf0a9 --- /dev/null +++ b/drivers/gpio/vybrid_gpio.c @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2015 + * Bhuvanchandra DV, Toradex, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct vybrid_gpios { + unsigned int chip; + struct vybrid_gpio_regs *reg; +}; + +static int vybrid_gpio_direction_input(struct udevice *dev, unsigned gpio) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + + gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT); + imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_IN); + + return 0; +} + +static int vybrid_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + + gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT); + gpio_set_value(gpio, value); + imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_OUT); + + return 0; +} + +static int vybrid_gpio_get_value(struct udevice *dev, unsigned gpio) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + + return ((readl(&gpios->reg->gpio_pdir) & (1 << gpio))) ? 1 : 0; +} + +static int vybrid_gpio_set_value(struct udevice *dev, unsigned gpio, + int value) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + if (value) + writel((1 << gpio), &gpios->reg->gpio_psor); + else + writel((1 << gpio), &gpios->reg->gpio_pcor); + + return 0; +} + +static int vybrid_gpio_get_function(struct udevice *dev, unsigned gpio) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + u32 g_state = 0; + + gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT); + + imx_iomux_gpio_get_function(gpio, &g_state); + + if (((g_state & (0x07 << PAD_MUX_MODE_SHIFT)) >> PAD_MUX_MODE_SHIFT) > 0) + return GPIOF_FUNC; + if (g_state & PAD_CTL_OBE_ENABLE) + return GPIOF_OUTPUT; + if (g_state & PAD_CTL_IBE_ENABLE) + return GPIOF_INPUT; + if (!(g_state & PAD_CTL_OBE_IBE_ENABLE)) + return GPIOF_UNUSED; + + return GPIOF_UNKNOWN; +} + +static const struct dm_gpio_ops gpio_vybrid_ops = { + .direction_input = vybrid_gpio_direction_input, + .direction_output = vybrid_gpio_direction_output, + .get_value = vybrid_gpio_get_value, + .set_value = vybrid_gpio_set_value, + .get_function = vybrid_gpio_get_function, +}; + +static int vybrid_gpio_probe(struct udevice *dev) +{ + struct vybrid_gpios *gpios = dev_get_priv(dev); + struct vybrid_gpio_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->bank_name = plat->port_name; + uc_priv->gpio_count = VYBRID_GPIO_COUNT; + gpios->reg = (struct vybrid_gpio_regs *)plat->base; + gpios->chip = plat->chip; + + return 0; +} + +static int vybrid_gpio_bind(struct udevice *dev) +{ + struct vybrid_gpio_platdata *plat = dev->platdata; + fdt_addr_t base_addr; + + if (plat) + return 0; + + base_addr = dev_get_addr(dev); + if (base_addr == FDT_ADDR_T_NONE) + return -ENODEV; + + /* + * TODO: + * When every board is converted to driver model and DT is + * supported, this can be done by auto-alloc feature, but + * not using calloc to alloc memory for platdata. + */ + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + + plat->base = base_addr; + plat->chip = dev->req_seq; + plat->port_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL); + dev->platdata = plat; + + return 0; +} + +#ifndef CONFIG_OF_CONTROL +static const struct vybrid_gpio_platdata vybrid_gpio[] = { + {0, GPIO0_BASE_ADDR, "GPIO0 "}, + {1, GPIO1_BASE_ADDR, "GPIO1 "}, + {2, GPIO2_BASE_ADDR, "GPIO2 "}, + {3, GPIO3_BASE_ADDR, "GPIO3 "}, + {4, GPIO4_BASE_ADDR, "GPIO4 "}, +}; + +U_BOOT_DEVICES(vybrid_gpio) = { + { "gpio_vybrid", &vybrid_gpio[0] }, + { "gpio_vybrid", &vybrid_gpio[1] }, + { "gpio_vybrid", &vybrid_gpio[2] }, + { "gpio_vybrid", &vybrid_gpio[3] }, + { "gpio_vybrid", &vybrid_gpio[4] }, +}; +#endif + +static const struct udevice_id vybrid_gpio_ids[] = { + { .compatible = "fsl,vf610-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_vybrid) = { + .name = "gpio_vybrid", + .id = UCLASS_GPIO, + .ops = &gpio_vybrid_ops, + .probe = vybrid_gpio_probe, + .priv_auto_alloc_size = sizeof(struct vybrid_gpios), + .of_match = vybrid_gpio_ids, + .bind = vybrid_gpio_bind, +}; -- cgit v1.1 From a7b1808ee3e87608bf740f845b6de6ebb550a339 Mon Sep 17 00:00:00 2001 From: Bhuvanchandra DV Date: Mon, 1 Jun 2015 18:37:17 +0530 Subject: colibri_vf: Add pinmux entries for GPIOs Inorder to use the pins as GPIO, apart from setting the alt-function, pinmuxing need to be done, this patch adds pinmux entries of few GPIOs. Acked-by: Stefan Agner Signed-off-by: Bhuvanchandra DV --- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 49 ++++++++++++++++++++++ board/toradex/colibri_vf/colibri_vf.c | 60 +++++++++++++++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 9226e69..e22e3f9 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -32,22 +32,56 @@ #define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \ PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE) +#define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE) + enum { VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTA7__GPIO_134 = IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA17__GPIO_7 = IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA20__GPIO_10 = IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA21__GPIO_11 = IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA30__GPIO_20 = IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA31__GPIO_21 = IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB0__GPIO_22 = IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB1__GPIO_23 = IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB6__GPIO_28 = IOMUX_PAD(0x0070, 0x0070, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB7__GPIO_29 = IOMUX_PAD(0x0074, 0x0074, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB8__GPIO_30 = IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB9__GPIO_31 = IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB12__GPIO_34 = IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB13__GPIO_35 = IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB16__GPIO_38 = IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB17__GPIO_39 = IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB18__GPIO_40 = IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB21__GPIO_43 = IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB22__GPIO_44 = IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB23__GPIO_93 = IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB26__GPIO_96 = IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB28__GPIO_98 = IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC1__GPIO_46 = IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC0__GPIO_45 = IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC2__GPIO_47 = IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC3__GPIO_48 = IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC4__GPIO_49 = IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC5__GPIO_50 = IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC6__GPIO_51 = IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC7__GPIO_52 = IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC8__GPIO_53 = IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), @@ -57,6 +91,8 @@ enum { VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC29__GPIO_102 = IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC30__GPIO_103 = IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), @@ -66,13 +102,21 @@ enum { VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), VF610_PAD_PTD31__NF_IO15 = IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD31__GPIO_63 = IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD30__NF_IO14 = IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD30__GPIO_64 = IOMUX_PAD(0x0100, 0x0100, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD29__NF_IO13 = IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD29__GPIO_65 = IOMUX_PAD(0x0104, 0x0104, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD28__NF_IO12 = IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD28__GPIO_66 = IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD27__NF_IO11 = IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD27__GPIO_67 = IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD26__NF_IO10 = IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD26__GPIO_68 = IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD25__NF_IO9 = IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD25__GPIO_69 = IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD24__NF_IO8 = IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD24__GPIO_70 = IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), @@ -83,9 +127,14 @@ enum { VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD9__GPIO_88 = IOMUX_PAD(0x0160, 0x0160, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD10__GPIO_89 = IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD11__GPIO_90 = IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD12__GPIO_91 = IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD13__GPIO_92 = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 31ebb19..e354c6d 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -146,6 +146,62 @@ static void setup_iomux_nfc(void) } #endif +#ifdef CONFIG_VYBRID_GPIO +static void setup_iomux_gpio(void) +{ + static const iomux_v3_cfg_t gpio_pads[] = { + VF610_PAD_PTA17__GPIO_7, + VF610_PAD_PTA20__GPIO_10, + VF610_PAD_PTA21__GPIO_11, + VF610_PAD_PTA30__GPIO_20, + VF610_PAD_PTA31__GPIO_21, + VF610_PAD_PTB0__GPIO_22, + VF610_PAD_PTB1__GPIO_23, + VF610_PAD_PTB6__GPIO_28, + VF610_PAD_PTB7__GPIO_29, + VF610_PAD_PTB8__GPIO_30, + VF610_PAD_PTB9__GPIO_31, + VF610_PAD_PTB12__GPIO_34, + VF610_PAD_PTB13__GPIO_35, + VF610_PAD_PTB16__GPIO_38, + VF610_PAD_PTB17__GPIO_39, + VF610_PAD_PTB18__GPIO_40, + VF610_PAD_PTB21__GPIO_43, + VF610_PAD_PTB22__GPIO_44, + VF610_PAD_PTC0__GPIO_45, + VF610_PAD_PTC1__GPIO_46, + VF610_PAD_PTC2__GPIO_47, + VF610_PAD_PTC3__GPIO_48, + VF610_PAD_PTC4__GPIO_49, + VF610_PAD_PTC5__GPIO_50, + VF610_PAD_PTC6__GPIO_51, + VF610_PAD_PTC7__GPIO_52, + VF610_PAD_PTC8__GPIO_53, + VF610_PAD_PTD31__GPIO_63, + VF610_PAD_PTD30__GPIO_64, + VF610_PAD_PTD29__GPIO_65, + VF610_PAD_PTD28__GPIO_66, + VF610_PAD_PTD27__GPIO_67, + VF610_PAD_PTD26__GPIO_68, + VF610_PAD_PTD25__GPIO_69, + VF610_PAD_PTD24__GPIO_70, + VF610_PAD_PTD9__GPIO_88, + VF610_PAD_PTD10__GPIO_89, + VF610_PAD_PTD11__GPIO_90, + VF610_PAD_PTD12__GPIO_91, + VF610_PAD_PTD13__GPIO_92, + VF610_PAD_PTB23__GPIO_93, + VF610_PAD_PTB26__GPIO_96, + VF610_PAD_PTB28__GPIO_98, + VF610_PAD_PTC29__GPIO_102, + VF610_PAD_PTC30__GPIO_103, + VF610_PAD_PTA7__GPIO_134, + }; + + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); +} +#endif + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[1] = { {ESDHC1_BASE_ADDR}, @@ -304,6 +360,10 @@ int board_early_init_f(void) setup_iomux_nfc(); #endif +#ifdef CONFIG_VYBRID_GPIO + setup_iomux_gpio(); +#endif + return 0; } -- cgit v1.1 From 30748d81d0b33f04c86b5b96aab2e8bf8d330ea2 Mon Sep 17 00:00:00 2001 From: Bhuvanchandra DV Date: Mon, 1 Jun 2015 18:37:18 +0530 Subject: colibri_vf: Enable GPIO support Acked-by: Stefan Agner Signed-off-by: Bhuvanchandra DV --- configs/colibri_vf_defconfig | 1 + include/configs/colibri_vf.h | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 3b1f66a..0715267 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -3,3 +3,4 @@ CONFIG_TARGET_COLIBRI_VF=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" CONFIG_NAND_VF610_NFC=y CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y +CONFIG_DM=y diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 804291d..195102b 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -54,6 +54,11 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR +/* GPIO support */ +#define CONFIG_DM_GPIO +#define CONFIG_CMD_GPIO +#define CONFIG_VYBRID_GPIO + /* Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */ #define CONFIG_MTD_PARTITIONS -- cgit v1.1 From 098d85840ebd72c87a547a87df2654a3ff7da725 Mon Sep 17 00:00:00 2001 From: Bhuvanchandra DV Date: Mon, 1 Jun 2015 18:37:19 +0530 Subject: arm: vf610: Add clock support for DSPI Signed-off-by: Bhuvanchandra DV --- arch/arm/cpu/armv7/vf610/generic.c | 7 +++++++ arch/arm/include/asm/arch-vf610/clock.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 1bb9b8e..05c401d 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -198,6 +198,11 @@ static u32 get_i2c_clk(void) return get_ipg_clk(); } +static u32 get_dspi_clk(void) +{ + return get_ipg_clk(); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { @@ -215,6 +220,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_fec_clk(); case MXC_I2C_CLK: return get_i2c_clk(); + case MXC_DSPI_CLK: + return get_dspi_clk(); default: break; } diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h index 535adad..e5a5c6d 100644 --- a/arch/arm/include/asm/arch-vf610/clock.h +++ b/arch/arm/include/asm/arch-vf610/clock.h @@ -17,6 +17,7 @@ enum mxc_clock { MXC_ESDHC_CLK, MXC_FEC_CLK, MXC_I2C_CLK, + MXC_DSPI_CLK, }; void enable_ocotp_clk(unsigned char enable); diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index bc6db2a..fdb45e9 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -189,6 +189,8 @@ struct anadig_reg { #define CCM_REG_CTRL_MASK 0xffffffff #define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) +#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26) #define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) @@ -206,6 +208,8 @@ struct anadig_reg { #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) #define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12) #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) +#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24) +#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26) #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) #define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8) -- cgit v1.1 From 508f412125c417623880b98fa860471c7000fbca Mon Sep 17 00:00:00 2001 From: Bhuvanchandra DV Date: Mon, 1 Jun 2015 18:37:20 +0530 Subject: arm: vf610: Add iomux support for DSPI Add iomux definitions for DSPI second instance. Signed-off-by: Bhuvanchandra DV --- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 9 +++++++++ board/toradex/colibri_vf/colibri_vf.c | 21 +++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index e22e3f9..b8b22b1 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -35,6 +35,11 @@ #define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \ PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE) +#define VF610_DSPI_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) +#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) + enum { VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), @@ -91,6 +96,10 @@ enum { VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTD5__DSPI1_CS0 = IOMUX_PAD(0x0150, 0x0150, 3, 0x300, 1, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTD6__DSPI1_SIN = IOMUX_PAD(0x0154, 0x0154, 3, 0x2fc, 1, VF610_DSPI_SIN_PAD_CTRL), + VF610_PAD_PTD7__DSPI1_SOUT = IOMUX_PAD(0x0158, 0x0158, 3, __NA_, 0, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTD8__DSPI1_SCK = IOMUX_PAD(0x015c, 0x015c, 3, 0x2f8, 1, VF610_DSPI_PAD_CTRL), VF610_PAD_PTC29__GPIO_102 = IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC30__GPIO_103 = IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index e354c6d..7173022 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -146,6 +146,20 @@ static void setup_iomux_nfc(void) } #endif +#ifdef CONFIG_FSL_DSPI +static void setup_iomux_dspi(void) +{ + static const iomux_v3_cfg_t dspi1_pads[] = { + VF610_PAD_PTD5__DSPI1_CS0, + VF610_PAD_PTD6__DSPI1_SIN, + VF610_PAD_PTD7__DSPI1_SOUT, + VF610_PAD_PTD8__DSPI1_SCK, + }; + + imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads)); +} +#endif + #ifdef CONFIG_VYBRID_GPIO static void setup_iomux_gpio(void) { @@ -252,6 +266,9 @@ static void clock_init(void) clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, CCM_CCGR0_UART0_CTRL_MASK); +#ifdef CONFIG_FSL_DSPI + setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK); +#endif clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, @@ -364,6 +381,10 @@ int board_early_init_f(void) setup_iomux_gpio(); #endif +#ifdef CONFIG_FSL_DSPI + setup_iomux_dspi(); +#endif + return 0; } -- cgit v1.1 From d470030680005d65d624eecd51f5ffe03019de65 Mon Sep 17 00:00:00 2001 From: Bhuvanchandra DV Date: Mon, 1 Jun 2015 18:37:21 +0530 Subject: vf610: dts: Add device tree support Add device tree files for Freescale Vybrid platform and Toradex Colibri VF50, VF61 modules. Device tree files are taken from upstream Kernel. Removed the stuff which are not used/supported yet in U-Boot. Signed-off-by: Bhuvanchandra DV --- arch/arm/dts/Makefile | 3 ++ arch/arm/dts/vf-colibri.dtsi | 21 +++++++++ arch/arm/dts/vf.dtsi | 100 +++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/vf500-colibri.dts | 18 ++++++++ arch/arm/dts/vf610-colibri.dts | 18 ++++++++ 5 files changed, 160 insertions(+) create mode 100644 arch/arm/dts/vf-colibri.dtsi create mode 100644 arch/arm/dts/vf.dtsi create mode 100644 arch/arm/dts/vf500-colibri.dts create mode 100644 arch/arm/dts/vf610-colibri.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 267fd17..55039df 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -130,6 +130,9 @@ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ + vf610-colibri.dtb + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi new file mode 100644 index 0000000..7a8e9bee --- /dev/null +++ b/arch/arm/dts/vf-colibri.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include "vf.dtsi" + +&dspi1 { + status = "okay"; + bus-num = <1>; + + spi_cmd: sspi@0 { + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi new file mode 100644 index 0000000..78706e1 --- /dev/null +++ b/arch/arm/dts/vf.dtsi @@ -0,0 +1,100 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +/include/ "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + spi0 = &dspi0; + spi1 = &dspi1; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aips0: aips-bus@40000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dspi0: dspi0@4002c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x4002c000 0x1000>; + num-cs = <5>; + status = "disabled"; + }; + + dspi1: dspi1@4002d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x4002d000 0x1000>; + num-cs = <5>; + status = "disabled"; + }; + + qspi0: quadspi@40044000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-qspi"; + reg = <0x40044000 0x1000>; + status = "disabled"; + }; + + gpio0: gpio@40049000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff000 0x40>; + #gpio-cells = <2>; + }; + + gpio1: gpio@4004a000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff040 0x40>; + #gpio-cells = <2>; + }; + + gpio2: gpio@4004b000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff080 0x40>; + #gpio-cells = <2>; + }; + + gpio3: gpio@4004c000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff0c0 0x40>; + #gpio-cells = <2>; + }; + + gpio4: gpio@4004d000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff100 0x40>; + #gpio-cells = <2>; + }; + }; + + aips1: aips-bus@40080000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + }; +}; diff --git a/arch/arm/dts/vf500-colibri.dts b/arch/arm/dts/vf500-colibri.dts new file mode 100644 index 0000000..e383306 --- /dev/null +++ b/arch/arm/dts/vf500-colibri.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF50"; + compatible = "toradex,vf500-colibri_vf50", "toradex,vf500-colibri_vf50", "fsl,vf500"; +}; diff --git a/arch/arm/dts/vf610-colibri.dts b/arch/arm/dts/vf610-colibri.dts new file mode 100644 index 0000000..63bb3f4 --- /dev/null +++ b/arch/arm/dts/vf610-colibri.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF61"; + compatible = "toradex,vf610-colibri_vf61", "toradex,vf610-colibri_vf61", "fsl,vf610"; +}; -- cgit v1.1 From 98e3fd3ddfac658be7c63256c8c6a9a9db2f23bf Mon Sep 17 00:00:00 2001 From: Bhuvanchandra DV Date: Mon, 1 Jun 2015 18:37:22 +0530 Subject: colibri-vf: Enable SPI support Signed-off-by: Bhuvanchandra DV Acked-by: Stefan Agner --- include/configs/colibri_vf.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 195102b..56e6d97 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -272,4 +272,11 @@ #define CONFIG_USB_GADGET_MASS_STORAGE #define CONFIG_CMD_USB_MASS_STORAGE +/* Enable SPI support */ +#ifdef CONFIG_OF_CONTROL +#define CONFIG_DM_SPI +#define CONFIG_CMD_SPI +#define CONFIG_FSL_DSPI +#endif + #endif /* __CONFIG_H */ -- cgit v1.1 From dde8c15b133b364c413bb95e3d89445b2427908b Mon Sep 17 00:00:00 2001 From: Bhuvanchandra DV Date: Mon, 1 Jun 2015 18:37:23 +0530 Subject: colibri_vf: Add separate defconfig for device tree support Most of the drivers available for Vybrid are not yet converted to OF model to use device tree model, only few drivers like SPI and GPIO drivers use device trees. Add separate defconfig for who needs to use device tree model. Later this can be integrated to single defconfig. Acked-by: Stefan Agner Signed-off-by: Bhuvanchandra DV --- board/toradex/colibri_vf/MAINTAINERS | 4 ++++ configs/colibri_vf_dtb_defconfig | 8 ++++++++ 2 files changed, 12 insertions(+) create mode 100644 configs/colibri_vf_dtb_defconfig diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index 551c575..a1217a4 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -4,3 +4,7 @@ S: Maintained F: board/toradex/colibri_vf/ F: include/configs/colibri_vf.h F: configs/colibri_vf_defconfig +F: configs/colibri_vf_dtb_defconfig +F: arch/arm/dts/vf-colibri.dtsi +F: arch/arm/dts/vf500-colibri.dts +F: arch/arm/dts/vf610-colibri.dts diff --git a/configs/colibri_vf_dtb_defconfig b/configs/colibri_vf_dtb_defconfig new file mode 100644 index 0000000..d4c8c58 --- /dev/null +++ b/configs/colibri_vf_dtb_defconfig @@ -0,0 +1,8 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_VF=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri" -- cgit v1.1 From 60ed286453c8c14facdbeb3807c6d03596fc3ce9 Mon Sep 17 00:00:00 2001 From: Sanchayan Maity Date: Mon, 1 Jun 2015 18:37:24 +0530 Subject: usb: ehci-vf: Add weak function for board specific initialisation Add a weak function board_ehci_hcd_init which can be used by the board file for board specific initialisation. Signed-off-by: Sanchayan Maity --- drivers/usb/host/ehci-vf.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 5454855..98e0fc6 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -121,6 +121,11 @@ static void usb_oc_config(int index) setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); } +int __weak board_ehci_hcd_init(int port) +{ + return 0; +} + int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { @@ -136,6 +141,9 @@ int ehci_hcd_init(int index, enum usb_init_type init, ehci = (struct usb_ehci *)nc_reg_bases[index]; + /* Do board specific initialisation */ + board_ehci_hcd_init(index); + usb_power_config(index); usb_oc_config(index); usb_internal_phy_clock_gate(index); -- cgit v1.1 From 09cfa8ee6aa5c2a126da402af85fbfdcbf9cce06 Mon Sep 17 00:00:00 2001 From: Sanchayan Maity Date: Mon, 1 Jun 2015 18:37:25 +0530 Subject: colibri_vf: Enable board specific USB initialisation for USB pen gpio Add IOMUX for the pad used as USB pen. This needs to be driven low for the Iris and Viola boards where it is pulled up high by default. This is required for the USB host functionality to work on these boards. Use the board specific weak initialisation function, to drive the pin low which would be called on "usb start". Signed-off-by: Sanchayan Maity --- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 1 + board/toradex/colibri_vf/colibri_vf.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index b8b22b1..019307b 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -131,6 +131,7 @@ enum { VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 7173022..8618fd0 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -20,6 +20,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -32,6 +33,12 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) +#define USB_PEN_GPIO 83 + +static const iomux_v3_cfg_t usb_pads[] = { + VF610_PAD_PTD4__GPIO_83, +}; + int dram_init(void) { static const struct ddr3_jedec_timings timings = { @@ -464,3 +471,21 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) return 0; } + +#ifdef CONFIG_USB_EHCI_VF +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + switch (port) { + case 0: + /* USBC does not have PEN, also configured as USB client only */ + break; + case 1: + gpio_request(USB_PEN_GPIO, "usb-pen-gpio"); + gpio_direction_output(USB_PEN_GPIO, 0); + break; + } + return 0; +} +#endif -- cgit v1.1 From cefe06bf84c3093c875f19490841ff12e0939bda Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Wed, 3 Jun 2015 11:33:22 +0200 Subject: ot1200: setup i2c bus in board_early_init_f(..) Make it possible to use the i2c bus in SPL. Signed-off-by: Christian Gmeiner --- board/bachmann/ot1200/ot1200.c | 40 ++++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index e434ed9..a33d496 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -120,6 +120,27 @@ static void setup_iomux_features(void) ARRAY_SIZE(feature_pads)); } +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C3 - IO expander */ +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +static void setup_iomux_i2c(void) +{ + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +} + static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -151,6 +172,7 @@ int board_early_init_f(void) setup_iomux_uart(); setup_iomux_spi(); + setup_iomux_i2c(); setup_iomux_features(); return 0; @@ -236,22 +258,6 @@ int board_mmc_init(bd_t *bis) return 0; } -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -/* I2C3 - IO expander */ -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, - .gp = IMX_GPIO_NR(3, 17) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; - static iomux_v3_cfg_t const pwm_pad[] = { MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM), }; @@ -315,8 +321,6 @@ int board_init(void) backlight_lcd_off(); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - leds_on(); #ifdef CONFIG_CMD_SATA -- cgit v1.1 From 130e6c8cbd9c255da218e9fa1a136c065808aa93 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Wed, 3 Jun 2015 11:33:23 +0200 Subject: ot1200: setup i2c bus 1 in setup_iomux_i2c() On this bus there is a EEPROM containing EDID and ddr3 calibration information. Signed-off-by: Christian Gmeiner --- board/bachmann/ot1200/ot1200.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index a33d496..2237b7a 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -122,6 +122,20 @@ static void setup_iomux_features(void) #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C2 - EEPROM */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, + .gp = IMX_GPIO_NR(2, 30) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, + .gp = IMX_GPIO_NR(3, 16) + } +}; + /* I2C3 - IO expander */ static struct i2c_pads_info i2c_pad_info2 = { .scl = { @@ -138,6 +152,7 @@ static struct i2c_pads_info i2c_pad_info2 = { static void setup_iomux_i2c(void) { + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); } -- cgit v1.1 From 943a3f2ccb71bcb4a6041bc2946129c4d4bb197e Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 26 May 2015 19:53:41 +0200 Subject: imx: drop warning: unused variable 'max_freq' max_freq in print_cpuinfo is used only with imx6. Signed-off-by: Stefano Babic --- arch/arm/imx-common/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 275befd..5e56cfe 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -145,7 +145,8 @@ const char *get_imx_type(u32 imxtype) int print_cpuinfo(void) { - u32 cpurev, max_freq; + u32 cpurev; + __maybe_unused u32 max_freq; #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL) struct udevice *thermal_dev; -- cgit v1.1