From 9147ce15c07a766c134b407a0bcdcb4955a1fa6f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 9 Nov 2010 23:19:27 -0600 Subject: powerpc/8xxx: Fix merge issue with P2020DS DDR2 build config When P2020DS DDR2 was merged it was merged incorrectly and propogated to boards.cfg. Fix this by moving DDR2 config to be associated with P2020DS and not P1_P2_RDB. Signed-off-by: Kumar Gala --- boards.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards.cfg b/boards.cfg index 6c2a667..08e531e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -569,6 +569,7 @@ MPC8540EVAL powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M MPC8540EVAL_33 powerpc mpc85xx mpc8540eval - - MPC8540EVAL MPC8540EVAL_66 powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT +P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2 MPC8536DS powerpc mpc85xx mpc8536ds freescale - MPC8536DS MPC8536DS_36BIT powerpc mpc85xx mpc8536ds freescale - MPC8536DS:36BIT MPC8536DS_NAND powerpc mpc85xx mpc8536ds freescale - MPC8536DS:NAND @@ -589,7 +590,6 @@ P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010 P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,NAND P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,SDCARD -P2020DS_DDR2 powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,DDR2 P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020 P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,NAND P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SDCARD -- cgit v1.1 From 16855ec139c24877d6474cda8820ac41a0ea85b0 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 9 Nov 2010 23:19:50 -0600 Subject: powerpc/8xxx: Enable e1000 driver on some FSL boards Signed-off-by: Kumar Gala --- include/configs/MPC8569MDS.h | 1 + include/configs/MPC8572DS.h | 1 + include/configs/P1022DS.h | 1 + 3 files changed, 3 insertions(+) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 6a15da5..b2d372e 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -488,6 +488,7 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_EEPRO100 #undef CONFIG_TULIP +#define CONFIG_E1000 /* Define e1000 pci Ethernet card */ #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index f949cc2..692c811 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -474,6 +474,7 @@ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP #undef CONFIG_RTL8139 +#define CONFIG_E1000 /* Define e1000 pci Ethernet card */ #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 6c8579f..b411fc8 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -270,6 +270,7 @@ #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_E1000 /* Define e1000 pci Ethernet card */ #endif /* SATA */ -- cgit v1.1 From 36ae6a8e70ed05c267d4db7224c4ff45146b808e Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 10 Nov 2010 14:32:36 -0500 Subject: powerpc/85xx: Fix lds for nand build Fix u-boot-nand.lds and u-boot-nand_spl.lds according to: Author: Peter Tyser Date: Wed Sep 29 14:05:56 2010 -0500 commit fbe53f59bd40b3b1ab66dc98859e26589d64d1b7 85xx: Use gc-sections to reduce image size Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 49 +++++----------------------- arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds | 12 +++---- 2 files changed, 15 insertions(+), 46 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index 5fd3e6c..fa2088b 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -34,42 +34,16 @@ SECTIONS /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } .text : { - *(.text) - *(.got1) + *(.text*) } :text _etext = .; PROVIDE (etext = .); .rodata : { - *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } :text - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } /* Read-write section, merged into data segment: */ . = (. + 0x00FF) & 0xFFFFFF00; @@ -77,23 +51,19 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - *(.got) + KEEP(*(.got)) _GOT2_TABLE_ = .; - *(.got2) + KEEP(*(.got2)) _FIXUP_TABLE_ = .; - *(.fixup) + KEEP(*(.fixup)) } __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS + *(.data*) + *(.sdata*) } _edata = .; PROVIDE (edata = .); @@ -117,7 +87,7 @@ SECTIONS .bootpg ADDR(.text) - 0x1000 : { - arch/powerpc/cpu/mpc85xx/start.o (.bootpg) + arch/powerpc/cpu/mpc85xx/start.o KEEP(*(.bootpg)) } :text = 0xffff . = ADDR(.text) + 0x80000; @@ -125,9 +95,8 @@ SECTIONS __bss_start = .; .bss (NOLOAD) : { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) + *(.sbss*) + *(.bss*) *(COMMON) } :bss diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index 7d9cee9..b10e0f9 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -28,15 +28,15 @@ SECTIONS { . = 0xfff00000; .text : { - *(.text) + *(.text*) } _etext = .; .reloc : { _GOT2_TABLE_ = .; - *(.got2) + KEEP(*(.got2)) _FIXUP_TABLE_ = .; - *(.fixup) + KEEP(*(.fixup)) } __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; @@ -54,13 +54,13 @@ SECTIONS __init_end = .; .resetvec ADDR(.text) + 0xffc : { - *(.resetvec) + KEEP(*(.resetvec)) } = 0xffff __bss_start = .; .bss : { - *(.sbss) - *(.bss) + *(.sbss*) + *(.bss*) } _end = .; } -- cgit v1.1 From 0635b09cc04b4d0f5bd6fbdf8380d6a564445b87 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 10 Nov 2010 15:37:13 -0500 Subject: powerpc/85xx: rename CONFIG_SYS_TEXT_BASE to CONFIG_SYS_MONITOR_BASE Use CONFIG_SYS_MONITOR_BASE instead of CONFIG_SYS_TEXT_BASE in early init code so we can share the same code with NAND or NOR boot and not have additional ifdefs in here. Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/start.S | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 291557d..af7e39b 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -146,7 +146,7 @@ _start_e500: beq 2b /* Setup interrupt vectors */ - lis r1,CONFIG_SYS_TEXT_BASE@h + lis r1,CONFIG_SYS_MONITOR_BASE@h mtspr IVPR,r1 li r1,0x0100 @@ -292,25 +292,25 @@ _start_e500: lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l #else /* - * create a temp mapping in AS=1 to the 1M CONFIG_SYS_TEXT_BASE space, the main - * image has been relocated to CONFIG_SYS_TEXT_BASE on the second stage. + * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main + * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. */ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@l + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l #endif mtspr MAS0,r6 -- cgit v1.1 From 96196a1f7546904563994d2d041804a816d7c139 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 10 Nov 2010 15:37:13 -0500 Subject: powerpc/85xx: add CONFIG_SYS_TEXT_BASE_SPL for 85xx nand spl build Introduce a SPL specific CONFIG_SYS_TEXT_BASE_SPL define to be used by the linker. This has similiar semantics to CONFIG_SYS_TEXT_BASE however since SPL is a unqiue image we introduce a new variable to control its text base address. Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala --- include/configs/MPC8536DS.h | 11 +++++++++-- include/configs/MPC8569MDS.h | 11 +++++++++-- include/configs/P1_P2_RDB.h | 13 ++++++++++--- nand_spl/board/freescale/mpc8536ds/Makefile | 4 ++-- nand_spl/board/freescale/mpc8569mds/Makefile | 4 ++-- nand_spl/board/freescale/p1_p2_rdb/Makefile | 4 ++-- 6 files changed, 34 insertions(+), 13 deletions(-) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 8410bb7..850665a 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -36,7 +36,12 @@ #ifdef CONFIG_NAND #define CONFIG_NAND_U_BOOT 1 #define CONFIG_RAMBOOT_NAND 1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#endif /* CONFIG_NAND_SPL */ #endif #ifdef CONFIG_SDCARD @@ -53,6 +58,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -233,8 +242,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index b2d372e..c7973b4 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -65,13 +65,22 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_NAND #define CONFIG_NAND_U_BOOT 1 #define CONFIG_RAMBOOT_NAND 1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif +#endif #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 #endif +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + /* * Only possible on E500 Version 2 or newer cores. */ @@ -194,8 +203,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) #define CONFIG_SYS_RAMBOOT #else diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index b99f383..08c5ef9 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -46,7 +46,12 @@ #ifdef CONFIG_NAND #define CONFIG_NAND_U_BOOT 1 #define CONFIG_RAMBOOT_NAND 1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#endif /* CONFIG_NAND_SPL */ #endif #ifdef CONFIG_SDCARD @@ -63,6 +68,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -192,8 +201,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile index d1c0ef8..9c9d63e 100644 --- a/nand_spl/board/freescale/mpc8536ds/Makefile +++ b/nand_spl/board/freescale/mpc8536ds/Makefile @@ -24,13 +24,13 @@ # NAND_SPL := y -CONFIG_SYS_TEXT_BASE := 0xfff00000 +CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 PAD_TO := 0xfff01000 include $(TOPDIR)/config.mk LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS) AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile index d1c0ef8..9c9d63e 100644 --- a/nand_spl/board/freescale/mpc8569mds/Makefile +++ b/nand_spl/board/freescale/mpc8569mds/Makefile @@ -24,13 +24,13 @@ # NAND_SPL := y -CONFIG_SYS_TEXT_BASE := 0xfff00000 +CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 PAD_TO := 0xfff01000 include $(TOPDIR)/config.mk LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS) AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile index d1c0ef8..9c9d63e 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile @@ -24,13 +24,13 @@ # NAND_SPL := y -CONFIG_SYS_TEXT_BASE := 0xfff00000 +CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 PAD_TO := 0xfff01000 include $(TOPDIR)/config.mk LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS) AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL -- cgit v1.1 From 39c2a6eb75fabd9745c5762c8dec9d1a85dabf00 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 25 Oct 2010 14:52:53 +0530 Subject: p1_p2_rdb: to set SQW/INT pin of RTC as INT line SQW/INT pin in RTC can be used for generating square wave(by default) or as interrupt line. U-boot is registering this pin for interrupts. Configuring SQW/INT bit as interrupt line during board initialization to avoid spurious interrupts generated by square wave. Signed-off-by: Priyanka Jain Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/p1_p2_rdb.c | 4 +++- include/configs/P1_P2_RDB.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index fae31f2..1c4c020 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -33,6 +33,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -156,6 +157,7 @@ int board_early_init_r(void) set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_16M, 1); + rtc_reset(); return 0; } diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 08c5ef9..610f3ed 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -350,6 +350,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_EEPROM_BUS_NUM 1 #define CONFIG_RTC_DS1337 +#define CONFIG_SYS_RTC_DS1337_NOOSC #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* * General PCI -- cgit v1.1 From 4f55d51250c5af3069385851b37ce4273f10af04 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 10 Nov 2010 08:40:41 -0600 Subject: powerpc/corenet_ds: Enable DHCP suport Signed-off-by: Kumar Gala --- include/configs/corenet_ds.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 2ac59e5..5b36a56 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -475,6 +475,7 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_DHCP #ifdef CONFIG_PCI #define CONFIG_CMD_PCI -- cgit v1.1 From ed1791524f3b40abd7427ff90db2296d45ec6dfb Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 20 Oct 2010 16:02:41 -0500 Subject: powerpc/corenet_ds: Move CONFIG_SYS_TEXT_BASE into corenet_ds.h CONFIG_SYS_TEXT_BASE setting is common across the 'corenet_ds' board family so move it out of P4080DS.h and into corenet_ds.h Signed-off-by: Kumar Gala --- include/configs/P4080DS.h | 4 ---- include/configs/corenet_ds.h | 4 ++++ 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 5e7b81f..87703c9 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -36,8 +36,4 @@ #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 -#endif - #include "corenet_ds.h" diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 5b36a56..c5dcdca 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -37,6 +37,10 @@ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ -- cgit v1.1 From 0ce8437f3006f86d093f83120c64f657bbac3c31 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 30 Sep 2010 15:47:16 -0500 Subject: powerpc/p4080ds: Move ICS refclk define into P4080DS.h We appear to have different refclk's on the different corenet DS boards so move the define out of the common header. Signed-off-by: Kumar Gala --- include/configs/P4080DS.h | 2 ++ include/configs/corenet_ds.h | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 87703c9..21b48e9 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -33,6 +33,8 @@ #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ + #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c5dcdca..454a30a 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -68,7 +68,6 @@ #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ /* * These can be toggled for performance analysis, otherwise use default. -- cgit v1.1 From 46299078e6b99f6252a4328a12fa0b3305d04b5e Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 5 Mar 2010 21:29:26 +0000 Subject: powerpc/corenet_ds: display the RCW at boot Display the 64-byte Reset Configuration Word (RCW) during boot, so that there's no confusion as to what RCW U-boot is using. Reset Configuration Word (RCW): 00000000: 4a500000 00000000 18181818 00008888 00000010: 28402400 00002000 fe800000 01200000 00000020: 00000000 00000000 00000000 000b0000 00000030: 00000000 00000000 00000000 00000000 Signed-off-by: Timur Tabi Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- board/freescale/corenet_ds/corenet_ds.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 68c63ac..f183cf6 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -45,6 +45,8 @@ int checkboard (void) { u8 sw; struct cpu_type *cpu = gd->cpu; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + unsigned int i; printf("Board: %sDS, ", cpu->name); printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", @@ -66,6 +68,19 @@ int checkboard (void) puts("36-bit Addressing\n"); #endif + /* Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + /* Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could * technically be set to force the reference clocks to match the -- cgit v1.1 From b1b7646493f1ccb42f0d78ad210116205e679986 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Thu, 11 Nov 2010 11:33:05 -0600 Subject: TQM85xx: Fix bug introduced by 83xx/85xx/86xx: LBC register cleanup The size of the other bank needed to be added to the br0 setting; this got dropped in the LBC cleanup. Signed-off-by: Becky Bruce Tested-by: Wolfgang Denk Acked-by: Wolfgang Denk Signed-off-by: Kumar Gala --- board/tqc/tqm85xx/tqm85xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 2c3885f..b21e791 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -298,7 +298,7 @@ int misc_init_r (void) */ set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) | (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); - set_lbc_br(0, gd->bd->bi_flashstart | + set_lbc_br(0, (gd->bd->bi_flashstart + flash_info[0].size) | (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); /* -- cgit v1.1