From 4329120dc09c03ca42118146f9ca5f863b48fb91 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 4 May 2016 15:00:05 +0800 Subject: MLK-12629-1: imx6: cache: disable L2 before touching Auxiliary Control Register According PL310 TRM, Auxiliary Control Register " The register must be written to using a secure access, and it can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR. " So If L2 cache is already enabled, chaning value of ACR will cause SLVERR, uboot hangs. In some cases, such as plugin, L2 Cache enabled bit is not cleared, then "Set bit 22 in the auxiliary control register" cause uboot hangs. Signed-off-by: Peng Fan --- arch/arm/imx-common/cache.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c index 02aced9..250b016 100644 --- a/arch/arm/imx-common/cache.c +++ b/arch/arm/imx-common/cache.c @@ -43,6 +43,12 @@ void v7_outer_cache_enable(void) /* + * Must disable the L2 before changing the latency parameters + * and auxiliary control register. + */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + /* * Set bit 22 in the auxiliary control register. If this bit * is cleared, PL310 treats Normal Shared Non-cacheable * accesses as Cacheable no-allocate. @@ -59,9 +65,6 @@ void v7_outer_cache_enable(void) } #endif - /* Must disable the L2 before changing the latency parameters */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - writel(0x132, &pl310->pl310_tag_latency_ctrl); writel(0x132, &pl310->pl310_data_latency_ctrl); -- cgit v1.1