From 3a13770bd01f785ce7e587c398c47436b6fa703f Mon Sep 17 00:00:00 2001 From: Terry Lv Date: Thu, 4 Nov 2010 22:20:06 +0800 Subject: ENGR00133124: Add nand support for mx50 rdp Add nand support for mx50 rdp. Signed-off-by: Terry Lv --- board/freescale/mx50_arm2/mx50_arm2.c | 4 +- board/freescale/mx50_rdp/mx50_rdp.c | 214 +++++++++++++++++++++++++++++++++- drivers/mtd/nand/gpmi_nfc_hal.c | 7 -- drivers/mtd/nand/gpmi_nfc_mil.c | 16 +-- include/configs/mx50_arm2.h | 5 +- include/configs/mx50_arm2_ddr2.h | 44 ++++++- include/configs/mx50_arm2_lpddr2.h | 17 +-- include/configs/mx50_rdp.h | 45 ++++++- 8 files changed, 309 insertions(+), 43 deletions(-) diff --git a/board/freescale/mx50_arm2/mx50_arm2.c b/board/freescale/mx50_arm2/mx50_arm2.c index 89b8b11..5b3a8e1 100644 --- a/board/freescale/mx50_arm2/mx50_arm2.c +++ b/board/freescale/mx50_arm2/mx50_arm2.c @@ -352,7 +352,7 @@ void spi_io_init(struct imx_spi_dev_t *dev) #endif #ifdef CONFIG_NAND_GPMI -void setup_gpmi_nand() +void setup_gpmi_nand(void) { u32 src_sbmr = readl(SRC_BASE_ADDR + 0x4); @@ -647,7 +647,7 @@ struct fsl_esdhc_cfg esdhc_cfg[3] = { #ifdef CONFIG_DYNAMIC_MMC_DEVNO -int get_mmc_env_devno() +int get_mmc_env_devno(void) { uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); int mmc_devno = 0; diff --git a/board/freescale/mx50_rdp/mx50_rdp.c b/board/freescale/mx50_rdp/mx50_rdp.c index 809f124..0235441 100644 --- a/board/freescale/mx50_rdp/mx50_rdp.c +++ b/board/freescale/mx50_rdp/mx50_rdp.c @@ -328,6 +328,210 @@ void spi_io_init(struct imx_spi_dev_t *dev) } #endif +#ifdef CONFIG_NAND_GPMI +void setup_gpmi_nand(void) +{ + u32 src_sbmr = readl(SRC_BASE_ADDR + 0x4); + + /* Fix for gpmi gatelevel issue */ + mxc_iomux_set_pad(MX50_PIN_SD3_CLK, 0x00e4); + + /* RESETN,WRN,RDN,DATA0~7 Signals iomux*/ + /* Check if 1.8v NAND is to be supported */ + if ((src_sbmr & 0x00000004) >> 2) + *(u32 *)(IOMUXC_BASE_ADDR + PAD_GRP_START + 0x58) = (0x1 << 13); + + /* RESETN */ + mxc_request_iomux(MX50_PIN_SD3_WP, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_SD3_WP, PAD_CTL_DRV_HIGH); + + /* WRN */ + mxc_request_iomux(MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_SD3_CMD, PAD_CTL_DRV_HIGH); + + /* RDN */ + mxc_request_iomux(MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_SD3_CLK, PAD_CTL_DRV_HIGH); + + /* D0 */ + mxc_request_iomux(MX50_PIN_SD3_D4, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_SD3_D4, PAD_CTL_DRV_HIGH); + + /* D1 */ + mxc_request_iomux(MX50_PIN_SD3_D5, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_SD3_D5, PAD_CTL_DRV_HIGH); + + /* D2 */ + mxc_request_iomux(MX50_PIN_SD3_D6, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_SD3_D6, PAD_CTL_DRV_HIGH); + + /* D3 */ + mxc_request_iomux(MX50_PIN_SD3_D7, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_SD3_D7, PAD_CTL_DRV_HIGH); + + /* D4 */ + mxc_request_iomux(MX50_PIN_SD3_D0, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_SD3_D0, PAD_CTL_DRV_HIGH); + + /* D5 */ + mxc_request_iomux(MX50_PIN_SD3_D1, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_SD3_D1, PAD_CTL_DRV_HIGH); + + /* D6 */ + mxc_request_iomux(MX50_PIN_SD3_D2, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_SD3_D2, PAD_CTL_DRV_HIGH); + + /* D7 */ + mxc_request_iomux(MX50_PIN_SD3_D3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_SD3_D3, PAD_CTL_DRV_HIGH); + + /*CE0~3,and other four controls signals muxed on KPP*/ + switch ((src_sbmr & 0x00000018) >> 3) { + case 0: + /* Muxed on key */ + if ((src_sbmr & 0x00000004) >> 2) + *(u32 *)(IOMUXC_BASE_ADDR + PAD_GRP_START + 0x20) = + (0x1 << 13); + + /* CLE */ + mxc_request_iomux(MX50_PIN_KEY_COL0, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_KEY_COL0, PAD_CTL_DRV_HIGH); + + /* ALE */ + mxc_request_iomux(MX50_PIN_KEY_ROW0, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_KEY_ROW0, PAD_CTL_DRV_HIGH); + + /* READY0 */ + mxc_request_iomux(MX50_PIN_KEY_COL3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_KEY_COL3, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU); + mxc_iomux_set_input( + MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + + /* DQS */ + mxc_request_iomux(MX50_PIN_KEY_ROW3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_KEY_ROW3, PAD_CTL_DRV_HIGH); + mxc_iomux_set_input( + MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + + /* CE0 */ + mxc_request_iomux(MX50_PIN_KEY_COL1, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_KEY_COL1, PAD_CTL_DRV_HIGH); + + /* CE1 */ + mxc_request_iomux(MX50_PIN_KEY_ROW1, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_KEY_ROW1, PAD_CTL_DRV_HIGH); + + /* CE2 */ + mxc_request_iomux(MX50_PIN_KEY_COL2, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_KEY_COL2, PAD_CTL_DRV_HIGH); + + /* CE3 */ + mxc_request_iomux(MX50_PIN_KEY_ROW2, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH); + + break; + case 1: + if ((src_sbmr & 0x00000004) >> 2) + *(u32 *)(IOMUXC_BASE_ADDR + PAD_GRP_START + 0xc) = + (0x1 << 13); + + /* CLE */ + mxc_request_iomux(MX50_PIN_EIM_DA8, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_EIM_DA8, PAD_CTL_DRV_HIGH); + + /* ALE */ + mxc_request_iomux(MX50_PIN_EIM_DA9, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_EIM_DA9, PAD_CTL_DRV_HIGH); + + /* READY0 */ + mxc_request_iomux(MX50_PIN_EIM_DA14, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_EIM_DA14, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU); + mxc_iomux_set_input( + MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT, + INPUT_CTL_PATH2); + + /* DQS */ + mxc_request_iomux(MX50_PIN_EIM_DA15, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_EIM_DA15, PAD_CTL_DRV_HIGH); + mxc_iomux_set_input( + MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT, + INPUT_CTL_PATH2); + + /* CE0 */ + mxc_request_iomux(MX50_PIN_EIM_DA10, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_EIM_DA10, PAD_CTL_DRV_HIGH); + + /* CE1 */ + mxc_request_iomux(MX50_PIN_EIM_DA11, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_EIM_DA11, PAD_CTL_DRV_HIGH); + + /* CE2 */ + mxc_request_iomux(MX50_PIN_EIM_DA12, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_EIM_DA12, PAD_CTL_DRV_HIGH); + + /* CE3 */ + mxc_request_iomux(MX50_PIN_EIM_DA13, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_EIM_DA13, PAD_CTL_DRV_HIGH); + + break; + case 2: + if ((src_sbmr & 0x00000004) >> 2) + *(u32 *)(IOMUXC_BASE_ADDR + PAD_GRP_START + 0x48) = + (0x1 << 13); + + /* CLE */ + mxc_request_iomux(MX50_PIN_DISP_D8, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D8, PAD_CTL_DRV_HIGH); + + /* ALE */ + mxc_request_iomux(MX50_PIN_DISP_D9, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D9, PAD_CTL_DRV_HIGH); + + /* READY0 */ + mxc_request_iomux(MX50_PIN_DISP_D14, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D14, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU); + mxc_iomux_set_input( + MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT, + INPUT_CTL_PATH1); + + /* DQS */ + mxc_request_iomux(MX50_PIN_DISP_D15, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D15, PAD_CTL_DRV_HIGH); + mxc_iomux_set_input( + MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT, + INPUT_CTL_PATH1); + + /* CE0 */ + mxc_request_iomux(MX50_PIN_DISP_D10, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D10, PAD_CTL_DRV_HIGH); + + /* CE1 */ + mxc_request_iomux(MX50_PIN_EIM_DA11, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_EIM_DA11, PAD_CTL_DRV_HIGH); + + /* CE2 */ + mxc_request_iomux(MX50_PIN_DISP_D12, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D12, PAD_CTL_DRV_HIGH); + + /* CE3 */ + mxc_request_iomux(MX50_PIN_DISP_D13, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX50_PIN_DISP_D13, PAD_CTL_DRV_HIGH); + + break; + default: + break; + } +} +#endif + #ifdef CONFIG_MXC_FEC #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM @@ -438,7 +642,7 @@ struct fsl_esdhc_cfg esdhc_cfg[3] = { #ifdef CONFIG_DYNAMIC_MMC_DEVNO -int get_mmc_env_devno() +int get_mmc_env_devno(void) { uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); int mmc_devno = 0; @@ -510,6 +714,7 @@ int esdhc_gpio_init(bd_t *bis) break; case 2: +#ifndef CONFIG_NAND_GPMI mxc_request_iomux(MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT0); mxc_request_iomux(MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT0); mxc_request_iomux(MX50_PIN_SD3_D0, IOMUX_CONFIG_ALT0); @@ -531,7 +736,7 @@ int esdhc_gpio_init(bd_t *bis) mxc_iomux_set_pad(MX50_PIN_SD3_D5, 0x1D4); mxc_iomux_set_pad(MX50_PIN_SD3_D6, 0x1D4); mxc_iomux_set_pad(MX50_PIN_SD3_D7, 0x1D4); - +#endif break; default: printf("Warning: you configured more ESDHC controller" @@ -561,7 +766,6 @@ static void setup_power(void) { struct spi_slave *slave; unsigned int val; - unsigned int reg; puts("PMIC Mode: SPI\n"); @@ -626,6 +830,10 @@ int board_init(void) setup_fec(); #endif +#ifdef CONFIG_NAND_GPMI + setup_gpmi_nand(); +#endif + return 0; } diff --git a/drivers/mtd/nand/gpmi_nfc_hal.c b/drivers/mtd/nand/gpmi_nfc_hal.c index 23ce265..568e3c5 100644 --- a/drivers/mtd/nand/gpmi_nfc_hal.c +++ b/drivers/mtd/nand/gpmi_nfc_hal.c @@ -918,13 +918,6 @@ static int send_command(struct mtd_info *mtd, unsigned chip, MTDDEBUG(MTD_DEBUG_LEVEL2, "Chip: %d DMA Buf: 0x%08x Length: %d\n", chip, buffer, length); -#ifdef CONFIG_ARCH_MMU - /* FIXME: I don't know why this delay is needed. - * But with this delay, nand operations can be ok. - */ - udelay(200); -#endif - /* Compute the DMA channel. */ dma_channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + chip; diff --git a/drivers/mtd/nand/gpmi_nfc_mil.c b/drivers/mtd/nand/gpmi_nfc_mil.c index d5433f8..8d50da6 100644 --- a/drivers/mtd/nand/gpmi_nfc_mil.c +++ b/drivers/mtd/nand/gpmi_nfc_mil.c @@ -69,8 +69,8 @@ static void gpmi_nfc_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) if (!cmd_queue) { #ifdef CONFIG_ARCH_MMU cmd_queue = - (u8 *)ioremap_nocache((u32)iomem_to_phys((ulong)kmalloc(GPMI_NFC_COMMAND_BUFFER_SIZE, - GFP_KERNEL)), + (u8 *)ioremap_nocache((u32)iomem_to_phys((ulong)memalign(MXS_DMA_ALIGNMENT, + GPMI_NFC_COMMAND_BUFFER_SIZE)), MXS_DMA_ALIGNMENT); #else cmd_queue = @@ -351,7 +351,7 @@ static int gpmi_nfc_ecc_read_page(struct mtd_info *mtd, MTDDEBUG(MTD_DEBUG_LEVEL1, "Buf: 0x%08x, data_buf: 0x%08x, " "oob_buf: 0x%08x", - buf, (u32)gpmi_info->data_buf, (u32)gpmi_info->oob_buf); + (u32)buf, (u32)gpmi_info->data_buf, (u32)gpmi_info->oob_buf); /* Ask the NFC. */ #ifdef CONFIG_ARCH_MMU error = nfc->read_page(mtd, gpmi_info->cur_chip, @@ -441,7 +441,7 @@ static void gpmi_nfc_ecc_write_page(struct mtd_info *mtd, MTDDEBUG(MTD_DEBUG_LEVEL3, "%s =>\n", __func__); MTDDEBUG(MTD_DEBUG_LEVEL1, "Buf: 0x%08x, data_buf: 0x%08x, " - "oob_buf: 0x%08x\n", buf, (u32)data_buf, (u32)oob_buf); + "oob_buf: 0x%08x\n", (u32)buf, (u32)data_buf, (u32)oob_buf); memcpy(data_buf, buf, mtd->writesize); memcpy(oob_buf, nand->oob_poi, mtd->oobsize); @@ -1116,11 +1116,11 @@ int board_nand_init(struct nand_chip *nand) */ chip->cmdfunc = NULL; chip->waitfunc = NULL; - chip->dev_ready = gpmi_nfc_dev_ready; + chip->dev_ready = gpmi_nfc_dev_ready; chip->select_chip = gpmi_nfc_select_chip; - chip->block_bad = gpmi_nfc_block_bad; + chip->block_bad = gpmi_nfc_block_bad; chip->block_markbad = NULL; - chip->read_byte = gpmi_nfc_read_byte; + chip->read_byte = gpmi_nfc_read_byte; /* * Low-level I/O * @@ -1129,7 +1129,7 @@ int board_nand_init(struct nand_chip *nand) * * We rely on the reference implentation of verify_buf. */ - chip->read_word = NULL; + chip->read_word = NULL; chip->write_buf = gpmi_nfc_write_buf; chip->read_buf = gpmi_nfc_read_buf; chip->verify_buf = NULL; diff --git a/include/configs/mx50_arm2.h b/include/configs/mx50_arm2.h index 421740c..8dfbb3f 100644 --- a/include/configs/mx50_arm2.h +++ b/include/configs/mx50_arm2.h @@ -133,7 +133,7 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "ARM2 U-Boot > " +#define CONFIG_SYS_PROMPT "MX50_ARM2 U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ @@ -246,7 +246,6 @@ /* Indicate to esdhc driver which ports support 8-bit data */ #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */ - #endif /* @@ -265,8 +264,6 @@ #define NAND_MAX_CHIPS 8 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 - - #endif /* diff --git a/include/configs/mx50_arm2_ddr2.h b/include/configs/mx50_arm2_ddr2.h index 744253f..c4dff04 100644 --- a/include/configs/mx50_arm2_ddr2.h +++ b/include/configs/mx50_arm2_ddr2.h @@ -132,7 +132,7 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "ARM_EVK U-Boot > " +#define CONFIG_SYS_PROMPT "MX50_ARM2 U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ @@ -197,11 +197,13 @@ * I2C Configs */ #define CONFIG_CMD_I2C 1 -#define CONFIG_HARD_I2C 1 -#define CONFIG_I2C_MXC 1 -#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe +#ifdef CONFIG_CMD_I2C + #define CONFIG_HARD_I2C 1 + #define CONFIG_I2C_MXC 1 + #define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR + #define CONFIG_SYS_I2C_SPEED 100000 + #define CONFIG_SYS_I2C_SLAVE 0xfe +#endif /* @@ -241,8 +243,38 @@ /* Indicate to esdhc driver which ports support 8-bit data */ #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */ +#endif + +/* + * GPMI Nand Configs + */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND + #define CONFIG_NAND_GPMI + #define CONFIG_GPMI_NFC_SWAP_BLOCK_MARK + #define CONFIG_GPMI_NFC_V2 + + #define CONFIG_GPMI_REG_BASE GPMI_BASE_ADDR + #define CONFIG_BCH_REG_BASE BCH_BASE_ADDR + + #define NAND_MAX_CHIPS 8 + #define CONFIG_SYS_NAND_BASE 0x40000000 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #endif + +/* + * APBH DMA Configs + */ +#define CONFIG_APBH_DMA + +#ifdef CONFIG_APBH_DMA + #define CONFIG_APBH_DMA_V2 + #define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR +#endif + /*----------------------------------------------------------------------- * Stack sizes * diff --git a/include/configs/mx50_arm2_lpddr2.h b/include/configs/mx50_arm2_lpddr2.h index ea11c02..0b52cba 100644 --- a/include/configs/mx50_arm2_lpddr2.h +++ b/include/configs/mx50_arm2_lpddr2.h @@ -132,7 +132,7 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "ARM2 U-Boot > " +#define CONFIG_SYS_PROMPT "MX50_ARM2 U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ @@ -197,11 +197,14 @@ * I2C Configs */ #define CONFIG_CMD_I2C 1 -#define CONFIG_HARD_I2C 1 -#define CONFIG_I2C_MXC 1 -#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe + +#ifdef CONFIG_CMD_I2C + #define CONFIG_HARD_I2C 1 + #define CONFIG_I2C_MXC 1 + #define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR + #define CONFIG_SYS_I2C_SPEED 100000 + #define CONFIG_SYS_I2C_SLAVE 0xfe +#endif /* @@ -267,7 +270,7 @@ #ifdef CONFIG_APBH_DMA #define CONFIG_APBH_DMA_V2 - #define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR + #define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR #endif /*----------------------------------------------------------------------- diff --git a/include/configs/mx50_rdp.h b/include/configs/mx50_rdp.h index fcfe4e0..b65afde 100644 --- a/include/configs/mx50_rdp.h +++ b/include/configs/mx50_rdp.h @@ -33,8 +33,10 @@ #define CONFIG_SKIP_RELOCATE_UBOOT +/* #define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MMU +*/ #define CONFIG_MX50_HCLK_FREQ 24000000 #define CONFIG_SYS_PLL2_FREQ 400 @@ -131,7 +133,7 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "RDP U-Boot > " +#define CONFIG_SYS_PROMPT "MX50_RDP U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ @@ -166,11 +168,14 @@ * I2C Configs */ #define CONFIG_CMD_I2C 1 -#define CONFIG_HARD_I2C 1 -#define CONFIG_I2C_MXC 1 -#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe + +#ifdef CONFIG_CMD_I2C + #define CONFIG_HARD_I2C 1 + #define CONFIG_I2C_MXC 1 + #define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR + #define CONFIG_SYS_I2C_SPEED 100000 + #define CONFIG_SYS_I2C_SLAVE 0xfe +#endif /* @@ -209,8 +214,36 @@ /* Indicate to esdhc driver which ports support 8-bit data */ #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */ +#endif + +/* + * GPMI Nand Configs + */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND + #define CONFIG_NAND_GPMI + #define CONFIG_GPMI_NFC_SWAP_BLOCK_MARK + #define CONFIG_GPMI_NFC_V2 + #define CONFIG_GPMI_REG_BASE GPMI_BASE_ADDR + #define CONFIG_BCH_REG_BASE BCH_BASE_ADDR + + #define NAND_MAX_CHIPS 8 + #define CONFIG_SYS_NAND_BASE 0x40000000 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 #endif + +/* + * APBH DMA Configs + */ +#define CONFIG_APBH_DMA + +#ifdef CONFIG_APBH_DMA + #define CONFIG_APBH_DMA_V2 + #define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR +#endif + /*----------------------------------------------------------------------- * Stack sizes * -- cgit v1.1